1 /* $OpenBSD: machdep.c,v 1.637 2020/07/22 08:33:43 fcambus Exp $ */ 2 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 36 * Copyright (c) 1992 Terrence R. Lambert. 37 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to Berkeley by 41 * William Jolitz. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/signalvar.h> 73 #include <sys/kernel.h> 74 #include <sys/proc.h> 75 #include <sys/user.h> 76 #include <sys/exec.h> 77 #include <sys/buf.h> 78 #include <sys/reboot.h> 79 #include <sys/conf.h> 80 #include <sys/timeout.h> 81 #include <sys/malloc.h> 82 #include <sys/mbuf.h> 83 #include <sys/msgbuf.h> 84 #include <sys/mount.h> 85 #include <sys/vnode.h> 86 #include <sys/device.h> 87 #include <sys/extent.h> 88 #include <sys/sysctl.h> 89 #include <sys/syscallargs.h> 90 #include <sys/core.h> 91 #include <sys/kcore.h> 92 #include <sys/sensors.h> 93 94 #include <dev/cons.h> 95 #include <stand/boot/bootarg.h> 96 97 #include <net/if.h> 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <machine/cpu.h> 103 #include <machine/cpu_full.h> 104 #include <machine/cpufunc.h> 105 #include <machine/cpuvar.h> 106 #include <machine/gdt.h> 107 #include <machine/kcore.h> 108 #include <machine/pio.h> 109 #include <machine/psl.h> 110 #include <machine/reg.h> 111 #include <machine/specialreg.h> 112 #include <machine/biosvar.h> 113 #include <machine/pte.h> 114 #ifdef MULTIPROCESSOR 115 #include <machine/mpbiosvar.h> 116 #endif /* MULTIPROCESSOR */ 117 118 #include <dev/isa/isareg.h> 119 #include <dev/isa/isavar.h> 120 #include <dev/ic/i8042reg.h> 121 #include <dev/ic/mc146818reg.h> 122 #include <i386/isa/isa_machdep.h> 123 #include <i386/isa/nvram.h> 124 125 #include "acpi.h" 126 #if NACPI > 0 127 #include <dev/acpi/acpivar.h> 128 #endif 129 130 #include "apm.h" 131 #if NAPM > 0 132 #include <machine/apmvar.h> 133 #endif 134 135 #ifdef DDB 136 #include <machine/db_machdep.h> 137 #include <ddb/db_access.h> 138 #include <ddb/db_sym.h> 139 #include <ddb/db_extern.h> 140 #endif 141 142 #include "isa.h" 143 #include "isadma.h" 144 #include "npx.h" 145 #if NNPX > 0 146 extern struct proc *npxproc; 147 #endif 148 149 #include "bios.h" 150 #include "com.h" 151 152 #if NCOM > 0 153 #include <sys/termios.h> 154 #include <dev/ic/comreg.h> 155 #include <dev/ic/comvar.h> 156 #endif /* NCOM > 0 */ 157 158 #ifdef HIBERNATE 159 #include <machine/hibernate_var.h> 160 #endif /* HIBERNATE */ 161 162 #include "ukbd.h" 163 #include "pckbc.h" 164 #if NPCKBC > 0 && NUKBD > 0 165 #include <dev/ic/pckbcvar.h> 166 #endif 167 168 /* #define MACHDEP_DEBUG */ 169 170 #ifdef MACHDEP_DEBUG 171 #define DPRINTF(x...) do { printf(x); } while (0) 172 #else 173 #define DPRINTF(x...) 174 #endif /* MACHDEP_DEBUG */ 175 176 void replacesmap(void); 177 int intr_handler(struct intrframe *, struct intrhand *); 178 179 /* the following is used externally (sysctl_hw) */ 180 char machine[] = MACHINE; 181 182 /* 183 * switchto vectors 184 */ 185 void (*cpu_idle_leave_fcn)(void) = NULL; 186 void (*cpu_idle_cycle_fcn)(void) = NULL; 187 void (*cpu_idle_enter_fcn)(void) = NULL; 188 189 190 struct uvm_constraint_range isa_constraint = { 0x0, 0x00ffffffUL }; 191 struct uvm_constraint_range dma_constraint = { 0x0, 0xffffffffUL }; 192 struct uvm_constraint_range *uvm_md_constraints[] = { 193 &isa_constraint, 194 &dma_constraint, 195 NULL 196 }; 197 198 extern int boothowto; 199 int physmem; 200 201 struct dumpmem dumpmem[VM_PHYSSEG_MAX]; 202 u_int ndumpmem; 203 204 /* 205 * These variables are needed by /sbin/savecore 206 */ 207 u_long dumpmag = 0x8fca0101; /* magic number */ 208 int dumpsize = 0; /* pages */ 209 long dumplo = 0; /* blocks */ 210 211 int cpu_class; 212 int i386_fpu_present; 213 int i386_fpu_exception; 214 int i386_fpu_fdivbug; 215 216 int i386_use_fxsave; 217 int i386_has_sse; 218 int i386_has_sse2; 219 int i386_has_xcrypt; 220 221 bootarg_t *bootargp; 222 paddr_t avail_end; 223 224 struct vm_map *exec_map = NULL; 225 struct vm_map *phys_map = NULL; 226 227 #if !defined(SMALL_KERNEL) 228 int p4_model; 229 int p3_early; 230 void (*update_cpuspeed)(void) = NULL; 231 void via_update_sensor(void *args); 232 #endif 233 int kbd_reset; 234 int lid_action = 1; 235 int pwr_action = 1; 236 int forceukbd; 237 238 /* 239 * safepri is a safe priority for sleep to set for a spin-wait 240 * during autoconfiguration or after a panic. 241 */ 242 int safepri = 0; 243 244 #if !defined(SMALL_KERNEL) 245 int bus_clock; 246 #endif 247 void (*setperf_setup)(struct cpu_info *); 248 int setperf_prio = 0; /* for concurrent handlers */ 249 250 void (*cpusensors_setup)(struct cpu_info *); 251 252 void (*delay_func)(int) = i8254_delay; 253 void (*initclock_func)(void) = i8254_initclocks; 254 255 /* 256 * Extent maps to manage I/O and ISA memory hole space. Allocate 257 * storage for 16 regions in each, initially. Later, ioport_malloc_safe 258 * will indicate that it's safe to use malloc() to dynamically allocate 259 * region descriptors. 260 * 261 * N.B. At least two regions are _always_ allocated from the iomem 262 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM). 263 * 264 * The extent maps are not static! Machine-dependent ISA and EISA 265 * routines need access to them for bus address space allocation. 266 */ 267 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 268 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 269 struct extent *ioport_ex; 270 struct extent *iomem_ex; 271 static int ioport_malloc_safe; 272 273 void dumpsys(void); 274 int cpu_dump(void); 275 void init386(paddr_t); 276 void consinit(void); 277 void (*cpuresetfn)(void); 278 279 int bus_mem_add_mapping(bus_addr_t, bus_size_t, 280 int, bus_space_handle_t *); 281 282 #ifdef APERTURE 283 int allowaperture = 0; 284 #endif 285 286 int has_rdrand; 287 int has_rdseed; 288 289 #include "pvbus.h" 290 #if NPVBUS > 0 291 #include <dev/pv/pvvar.h> 292 #endif 293 294 void winchip_cpu_setup(struct cpu_info *); 295 void amd_family5_setperf_setup(struct cpu_info *); 296 void amd_family5_setup(struct cpu_info *); 297 void amd_family6_setperf_setup(struct cpu_info *); 298 void amd_family6_setup(struct cpu_info *); 299 void cyrix3_setperf_setup(struct cpu_info *); 300 void cyrix3_cpu_setup(struct cpu_info *); 301 void cyrix6x86_cpu_setup(struct cpu_info *); 302 void natsem6x86_cpu_setup(struct cpu_info *); 303 void intel586_cpu_setup(struct cpu_info *); 304 void intel686_cpusensors_setup(struct cpu_info *); 305 void intel686_setperf_setup(struct cpu_info *); 306 void intel686_common_cpu_setup(struct cpu_info *); 307 void intel686_cpu_setup(struct cpu_info *); 308 void intel686_p4_cpu_setup(struct cpu_info *); 309 void intelcore_update_sensor(void *); 310 void tm86_cpu_setup(struct cpu_info *); 311 char * intel686_cpu_name(int); 312 char * cyrix3_cpu_name(int, int); 313 char * tm86_cpu_name(int); 314 void cyrix3_get_bus_clock(struct cpu_info *); 315 void p4_get_bus_clock(struct cpu_info *); 316 void p3_get_bus_clock(struct cpu_info *); 317 void p4_update_cpuspeed(void); 318 void p3_update_cpuspeed(void); 319 int pentium_cpuspeed(int *); 320 void enter_shared_special_pages(void); 321 322 static __inline u_char 323 cyrix_read_reg(u_char reg) 324 { 325 outb(0x22, reg); 326 return inb(0x23); 327 } 328 329 static __inline void 330 cyrix_write_reg(u_char reg, u_char data) 331 { 332 outb(0x22, reg); 333 outb(0x23, data); 334 } 335 336 /* 337 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx. 338 * requires caller to provide u_int32_t regs[4] array. 339 */ 340 void 341 cpuid(u_int32_t ax, u_int32_t *regs) 342 { 343 __asm volatile( 344 "cpuid\n\t" 345 "movl %%eax, 0(%2)\n\t" 346 "movl %%ebx, 4(%2)\n\t" 347 "movl %%ecx, 8(%2)\n\t" 348 "movl %%edx, 12(%2)\n\t" 349 :"=a" (ax) 350 :"0" (ax), "S" (regs) 351 :"bx", "cx", "dx"); 352 } 353 354 /* 355 * Machine-dependent startup code 356 */ 357 void 358 cpu_startup(void) 359 { 360 unsigned i; 361 vaddr_t minaddr, maxaddr, va; 362 paddr_t pa; 363 364 /* 365 * Initialize error message buffer (at end of core). 366 * (space reserved in pmap_bootstrap) 367 */ 368 pa = avail_end; 369 va = (vaddr_t)msgbufp; 370 for (i = 0; i < atop(MSGBUFSIZE); i++) { 371 pmap_kenter_pa(va, pa, PROT_READ | PROT_WRITE); 372 va += PAGE_SIZE; 373 pa += PAGE_SIZE; 374 } 375 pmap_update(pmap_kernel()); 376 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); 377 378 printf("%s", version); 379 startclocks(); 380 rtcinit(); 381 382 printf("real mem = %llu (%lluMB)\n", 383 (unsigned long long)ptoa((psize_t)physmem), 384 (unsigned long long)ptoa((psize_t)physmem)/1024U/1024U); 385 386 /* 387 * Allocate a submap for exec arguments. This map effectively 388 * limits the number of processes exec'ing at any time. 389 */ 390 minaddr = vm_map_min(kernel_map); 391 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 392 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 393 394 /* 395 * Allocate a submap for physio 396 */ 397 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 398 VM_PHYS_SIZE, 0, FALSE, NULL); 399 400 printf("avail mem = %llu (%lluMB)\n", 401 (unsigned long long)ptoa((psize_t)uvmexp.free), 402 (unsigned long long)ptoa((psize_t)uvmexp.free)/1024U/1024U); 403 404 /* 405 * Set up buffers, so they can be used to read disk labels. 406 */ 407 bufinit(); 408 409 /* 410 * Configure the system. 411 */ 412 if (boothowto & RB_CONFIG) { 413 #ifdef BOOT_CONFIG 414 user_config(); 415 #else 416 printf("kernel does not support -c; continuing..\n"); 417 #endif 418 } 419 ioport_malloc_safe = 1; 420 421 #ifndef SMALL_KERNEL 422 cpu_ucode_setup(); 423 #endif 424 425 /* enter the IDT and trampoline code in the u-k maps */ 426 enter_shared_special_pages(); 427 428 /* initialize CPU0's TSS and GDT and put them in the u-k maps */ 429 cpu_enter_pages(&cpu_info_full_primary); 430 } 431 432 void 433 enter_shared_special_pages(void) 434 { 435 extern char __kutext_start[], __kutext_end[], __kernel_kutext_phys[]; 436 extern char __kudata_start[], __kudata_end[], __kernel_kudata_phys[]; 437 vaddr_t va; 438 paddr_t pa; 439 440 /* idt */ 441 pmap_extract(pmap_kernel(), (vaddr_t)idt, &pa); 442 pmap_enter_special((vaddr_t)idt, pa, PROT_READ, 0); 443 444 /* .kutext section */ 445 va = (vaddr_t)__kutext_start; 446 pa = (paddr_t)__kernel_kutext_phys; 447 while (va < (vaddr_t)__kutext_end) { 448 pmap_enter_special(va, pa, PROT_READ | PROT_EXEC, 0); 449 DPRINTF("%s: entered kutext page va 0x%08lx pa 0x%08lx\n", 450 __func__, (unsigned long)va, (unsigned long)pa); 451 va += PAGE_SIZE; 452 pa += PAGE_SIZE; 453 } 454 455 /* .kudata section */ 456 va = (vaddr_t)__kudata_start; 457 pa = (paddr_t)__kernel_kudata_phys; 458 while (va < (vaddr_t)__kudata_end) { 459 pmap_enter_special(va, pa, PROT_READ | PROT_WRITE, 0); 460 DPRINTF("%s: entered kudata page va 0x%08lx pa 0x%08lx\n", 461 __func__, (unsigned long)va, (unsigned long)pa); 462 va += PAGE_SIZE; 463 pa += PAGE_SIZE; 464 } 465 } 466 467 /* 468 * Set up proc0's TSS 469 */ 470 void 471 i386_proc0_tss_init(void) 472 { 473 struct pcb *pcb; 474 475 curpcb = pcb = &proc0.p_addr->u_pcb; 476 pcb->pcb_cr0 = rcr0(); 477 pcb->pcb_kstack = (int)proc0.p_addr + USPACE - 16; 478 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_kstack - 1; 479 } 480 481 #ifdef MULTIPROCESSOR 482 void 483 i386_init_pcb_tss(struct cpu_info *ci) 484 { 485 struct pcb *pcb = ci->ci_idle_pcb; 486 487 pcb->pcb_cr0 = rcr0(); 488 } 489 #endif /* MULTIPROCESSOR */ 490 491 /* 492 * Info for CTL_HW 493 */ 494 char cpu_model[120]; 495 496 /* 497 * Note: these are just the ones that may not have a cpuid instruction. 498 * We deal with the rest in a different way. 499 */ 500 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 501 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 502 NULL}, /* CPU_386SX */ 503 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 504 NULL}, /* CPU_386 */ 505 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 506 NULL}, /* CPU_486SX */ 507 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 508 NULL}, /* CPU_486 */ 509 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 510 NULL}, /* CPU_486DLC */ 511 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 512 cyrix6x86_cpu_setup}, /* CPU_6x86 */ 513 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 514 NULL}, /* CPU_NX586 */ 515 }; 516 517 const char *classnames[] = { 518 "386", 519 "486", 520 "586", 521 "686" 522 }; 523 524 const char *modifiers[] = { 525 "", 526 "OverDrive ", 527 "Dual ", 528 "" 529 }; 530 531 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 532 { 533 "GenuineIntel", 534 CPUVENDOR_INTEL, 535 "Intel", 536 /* Family 4 */ 537 { { 538 CPUCLASS_486, 539 { 540 "486DX", "486DX", "486SX", "486DX2", "486SL", 541 "486SX2", 0, "486DX2 W/B", 542 "486DX4", 0, 0, 0, 0, 0, 0, 0, 543 "486" /* Default */ 544 }, 545 NULL 546 }, 547 /* Family 5 */ 548 { 549 CPUCLASS_586, 550 { 551 "Pentium (A-step)", "Pentium (P5)", 552 "Pentium (P54C)", "Pentium (P24T)", 553 "Pentium/MMX", "Pentium", 0, 554 "Pentium (P54C)", "Pentium/MMX", 555 0, 0, 0, 0, 0, 0, 0, 556 "Pentium" /* Default */ 557 }, 558 intel586_cpu_setup 559 }, 560 /* Family 6 */ 561 { 562 CPUCLASS_686, 563 { 564 "Pentium Pro", "Pentium Pro", 0, 565 "Pentium II", "Pentium Pro", 566 "Pentium II/Celeron", 567 "Celeron", 568 "Pentium III", 569 "Pentium III", 570 "Pentium M", 571 "Pentium III Xeon", 572 "Pentium III", 0, 573 "Pentium M", 574 "Core Duo/Solo", 0, 575 "Pentium Pro, II or III" /* Default */ 576 }, 577 intel686_cpu_setup 578 }, 579 /* Family 7 */ 580 { 581 CPUCLASS_686, 582 } , 583 /* Family 8 */ 584 { 585 CPUCLASS_686, 586 } , 587 /* Family 9 */ 588 { 589 CPUCLASS_686, 590 } , 591 /* Family A */ 592 { 593 CPUCLASS_686, 594 } , 595 /* Family B */ 596 { 597 CPUCLASS_686, 598 } , 599 /* Family C */ 600 { 601 CPUCLASS_686, 602 } , 603 /* Family D */ 604 { 605 CPUCLASS_686, 606 } , 607 /* Family E */ 608 { 609 CPUCLASS_686, 610 } , 611 /* Family F */ 612 { 613 CPUCLASS_686, 614 { 615 "Pentium 4", 0, 0, 0, 616 0, 0, 0, 0, 617 0, 0, 0, 0, 618 0, 0, 0, 0, 619 "Pentium 4" /* Default */ 620 }, 621 intel686_p4_cpu_setup 622 } } 623 }, 624 { 625 "AuthenticAMD", 626 CPUVENDOR_AMD, 627 "AMD", 628 /* Family 4 */ 629 { { 630 CPUCLASS_486, 631 { 632 0, 0, 0, "Am486DX2 W/T", 633 0, 0, 0, "Am486DX2 W/B", 634 "Am486DX4 W/T or Am5x86 W/T 150", 635 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 636 0, 0, "Am5x86 W/T 133/160", 637 "Am5x86 W/B 133/160", 638 "Am486 or Am5x86" /* Default */ 639 }, 640 NULL 641 }, 642 /* Family 5 */ 643 { 644 CPUCLASS_586, 645 { 646 "K5", "K5", "K5", "K5", 0, 0, "K6", 647 "K6", "K6-2", "K6-III", 0, 0, 0, 648 "K6-2+/III+", 0, 0, 649 "K5 or K6" /* Default */ 650 }, 651 amd_family5_setup 652 }, 653 /* Family 6 */ 654 { 655 CPUCLASS_686, 656 { 657 0, "Athlon Model 1", "Athlon Model 2", 658 "Duron Model 3", 659 "Athlon Model 4", 660 0, "Athlon XP Model 6", 661 "Duron Model 7", 662 "Athlon XP Model 8", 663 0, "Athlon XP Model 10", 664 0, 0, 0, 0, 0, 665 "K7" /* Default */ 666 }, 667 amd_family6_setup 668 }, 669 /* Family 7 */ 670 { 671 CPUCLASS_686, 672 } , 673 /* Family 8 */ 674 { 675 CPUCLASS_686, 676 } , 677 /* Family 9 */ 678 { 679 CPUCLASS_686, 680 } , 681 /* Family A */ 682 { 683 CPUCLASS_686, 684 } , 685 /* Family B */ 686 { 687 CPUCLASS_686, 688 } , 689 /* Family C */ 690 { 691 CPUCLASS_686, 692 } , 693 /* Family D */ 694 { 695 CPUCLASS_686, 696 } , 697 /* Family E */ 698 { 699 CPUCLASS_686, 700 } , 701 /* Family F */ 702 { 703 CPUCLASS_686, 704 { 705 0, 0, 0, 0, "Athlon64", 706 "Opteron or Athlon64FX", 0, 0, 707 0, 0, 0, 0, 0, 0, 0, 0, 708 "AMD64" /* DEFAULT */ 709 }, 710 amd_family6_setup 711 } } 712 }, 713 { 714 "CyrixInstead", 715 CPUVENDOR_CYRIX, 716 "Cyrix", 717 /* Family 4 */ 718 { { 719 CPUCLASS_486, 720 { 721 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0, 722 0, 0, 0, 0, 723 "486 class" /* Default */ 724 }, 725 NULL 726 }, 727 /* Family 5 */ 728 { 729 CPUCLASS_586, 730 { 731 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0, 732 0, 0, 0, 0, 0, 0, 733 "586 class" /* Default */ 734 }, 735 cyrix6x86_cpu_setup 736 }, 737 /* Family 6 */ 738 { 739 CPUCLASS_686, 740 { 741 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 742 0, 0, 0, 0, 743 "686 class" /* Default */ 744 }, 745 NULL 746 } } 747 }, 748 { 749 "CentaurHauls", 750 CPUVENDOR_IDT, 751 "IDT", 752 /* Family 4, not available from IDT */ 753 { { 754 CPUCLASS_486, 755 { 756 0, 0, 0, 0, 0, 0, 0, 0, 757 0, 0, 0, 0, 0, 0, 0, 0, 758 "486 class" /* Default */ 759 }, 760 NULL 761 }, 762 /* Family 5 */ 763 { 764 CPUCLASS_586, 765 { 766 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 767 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 768 "WinChip" /* Default */ 769 }, 770 winchip_cpu_setup 771 }, 772 /* Family 6 */ 773 { 774 CPUCLASS_686, 775 { 776 0, 0, 0, 0, 0, 0, 777 "C3 Samuel", 778 "C3 Samuel 2/Ezra", 779 "C3 Ezra-T", 780 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0, 781 "C3" /* Default */ 782 }, 783 cyrix3_cpu_setup 784 } } 785 }, 786 { 787 "RiseRiseRise", 788 CPUVENDOR_RISE, 789 "Rise", 790 /* Family 4, not available from Rise */ 791 { { 792 CPUCLASS_486, 793 { 794 0, 0, 0, 0, 0, 0, 0, 0, 795 0, 0, 0, 0, 0, 0, 0, 0, 796 "486 class" /* Default */ 797 }, 798 NULL 799 }, 800 /* Family 5 */ 801 { 802 CPUCLASS_586, 803 { 804 "mP6", 0, "mP6", 0, 0, 0, 0, 0, 805 0, 0, 0, 0, 0, 0, 0, 0, 806 "mP6" /* Default */ 807 }, 808 NULL 809 }, 810 /* Family 6, not yet available from Rise */ 811 { 812 CPUCLASS_686, 813 { 814 0, 0, 0, 0, 0, 0, 0, 0, 815 0, 0, 0, 0, 0, 0, 0, 0, 816 "686 class" /* Default */ 817 }, 818 NULL 819 } } 820 }, 821 { 822 "GenuineTMx86", 823 CPUVENDOR_TRANSMETA, 824 "Transmeta", 825 /* Family 4, not available from Transmeta */ 826 { { 827 CPUCLASS_486, 828 { 829 0, 0, 0, 0, 0, 0, 0, 0, 830 0, 0, 0, 0, 0, 0, 0, 0, 831 "486 class" /* Default */ 832 }, 833 NULL 834 }, 835 /* Family 5 */ 836 { 837 CPUCLASS_586, 838 { 839 0, 0, 0, 0, "TMS5x00", 0, 0, 840 0, 0, 0, 0, 0, 0, 0, 0, 0, 841 "TMS5x00" /* Default */ 842 }, 843 tm86_cpu_setup 844 }, 845 /* Family 6, not yet available from Transmeta */ 846 { 847 CPUCLASS_686, 848 { 849 0, 0, 0, 0, 0, 0, 0, 0, 850 0, 0, 0, 0, 0, 0, 0, 0, 851 "686 class" /* Default */ 852 }, 853 NULL 854 }, 855 /* Family 7 */ 856 { 857 CPUCLASS_686, 858 } , 859 /* Family 8 */ 860 { 861 CPUCLASS_686, 862 } , 863 /* Family 9 */ 864 { 865 CPUCLASS_686, 866 } , 867 /* Family A */ 868 { 869 CPUCLASS_686, 870 } , 871 /* Family B */ 872 { 873 CPUCLASS_686, 874 } , 875 /* Family C */ 876 { 877 CPUCLASS_686, 878 } , 879 /* Family D */ 880 { 881 CPUCLASS_686, 882 } , 883 /* Family E */ 884 { 885 CPUCLASS_686, 886 } , 887 /* Family F */ 888 { 889 /* Extended processor family - Transmeta Efficeon */ 890 CPUCLASS_686, 891 { 892 0, 0, "TM8000", "TM8000", 893 0, 0, 0, 0, 894 0, 0, 0, 0, 895 0, 0, 0, 0, 896 "TM8000" /* Default */ 897 }, 898 tm86_cpu_setup 899 } } 900 }, 901 { 902 "Geode by NSC", 903 CPUVENDOR_NS, 904 "National Semiconductor", 905 /* Family 4, not available from National Semiconductor */ 906 { { 907 CPUCLASS_486, 908 { 909 0, 0, 0, 0, 0, 0, 0, 0, 910 0, 0, 0, 0, 0, 0, 0, 0, 911 "486 class" /* Default */ 912 }, 913 NULL 914 }, 915 /* Family 5 */ 916 { 917 CPUCLASS_586, 918 { 919 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0, 920 0, 0, 0, 0, 0, 0, 921 "586 class" /* Default */ 922 }, 923 natsem6x86_cpu_setup 924 } } 925 }, 926 { 927 "SiS SiS SiS ", 928 CPUVENDOR_SIS, 929 "SiS", 930 /* Family 4, not available from SiS */ 931 { { 932 CPUCLASS_486, 933 { 934 0, 0, 0, 0, 0, 0, 0, 0, 935 0, 0, 0, 0, 0, 0, 0, 0, 936 "486 class" /* Default */ 937 }, 938 NULL 939 }, 940 /* Family 5 */ 941 { 942 CPUCLASS_586, 943 { 944 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0, 945 0, 0, 0, 0, 0, 0, 946 "586 class" /* Default */ 947 }, 948 NULL 949 } } 950 } 951 }; 952 953 const struct cpu_cpuid_feature i386_cpuid_features[] = { 954 { CPUID_FPU, "FPU" }, 955 { CPUID_VME, "V86" }, 956 { CPUID_DE, "DE" }, 957 { CPUID_PSE, "PSE" }, 958 { CPUID_TSC, "TSC" }, 959 { CPUID_MSR, "MSR" }, 960 { CPUID_PAE, "PAE" }, 961 { CPUID_MCE, "MCE" }, 962 { CPUID_CX8, "CX8" }, 963 { CPUID_APIC, "APIC" }, 964 { CPUID_SYS1, "SYS" }, 965 { CPUID_SEP, "SEP" }, 966 { CPUID_MTRR, "MTRR" }, 967 { CPUID_PGE, "PGE" }, 968 { CPUID_MCA, "MCA" }, 969 { CPUID_CMOV, "CMOV" }, 970 { CPUID_PAT, "PAT" }, 971 { CPUID_PSE36, "PSE36" }, 972 { CPUID_PSN, "PSN" }, 973 { CPUID_CFLUSH, "CFLUSH" }, 974 { CPUID_DS, "DS" }, 975 { CPUID_ACPI, "ACPI" }, 976 { CPUID_MMX, "MMX" }, 977 { CPUID_FXSR, "FXSR" }, 978 { CPUID_SSE, "SSE" }, 979 { CPUID_SSE2, "SSE2" }, 980 { CPUID_SS, "SS" }, 981 { CPUID_HTT, "HTT" }, 982 { CPUID_TM, "TM" }, 983 { CPUID_PBE, "PBE" } 984 }; 985 986 const struct cpu_cpuid_feature i386_ecpuid_features[] = { 987 { CPUID_MPC, "MPC" }, 988 { CPUID_NXE, "NXE" }, 989 { CPUID_MMXX, "MMXX" }, 990 { CPUID_FFXSR, "FFXSR" }, 991 { CPUID_PAGE1GB, "PAGE1GB" }, 992 { CPUID_RDTSCP, "RDTSCP" }, 993 { CPUID_LONG, "LONG" }, 994 { CPUID_3DNOW2, "3DNOW2" }, 995 { CPUID_3DNOW, "3DNOW" } 996 }; 997 998 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = { 999 { CPUIDECX_SSE3, "SSE3" }, 1000 { CPUIDECX_PCLMUL, "PCLMUL" }, 1001 { CPUIDECX_DTES64, "DTES64" }, 1002 { CPUIDECX_MWAIT, "MWAIT" }, 1003 { CPUIDECX_DSCPL, "DS-CPL" }, 1004 { CPUIDECX_VMX, "VMX" }, 1005 { CPUIDECX_SMX, "SMX" }, 1006 { CPUIDECX_EST, "EST" }, 1007 { CPUIDECX_TM2, "TM2" }, 1008 { CPUIDECX_SSSE3, "SSSE3" }, 1009 { CPUIDECX_CNXTID, "CNXT-ID" }, 1010 { CPUIDECX_SDBG, "SDBG" }, 1011 { CPUIDECX_FMA3, "FMA3" }, 1012 { CPUIDECX_CX16, "CX16" }, 1013 { CPUIDECX_XTPR, "xTPR" }, 1014 { CPUIDECX_PDCM, "PDCM" }, 1015 { CPUIDECX_PCID, "PCID" }, 1016 { CPUIDECX_DCA, "DCA" }, 1017 { CPUIDECX_SSE41, "SSE4.1" }, 1018 { CPUIDECX_SSE42, "SSE4.2" }, 1019 { CPUIDECX_X2APIC, "x2APIC" }, 1020 { CPUIDECX_MOVBE, "MOVBE" }, 1021 { CPUIDECX_POPCNT, "POPCNT" }, 1022 { CPUIDECX_DEADLINE, "DEADLINE" }, 1023 { CPUIDECX_AES, "AES" }, 1024 { CPUIDECX_XSAVE, "XSAVE" }, 1025 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 1026 { CPUIDECX_AVX, "AVX" }, 1027 { CPUIDECX_F16C, "F16C" }, 1028 { CPUIDECX_RDRAND, "RDRAND" }, 1029 { CPUIDECX_HV, "HV" }, 1030 }; 1031 1032 const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = { 1033 { CPUIDECX_LAHF, "LAHF" }, 1034 { CPUIDECX_CMPLEG, "CMPLEG" }, 1035 { CPUIDECX_SVM, "SVM" }, 1036 { CPUIDECX_EAPICSP, "EAPICSP" }, 1037 { CPUIDECX_AMCR8, "AMCR8" }, 1038 { CPUIDECX_ABM, "ABM" }, 1039 { CPUIDECX_SSE4A, "SSE4A" }, 1040 { CPUIDECX_MASSE, "MASSE" }, 1041 { CPUIDECX_3DNOWP, "3DNOWP" }, 1042 { CPUIDECX_OSVW, "OSVW" }, 1043 { CPUIDECX_IBS, "IBS" }, 1044 { CPUIDECX_XOP, "XOP" }, 1045 { CPUIDECX_SKINIT, "SKINIT" }, 1046 { CPUIDECX_WDT, "WDT" }, 1047 { CPUIDECX_LWP, "LWP" }, 1048 { CPUIDECX_FMA4, "FMA4" }, 1049 { CPUIDECX_TCE, "TCE" }, 1050 { CPUIDECX_NODEID, "NODEID" }, 1051 { CPUIDECX_TBM, "TBM" }, 1052 { CPUIDECX_TOPEXT, "TOPEXT" }, 1053 { CPUIDECX_CPCTR, "CPCTR" }, 1054 { CPUIDECX_DBKP, "DBKP" }, 1055 { CPUIDECX_PERFTSC, "PERFTSC" }, 1056 { CPUIDECX_PCTRL3, "PCTRL3" }, 1057 { CPUIDECX_MWAITX, "MWAITX" }, 1058 }; 1059 1060 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { 1061 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 1062 { SEFF0EBX_TSC_ADJUST, "TSC_ADJUST" }, 1063 { SEFF0EBX_SGX, "SGX" }, 1064 { SEFF0EBX_BMI1, "BMI1" }, 1065 { SEFF0EBX_HLE, "HLE" }, 1066 { SEFF0EBX_AVX2, "AVX2" }, 1067 { SEFF0EBX_SMEP, "SMEP" }, 1068 { SEFF0EBX_BMI2, "BMI2" }, 1069 { SEFF0EBX_ERMS, "ERMS" }, 1070 { SEFF0EBX_INVPCID, "INVPCID" }, 1071 { SEFF0EBX_RTM, "RTM" }, 1072 { SEFF0EBX_PQM, "PQM" }, 1073 { SEFF0EBX_MPX, "MPX" }, 1074 { SEFF0EBX_AVX512F, "AVX512F" }, 1075 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 1076 { SEFF0EBX_RDSEED, "RDSEED" }, 1077 { SEFF0EBX_ADX, "ADX" }, 1078 { SEFF0EBX_SMAP, "SMAP" }, 1079 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 1080 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 1081 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 1082 { SEFF0EBX_CLWB, "CLWB" }, 1083 { SEFF0EBX_PT, "PT" }, 1084 { SEFF0EBX_AVX512PF, "AVX512PF" }, 1085 { SEFF0EBX_AVX512ER, "AVX512ER" }, 1086 { SEFF0EBX_AVX512CD, "AVX512CD" }, 1087 { SEFF0EBX_SHA, "SHA" }, 1088 { SEFF0EBX_AVX512BW, "AVX512BW" }, 1089 { SEFF0EBX_AVX512VL, "AVX512VL" }, 1090 }; 1091 1092 const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = { 1093 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 1094 { SEFF0ECX_UMIP, "UMIP" }, 1095 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 1096 { SEFF0ECX_PKU, "PKU" }, 1097 }; 1098 1099 const struct cpu_cpuid_feature cpu_seff0_edxfeatures[] = { 1100 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 1101 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 1102 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 1103 { SEFF0EDX_STIBP, "STIBP" }, 1104 { SEFF0EDX_L1DF, "L1DF" }, 1105 /* SEFF0EDX_ARCH_CAP (not printed) */ 1106 { SEFF0EDX_SSBD, "SSBD" }, 1107 }; 1108 1109 const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = { 1110 { TPM_SENSOR, "SENSOR" }, 1111 { TPM_ARAT, "ARAT" }, 1112 }; 1113 1114 const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = { 1115 { CPUIDEAX_VERID, "PERF" }, 1116 }; 1117 1118 const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = { 1119 { CPUIDEDX_ITSC, "ITSC" }, 1120 }; 1121 1122 const struct cpu_cpuid_feature cpu_xsave_extfeatures[] = { 1123 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 1124 { XSAVE_XSAVEC, "XSAVEC" }, 1125 { XSAVE_XGETBV1, "XGETBV1" }, 1126 { XSAVE_XSAVES, "XSAVES" }, 1127 }; 1128 1129 void 1130 winchip_cpu_setup(struct cpu_info *ci) 1131 { 1132 1133 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1134 case 4: /* WinChip C6 */ 1135 ci->ci_feature_flags &= ~CPUID_TSC; 1136 /* Disable RDTSC instruction from user-level. */ 1137 lcr4(rcr4() | CR4_TSD); 1138 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1139 break; 1140 } 1141 } 1142 1143 #if !defined(SMALL_KERNEL) 1144 void 1145 cyrix3_setperf_setup(struct cpu_info *ci) 1146 { 1147 if (cpu_ecxfeature & CPUIDECX_EST) { 1148 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1149 est_init(ci, CPUVENDOR_VIA); 1150 else 1151 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1152 ci->ci_dev->dv_xname); 1153 } 1154 } 1155 #endif 1156 1157 void 1158 cyrix3_cpu_setup(struct cpu_info *ci) 1159 { 1160 int model = (ci->ci_signature >> 4) & 15; 1161 int step = ci->ci_signature & 15; 1162 1163 u_int64_t msreg; 1164 u_int32_t regs[4]; 1165 unsigned int val; 1166 #if !defined(SMALL_KERNEL) 1167 extern void (*pagezero)(void *, size_t); 1168 extern void i686_pagezero(void *, size_t); 1169 1170 pagezero = i686_pagezero; 1171 1172 setperf_setup = cyrix3_setperf_setup; 1173 #endif 1174 1175 switch (model) { 1176 /* Possible earlier models */ 1177 case 0: case 1: case 2: 1178 case 3: case 4: case 5: 1179 break; 1180 1181 case 6: /* C3 Samuel 1 */ 1182 case 7: /* C3 Samuel 2 or C3 Ezra */ 1183 case 8: /* C3 Ezra-T */ 1184 cpuid(0x80000001, regs); 1185 val = regs[3]; 1186 if (val & (1U << 31)) { 1187 cpu_feature |= CPUID_3DNOW; 1188 } else { 1189 cpu_feature &= ~CPUID_3DNOW; 1190 } 1191 break; 1192 1193 case 9: 1194 if (step < 3) 1195 break; 1196 /* 1197 * C3 Nehemiah & later: fall through. 1198 */ 1199 1200 case 10: /* C7-M Type A */ 1201 case 13: /* C7-M Type D */ 1202 case 15: /* Nano */ 1203 #if !defined(SMALL_KERNEL) 1204 if (CPU_IS_PRIMARY(ci) && 1205 (model == 10 || model == 13 || model == 15)) { 1206 /* Setup the sensors structures */ 1207 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1208 sizeof(ci->ci_sensordev.xname)); 1209 ci->ci_sensor.type = SENSOR_TEMP; 1210 sensor_task_register(ci, via_update_sensor, 5); 1211 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1212 sensordev_install(&ci->ci_sensordev); 1213 } 1214 #endif 1215 1216 default: 1217 /* 1218 * C3 Nehemiah/Esther & later models: 1219 * First we check for extended feature flags, and then 1220 * (if present) retrieve the ones at 0xC0000001. In this 1221 * bit 2 tells us if the RNG is present. Bit 3 tells us 1222 * if the RNG has been enabled. In order to use the RNG 1223 * we need 3 things: We need an RNG, we need the FXSR bit 1224 * enabled in cr4 (SSE/SSE2 stuff), and we need to have 1225 * Bit 6 of MSR 0x110B set to 1 (the default), which will 1226 * show up as bit 3 set here. 1227 */ 1228 cpuid(0xC0000000, regs); /* Check for RNG */ 1229 val = regs[0]; 1230 if (val >= 0xC0000001) { 1231 cpuid(0xC0000001, regs); 1232 val = regs[3]; 1233 } else 1234 val = 0; 1235 1236 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 1237 printf("%s:", ci->ci_dev->dv_xname); 1238 1239 /* Enable RNG if present and disabled */ 1240 if (val & C3_CPUID_HAS_RNG) { 1241 extern int viac3_rnd_present; 1242 1243 if (!(val & C3_CPUID_DO_RNG)) { 1244 msreg = rdmsr(0x110B); 1245 msreg |= 0x40; 1246 wrmsr(0x110B, msreg); 1247 } 1248 viac3_rnd_present = 1; 1249 printf(" RNG"); 1250 } 1251 1252 /* Enable AES engine if present and disabled */ 1253 if (val & C3_CPUID_HAS_ACE) { 1254 #ifdef CRYPTO 1255 if (!(val & C3_CPUID_DO_ACE)) { 1256 msreg = rdmsr(0x1107); 1257 msreg |= (0x01 << 28); 1258 wrmsr(0x1107, msreg); 1259 } 1260 i386_has_xcrypt |= C3_HAS_AES; 1261 #endif /* CRYPTO */ 1262 printf(" AES"); 1263 } 1264 1265 /* Enable ACE2 engine if present and disabled */ 1266 if (val & C3_CPUID_HAS_ACE2) { 1267 #ifdef CRYPTO 1268 if (!(val & C3_CPUID_DO_ACE2)) { 1269 msreg = rdmsr(0x1107); 1270 msreg |= (0x01 << 28); 1271 wrmsr(0x1107, msreg); 1272 } 1273 i386_has_xcrypt |= C3_HAS_AESCTR; 1274 #endif /* CRYPTO */ 1275 printf(" AES-CTR"); 1276 } 1277 1278 /* Enable SHA engine if present and disabled */ 1279 if (val & C3_CPUID_HAS_PHE) { 1280 #ifdef CRYPTO 1281 if (!(val & C3_CPUID_DO_PHE)) { 1282 msreg = rdmsr(0x1107); 1283 msreg |= (0x01 << 28/**/); 1284 wrmsr(0x1107, msreg); 1285 } 1286 i386_has_xcrypt |= C3_HAS_SHA; 1287 #endif /* CRYPTO */ 1288 printf(" SHA1 SHA256"); 1289 } 1290 1291 /* Enable MM engine if present and disabled */ 1292 if (val & C3_CPUID_HAS_PMM) { 1293 #ifdef CRYPTO 1294 if (!(val & C3_CPUID_DO_PMM)) { 1295 msreg = rdmsr(0x1107); 1296 msreg |= (0x01 << 28/**/); 1297 wrmsr(0x1107, msreg); 1298 } 1299 i386_has_xcrypt |= C3_HAS_MM; 1300 #endif /* CRYPTO */ 1301 printf(" RSA"); 1302 } 1303 1304 printf("\n"); 1305 break; 1306 } 1307 } 1308 1309 #if !defined(SMALL_KERNEL) 1310 void 1311 via_update_sensor(void *args) 1312 { 1313 struct cpu_info *ci = (struct cpu_info *) args; 1314 u_int64_t msr; 1315 1316 switch (ci->ci_model) { 1317 case 0xa: 1318 case 0xd: 1319 msr = rdmsr(MSR_C7M_TMTEMPERATURE); 1320 break; 1321 case 0xf: 1322 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 1323 break; 1324 } 1325 ci->ci_sensor.value = (msr & 0xffffff); 1326 /* micro degrees */ 1327 ci->ci_sensor.value *= 1000000; 1328 ci->ci_sensor.value += 273150000; 1329 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1330 } 1331 #endif 1332 1333 void 1334 cyrix6x86_cpu_setup(struct cpu_info *ci) 1335 { 1336 extern int clock_broken_latch; 1337 1338 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1339 case -1: /* M1 w/o cpuid */ 1340 case 2: /* M1 */ 1341 /* set up various cyrix registers */ 1342 /* Enable suspend on halt */ 1343 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 1344 /* enable access to ccr4/ccr5 */ 1345 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10); 1346 /* cyrix's workaround for the "coma bug" */ 1347 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 1348 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 1349 cyrix_read_reg(0x33); cyrix_write_reg(0x33, 0); 1350 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 1351 /* disable access to ccr4/ccr5 */ 1352 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10); 1353 1354 printf("%s: xchg bug workaround performed\n", 1355 ci->ci_dev->dv_xname); 1356 break; /* fallthrough? */ 1357 case 4: /* GXm */ 1358 /* Unset the TSC bit until calibrate_delay() gets fixed. */ 1359 clock_broken_latch = 1; 1360 curcpu()->ci_feature_flags &= ~CPUID_TSC; 1361 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1362 break; 1363 } 1364 } 1365 1366 void 1367 natsem6x86_cpu_setup(struct cpu_info *ci) 1368 { 1369 extern int clock_broken_latch; 1370 int model = (ci->ci_signature >> 4) & 15; 1371 1372 clock_broken_latch = 1; 1373 switch (model) { 1374 case 4: 1375 cpu_feature &= ~CPUID_TSC; 1376 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1377 break; 1378 } 1379 } 1380 1381 void 1382 intel586_cpu_setup(struct cpu_info *ci) 1383 { 1384 if (!cpu_f00f_bug) { 1385 fix_f00f(); 1386 printf("%s: F00F bug workaround installed\n", 1387 ci->ci_dev->dv_xname); 1388 } 1389 } 1390 1391 #if !defined(SMALL_KERNEL) 1392 void 1393 amd_family5_setperf_setup(struct cpu_info *ci) 1394 { 1395 k6_powernow_init(); 1396 } 1397 #endif 1398 1399 void 1400 amd_family5_setup(struct cpu_info *ci) 1401 { 1402 int model = (ci->ci_signature >> 4) & 15; 1403 1404 switch (model) { 1405 case 0: /* AMD-K5 Model 0 */ 1406 /* 1407 * According to the AMD Processor Recognition App Note, 1408 * the AMD-K5 Model 0 uses the wrong bit to indicate 1409 * support for global PTEs, instead using bit 9 (APIC) 1410 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1411 */ 1412 if (cpu_feature & CPUID_APIC) 1413 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE; 1414 /* 1415 * XXX But pmap_pg_g is already initialized -- need to kick 1416 * XXX the pmap somehow. How does the MP branch do this? 1417 */ 1418 break; 1419 case 12: 1420 case 13: 1421 #if !defined(SMALL_KERNEL) 1422 setperf_setup = amd_family5_setperf_setup; 1423 #endif 1424 break; 1425 } 1426 } 1427 1428 #if !defined(SMALL_KERNEL) 1429 void 1430 amd_family6_setperf_setup(struct cpu_info *ci) 1431 { 1432 int family = (ci->ci_signature >> 8) & 15; 1433 1434 switch (family) { 1435 case 6: 1436 k7_powernow_init(); 1437 break; 1438 case 15: 1439 k8_powernow_init(); 1440 break; 1441 } 1442 if (ci->ci_family >= 0x10) 1443 k1x_init(ci); 1444 } 1445 #endif 1446 1447 void 1448 amd_family6_setup(struct cpu_info *ci) 1449 { 1450 #if !defined(SMALL_KERNEL) 1451 int family = (ci->ci_signature >> 8) & 15; 1452 extern void (*pagezero)(void *, size_t); 1453 extern void sse2_pagezero(void *, size_t); 1454 extern void i686_pagezero(void *, size_t); 1455 1456 if (cpu_feature & CPUID_SSE2) 1457 pagezero = sse2_pagezero; 1458 else 1459 pagezero = i686_pagezero; 1460 1461 setperf_setup = amd_family6_setperf_setup; 1462 1463 if (family == 0xf) { 1464 amd64_errata(ci); 1465 } 1466 #endif 1467 } 1468 1469 #if !defined(SMALL_KERNEL) 1470 /* 1471 * Temperature read on the CPU is relative to the maximum 1472 * temperature supported by the CPU, Tj(Max). 1473 * Refer to: 1474 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 1475 * Section 35 and 1476 * http://www.intel.com/content/dam/www/public/us/en/documents/ 1477 * white-papers/cpu-monitoring-dts-peci-paper.pdf 1478 * 1479 * The temperature on Intel CPUs can be between 70 and 105 degC, since 1480 * Westmere we can read the TJmax from the die. For older CPUs we have 1481 * to guess or use undocumented MSRs. Then we subtract the temperature 1482 * portion of thermal status from max to get current temperature. 1483 */ 1484 void 1485 intelcore_update_sensor(void *args) 1486 { 1487 struct cpu_info *ci = (struct cpu_info *) args; 1488 u_int64_t msr; 1489 int max = 100; 1490 1491 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 1492 if (ci->ci_model == 0x0e && 1493 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 1494 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 1495 max = 85; 1496 1497 /* 1498 * Newer CPUs can tell you what their max temperature is. 1499 * See: '64-ia-32-architectures-software-developer- 1500 * vol-3c-part-3-manual.pdf' 1501 */ 1502 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 1503 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 1504 ci->ci_model != 0x35 && ci->ci_model != 0x36) 1505 max = MSR_TEMPERATURE_TARGET_TJMAX( 1506 rdmsr(MSR_TEMPERATURE_TARGET)); 1507 1508 msr = rdmsr(MSR_THERM_STATUS); 1509 if (msr & MSR_THERM_STATUS_VALID_BIT) { 1510 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 1511 /* micro degrees */ 1512 ci->ci_sensor.value *= 1000000; 1513 /* kelvin */ 1514 ci->ci_sensor.value += 273150000; 1515 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1516 } else { 1517 ci->ci_sensor.value = 0; 1518 ci->ci_sensor.flags |= SENSOR_FINVALID; 1519 } 1520 } 1521 1522 void 1523 intel686_cpusensors_setup(struct cpu_info *ci) 1524 { 1525 if (!CPU_IS_PRIMARY(ci) || (ci->ci_feature_tpmflags & TPM_SENSOR) == 0) 1526 return; 1527 1528 /* Setup the sensors structures */ 1529 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1530 sizeof(ci->ci_sensordev.xname)); 1531 ci->ci_sensor.type = SENSOR_TEMP; 1532 sensor_task_register(ci, intelcore_update_sensor, 5); 1533 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1534 sensordev_install(&ci->ci_sensordev); 1535 } 1536 #endif 1537 1538 #if !defined(SMALL_KERNEL) 1539 void 1540 intel686_setperf_setup(struct cpu_info *ci) 1541 { 1542 int family = (ci->ci_signature >> 8) & 15; 1543 int step = ci->ci_signature & 15; 1544 1545 if (cpu_ecxfeature & CPUIDECX_EST) { 1546 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1547 est_init(ci, CPUVENDOR_INTEL); 1548 else 1549 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1550 ci->ci_dev->dv_xname); 1551 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) == 1552 (CPUID_ACPI | CPUID_TM)) 1553 p4tcc_init(family, step); 1554 } 1555 #endif 1556 1557 void 1558 intel686_common_cpu_setup(struct cpu_info *ci) 1559 { 1560 1561 #if !defined(SMALL_KERNEL) 1562 setperf_setup = intel686_setperf_setup; 1563 cpusensors_setup = intel686_cpusensors_setup; 1564 { 1565 extern void (*pagezero)(void *, size_t); 1566 extern void sse2_pagezero(void *, size_t); 1567 extern void i686_pagezero(void *, size_t); 1568 1569 if (cpu_feature & CPUID_SSE2) 1570 pagezero = sse2_pagezero; 1571 else 1572 pagezero = i686_pagezero; 1573 } 1574 #endif 1575 /* 1576 * Make sure SYSENTER is disabled. 1577 */ 1578 if (cpu_feature & CPUID_SEP) 1579 wrmsr(MSR_SYSENTER_CS, 0); 1580 } 1581 1582 void 1583 intel686_cpu_setup(struct cpu_info *ci) 1584 { 1585 int model = (ci->ci_signature >> 4) & 15; 1586 int step = ci->ci_signature & 15; 1587 u_quad_t msr119; 1588 1589 intel686_common_cpu_setup(ci); 1590 1591 /* 1592 * Original PPro returns SYSCALL in CPUID but is non-functional. 1593 * From Intel Application Note #485. 1594 */ 1595 if ((model == 1) && (step < 3)) 1596 ci->ci_feature_flags &= ~CPUID_SEP; 1597 1598 /* 1599 * Disable the Pentium3 serial number. 1600 */ 1601 if ((model == 7) && (ci->ci_feature_flags & CPUID_PSN)) { 1602 msr119 = rdmsr(MSR_BBL_CR_CTL); 1603 msr119 |= 0x0000000000200000LL; 1604 wrmsr(MSR_BBL_CR_CTL, msr119); 1605 1606 printf("%s: disabling processor serial number\n", 1607 ci->ci_dev->dv_xname); 1608 ci->ci_feature_flags &= ~CPUID_PSN; 1609 ci->ci_level = 2; 1610 } 1611 1612 #if !defined(SMALL_KERNEL) 1613 p3_early = (model == 8 && step == 1) ? 1 : 0; 1614 update_cpuspeed = p3_update_cpuspeed; 1615 #endif 1616 } 1617 1618 void 1619 intel686_p4_cpu_setup(struct cpu_info *ci) 1620 { 1621 intel686_common_cpu_setup(ci); 1622 1623 #if !defined(SMALL_KERNEL) 1624 p4_model = (ci->ci_signature >> 4) & 15; 1625 update_cpuspeed = p4_update_cpuspeed; 1626 #endif 1627 } 1628 1629 void 1630 tm86_cpu_setup(struct cpu_info *ci) 1631 { 1632 #if !defined(SMALL_KERNEL) 1633 longrun_init(); 1634 #endif 1635 } 1636 1637 char * 1638 intel686_cpu_name(int model) 1639 { 1640 char *ret = NULL; 1641 1642 switch (model) { 1643 case 5: 1644 switch (cpu_cache_edx & 0xFF) { 1645 case 0x40: 1646 case 0x41: 1647 ret = "Celeron"; 1648 break; 1649 /* 0x42 should not exist in this model. */ 1650 case 0x43: 1651 ret = "Pentium II"; 1652 break; 1653 case 0x44: 1654 case 0x45: 1655 ret = "Pentium II Xeon"; 1656 break; 1657 } 1658 break; 1659 case 7: 1660 switch (cpu_cache_edx & 0xFF) { 1661 /* 0x40 - 0x42 should not exist in this model. */ 1662 case 0x43: 1663 ret = "Pentium III"; 1664 break; 1665 case 0x44: 1666 case 0x45: 1667 ret = "Pentium III Xeon"; 1668 break; 1669 } 1670 break; 1671 } 1672 1673 return (ret); 1674 } 1675 1676 char * 1677 cyrix3_cpu_name(int model, int step) 1678 { 1679 char *name = NULL; 1680 1681 switch (model) { 1682 case 7: 1683 if (step < 8) 1684 name = "C3 Samuel 2"; 1685 else 1686 name = "C3 Ezra"; 1687 break; 1688 } 1689 return name; 1690 } 1691 1692 /* 1693 * Print identification for the given CPU. 1694 * XXX XXX 1695 * This is not as clean as one might like, because it references 1696 * 1697 * the "cpuid_level" and "cpu_vendor" globals. 1698 * cpuid_level isn't so bad, since both CPU's will hopefully 1699 * be of the same level. 1700 * 1701 * The Intel multiprocessor spec doesn't give us the cpu_vendor 1702 * information; however, the chance of multi-vendor SMP actually 1703 * ever *working* is sufficiently low that it's probably safe to assume 1704 * all processors are of the same vendor. 1705 */ 1706 void 1707 identifycpu(struct cpu_info *ci) 1708 { 1709 const char *name, *modifier, *vendorname, *token; 1710 int class = CPUCLASS_386, vendor, i, max; 1711 int family, model, step, modif, cachesize; 1712 const struct cpu_cpuid_nameclass *cpup = NULL; 1713 char *brandstr_from, *brandstr_to; 1714 char *cpu_device = ci->ci_dev->dv_xname; 1715 int skipspace; 1716 extern uint32_t cpu_meltdown; 1717 1718 if (cpuid_level == -1) { 1719 #ifdef DIAGNOSTIC 1720 if (cpu < 0 || cpu >= 1721 (sizeof i386_nocpuid_cpus/sizeof(struct cpu_nocpuid_nameclass))) 1722 panic("unknown cpu type %d", cpu); 1723 #endif 1724 name = i386_nocpuid_cpus[cpu].cpu_name; 1725 vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1726 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1727 model = -1; 1728 step = -1; 1729 class = i386_nocpuid_cpus[cpu].cpu_class; 1730 ci->cpu_setup = i386_nocpuid_cpus[cpu].cpu_setup; 1731 modifier = ""; 1732 token = ""; 1733 } else { 1734 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1735 modif = (ci->ci_signature >> 12) & 3; 1736 family = (ci->ci_signature >> 8) & 15; 1737 ci->ci_family = family; 1738 model = (ci->ci_signature >> 4) & 15; 1739 ci->ci_model = model; 1740 step = ci->ci_signature & 15; 1741 #ifdef CPUDEBUG 1742 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n", 1743 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx, 1744 cpu_cache_ecx, cpu_cache_edx); 1745 #endif 1746 if (family < CPU_MINFAMILY) 1747 panic("identifycpu: strange family value"); 1748 1749 for (i = 0; i < max; i++) { 1750 if (!strncmp(cpu_vendor, 1751 i386_cpuid_cpus[i].cpu_id, 12)) { 1752 cpup = &i386_cpuid_cpus[i]; 1753 break; 1754 } 1755 } 1756 1757 if (cpup == NULL) { 1758 vendor = CPUVENDOR_UNKNOWN; 1759 if (cpu_vendor[0] != '\0') 1760 vendorname = &cpu_vendor[0]; 1761 else 1762 vendorname = "Unknown"; 1763 if (family > CPU_MAXFAMILY) 1764 family = CPU_MAXFAMILY; 1765 class = family - 3; 1766 if (class > CPUCLASS_686) 1767 class = CPUCLASS_686; 1768 modifier = ""; 1769 name = ""; 1770 token = ""; 1771 ci->cpu_setup = NULL; 1772 } else { 1773 token = cpup->cpu_id; 1774 vendor = cpup->cpu_vendor; 1775 vendorname = cpup->cpu_vendorname; 1776 /* 1777 * Special hack for the VIA C3 series. 1778 * 1779 * VIA bought Centaur Technology from IDT in Aug 1999 1780 * and marketed the processors as VIA Cyrix III/C3. 1781 */ 1782 if (vendor == CPUVENDOR_IDT && family >= 6) { 1783 vendor = CPUVENDOR_VIA; 1784 vendorname = "VIA"; 1785 } 1786 modifier = modifiers[modif]; 1787 if (family > CPU_MAXFAMILY) { 1788 family = CPU_MAXFAMILY; 1789 model = CPU_DEFMODEL; 1790 } else if (model > CPU_MAXMODEL) 1791 model = CPU_DEFMODEL; 1792 i = family - CPU_MINFAMILY; 1793 1794 /* store extended family/model values for later use */ 1795 if ((vendor == CPUVENDOR_INTEL && 1796 (family == 0x6 || family == 0xf)) || 1797 (vendor == CPUVENDOR_AMD && family == 0xf)) { 1798 ci->ci_family += (ci->ci_signature >> 20) & 1799 0xff; 1800 ci->ci_model += ((ci->ci_signature >> 16) & 1801 0x0f) << 4; 1802 } 1803 1804 /* Special hack for the PentiumII/III series. */ 1805 if (vendor == CPUVENDOR_INTEL && family == 6 && 1806 (model == 5 || model == 7)) { 1807 name = intel686_cpu_name(model); 1808 /* Special hack for the VIA C3 series. */ 1809 } else if (vendor == CPUVENDOR_VIA && family == 6 && 1810 model == 7) { 1811 name = cyrix3_cpu_name(model, step); 1812 /* Special hack for the TMS5x00 series. */ 1813 } else if (vendor == CPUVENDOR_TRANSMETA && 1814 family == 5 && model == 4) { 1815 name = tm86_cpu_name(model); 1816 } else 1817 name = cpup->cpu_family[i].cpu_models[model]; 1818 if (name == NULL) { 1819 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL]; 1820 if (name == NULL) 1821 name = ""; 1822 } 1823 class = cpup->cpu_family[i].cpu_class; 1824 ci->cpu_setup = cpup->cpu_family[i].cpu_setup; 1825 } 1826 } 1827 1828 /* Find the amount of on-chip L2 cache. */ 1829 cachesize = -1; 1830 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) { 1831 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 }; 1832 1833 if ((cpu_cache_edx & 0xFF) >= 0x40 && 1834 (cpu_cache_edx & 0xFF) <= 0x45) 1835 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40]; 1836 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) { 1837 u_int regs[4]; 1838 cpuid(0x80000000, regs); 1839 1840 if (regs[0] >= 0x80000005) 1841 cpuid(0x80000005, ci->ci_amdcacheinfo); 1842 1843 if (regs[0] >= 0x80000006) { 1844 cpuid(0x80000006, ci->ci_extcacheinfo); 1845 cachesize = (ci->ci_extcacheinfo[2] >> 16); 1846 } 1847 } 1848 1849 if (ci->ci_feature_flags & CPUID_CFLUSH) { 1850 u_int regs[4]; 1851 1852 /* to get the cacheline size you must do cpuid 1853 * with eax 0x01 1854 */ 1855 1856 cpuid(0x01, regs); 1857 ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; 1858 } 1859 1860 if (vendor == CPUVENDOR_INTEL) { 1861 u_int regs[4]; 1862 /* 1863 * PIII, Core Solo and Core Duo CPUs have known 1864 * errata stating: 1865 * "Page with PAT set to WC while associated MTRR is UC 1866 * may consolidate to UC". 1867 * Because of this it is best we just fallback to mtrrs 1868 * in this case. 1869 */ 1870 if (ci->ci_family == 6 && ci->ci_model < 15) 1871 ci->ci_feature_flags &= ~CPUID_PAT; 1872 1873 if (cpuid_level >= 0x1) { 1874 cpuid(0x80000000, regs); 1875 if (regs[0] >= 0x80000006) 1876 cpuid(0x80000006, ci->ci_extcacheinfo); 1877 } 1878 } 1879 1880 /* Remove leading, trailing and duplicated spaces from cpu_brandstr */ 1881 brandstr_from = brandstr_to = cpu_brandstr; 1882 skipspace = 1; 1883 while (*brandstr_from != '\0') { 1884 if (!skipspace || *brandstr_from != ' ') { 1885 skipspace = 0; 1886 *(brandstr_to++) = *brandstr_from; 1887 } 1888 if (*brandstr_from == ' ') 1889 skipspace = 1; 1890 brandstr_from++; 1891 } 1892 if (skipspace && brandstr_to > cpu_brandstr) 1893 brandstr_to--; 1894 *brandstr_to = '\0'; 1895 1896 if (cpu_brandstr[0] == '\0') { 1897 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */, 1898 "%s %s%s", vendorname, modifier, name); 1899 } 1900 1901 if (cachesize > -1) { 1902 snprintf(cpu_model, sizeof(cpu_model), 1903 "%s (%s%s%s%s-class, %dKB L2 cache)", 1904 cpu_brandstr, 1905 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1906 ((*token) ? "\" " : ""), classnames[class], cachesize); 1907 } else { 1908 snprintf(cpu_model, sizeof(cpu_model), 1909 "%s (%s%s%s%s-class)", 1910 cpu_brandstr, 1911 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1912 ((*token) ? "\" " : ""), classnames[class]); 1913 } 1914 1915 printf("%s: %s", cpu_device, cpu_model); 1916 1917 if (ci->ci_feature_flags && (ci->ci_feature_flags & CPUID_TSC)) { 1918 /* Has TSC, check if it's constant */ 1919 switch (vendor) { 1920 case CPUVENDOR_INTEL: 1921 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 1922 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 1923 ci->ci_flags |= CPUF_CONST_TSC; 1924 } 1925 break; 1926 case CPUVENDOR_VIA: 1927 if (ci->ci_model >= 0x0f) { 1928 ci->ci_flags |= CPUF_CONST_TSC; 1929 } 1930 break; 1931 } 1932 calibrate_cyclecounter(); 1933 if (cpuspeed > 994) { 1934 int ghz, fr; 1935 1936 ghz = (cpuspeed + 9) / 1000; 1937 fr = ((cpuspeed + 9) / 10 ) % 100; 1938 if (fr) 1939 printf(" %d.%02d GHz", ghz, fr); 1940 else 1941 printf(" %d GHz", ghz); 1942 } else { 1943 printf(" %d MHz", cpuspeed); 1944 } 1945 } 1946 1947 if (cpuid_level != -1) 1948 printf(", %02x-%02x-%02x", ci->ci_family, ci->ci_model, 1949 step); 1950 1951 printf("\n"); 1952 1953 if (ci->ci_feature_flags) { 1954 int numbits = 0; 1955 1956 printf("%s: ", cpu_device); 1957 max = sizeof(i386_cpuid_features) / 1958 sizeof(i386_cpuid_features[0]); 1959 for (i = 0; i < max; i++) { 1960 if (ci->ci_feature_flags & 1961 i386_cpuid_features[i].feature_bit) { 1962 printf("%s%s", (numbits == 0 ? "" : ","), 1963 i386_cpuid_features[i].feature_name); 1964 numbits++; 1965 } 1966 } 1967 max = sizeof(i386_cpuid_ecxfeatures) 1968 / sizeof(i386_cpuid_ecxfeatures[0]); 1969 for (i = 0; i < max; i++) { 1970 if (cpu_ecxfeature & 1971 i386_cpuid_ecxfeatures[i].feature_bit) { 1972 printf("%s%s", (numbits == 0 ? "" : ","), 1973 i386_cpuid_ecxfeatures[i].feature_name); 1974 numbits++; 1975 } 1976 } 1977 for (i = 0; i < nitems(i386_ecpuid_features); i++) { 1978 if (ecpu_feature & 1979 i386_ecpuid_features[i].feature_bit) { 1980 printf("%s%s", (numbits == 0 ? "" : ","), 1981 i386_ecpuid_features[i].feature_name); 1982 numbits++; 1983 } 1984 } 1985 for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) { 1986 if (ecpu_ecxfeature & 1987 i386_ecpuid_ecxfeatures[i].feature_bit) { 1988 printf("%s%s", (numbits == 0 ? "" : ","), 1989 i386_ecpuid_ecxfeatures[i].feature_name); 1990 numbits++; 1991 } 1992 } 1993 for (i = 0; i < nitems(i386_cpuid_eaxperf); i++) { 1994 if (cpu_perf_eax & 1995 i386_cpuid_eaxperf[i].feature_bit) { 1996 printf("%s%s", (numbits == 0 ? "" : ","), 1997 i386_cpuid_eaxperf[i].feature_name); 1998 numbits++; 1999 } 2000 } 2001 for (i = 0; i < nitems(i386_cpuid_edxapmi); i++) { 2002 if (cpu_apmi_edx & 2003 i386_cpuid_edxapmi[i].feature_bit) { 2004 printf("%s%s", (numbits == 0 ? "" : ","), 2005 i386_cpuid_edxapmi[i].feature_name); 2006 numbits++; 2007 } 2008 } 2009 2010 if (cpuid_level >= 0x07) { 2011 u_int dummy; 2012 2013 /* "Structured Extended Feature Flags" */ 2014 CPUID_LEAF(0x7, 0, dummy, 2015 ci->ci_feature_sefflags_ebx, 2016 ci->ci_feature_sefflags_ecx, 2017 ci->ci_feature_sefflags_edx); 2018 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 2019 if (ci->ci_feature_sefflags_ebx & 2020 cpu_seff0_ebxfeatures[i].feature_bit) 2021 printf("%s%s", 2022 (numbits == 0 ? "" : ","), 2023 cpu_seff0_ebxfeatures[i].feature_name); 2024 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 2025 if (ci->ci_feature_sefflags_ecx & 2026 cpu_seff0_ecxfeatures[i].feature_bit) 2027 printf("%s%s", 2028 (numbits == 0 ? "" : ","), 2029 cpu_seff0_ecxfeatures[i].feature_name); 2030 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 2031 if (ci->ci_feature_sefflags_edx & 2032 cpu_seff0_edxfeatures[i].feature_bit) 2033 printf("%s%s", 2034 (numbits == 0 ? "" : ","), 2035 cpu_seff0_edxfeatures[i].feature_name); 2036 } 2037 2038 if (!strcmp(cpu_vendor, "GenuineIntel") && 2039 cpuid_level >= 0x06 ) { 2040 u_int dummy; 2041 2042 CPUID(0x06, ci->ci_feature_tpmflags, dummy, 2043 dummy, dummy); 2044 max = nitems(cpu_tpm_eaxfeatures); 2045 for (i = 0; i < max; i++) 2046 if (ci->ci_feature_tpmflags & 2047 cpu_tpm_eaxfeatures[i].feature_bit) 2048 printf(",%s", cpu_tpm_eaxfeatures[i].feature_name); 2049 } 2050 2051 /* xsave subfeatures */ 2052 if (cpuid_level >= 0xd) { 2053 uint32_t dummy, val; 2054 2055 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 2056 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 2057 if (val & cpu_xsave_extfeatures[i].feature_bit) 2058 printf(",%s", 2059 cpu_xsave_extfeatures[i].feature_name); 2060 } 2061 2062 if (cpu_meltdown) 2063 printf(",MELTDOWN"); 2064 2065 printf("\n"); 2066 } 2067 2068 /* 2069 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques 2070 * for Managing Speculation on AMD Processors" 2071 * 2072 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch 2073 * serializing instruction. 2074 * 2075 * This MSR is available on all AMD families >= 10h, except 11h 2076 * where LFENCE is always serializing. 2077 */ 2078 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 2079 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) { 2080 uint64_t msr; 2081 2082 msr = rdmsr(MSR_DE_CFG); 2083 if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { 2084 msr |= DE_CFG_SERIALIZE_LFENCE; 2085 wrmsr(MSR_DE_CFG, msr); 2086 } 2087 } 2088 } 2089 2090 /* 2091 * Attempt to disable Silicon Debug and lock the configuration 2092 * if it's enabled and unlocked. 2093 */ 2094 if (!strcmp(cpu_vendor, "GenuineIntel") && 2095 (cpu_ecxfeature & CPUIDECX_SDBG)) { 2096 uint64_t msr; 2097 2098 msr = rdmsr(IA32_DEBUG_INTERFACE); 2099 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 2100 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 2101 msr &= IA32_DEBUG_INTERFACE_MASK; 2102 msr |= IA32_DEBUG_INTERFACE_LOCK; 2103 wrmsr(IA32_DEBUG_INTERFACE, msr); 2104 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 2105 printf("%s: cannot disable silicon debug\n", 2106 cpu_device); 2107 } 2108 2109 if (CPU_IS_PRIMARY(ci)) { 2110 if (cpu_ecxfeature & CPUIDECX_RDRAND) 2111 has_rdrand = 1; 2112 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 2113 has_rdseed = 1; 2114 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 2115 replacesmap(); 2116 } 2117 2118 #ifndef SMALL_KERNEL 2119 if (cpuspeed != 0 && cpu_cpuspeed == NULL) 2120 cpu_cpuspeed = pentium_cpuspeed; 2121 #endif 2122 2123 cpu_class = class; 2124 2125 if (cpu_class == CPUCLASS_386) { 2126 printf("WARNING: 386 (possibly unknown?) cpu class, assuming 486\n"); 2127 cpu_class = CPUCLASS_486; 2128 } 2129 2130 ci->cpu_class = class; 2131 2132 if (cpu == CPU_486DLC) 2133 printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2134 2135 /* 2136 * Enable ring 0 write protection (486 or above, but 386 2137 * no longer supported). 2138 */ 2139 lcr0(rcr0() | CR0_WP); 2140 2141 /* 2142 * If we have FXSAVE/FXRESTOR, use them. 2143 */ 2144 if (cpu_feature & CPUID_FXSR) { 2145 i386_use_fxsave = 1; 2146 lcr4(rcr4() | CR4_OSFXSR); 2147 2148 /* 2149 * If we have SSE/SSE2, enable XMM exceptions, and 2150 * notify userland. 2151 */ 2152 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) { 2153 if (cpu_feature & CPUID_SSE) 2154 i386_has_sse = 1; 2155 if (cpu_feature & CPUID_SSE2) 2156 i386_has_sse2 = 1; 2157 lcr4(rcr4() | CR4_OSXMMEXCPT); 2158 } 2159 } else 2160 i386_use_fxsave = 0; 2161 2162 } 2163 2164 char * 2165 tm86_cpu_name(int model) 2166 { 2167 u_int32_t regs[4]; 2168 char *name = NULL; 2169 2170 cpuid(0x80860001, regs); 2171 2172 switch (model) { 2173 case 4: 2174 if (((regs[1] >> 16) & 0xff) >= 0x3) 2175 name = "TMS5800"; 2176 else 2177 name = "TMS5600"; 2178 } 2179 2180 return name; 2181 } 2182 2183 #ifndef SMALL_KERNEL 2184 void 2185 cyrix3_get_bus_clock(struct cpu_info *ci) 2186 { 2187 u_int64_t msr; 2188 int bus; 2189 2190 msr = rdmsr(MSR_EBL_CR_POWERON); 2191 bus = (msr >> 18) & 0x3; 2192 switch (bus) { 2193 case 0: 2194 bus_clock = BUS100; 2195 break; 2196 case 1: 2197 bus_clock = BUS133; 2198 break; 2199 case 2: 2200 bus_clock = BUS200; 2201 break; 2202 case 3: 2203 bus_clock = BUS166; 2204 break; 2205 } 2206 } 2207 2208 void 2209 p4_get_bus_clock(struct cpu_info *ci) 2210 { 2211 u_int64_t msr; 2212 int model, bus; 2213 2214 model = (ci->ci_signature >> 4) & 15; 2215 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2216 if (model < 2) { 2217 bus = (msr >> 21) & 0x7; 2218 switch (bus) { 2219 case 0: 2220 bus_clock = BUS100; 2221 break; 2222 case 1: 2223 bus_clock = BUS133; 2224 break; 2225 default: 2226 printf("%s: unknown Pentium 4 (model %d) " 2227 "EBC_FREQUENCY_ID value %d\n", 2228 ci->ci_dev->dv_xname, model, bus); 2229 break; 2230 } 2231 } else { 2232 bus = (msr >> 16) & 0x7; 2233 switch (bus) { 2234 case 0: 2235 bus_clock = (model == 2) ? BUS100 : BUS266; 2236 break; 2237 case 1: 2238 bus_clock = BUS133; 2239 break; 2240 case 2: 2241 bus_clock = BUS200; 2242 break; 2243 case 3: 2244 bus_clock = BUS166; 2245 break; 2246 default: 2247 printf("%s: unknown Pentium 4 (model %d) " 2248 "EBC_FREQUENCY_ID value %d\n", 2249 ci->ci_dev->dv_xname, model, bus); 2250 break; 2251 } 2252 } 2253 } 2254 2255 void 2256 p3_get_bus_clock(struct cpu_info *ci) 2257 { 2258 u_int64_t msr; 2259 int bus; 2260 2261 switch (ci->ci_model) { 2262 case 0x9: /* Pentium M (130 nm, Banias) */ 2263 bus_clock = BUS100; 2264 break; 2265 case 0xd: /* Pentium M (90 nm, Dothan) */ 2266 msr = rdmsr(MSR_FSB_FREQ); 2267 bus = (msr >> 0) & 0x7; 2268 switch (bus) { 2269 case 0: 2270 bus_clock = BUS100; 2271 break; 2272 case 1: 2273 bus_clock = BUS133; 2274 break; 2275 default: 2276 printf("%s: unknown Pentium M FSB_FREQ value %d", 2277 ci->ci_dev->dv_xname, bus); 2278 goto print_msr; 2279 } 2280 break; 2281 case 0x15: /* EP80579 no FSB */ 2282 break; 2283 case 0xe: /* Core Duo/Solo */ 2284 case 0xf: /* Core Xeon */ 2285 case 0x16: /* 65nm Celeron */ 2286 case 0x17: /* Core 2 Extreme/45nm Xeon */ 2287 case 0x1d: /* Xeon MP 7400 */ 2288 msr = rdmsr(MSR_FSB_FREQ); 2289 bus = (msr >> 0) & 0x7; 2290 switch (bus) { 2291 case 5: 2292 bus_clock = BUS100; 2293 break; 2294 case 1: 2295 bus_clock = BUS133; 2296 break; 2297 case 3: 2298 bus_clock = BUS166; 2299 break; 2300 case 2: 2301 bus_clock = BUS200; 2302 break; 2303 case 0: 2304 bus_clock = BUS266; 2305 break; 2306 case 4: 2307 bus_clock = BUS333; 2308 break; 2309 default: 2310 printf("%s: unknown Core FSB_FREQ value %d", 2311 ci->ci_dev->dv_xname, bus); 2312 goto print_msr; 2313 } 2314 break; 2315 case 0x1c: /* Atom */ 2316 case 0x26: /* Atom Z6xx */ 2317 case 0x36: /* Atom [DN]2xxx */ 2318 msr = rdmsr(MSR_FSB_FREQ); 2319 bus = (msr >> 0) & 0x7; 2320 switch (bus) { 2321 case 5: 2322 bus_clock = BUS100; 2323 break; 2324 case 1: 2325 bus_clock = BUS133; 2326 break; 2327 case 3: 2328 bus_clock = BUS166; 2329 break; 2330 case 2: 2331 bus_clock = BUS200; 2332 break; 2333 default: 2334 printf("%s: unknown Atom FSB_FREQ value %d", 2335 ci->ci_dev->dv_xname, bus); 2336 goto print_msr; 2337 } 2338 break; 2339 case 0x1: /* Pentium Pro, model 1 */ 2340 case 0x3: /* Pentium II, model 3 */ 2341 case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */ 2342 case 0x6: /* Celeron, model 6 */ 2343 case 0x7: /* Pentium III, III Xeon, model 7 */ 2344 case 0x8: /* Pentium III, III Xeon, Celeron, model 8 */ 2345 case 0xa: /* Pentium III Xeon, model A */ 2346 case 0xb: /* Pentium III, model B */ 2347 msr = rdmsr(MSR_EBL_CR_POWERON); 2348 bus = (msr >> 18) & 0x3; 2349 switch (bus) { 2350 case 0: 2351 bus_clock = BUS66; 2352 break; 2353 case 1: 2354 bus_clock = BUS133; 2355 break; 2356 case 2: 2357 bus_clock = BUS100; 2358 break; 2359 default: 2360 printf("%s: unknown i686 EBL_CR_POWERON value %d", 2361 ci->ci_dev->dv_xname, bus); 2362 goto print_msr; 2363 } 2364 break; 2365 default: 2366 /* no FSB on modern Intel processors */ 2367 break; 2368 } 2369 return; 2370 print_msr: 2371 /* 2372 * Show the EBL_CR_POWERON MSR, so we'll at least have 2373 * some extra information, such as clock ratio, etc. 2374 */ 2375 printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON)); 2376 } 2377 2378 void 2379 p4_update_cpuspeed(void) 2380 { 2381 struct cpu_info *ci; 2382 u_int64_t msr; 2383 int mult; 2384 2385 ci = curcpu(); 2386 p4_get_bus_clock(ci); 2387 2388 if (bus_clock == 0) { 2389 printf("p4_update_cpuspeed: unknown bus clock\n"); 2390 return; 2391 } 2392 2393 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2394 mult = ((msr >> 24) & 0xff); 2395 2396 cpuspeed = (bus_clock * mult) / 100; 2397 } 2398 2399 void 2400 p3_update_cpuspeed(void) 2401 { 2402 struct cpu_info *ci; 2403 u_int64_t msr; 2404 int mult; 2405 const u_int8_t mult_code[] = { 2406 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 }; 2407 2408 ci = curcpu(); 2409 p3_get_bus_clock(ci); 2410 2411 if (bus_clock == 0) { 2412 printf("p3_update_cpuspeed: unknown bus clock\n"); 2413 return; 2414 } 2415 2416 msr = rdmsr(MSR_EBL_CR_POWERON); 2417 mult = (msr >> 22) & 0xf; 2418 mult = mult_code[mult]; 2419 if (!p3_early) 2420 mult += ((msr >> 27) & 0x1) * 40; 2421 2422 cpuspeed = (bus_clock * mult) / 1000; 2423 } 2424 2425 int 2426 pentium_cpuspeed(int *freq) 2427 { 2428 *freq = cpuspeed; 2429 return (0); 2430 } 2431 #endif /* !SMALL_KERNEL */ 2432 2433 /* 2434 * Send an interrupt to process. 2435 * 2436 * Stack is set up to allow sigcode stored 2437 * in u. to call routine, followed by kcall 2438 * to sigreturn routine below. After sigreturn 2439 * resets the signal mask, the stack, and the 2440 * frame pointer, it returns to the user 2441 * specified pc, psl. 2442 */ 2443 void 2444 sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip) 2445 { 2446 struct proc *p = curproc; 2447 struct trapframe *tf = p->p_md.md_regs; 2448 struct sigframe *fp, frame; 2449 struct sigacts *psp = p->p_p->ps_sigacts; 2450 register_t sp; 2451 2452 /* 2453 * Build the argument list for the signal handler. 2454 */ 2455 bzero(&frame, sizeof(frame)); 2456 frame.sf_signum = sig; 2457 2458 /* 2459 * Allocate space for the signal handler context. 2460 */ 2461 if ((p->p_sigstk.ss_flags & SS_DISABLE) == 0 && 2462 !sigonstack(tf->tf_esp) && (psp->ps_sigonstack & sigmask(sig))) 2463 sp = trunc_page((vaddr_t)p->p_sigstk.ss_sp + p->p_sigstk.ss_size); 2464 else 2465 sp = tf->tf_esp; 2466 2467 frame.sf_sc.sc_fpstate = NULL; 2468 if (p->p_md.md_flags & MDP_USEDFPU) { 2469 npxsave_proc(p, 1); 2470 sp -= sizeof(union savefpu); 2471 sp &= ~0xf; /* for XMM regs */ 2472 frame.sf_sc.sc_fpstate = (void *)sp; 2473 if (copyout(&p->p_addr->u_pcb.pcb_savefpu, 2474 (void *)sp, sizeof(union savefpu))) 2475 sigexit(p, SIGILL); 2476 2477 /* Signal handlers get a completely clean FP state */ 2478 p->p_md.md_flags &= ~MDP_USEDFPU; 2479 } 2480 2481 fp = (struct sigframe *)sp - 1; 2482 frame.sf_scp = &fp->sf_sc; 2483 frame.sf_sip = NULL; 2484 frame.sf_handler = catcher; 2485 2486 /* 2487 * Build the signal context to be used by sigreturn. 2488 */ 2489 frame.sf_sc.sc_err = tf->tf_err; 2490 frame.sf_sc.sc_trapno = tf->tf_trapno; 2491 frame.sf_sc.sc_mask = mask; 2492 frame.sf_sc.sc_fs = tf->tf_fs; 2493 frame.sf_sc.sc_gs = tf->tf_gs; 2494 frame.sf_sc.sc_es = tf->tf_es; 2495 frame.sf_sc.sc_ds = tf->tf_ds; 2496 frame.sf_sc.sc_eflags = tf->tf_eflags; 2497 frame.sf_sc.sc_edi = tf->tf_edi; 2498 frame.sf_sc.sc_esi = tf->tf_esi; 2499 frame.sf_sc.sc_ebp = tf->tf_ebp; 2500 frame.sf_sc.sc_ebx = tf->tf_ebx; 2501 frame.sf_sc.sc_edx = tf->tf_edx; 2502 frame.sf_sc.sc_ecx = tf->tf_ecx; 2503 frame.sf_sc.sc_eax = tf->tf_eax; 2504 frame.sf_sc.sc_eip = tf->tf_eip; 2505 frame.sf_sc.sc_cs = tf->tf_cs; 2506 frame.sf_sc.sc_esp = tf->tf_esp; 2507 frame.sf_sc.sc_ss = tf->tf_ss; 2508 2509 if (psp->ps_siginfo & sigmask(sig)) { 2510 frame.sf_sip = &fp->sf_si; 2511 frame.sf_si = *ksip; 2512 } 2513 2514 /* XXX don't copyout siginfo if not needed? */ 2515 frame.sf_sc.sc_cookie = (long)&fp->sf_sc ^ p->p_p->ps_sigcookie; 2516 if (copyout(&frame, fp, sizeof(frame)) != 0) { 2517 /* 2518 * Process has trashed its stack; give it an illegal 2519 * instruction to halt it in its tracks. 2520 */ 2521 sigexit(p, SIGILL); 2522 /* NOTREACHED */ 2523 } 2524 2525 /* 2526 * Build context to run handler in. 2527 */ 2528 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2529 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2530 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2531 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2532 tf->tf_eip = p->p_p->ps_sigcode; 2533 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2534 tf->tf_eflags &= ~(PSL_T|PSL_D|PSL_VM|PSL_AC); 2535 tf->tf_esp = (int)fp; 2536 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2537 } 2538 2539 /* 2540 * System call to cleanup state after a signal 2541 * has been taken. Reset signal mask and 2542 * stack state from context left by sendsig (above). 2543 * Return to previous pc and psl as specified by 2544 * context left by sendsig. Check carefully to 2545 * make sure that the user has not modified the 2546 * psl to gain improper privileges or to cause 2547 * a machine fault. 2548 */ 2549 int 2550 sys_sigreturn(struct proc *p, void *v, register_t *retval) 2551 { 2552 struct sys_sigreturn_args /* { 2553 syscallarg(struct sigcontext *) sigcntxp; 2554 } */ *uap = v; 2555 struct sigcontext ksc, *scp = SCARG(uap, sigcntxp); 2556 struct trapframe *tf = p->p_md.md_regs; 2557 int error; 2558 2559 if (PROC_PC(p) != p->p_p->ps_sigcoderet) { 2560 sigexit(p, SIGILL); 2561 return (EPERM); 2562 } 2563 2564 if ((error = copyin((caddr_t)scp, &ksc, sizeof(*scp)))) 2565 return (error); 2566 2567 if (ksc.sc_cookie != ((long)scp ^ p->p_p->ps_sigcookie)) { 2568 sigexit(p, SIGILL); 2569 return (EFAULT); 2570 } 2571 2572 /* Prevent reuse of the sigcontext cookie */ 2573 ksc.sc_cookie = 0; 2574 (void)copyout(&ksc.sc_cookie, (caddr_t)scp + 2575 offsetof(struct sigcontext, sc_cookie), sizeof (ksc.sc_cookie)); 2576 2577 /* 2578 * Restore signal ksc. 2579 */ 2580 /* 2581 * Check for security violations. If we're returning to 2582 * protected mode, the CPU will validate the segment registers 2583 * automatically and generate a trap on violations. We handle 2584 * the trap, rather than doing all of the checking here. 2585 */ 2586 if (((ksc.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 || 2587 !USERMODE(ksc.sc_cs, ksc.sc_eflags)) 2588 return (EINVAL); 2589 2590 tf->tf_fs = ksc.sc_fs; 2591 tf->tf_gs = ksc.sc_gs; 2592 tf->tf_es = ksc.sc_es; 2593 tf->tf_ds = ksc.sc_ds; 2594 tf->tf_eflags = ksc.sc_eflags; 2595 tf->tf_edi = ksc.sc_edi; 2596 tf->tf_esi = ksc.sc_esi; 2597 tf->tf_ebp = ksc.sc_ebp; 2598 tf->tf_ebx = ksc.sc_ebx; 2599 tf->tf_edx = ksc.sc_edx; 2600 tf->tf_ecx = ksc.sc_ecx; 2601 tf->tf_eax = ksc.sc_eax; 2602 tf->tf_eip = ksc.sc_eip; 2603 tf->tf_cs = ksc.sc_cs; 2604 tf->tf_esp = ksc.sc_esp; 2605 tf->tf_ss = ksc.sc_ss; 2606 2607 if (p->p_md.md_flags & MDP_USEDFPU) 2608 npxsave_proc(p, 0); 2609 2610 if (ksc.sc_fpstate) { 2611 union savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu; 2612 2613 if ((error = copyin(ksc.sc_fpstate, sfp, sizeof(*sfp)))) 2614 return (error); 2615 if (i386_use_fxsave) 2616 sfp->sv_xmm.sv_env.en_mxcsr &= fpu_mxcsr_mask; 2617 p->p_md.md_flags |= MDP_USEDFPU; 2618 } 2619 2620 p->p_sigmask = ksc.sc_mask & ~sigcantmask; 2621 2622 return (EJUSTRETURN); 2623 } 2624 2625 #ifdef MULTIPROCESSOR 2626 /* force a CPU into the kernel, whether or not it's idle */ 2627 void 2628 cpu_kick(struct cpu_info *ci) 2629 { 2630 /* only need to kick other CPUs */ 2631 if (ci != curcpu()) { 2632 if (cpu_mwait_size > 0) { 2633 /* 2634 * If not idling, then send an IPI, else 2635 * just clear the "keep idling" bit. 2636 */ 2637 if ((ci->ci_mwait & MWAIT_IN_IDLE) == 0) 2638 i386_send_ipi(ci, I386_IPI_NOP); 2639 else 2640 atomic_clearbits_int(&ci->ci_mwait, 2641 MWAIT_KEEP_IDLING); 2642 } else { 2643 /* no mwait, so need an IPI */ 2644 i386_send_ipi(ci, I386_IPI_NOP); 2645 } 2646 } 2647 } 2648 #endif 2649 2650 /* 2651 * Notify the current process (p) that it has a signal pending, 2652 * process as soon as possible. 2653 */ 2654 void 2655 signotify(struct proc *p) 2656 { 2657 aston(p); 2658 cpu_kick(p->p_cpu); 2659 } 2660 2661 #ifdef MULTIPROCESSOR 2662 void 2663 cpu_unidle(struct cpu_info *ci) 2664 { 2665 if (cpu_mwait_size > 0 && (ci->ci_mwait & MWAIT_ONLY)) { 2666 /* 2667 * Just clear the "keep idling" bit; if it wasn't 2668 * idling then we didn't need to do anything anyway. 2669 */ 2670 atomic_clearbits_int(&ci->ci_mwait, MWAIT_KEEP_IDLING); 2671 return; 2672 } 2673 2674 if (ci != curcpu()) 2675 i386_send_ipi(ci, I386_IPI_NOP); 2676 } 2677 #endif 2678 2679 int waittime = -1; 2680 struct pcb dumppcb; 2681 2682 __dead void 2683 boot(int howto) 2684 { 2685 if ((howto & RB_POWERDOWN) != 0) 2686 lid_action = 0; 2687 2688 if ((howto & RB_RESET) != 0) 2689 goto doreset; 2690 2691 if (cold) { 2692 if ((howto & RB_USERREQ) == 0) 2693 howto |= RB_HALT; 2694 goto haltsys; 2695 } 2696 2697 boothowto = howto; 2698 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 2699 waittime = 0; 2700 vfs_shutdown(curproc); 2701 2702 if ((howto & RB_TIMEBAD) == 0) { 2703 resettodr(); 2704 } else { 2705 printf("WARNING: not updating battery clock\n"); 2706 } 2707 } 2708 if_downall(); 2709 2710 uvm_shutdown(); 2711 splhigh(); 2712 cold = 1; 2713 2714 if ((howto & RB_DUMP) != 0) 2715 dumpsys(); 2716 2717 haltsys: 2718 config_suspend_all(DVACT_POWERDOWN); 2719 2720 #ifdef MULTIPROCESSOR 2721 i386_broadcast_ipi(I386_IPI_HALT); 2722 #endif 2723 2724 if ((howto & RB_HALT) != 0) { 2725 #if NACPI > 0 && !defined(SMALL_KERNEL) 2726 extern int acpi_enabled; 2727 2728 if (acpi_enabled) { 2729 delay(500000); 2730 if ((howto & RB_POWERDOWN) != 0) 2731 acpi_powerdown(); 2732 } 2733 #endif 2734 2735 #if NAPM > 0 2736 if ((howto & RB_POWERDOWN) != 0) { 2737 int rv; 2738 2739 printf("\nAttempting to power down...\n"); 2740 /* 2741 * Turn off, if we can. But try to turn disk off and 2742 * wait a bit first--some disk drives are slow to 2743 * clean up and users have reported disk corruption. 2744 * 2745 * If apm_set_powstate() fails the first time, don't 2746 * try to turn the system off. 2747 */ 2748 delay(500000); 2749 apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2750 delay(500000); 2751 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2752 if (rv == 0 || rv == ENXIO) { 2753 delay(500000); 2754 (void) apm_set_powstate(APM_DEV_ALLDEVS, 2755 APM_SYS_OFF); 2756 } 2757 } 2758 #endif 2759 printf("\n"); 2760 printf("The operating system has halted.\n"); 2761 printf("Please press any key to reboot.\n\n"); 2762 cnpollc(1); /* for proper keyboard command handling */ 2763 cngetc(); 2764 cnpollc(0); 2765 } 2766 2767 doreset: 2768 printf("rebooting...\n"); 2769 cpu_reset(); 2770 for (;;) 2771 continue; 2772 /* NOTREACHED */ 2773 } 2774 2775 /* 2776 * This is called by configure to set dumplo and dumpsize. 2777 * Dumps always skip the first block of disk space 2778 * in case there might be a disk label stored there. 2779 * If there is extra space, put dump at the end to 2780 * reduce the chance that swapping trashes it. 2781 */ 2782 void 2783 dumpconf(void) 2784 { 2785 int nblks; /* size of dump area */ 2786 int i; 2787 2788 if (dumpdev == NODEV || 2789 (nblks = (bdevsw[major(dumpdev)].d_psize)(dumpdev)) == 0) 2790 return; 2791 if (nblks <= ctod(1)) 2792 return; 2793 2794 /* Always skip the first block, in case there is a label there. */ 2795 if (dumplo < ctod(1)) 2796 dumplo = ctod(1); 2797 2798 for (i = 0; i < ndumpmem; i++) 2799 dumpsize = max(dumpsize, dumpmem[i].end); 2800 2801 /* Put dump at end of partition, and make it fit. */ 2802 if (dumpsize > dtoc(nblks - dumplo - 1)) 2803 dumpsize = dtoc(nblks - dumplo - 1); 2804 if (dumplo < nblks - ctod(dumpsize) - 1) 2805 dumplo = nblks - ctod(dumpsize) - 1; 2806 } 2807 2808 /* 2809 * cpu_dump: dump machine-dependent kernel core dump headers. 2810 */ 2811 int 2812 cpu_dump(void) 2813 { 2814 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2815 long buf[dbtob(1) / sizeof (long)]; 2816 kcore_seg_t *segp; 2817 2818 dump = bdevsw[major(dumpdev)].d_dump; 2819 2820 segp = (kcore_seg_t *)buf; 2821 2822 /* 2823 * Generate a segment header. 2824 */ 2825 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 2826 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); 2827 2828 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1))); 2829 } 2830 2831 /* 2832 * Doadump comes here after turning off memory management and 2833 * getting on the dump stack, either when called above, or by 2834 * the auto-restart code. 2835 */ 2836 static vaddr_t dumpspace; 2837 2838 vaddr_t 2839 reserve_dumppages(vaddr_t p) 2840 { 2841 2842 dumpspace = p; 2843 return (p + PAGE_SIZE); 2844 } 2845 2846 void 2847 dumpsys(void) 2848 { 2849 u_int i, j, npg; 2850 int maddr; 2851 daddr_t blkno; 2852 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2853 int error; 2854 char *str; 2855 extern int msgbufmapped; 2856 2857 /* Save registers. */ 2858 savectx(&dumppcb); 2859 2860 msgbufmapped = 0; /* don't record dump msgs in msgbuf */ 2861 if (dumpdev == NODEV) 2862 return; 2863 2864 /* 2865 * For dumps during autoconfiguration, 2866 * if dump device has already configured... 2867 */ 2868 if (dumpsize == 0) 2869 dumpconf(); 2870 if (dumplo < 0) 2871 return; 2872 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo); 2873 2874 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); 2875 printf("dump "); 2876 if (error == -1) { 2877 printf("area unavailable\n"); 2878 return; 2879 } 2880 2881 #if 0 /* XXX this doesn't work. grr. */ 2882 /* toss any characters present prior to dump */ 2883 while (sget() != NULL); /*syscons and pccons differ */ 2884 #endif 2885 2886 /* scan through the dumpmem list */ 2887 dump = bdevsw[major(dumpdev)].d_dump; 2888 error = cpu_dump(); 2889 for (i = 0; !error && i < ndumpmem; i++) { 2890 2891 npg = dumpmem[i].end - dumpmem[i].start; 2892 maddr = ptoa(dumpmem[i].start); 2893 blkno = dumplo + btodb(maddr) + 1; 2894 #if 0 2895 printf("(%d %lld %d) ", maddr, (long long)blkno, npg); 2896 #endif 2897 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) { 2898 2899 /* Print out how many MBs we have more to go. */ 2900 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG) 2901 printf("%ld ", 2902 (ptoa(dumpsize) - maddr) / (1024 * 1024)); 2903 #if 0 2904 printf("(%x %lld) ", maddr, (long long)blkno); 2905 #endif 2906 pmap_enter(pmap_kernel(), dumpspace, maddr, 2907 PROT_READ, PMAP_WIRED); 2908 if ((error = (*dump)(dumpdev, blkno, 2909 (caddr_t)dumpspace, NBPG))) 2910 break; 2911 2912 #if 0 /* XXX this doesn't work. grr. */ 2913 /* operator aborting dump? */ 2914 if (sget() != NULL) { 2915 error = EINTR; 2916 break; 2917 } 2918 #endif 2919 } 2920 } 2921 2922 switch (error) { 2923 2924 case 0: str = "succeeded\n\n"; break; 2925 case ENXIO: str = "device bad\n\n"; break; 2926 case EFAULT: str = "device not ready\n\n"; break; 2927 case EINVAL: str = "area improper\n\n"; break; 2928 case EIO: str = "i/o error\n\n"; break; 2929 case EINTR: str = "aborted from console\n\n"; break; 2930 default: str = "error %d\n\n"; break; 2931 } 2932 printf(str, error); 2933 2934 delay(5000000); /* 5 seconds */ 2935 } 2936 2937 /* 2938 * Clear registers on exec 2939 */ 2940 void 2941 setregs(struct proc *p, struct exec_package *pack, u_long stack, 2942 register_t *retval) 2943 { 2944 struct pcb *pcb = &p->p_addr->u_pcb; 2945 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map); 2946 struct trapframe *tf = p->p_md.md_regs; 2947 2948 #if NNPX > 0 2949 /* If we were using the FPU, forget about it. */ 2950 if (pcb->pcb_fpcpu != NULL) 2951 npxsave_proc(p, 0); 2952 p->p_md.md_flags &= ~MDP_USEDFPU; 2953 #endif 2954 2955 /* 2956 * Reset the code segment limit to I386_MAX_EXE_ADDR in the pmap; 2957 * this gets copied into the GDT for GUCODE_SEL by pmap_activate(). 2958 * Similarly, reset the base of each of the two thread data 2959 * segments to zero in the pcb; they'll get copied into the 2960 * GDT for GUFS_SEL and GUGS_SEL. 2961 */ 2962 setsegment(&pmap->pm_codeseg, 0, atop(I386_MAX_EXE_ADDR) - 1, 2963 SDT_MEMERA, SEL_UPL, 1, 1); 2964 setsegment(&pcb->pcb_threadsegs[TSEG_FS], 0, 2965 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2966 setsegment(&pcb->pcb_threadsegs[TSEG_GS], 0, 2967 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2968 2969 /* 2970 * And update the GDT since we return to the user process 2971 * by leaving the syscall (we don't do another pmap_activate()). 2972 */ 2973 curcpu()->ci_gdt[GUCODE_SEL].sd = pmap->pm_codeseg; 2974 curcpu()->ci_gdt[GUFS_SEL].sd = pcb->pcb_threadsegs[TSEG_FS]; 2975 curcpu()->ci_gdt[GUGS_SEL].sd = pcb->pcb_threadsegs[TSEG_GS]; 2976 2977 /* 2978 * And reset the hiexec marker in the pmap. 2979 */ 2980 pmap->pm_hiexec = 0; 2981 2982 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2983 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2984 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2985 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2986 tf->tf_edi = 0; 2987 tf->tf_esi = 0; 2988 tf->tf_ebp = 0; 2989 tf->tf_ebx = (int)p->p_p->ps_strings; 2990 tf->tf_edx = 0; 2991 tf->tf_ecx = 0; 2992 tf->tf_eax = 0; 2993 tf->tf_eip = pack->ep_entry; 2994 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2995 tf->tf_eflags = PSL_USERSET; 2996 tf->tf_esp = stack; 2997 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2998 2999 retval[1] = 0; 3000 } 3001 3002 /* 3003 * Initialize segments and descriptor tables 3004 */ 3005 3006 /* IDT is now a full page, so we can map it in u-k */ 3007 union { 3008 struct gate_descriptor idt[NIDT]; 3009 char align[PAGE_SIZE]; 3010 } _idt_region __aligned(PAGE_SIZE); 3011 #define idt_region _idt_region.idt 3012 struct gate_descriptor *idt = idt_region; 3013 3014 extern struct user *proc0paddr; 3015 3016 void 3017 setgate(struct gate_descriptor *gd, void *func, int args, int type, int dpl, 3018 int seg) 3019 { 3020 3021 gd->gd_looffset = (int)func; 3022 gd->gd_selector = GSEL(seg, SEL_KPL); 3023 gd->gd_stkcpy = args; 3024 gd->gd_xx = 0; 3025 gd->gd_type = type; 3026 gd->gd_dpl = dpl; 3027 gd->gd_p = 1; 3028 gd->gd_hioffset = (int)func >> 16; 3029 } 3030 3031 void 3032 unsetgate(struct gate_descriptor *gd) 3033 { 3034 gd->gd_p = 0; 3035 gd->gd_hioffset = 0; 3036 gd->gd_looffset = 0; 3037 gd->gd_selector = 0; 3038 gd->gd_xx = 0; 3039 gd->gd_stkcpy = 0; 3040 gd->gd_type = 0; 3041 gd->gd_dpl = 0; 3042 } 3043 3044 void 3045 setregion(struct region_descriptor *rd, void *base, size_t limit) 3046 { 3047 rd->rd_limit = (int)limit; 3048 rd->rd_base = (int)base; 3049 } 3050 3051 void 3052 setsegment(struct segment_descriptor *sd, void *base, size_t limit, int type, 3053 int dpl, int def32, int gran) 3054 { 3055 3056 sd->sd_lolimit = (int)limit; 3057 sd->sd_lobase = (int)base; 3058 sd->sd_type = type; 3059 sd->sd_dpl = dpl; 3060 sd->sd_p = 1; 3061 sd->sd_hilimit = (int)limit >> 16; 3062 sd->sd_xx = 0; 3063 sd->sd_def32 = def32; 3064 sd->sd_gran = gran; 3065 sd->sd_hibase = (int)base >> 24; 3066 } 3067 3068 #define IDTVEC(name) __CONCAT(X, name) 3069 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 3070 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm), 3071 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page), 3072 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall), IDTVEC(mchk), 3073 IDTVEC(simd); 3074 3075 extern int IDTVEC(f00f_redirect); 3076 3077 int cpu_f00f_bug = 0; 3078 3079 void 3080 fix_f00f(void) 3081 { 3082 struct region_descriptor region; 3083 vaddr_t va; 3084 paddr_t pa; 3085 void *p; 3086 3087 /* Allocate two new pages */ 3088 va = uvm_km_zalloc(kernel_map, NBPG*2); 3089 p = (void *)(va + NBPG - 7*sizeof(*idt)); 3090 3091 /* Copy over old IDT */ 3092 bcopy(idt, p, sizeof(idt_region)); 3093 idt = p; 3094 3095 /* Fix up paging redirect */ 3096 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386IGT, SEL_KPL, 3097 GCODE_SEL); 3098 3099 /* Map first page RO */ 3100 pmap_pte_setbits(va, 0, PG_RW); 3101 3102 /* add k-u read-only mappings XXX old IDT stays in place */ 3103 /* XXX hshoexer: are f00f affected CPUs affected by meltdown? */ 3104 pmap_extract(pmap_kernel(), va, &pa); 3105 pmap_enter_special(va, pa, PROT_READ, 0); 3106 pmap_extract(pmap_kernel(), va + PAGE_SIZE, &pa); 3107 pmap_enter_special(va + PAGE_SIZE, pa, PROT_READ, 0); 3108 3109 /* Reload idtr */ 3110 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3111 lidt(®ion); 3112 3113 /* Tell the rest of the world */ 3114 cpu_f00f_bug = 1; 3115 } 3116 3117 #ifdef MULTIPROCESSOR 3118 void 3119 cpu_init_idt(void) 3120 { 3121 struct region_descriptor region; 3122 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3123 lidt(®ion); 3124 } 3125 #endif /* MULTIPROCESSOR */ 3126 3127 void 3128 init386(paddr_t first_avail) 3129 { 3130 int i, kb; 3131 struct region_descriptor region; 3132 bios_memmap_t *im; 3133 3134 proc0.p_addr = proc0paddr; 3135 cpu_info_primary.ci_self = &cpu_info_primary; 3136 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb; 3137 cpu_info_primary.ci_tss = &cpu_info_full_primary.cif_tss; 3138 cpu_info_primary.ci_nmi_tss = &cpu_info_full_primary.cif_nmi_tss; 3139 cpu_info_primary.ci_gdt = (void *)&cpu_info_full_primary.cif_gdt; 3140 3141 /* make bootstrap gdt gates and memory segments */ 3142 setsegment(&cpu_info_primary.ci_gdt[GCODE_SEL].sd, 0, 0xfffff, 3143 SDT_MEMERA, SEL_KPL, 1, 1); 3144 setsegment(&cpu_info_primary.ci_gdt[GICODE_SEL].sd, 0, 0xfffff, 3145 SDT_MEMERA, SEL_KPL, 1, 1); 3146 setsegment(&cpu_info_primary.ci_gdt[GDATA_SEL].sd, 0, 0xfffff, 3147 SDT_MEMRWA, SEL_KPL, 1, 1); 3148 setsegment(&cpu_info_primary.ci_gdt[GUCODE_SEL].sd, 0, 3149 atop(I386_MAX_EXE_ADDR) - 1, SDT_MEMERA, SEL_UPL, 1, 1); 3150 setsegment(&cpu_info_primary.ci_gdt[GUDATA_SEL].sd, 0, 3151 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3152 setsegment(&cpu_info_primary.ci_gdt[GCPU_SEL].sd, &cpu_info_primary, 3153 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 0, 0); 3154 setsegment(&cpu_info_primary.ci_gdt[GUFS_SEL].sd, 0, 3155 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3156 setsegment(&cpu_info_primary.ci_gdt[GUGS_SEL].sd, 0, 3157 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3158 setsegment(&cpu_info_primary.ci_gdt[GTSS_SEL].sd, 3159 cpu_info_primary.ci_tss, sizeof(struct i386tss)-1, 3160 SDT_SYS386TSS, SEL_KPL, 0, 0); 3161 setsegment(&cpu_info_primary.ci_gdt[GNMITSS_SEL].sd, 3162 cpu_info_primary.ci_nmi_tss, sizeof(struct i386tss)-1, 3163 SDT_SYS386TSS, SEL_KPL, 0, 0); 3164 3165 /* exceptions */ 3166 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3167 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3168 setgate(&idt[ 2], NULL, 0, SDT_SYSTASKGT, SEL_KPL, GNMITSS_SEL); 3169 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3170 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3171 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3172 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3173 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3174 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3175 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3176 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3177 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3178 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3179 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3180 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3181 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3182 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3183 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3184 setgate(&idt[ 18], &IDTVEC(mchk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3185 setgate(&idt[ 19], &IDTVEC(simd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3186 for (i = 20; i < NRSVIDT; i++) 3187 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3188 for (i = NRSVIDT; i < NIDT; i++) 3189 unsetgate(&idt[i]); 3190 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3191 3192 setregion(®ion, cpu_info_primary.ci_gdt, GDT_SIZE - 1); 3193 lgdt(®ion); 3194 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3195 lidt(®ion); 3196 3197 /* 3198 * Initialize the I/O port and I/O mem extent maps. 3199 * Note: we don't have to check the return value since 3200 * creation of a fixed extent map will never fail (since 3201 * descriptor storage has already been allocated). 3202 * 3203 * N.B. The iomem extent manages _all_ physical addresses 3204 * on the machine. When the amount of RAM is found, the two 3205 * extents of RAM are allocated from the map (0 -> ISA hole 3206 * and end of ISA hole -> end of RAM). 3207 */ 3208 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF, 3209 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage), 3210 EX_NOCOALESCE|EX_NOWAIT); 3211 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF, 3212 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage), 3213 EX_NOCOALESCE|EX_NOWAIT); 3214 3215 #if NISA > 0 3216 isa_defaultirq(); 3217 #endif 3218 3219 /* 3220 * Attach the glass console early in case we need to display a panic. 3221 */ 3222 cninit(); 3223 3224 /* 3225 * Saving SSE registers won't work if the save area isn't 3226 * 16-byte aligned. 3227 */ 3228 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf) 3229 panic("init386: pcb_savefpu not 16-byte aligned"); 3230 3231 /* call pmap initialization to make new kernel address space */ 3232 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE); 3233 3234 /* 3235 * Boot arguments are in a single page specified by /boot. 3236 * 3237 * We require the "new" vector form, as well as memory ranges 3238 * to be given in bytes rather than KB. 3239 */ 3240 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) == 3241 (BAPIV_VECTOR | BAPIV_BMEMMAP)) { 3242 if (bootargc > NBPG) 3243 panic("too many boot args"); 3244 3245 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc, 3246 EX_NOWAIT)) 3247 panic("cannot reserve /boot args memory"); 3248 3249 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv, 3250 PROT_READ | PROT_WRITE, 3251 PROT_READ | PROT_WRITE | PMAP_WIRED); 3252 3253 bios_getopt(); 3254 3255 } else 3256 panic("/boot too old: upgrade!"); 3257 3258 #ifdef DIAGNOSTIC 3259 if (bios_memmap == NULL) 3260 panic("no BIOS memory map supplied"); 3261 #endif 3262 3263 /* 3264 * account all the memory passed in the map from /boot 3265 * calculate avail_end and count the physmem. 3266 */ 3267 avail_end = 0; 3268 physmem = 0; 3269 #ifdef DEBUG 3270 printf("memmap:"); 3271 #endif 3272 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++) 3273 if (im->type == BIOS_MAP_FREE) { 3274 paddr_t a, e; 3275 #ifdef DEBUG 3276 printf(" %llx-%llx", im->addr, im->addr + im->size); 3277 #endif 3278 3279 if (im->addr >= 0x100000000ULL) { 3280 #ifdef DEBUG 3281 printf("-H"); 3282 #endif 3283 continue; 3284 } 3285 3286 a = round_page(im->addr); 3287 if (im->addr + im->size <= 0xfffff000ULL) 3288 e = trunc_page(im->addr + im->size); 3289 else { 3290 #ifdef DEBUG 3291 printf("-T"); 3292 #endif 3293 e = 0xfffff000; 3294 } 3295 3296 /* skip first 16 pages due to SMI corruption */ 3297 if (a < 16 * NBPG) 3298 a = 16 * NBPG; 3299 3300 #ifdef MULTIPROCESSOR 3301 /* skip MP trampoline code page */ 3302 if (a < MP_TRAMPOLINE + NBPG) 3303 a = MP_TRAMPOLINE + NBPG; 3304 3305 /* skip MP trampoline data page */ 3306 if (a < MP_TRAMP_DATA + NBPG) 3307 a = MP_TRAMP_DATA + NBPG; 3308 #endif /* MULTIPROCESSOR */ 3309 3310 #if NACPI > 0 && !defined(SMALL_KERNEL) 3311 /* skip ACPI resume trampoline code page */ 3312 if (a < ACPI_TRAMPOLINE + NBPG) 3313 a = ACPI_TRAMPOLINE + NBPG; 3314 3315 /* skip ACPI resume trampoline data page */ 3316 if (a < ACPI_TRAMP_DATA + NBPG) 3317 a = ACPI_TRAMP_DATA + NBPG; 3318 #endif /* ACPI */ 3319 3320 #ifdef HIBERNATE 3321 /* skip hibernate reserved pages */ 3322 if (a < HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE) 3323 a = HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE; 3324 #endif /* HIBERNATE */ 3325 3326 /* skip shorter than page regions */ 3327 if (a >= e || (e - a) < NBPG) { 3328 #ifdef DEBUG 3329 printf("-S"); 3330 #endif 3331 continue; 3332 } 3333 3334 /* 3335 * XXX Some buggy ACPI BIOSes use memory that 3336 * they declare as free. Typically the 3337 * affected memory areas are small blocks 3338 * between areas reserved for ACPI and other 3339 * BIOS goo. So skip areas smaller than 1 MB 3340 * above the 16 MB boundary (to avoid 3341 * affecting legacy stuff). 3342 */ 3343 if (a > 16*1024*1024 && (e - a) < 1*1024*1024) { 3344 #ifdef DEBUG 3345 printf("-X"); 3346 #endif 3347 continue; 3348 } 3349 3350 /* skip legacy IO region */ 3351 if ((a > IOM_BEGIN && a < IOM_END) || 3352 (e > IOM_BEGIN && e < IOM_END)) { 3353 #ifdef DEBUG 3354 printf("-I"); 3355 #endif 3356 continue; 3357 } 3358 3359 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT)) 3360 /* XXX What should we do? */ 3361 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)" 3362 " FROM IOMEM EXTENT MAP!\n", a, e); 3363 3364 physmem += atop(e - a); 3365 dumpmem[i].start = atop(a); 3366 dumpmem[i].end = atop(e); 3367 i++; 3368 avail_end = max(avail_end, e); 3369 } 3370 3371 ndumpmem = i; 3372 avail_end -= round_page(MSGBUFSIZE); 3373 3374 #ifdef DEBUG 3375 printf(": %lx\n", avail_end); 3376 #endif 3377 if (physmem < atop(4 * 1024 * 1024)) { 3378 printf("\awarning: too little memory available;" 3379 "running in degraded mode\npress a key to confirm\n\n"); 3380 cnpollc(1); 3381 cngetc(); 3382 cnpollc(0); 3383 } 3384 3385 #ifdef DEBUG 3386 printf("physload: "); 3387 #endif 3388 kb = atop(KERNTEXTOFF - KERNBASE); 3389 if (kb > atop(IOM_END)) { 3390 paddr_t lim = atop(IOM_END); 3391 #ifdef DEBUG 3392 printf(" %lx-%x (<16M)", lim, kb); 3393 #endif 3394 uvm_page_physload(lim, kb, lim, kb, 0); 3395 } 3396 3397 for (i = 0; i < ndumpmem; i++) { 3398 paddr_t a, e; 3399 3400 a = dumpmem[i].start; 3401 e = dumpmem[i].end; 3402 if (a < atop(first_avail) && e > atop(first_avail)) 3403 a = atop(first_avail); 3404 if (e > atop(avail_end)) 3405 e = atop(avail_end); 3406 3407 if (a < e) { 3408 #ifdef DEBUG 3409 printf(" %lx-%lx", a, e); 3410 #endif 3411 uvm_page_physload(a, e, a, e, 0); 3412 } 3413 } 3414 #ifdef DEBUG 3415 printf("\n"); 3416 #endif 3417 3418 tlbflush(); 3419 #if 0 3420 #if NISADMA > 0 3421 /* 3422 * Some motherboards/BIOSes remap the 384K of RAM that would 3423 * normally be covered by the ISA hole to the end of memory 3424 * so that it can be used. However, on a 16M system, this 3425 * would cause bounce buffers to be allocated and used. 3426 * This is not desirable behaviour, as more than 384K of 3427 * bounce buffers might be allocated. As a work-around, 3428 * we round memory down to the nearest 1M boundary if 3429 * we're using any isadma devices and the remapped memory 3430 * is what puts us over 16M. 3431 */ 3432 if (extmem > (15*1024) && extmem < (16*1024)) { 3433 printf("Warning: ignoring %dk of remapped memory\n", 3434 extmem - (15*1024)); 3435 extmem = (15*1024); 3436 } 3437 #endif 3438 #endif 3439 3440 #ifdef DDB 3441 db_machine_init(); 3442 ddb_init(); 3443 if (boothowto & RB_KDB) 3444 db_enter(); 3445 #endif 3446 3447 softintr_init(); 3448 } 3449 3450 /* 3451 * consinit: 3452 * initialize the system console. 3453 */ 3454 void 3455 consinit(void) 3456 { 3457 /* Already done in init386(). */ 3458 } 3459 3460 void 3461 cpu_reset(void) 3462 { 3463 struct region_descriptor region; 3464 3465 intr_disable(); 3466 3467 if (cpuresetfn) 3468 (*cpuresetfn)(); 3469 3470 /* 3471 * The keyboard controller has 4 random output pins, one of which is 3472 * connected to the RESET pin on the CPU in many PCs. We tell the 3473 * keyboard controller to pulse this line a couple of times. 3474 */ 3475 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3476 delay(100000); 3477 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3478 delay(100000); 3479 3480 /* 3481 * Try to cause a triple fault and watchdog reset by setting the 3482 * IDT to point to nothing. 3483 */ 3484 bzero((caddr_t)idt, sizeof(idt_region)); 3485 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3486 lidt(®ion); 3487 __asm volatile("divl %0,%1" : : "q" (0), "a" (0)); 3488 3489 /* 3490 * Try to cause a triple fault and watchdog reset by unmapping the 3491 * entire address space. 3492 */ 3493 bzero((caddr_t)PTD, NBPG); 3494 tlbflush(); 3495 3496 for (;;) 3497 continue; 3498 /* NOTREACHED */ 3499 } 3500 3501 void 3502 cpu_initclocks(void) 3503 { 3504 (*initclock_func)(); /* lapic or i8254 */ 3505 } 3506 3507 void 3508 need_resched(struct cpu_info *ci) 3509 { 3510 ci->ci_want_resched = 1; 3511 3512 /* There's a risk we'll be called before the idle threads start */ 3513 if (ci->ci_curproc) { 3514 aston(ci->ci_curproc); 3515 cpu_kick(ci); 3516 } 3517 } 3518 3519 /* Allocate an IDT vector slot within the given range. 3520 * XXX needs locking to avoid MP allocation races. 3521 */ 3522 3523 int 3524 idt_vec_alloc(int low, int high) 3525 { 3526 int vec; 3527 3528 for (vec = low; vec <= high; vec++) 3529 if (idt[vec].gd_p == 0) 3530 return (vec); 3531 return (0); 3532 } 3533 3534 void 3535 idt_vec_set(int vec, void (*function)(void)) 3536 { 3537 setgate(&idt[vec], function, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL); 3538 } 3539 3540 void 3541 idt_vec_free(int vec) 3542 { 3543 unsetgate(&idt[vec]); 3544 } 3545 3546 /* 3547 * machine dependent system variables. 3548 */ 3549 int 3550 cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 3551 size_t newlen, struct proc *p) 3552 { 3553 dev_t dev; 3554 int val, error; 3555 3556 switch (name[0]) { 3557 case CPU_CONSDEV: 3558 if (namelen != 1) 3559 return (ENOTDIR); /* overloaded */ 3560 3561 if (cn_tab != NULL) 3562 dev = cn_tab->cn_dev; 3563 else 3564 dev = NODEV; 3565 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3566 #if NBIOS > 0 3567 case CPU_BIOS: 3568 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp, 3569 newp, newlen, p); 3570 #endif 3571 case CPU_BLK2CHR: 3572 if (namelen != 2) 3573 return (ENOTDIR); /* overloaded */ 3574 dev = blktochr((dev_t)name[1]); 3575 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3576 case CPU_CHR2BLK: 3577 if (namelen != 2) 3578 return (ENOTDIR); /* overloaded */ 3579 dev = chrtoblk((dev_t)name[1]); 3580 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3581 case CPU_ALLOWAPERTURE: 3582 #ifdef APERTURE 3583 if (securelevel > 0) 3584 return (sysctl_int_lower(oldp, oldlenp, newp, newlen, 3585 &allowaperture)); 3586 else 3587 return (sysctl_int(oldp, oldlenp, newp, newlen, 3588 &allowaperture)); 3589 #else 3590 return (sysctl_rdint(oldp, oldlenp, newp, 0)); 3591 #endif 3592 case CPU_CPUVENDOR: 3593 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor)); 3594 case CPU_CPUID: 3595 return (sysctl_rdint(oldp, oldlenp, newp, cpu_id)); 3596 case CPU_CPUFEATURE: 3597 return (sysctl_rdint(oldp, oldlenp, newp, curcpu()->ci_feature_flags)); 3598 case CPU_KBDRESET: 3599 if (securelevel > 0) 3600 return (sysctl_rdint(oldp, oldlenp, newp, 3601 kbd_reset)); 3602 else 3603 return (sysctl_int(oldp, oldlenp, newp, newlen, 3604 &kbd_reset)); 3605 case CPU_OSFXSR: 3606 return (sysctl_rdint(oldp, oldlenp, newp, i386_use_fxsave)); 3607 case CPU_SSE: 3608 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse)); 3609 case CPU_SSE2: 3610 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse2)); 3611 case CPU_XCRYPT: 3612 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_xcrypt)); 3613 case CPU_LIDACTION: 3614 val = lid_action; 3615 error = sysctl_int(oldp, oldlenp, newp, newlen, &val); 3616 if (!error) { 3617 if (val < 0 || val > 2) 3618 error = EINVAL; 3619 else 3620 lid_action = val; 3621 } 3622 return (error); 3623 #if NPCKBC > 0 && NUKBD > 0 3624 case CPU_FORCEUKBD: 3625 if (forceukbd) 3626 return (sysctl_rdint(oldp, oldlenp, newp, forceukbd)); 3627 3628 error = sysctl_int(oldp, oldlenp, newp, newlen, &forceukbd); 3629 if (forceukbd) 3630 pckbc_release_console(); 3631 return (error); 3632 #endif 3633 default: 3634 return (EOPNOTSUPP); 3635 } 3636 /* NOTREACHED */ 3637 } 3638 3639 int 3640 bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, 3641 bus_space_handle_t *bshp) 3642 { 3643 int error; 3644 struct extent *ex; 3645 3646 /* 3647 * Pick the appropriate extent map. 3648 */ 3649 if (t == I386_BUS_SPACE_IO) { 3650 ex = ioport_ex; 3651 if (flags & BUS_SPACE_MAP_LINEAR) 3652 return (EINVAL); 3653 } else if (t == I386_BUS_SPACE_MEM) { 3654 ex = iomem_ex; 3655 } else { 3656 panic("bus_space_map: bad bus space tag"); 3657 } 3658 3659 /* 3660 * Before we go any further, let's make sure that this 3661 * region is available. 3662 */ 3663 error = extent_alloc_region(ex, bpa, size, 3664 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0)); 3665 if (error) 3666 return (error); 3667 3668 /* 3669 * For I/O space, that's all she wrote. 3670 */ 3671 if (t == I386_BUS_SPACE_IO) { 3672 *bshp = bpa; 3673 return (0); 3674 } 3675 3676 if (IOM_BEGIN <= bpa && bpa <= IOM_END) { 3677 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa); 3678 return (0); 3679 } 3680 3681 /* 3682 * For memory space, map the bus physical address to 3683 * a kernel virtual address. 3684 */ 3685 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3686 if (error) { 3687 if (extent_free(ex, bpa, size, EX_NOWAIT | 3688 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3689 printf("bus_space_map: pa 0x%lx, size 0x%lx\n", 3690 bpa, size); 3691 printf("bus_space_map: can't free region\n"); 3692 } 3693 } 3694 3695 return (error); 3696 } 3697 3698 int 3699 _bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, 3700 int flags, bus_space_handle_t *bshp) 3701 { 3702 /* 3703 * For I/O space, that's all she wrote. 3704 */ 3705 if (t == I386_BUS_SPACE_IO) { 3706 *bshp = bpa; 3707 return (0); 3708 } 3709 3710 /* 3711 * For memory space, map the bus physical address to 3712 * a kernel virtual address. 3713 */ 3714 return (bus_mem_add_mapping(bpa, size, flags, bshp)); 3715 } 3716 3717 int 3718 bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, 3719 bus_size_t size, bus_size_t alignment, bus_size_t boundary, 3720 int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) 3721 { 3722 struct extent *ex; 3723 u_long bpa; 3724 int error; 3725 3726 /* 3727 * Pick the appropriate extent map. 3728 */ 3729 if (t == I386_BUS_SPACE_IO) { 3730 ex = ioport_ex; 3731 } else if (t == I386_BUS_SPACE_MEM) { 3732 ex = iomem_ex; 3733 } else { 3734 panic("bus_space_alloc: bad bus space tag"); 3735 } 3736 3737 /* 3738 * Sanity check the allocation against the extent's boundaries. 3739 */ 3740 if (rstart < ex->ex_start || rend > ex->ex_end) 3741 panic("bus_space_alloc: bad region start/end"); 3742 3743 /* 3744 * Do the requested allocation. 3745 */ 3746 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0, 3747 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0), 3748 &bpa); 3749 3750 if (error) 3751 return (error); 3752 3753 /* 3754 * For I/O space, that's all she wrote. 3755 */ 3756 if (t == I386_BUS_SPACE_IO) { 3757 *bshp = *bpap = bpa; 3758 return (0); 3759 } 3760 3761 /* 3762 * For memory space, map the bus physical address to 3763 * a kernel virtual address. 3764 */ 3765 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3766 if (error) { 3767 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT | 3768 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3769 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n", 3770 bpa, size); 3771 printf("bus_space_alloc: can't free region\n"); 3772 } 3773 } 3774 3775 *bpap = bpa; 3776 3777 return (error); 3778 } 3779 3780 int 3781 bus_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int flags, 3782 bus_space_handle_t *bshp) 3783 { 3784 paddr_t pa, endpa; 3785 vaddr_t va; 3786 bus_size_t map_size; 3787 int pmap_flags = PMAP_NOCACHE; 3788 3789 pa = trunc_page(bpa); 3790 endpa = round_page(bpa + size); 3791 3792 #ifdef DIAGNOSTIC 3793 if (endpa <= pa && endpa != 0) 3794 panic("bus_mem_add_mapping: overflow"); 3795 #endif 3796 3797 map_size = endpa - pa; 3798 3799 va = (vaddr_t)km_alloc(map_size, &kv_any, &kp_none, &kd_nowait); 3800 if (va == 0) 3801 return (ENOMEM); 3802 3803 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 3804 3805 if (flags & BUS_SPACE_MAP_CACHEABLE) 3806 pmap_flags = 0; 3807 else if (flags & BUS_SPACE_MAP_PREFETCHABLE) 3808 pmap_flags = PMAP_WC; 3809 3810 for (; map_size > 0; 3811 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE) 3812 pmap_kenter_pa(va, pa | pmap_flags, 3813 PROT_READ | PROT_WRITE); 3814 pmap_update(pmap_kernel()); 3815 3816 return 0; 3817 } 3818 3819 void 3820 bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3821 { 3822 struct extent *ex; 3823 u_long va, endva; 3824 bus_addr_t bpa; 3825 3826 /* 3827 * Find the correct extent and bus physical address. 3828 */ 3829 if (t == I386_BUS_SPACE_IO) { 3830 ex = ioport_ex; 3831 bpa = bsh; 3832 } else if (t == I386_BUS_SPACE_MEM) { 3833 ex = iomem_ex; 3834 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3835 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3836 goto ok; 3837 3838 va = trunc_page(bsh); 3839 endva = round_page(bsh + size); 3840 3841 #ifdef DIAGNOSTIC 3842 if (endva <= va) 3843 panic("bus_space_unmap: overflow"); 3844 #endif 3845 3846 (void) pmap_extract(pmap_kernel(), va, &bpa); 3847 bpa += (bsh & PGOFSET); 3848 3849 pmap_kremove(va, endva - va); 3850 pmap_update(pmap_kernel()); 3851 3852 /* 3853 * Free the kernel virtual mapping. 3854 */ 3855 km_free((void *)va, endva - va, &kv_any, &kp_none); 3856 } else 3857 panic("bus_space_unmap: bad bus space tag"); 3858 3859 ok: 3860 if (extent_free(ex, bpa, size, 3861 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3862 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n", 3863 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size); 3864 printf("bus_space_unmap: can't free region\n"); 3865 } 3866 } 3867 3868 void 3869 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size, 3870 bus_addr_t *adrp) 3871 { 3872 u_long va, endva; 3873 bus_addr_t bpa; 3874 3875 /* 3876 * Find the correct bus physical address. 3877 */ 3878 if (t == I386_BUS_SPACE_IO) { 3879 bpa = bsh; 3880 } else if (t == I386_BUS_SPACE_MEM) { 3881 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3882 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3883 goto ok; 3884 3885 va = trunc_page(bsh); 3886 endva = round_page(bsh + size); 3887 3888 #ifdef DIAGNOSTIC 3889 if (endva <= va) 3890 panic("_bus_space_unmap: overflow"); 3891 #endif 3892 3893 (void) pmap_extract(pmap_kernel(), va, &bpa); 3894 bpa += (bsh & PGOFSET); 3895 3896 pmap_kremove(va, endva - va); 3897 pmap_update(pmap_kernel()); 3898 3899 /* 3900 * Free the kernel virtual mapping. 3901 */ 3902 km_free((void *)va, endva - va, &kv_any, &kp_none); 3903 } else 3904 panic("bus_space_unmap: bad bus space tag"); 3905 3906 ok: 3907 if (adrp != NULL) 3908 *adrp = bpa; 3909 } 3910 3911 void 3912 bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3913 { 3914 3915 /* bus_space_unmap() does all that we need to do. */ 3916 bus_space_unmap(t, bsh, size); 3917 } 3918 3919 int 3920 bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 3921 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 3922 { 3923 *nbshp = bsh + offset; 3924 return (0); 3925 } 3926 3927 paddr_t 3928 bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags) 3929 { 3930 /* Can't mmap I/O space. */ 3931 if (t == I386_BUS_SPACE_IO) 3932 return (-1); 3933 3934 return (addr + off); 3935 } 3936 3937 #ifdef DIAGNOSTIC 3938 void 3939 splassert_check(int wantipl, const char *func) 3940 { 3941 if (lapic_tpr < wantipl) 3942 splassert_fail(wantipl, lapic_tpr, func); 3943 if (wantipl == IPL_NONE && curcpu()->ci_idepth != 0) 3944 splassert_fail(-1, curcpu()->ci_idepth, func); 3945 } 3946 #endif 3947 3948 int 3949 copyin32(const uint32_t *uaddr, uint32_t *kaddr) 3950 { 3951 if ((vaddr_t)uaddr & 0x3) 3952 return EFAULT; 3953 3954 /* copyin(9) is atomic */ 3955 return copyin(uaddr, kaddr, sizeof(uint32_t)); 3956 } 3957 3958 /* 3959 * True if the system has any non-level interrupts which are shared 3960 * on the same pin. 3961 */ 3962 int intr_shared_edge; 3963 3964 /* 3965 * Software interrupt registration 3966 * 3967 * We hand-code this to ensure that it's atomic. 3968 */ 3969 void 3970 softintr(int sir) 3971 { 3972 struct cpu_info *ci = curcpu(); 3973 3974 __asm volatile("orl %1, %0" : 3975 "=m" (ci->ci_ipending) : "ir" (1 << sir)); 3976 } 3977 3978 /* 3979 * Raise current interrupt priority level, and return the old one. 3980 */ 3981 int 3982 splraise(int ncpl) 3983 { 3984 int ocpl; 3985 3986 _SPLRAISE(ocpl, ncpl); 3987 return (ocpl); 3988 } 3989 3990 /* 3991 * Restore an old interrupt priority level. If any thereby unmasked 3992 * interrupts are pending, call Xspllower() to process them. 3993 */ 3994 void 3995 splx(int ncpl) 3996 { 3997 _SPLX(ncpl); 3998 } 3999 4000 /* 4001 * Same as splx(), but we return the old value of spl, for the 4002 * benefit of some splsoftclock() callers. 4003 */ 4004 int 4005 spllower(int ncpl) 4006 { 4007 int ocpl = lapic_tpr; 4008 4009 splx(ncpl); 4010 return (ocpl); 4011 } 4012 4013 int 4014 intr_handler(struct intrframe *frame, struct intrhand *ih) 4015 { 4016 int rc; 4017 #ifdef MULTIPROCESSOR 4018 int need_lock; 4019 4020 if (ih->ih_flags & IPL_MPSAFE) 4021 need_lock = 0; 4022 else 4023 need_lock = 1; 4024 4025 if (need_lock) 4026 __mp_lock(&kernel_lock); 4027 #endif 4028 rc = (*ih->ih_fun)(ih->ih_arg ? ih->ih_arg : frame); 4029 #ifdef MULTIPROCESSOR 4030 if (need_lock) 4031 __mp_unlock(&kernel_lock); 4032 #endif 4033 return rc; 4034 } 4035 4036 void 4037 intr_barrier(void *ih) 4038 { 4039 sched_barrier(NULL); 4040 } 4041 4042 unsigned int 4043 cpu_rnd_messybits(void) 4044 { 4045 struct timespec ts; 4046 4047 nanotime(&ts); 4048 return (ts.tv_nsec ^ (ts.tv_sec << 20)); 4049 } 4050