1 /* $OpenBSD: machdep.c,v 1.649 2022/07/07 00:56:46 daniel Exp $ */ 2 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 36 * Copyright (c) 1992 Terrence R. Lambert. 37 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to Berkeley by 41 * William Jolitz. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/signalvar.h> 73 #include <sys/kernel.h> 74 #include <sys/proc.h> 75 #include <sys/user.h> 76 #include <sys/exec.h> 77 #include <sys/buf.h> 78 #include <sys/reboot.h> 79 #include <sys/conf.h> 80 #include <sys/timeout.h> 81 #include <sys/malloc.h> 82 #include <sys/mbuf.h> 83 #include <sys/msgbuf.h> 84 #include <sys/mount.h> 85 #include <sys/vnode.h> 86 #include <sys/device.h> 87 #include <sys/extent.h> 88 #include <sys/sysctl.h> 89 #include <sys/syscallargs.h> 90 #include <sys/core.h> 91 #include <sys/kcore.h> 92 #include <sys/sensors.h> 93 94 #include <dev/cons.h> 95 #include <stand/boot/bootarg.h> 96 97 #include <net/if.h> 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <machine/cpu.h> 103 #include <machine/cpu_full.h> 104 #include <machine/cpufunc.h> 105 #include <machine/cpuvar.h> 106 #include <machine/gdt.h> 107 #include <machine/kcore.h> 108 #include <machine/pio.h> 109 #include <machine/psl.h> 110 #include <machine/reg.h> 111 #include <machine/specialreg.h> 112 #include <machine/biosvar.h> 113 #include <machine/pte.h> 114 #ifdef MULTIPROCESSOR 115 #include <machine/mpbiosvar.h> 116 #endif /* MULTIPROCESSOR */ 117 118 #include <dev/isa/isareg.h> 119 #include <dev/isa/isavar.h> 120 #include <dev/ic/i8042reg.h> 121 #include <dev/ic/mc146818reg.h> 122 #include <i386/isa/isa_machdep.h> 123 #include <i386/isa/nvram.h> 124 125 #include "acpi.h" 126 #if NACPI > 0 127 #include <dev/acpi/acpivar.h> 128 #endif 129 130 #include "apm.h" 131 #if NAPM > 0 132 #include <machine/apmvar.h> 133 #endif 134 135 #ifdef DDB 136 #include <machine/db_machdep.h> 137 #include <ddb/db_access.h> 138 #include <ddb/db_sym.h> 139 #include <ddb/db_extern.h> 140 #endif 141 142 #include "isa.h" 143 #include "isadma.h" 144 #include "npx.h" 145 #if NNPX > 0 146 extern struct proc *npxproc; 147 #endif 148 149 #include "bios.h" 150 #include "com.h" 151 152 #if NCOM > 0 153 #include <sys/termios.h> 154 #include <dev/ic/comreg.h> 155 #include <dev/ic/comvar.h> 156 #endif /* NCOM > 0 */ 157 158 #ifdef HIBERNATE 159 #include <machine/hibernate_var.h> 160 #endif /* HIBERNATE */ 161 162 #include "ukbd.h" 163 #include "pckbc.h" 164 #if NPCKBC > 0 && NUKBD > 0 165 #include <dev/ic/pckbcvar.h> 166 #endif 167 168 /* #define MACHDEP_DEBUG */ 169 170 #ifdef MACHDEP_DEBUG 171 #define DPRINTF(x...) do { printf(x); } while (0) 172 #else 173 #define DPRINTF(x...) 174 #endif /* MACHDEP_DEBUG */ 175 176 void replacesmap(void); 177 int intr_handler(struct intrframe *, struct intrhand *); 178 179 /* the following is used externally (sysctl_hw) */ 180 char machine[] = MACHINE; 181 182 /* 183 * switchto vectors 184 */ 185 void (*cpu_idle_leave_fcn)(void) = NULL; 186 void (*cpu_idle_cycle_fcn)(void) = NULL; 187 void (*cpu_idle_enter_fcn)(void) = NULL; 188 189 190 struct uvm_constraint_range isa_constraint = { 0x0, 0x00ffffffUL }; 191 struct uvm_constraint_range dma_constraint = { 0x0, 0xffffffffUL }; 192 struct uvm_constraint_range *uvm_md_constraints[] = { 193 &isa_constraint, 194 &dma_constraint, 195 NULL 196 }; 197 198 extern int boothowto; 199 int physmem; 200 201 struct dumpmem dumpmem[VM_PHYSSEG_MAX]; 202 u_int ndumpmem; 203 204 /* 205 * These variables are needed by /sbin/savecore 206 */ 207 u_long dumpmag = 0x8fca0101; /* magic number */ 208 int dumpsize = 0; /* pages */ 209 long dumplo = 0; /* blocks */ 210 211 int cpu_class; 212 int i386_fpu_present; 213 int i386_fpu_exception; 214 int i386_fpu_fdivbug; 215 216 int i386_use_fxsave; 217 int i386_has_sse; 218 int i386_has_sse2; 219 int i386_has_xcrypt; 220 221 bootarg_t *bootargp; 222 paddr_t avail_end; 223 224 struct vm_map *exec_map = NULL; 225 struct vm_map *phys_map = NULL; 226 227 #if !defined(SMALL_KERNEL) 228 int p4_model; 229 int p3_early; 230 void (*update_cpuspeed)(void) = NULL; 231 void via_update_sensor(void *args); 232 #endif 233 int kbd_reset; 234 int lid_action = 1; 235 int pwr_action = 1; 236 int forceukbd; 237 238 /* 239 * safepri is a safe priority for sleep to set for a spin-wait 240 * during autoconfiguration or after a panic. 241 */ 242 int safepri = 0; 243 244 #if !defined(SMALL_KERNEL) 245 int bus_clock; 246 #endif 247 void (*setperf_setup)(struct cpu_info *); 248 int setperf_prio = 0; /* for concurrent handlers */ 249 250 void (*cpusensors_setup)(struct cpu_info *); 251 252 void (*delay_func)(int) = i8254_delay; 253 void (*initclock_func)(void) = i8254_initclocks; 254 255 /* 256 * Extent maps to manage I/O and ISA memory hole space. Allocate 257 * storage for 16 regions in each, initially. Later, ioport_malloc_safe 258 * will indicate that it's safe to use malloc() to dynamically allocate 259 * region descriptors. 260 * 261 * N.B. At least two regions are _always_ allocated from the iomem 262 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM). 263 * 264 * The extent maps are not static! Machine-dependent ISA and EISA 265 * routines need access to them for bus address space allocation. 266 */ 267 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 268 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 269 struct extent *ioport_ex; 270 struct extent *iomem_ex; 271 static int ioport_malloc_safe; 272 273 void dumpsys(void); 274 int cpu_dump(void); 275 void init386(paddr_t); 276 void consinit(void); 277 void (*cpuresetfn)(void); 278 279 int bus_mem_add_mapping(bus_addr_t, bus_size_t, 280 int, bus_space_handle_t *); 281 282 #ifdef APERTURE 283 int allowaperture = 0; 284 #endif 285 286 int has_rdrand; 287 int has_rdseed; 288 289 #include "pvbus.h" 290 #if NPVBUS > 0 291 #include <dev/pv/pvvar.h> 292 #endif 293 294 void winchip_cpu_setup(struct cpu_info *); 295 void amd_family5_setperf_setup(struct cpu_info *); 296 void amd_family5_setup(struct cpu_info *); 297 void amd_family6_setperf_setup(struct cpu_info *); 298 void amd_family6_setup(struct cpu_info *); 299 void cyrix3_setperf_setup(struct cpu_info *); 300 void cyrix3_cpu_setup(struct cpu_info *); 301 void cyrix6x86_cpu_setup(struct cpu_info *); 302 void natsem6x86_cpu_setup(struct cpu_info *); 303 void intel586_cpu_setup(struct cpu_info *); 304 void intel686_cpusensors_setup(struct cpu_info *); 305 void intel686_setperf_setup(struct cpu_info *); 306 void intel686_common_cpu_setup(struct cpu_info *); 307 void intel686_cpu_setup(struct cpu_info *); 308 void intel686_p4_cpu_setup(struct cpu_info *); 309 void intelcore_update_sensor(void *); 310 void tm86_cpu_setup(struct cpu_info *); 311 char * intel686_cpu_name(int); 312 char * cyrix3_cpu_name(int, int); 313 char * tm86_cpu_name(int); 314 void cyrix3_get_bus_clock(struct cpu_info *); 315 void p4_get_bus_clock(struct cpu_info *); 316 void p3_get_bus_clock(struct cpu_info *); 317 void p4_update_cpuspeed(void); 318 void p3_update_cpuspeed(void); 319 int pentium_cpuspeed(int *); 320 void enter_shared_special_pages(void); 321 322 static __inline u_char 323 cyrix_read_reg(u_char reg) 324 { 325 outb(0x22, reg); 326 return inb(0x23); 327 } 328 329 static __inline void 330 cyrix_write_reg(u_char reg, u_char data) 331 { 332 outb(0x22, reg); 333 outb(0x23, data); 334 } 335 336 /* 337 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx. 338 * requires caller to provide u_int32_t regs[4] array. 339 */ 340 void 341 cpuid(u_int32_t ax, u_int32_t *regs) 342 { 343 __asm volatile( 344 "cpuid\n\t" 345 "movl %%eax, 0(%2)\n\t" 346 "movl %%ebx, 4(%2)\n\t" 347 "movl %%ecx, 8(%2)\n\t" 348 "movl %%edx, 12(%2)\n\t" 349 :"=a" (ax) 350 :"0" (ax), "S" (regs) 351 :"bx", "cx", "dx"); 352 } 353 354 /* 355 * Machine-dependent startup code 356 */ 357 void 358 cpu_startup(void) 359 { 360 unsigned i; 361 vaddr_t minaddr, maxaddr, va; 362 paddr_t pa; 363 364 /* 365 * Initialize error message buffer (at end of core). 366 * (space reserved in pmap_bootstrap) 367 */ 368 pa = avail_end; 369 va = (vaddr_t)msgbufp; 370 for (i = 0; i < atop(MSGBUFSIZE); i++) { 371 pmap_kenter_pa(va, pa, PROT_READ | PROT_WRITE); 372 va += PAGE_SIZE; 373 pa += PAGE_SIZE; 374 } 375 pmap_update(pmap_kernel()); 376 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); 377 378 printf("%s", version); 379 startclocks(); 380 rtcinit(); 381 382 printf("real mem = %llu (%lluMB)\n", 383 (unsigned long long)ptoa((psize_t)physmem), 384 (unsigned long long)ptoa((psize_t)physmem)/1024U/1024U); 385 386 /* 387 * Allocate a submap for exec arguments. This map effectively 388 * limits the number of processes exec'ing at any time. 389 */ 390 minaddr = vm_map_min(kernel_map); 391 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 392 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 393 394 /* 395 * Allocate a submap for physio 396 */ 397 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 398 VM_PHYS_SIZE, 0, FALSE, NULL); 399 400 printf("avail mem = %llu (%lluMB)\n", 401 (unsigned long long)ptoa((psize_t)uvmexp.free), 402 (unsigned long long)ptoa((psize_t)uvmexp.free)/1024U/1024U); 403 404 /* 405 * Set up buffers, so they can be used to read disk labels. 406 */ 407 bufinit(); 408 409 /* 410 * Configure the system. 411 */ 412 if (boothowto & RB_CONFIG) { 413 #ifdef BOOT_CONFIG 414 user_config(); 415 #else 416 printf("kernel does not support -c; continuing..\n"); 417 #endif 418 } 419 ioport_malloc_safe = 1; 420 421 #ifndef SMALL_KERNEL 422 cpu_ucode_setup(); 423 #endif 424 425 /* enter the IDT and trampoline code in the u-k maps */ 426 enter_shared_special_pages(); 427 428 /* initialize CPU0's TSS and GDT and put them in the u-k maps */ 429 cpu_enter_pages(&cpu_info_full_primary); 430 } 431 432 void 433 enter_shared_special_pages(void) 434 { 435 extern char __kutext_start[], __kutext_end[], __kernel_kutext_phys[]; 436 extern char __kudata_start[], __kudata_end[], __kernel_kudata_phys[]; 437 vaddr_t va; 438 paddr_t pa; 439 440 /* idt */ 441 pmap_extract(pmap_kernel(), (vaddr_t)idt, &pa); 442 pmap_enter_special((vaddr_t)idt, pa, PROT_READ, 0); 443 444 /* .kutext section */ 445 va = (vaddr_t)__kutext_start; 446 pa = (paddr_t)__kernel_kutext_phys; 447 while (va < (vaddr_t)__kutext_end) { 448 pmap_enter_special(va, pa, PROT_READ | PROT_EXEC, 0); 449 DPRINTF("%s: entered kutext page va 0x%08lx pa 0x%08lx\n", 450 __func__, (unsigned long)va, (unsigned long)pa); 451 va += PAGE_SIZE; 452 pa += PAGE_SIZE; 453 } 454 455 /* .kudata section */ 456 va = (vaddr_t)__kudata_start; 457 pa = (paddr_t)__kernel_kudata_phys; 458 while (va < (vaddr_t)__kudata_end) { 459 pmap_enter_special(va, pa, PROT_READ | PROT_WRITE, 0); 460 DPRINTF("%s: entered kudata page va 0x%08lx pa 0x%08lx\n", 461 __func__, (unsigned long)va, (unsigned long)pa); 462 va += PAGE_SIZE; 463 pa += PAGE_SIZE; 464 } 465 } 466 467 /* 468 * Set up proc0's TSS 469 */ 470 void 471 i386_proc0_tss_init(void) 472 { 473 struct pcb *pcb; 474 475 curpcb = pcb = &proc0.p_addr->u_pcb; 476 pcb->pcb_cr0 = rcr0(); 477 pcb->pcb_kstack = (int)proc0.p_addr + USPACE - 16; 478 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_kstack - 1; 479 } 480 481 #ifdef MULTIPROCESSOR 482 void 483 i386_init_pcb_tss(struct cpu_info *ci) 484 { 485 struct pcb *pcb = ci->ci_idle_pcb; 486 487 pcb->pcb_cr0 = rcr0(); 488 } 489 #endif /* MULTIPROCESSOR */ 490 491 /* 492 * Info for CTL_HW 493 */ 494 char cpu_model[120]; 495 496 /* 497 * Note: these are just the ones that may not have a cpuid instruction. 498 * We deal with the rest in a different way. 499 */ 500 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 501 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 502 NULL}, /* CPU_386SX */ 503 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 504 NULL}, /* CPU_386 */ 505 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 506 NULL}, /* CPU_486SX */ 507 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 508 NULL}, /* CPU_486 */ 509 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 510 NULL}, /* CPU_486DLC */ 511 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 512 cyrix6x86_cpu_setup}, /* CPU_6x86 */ 513 }; 514 515 const char *classnames[] = { 516 "386", 517 "486", 518 "586", 519 "686" 520 }; 521 522 const char *modifiers[] = { 523 "", 524 "OverDrive ", 525 "Dual ", 526 "" 527 }; 528 529 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 530 { 531 "GenuineIntel", 532 CPUVENDOR_INTEL, 533 "Intel", 534 /* Family 4 */ 535 { { 536 CPUCLASS_486, 537 { 538 "486DX", "486DX", "486SX", "486DX2", "486SL", 539 "486SX2", 0, "486DX2 W/B", 540 "486DX4", 0, 0, 0, 0, 0, 0, 0, 541 "486" /* Default */ 542 }, 543 NULL 544 }, 545 /* Family 5 */ 546 { 547 CPUCLASS_586, 548 { 549 "Pentium (A-step)", "Pentium (P5)", 550 "Pentium (P54C)", "Pentium (P24T)", 551 "Pentium/MMX", "Pentium", 0, 552 "Pentium (P54C)", "Pentium/MMX", 553 0, 0, 0, 0, 0, 0, 0, 554 "Pentium" /* Default */ 555 }, 556 intel586_cpu_setup 557 }, 558 /* Family 6 */ 559 { 560 CPUCLASS_686, 561 { 562 "Pentium Pro", "Pentium Pro", 0, 563 "Pentium II", "Pentium Pro", 564 "Pentium II/Celeron", 565 "Celeron", 566 "Pentium III", 567 "Pentium III", 568 "Pentium M", 569 "Pentium III Xeon", 570 "Pentium III", 0, 571 "Pentium M", 572 "Core Duo/Solo", 0, 573 "Pentium Pro, II or III" /* Default */ 574 }, 575 intel686_cpu_setup 576 }, 577 /* Family 7 */ 578 { 579 CPUCLASS_686, 580 } , 581 /* Family 8 */ 582 { 583 CPUCLASS_686, 584 } , 585 /* Family 9 */ 586 { 587 CPUCLASS_686, 588 } , 589 /* Family A */ 590 { 591 CPUCLASS_686, 592 } , 593 /* Family B */ 594 { 595 CPUCLASS_686, 596 } , 597 /* Family C */ 598 { 599 CPUCLASS_686, 600 } , 601 /* Family D */ 602 { 603 CPUCLASS_686, 604 } , 605 /* Family E */ 606 { 607 CPUCLASS_686, 608 } , 609 /* Family F */ 610 { 611 CPUCLASS_686, 612 { 613 "Pentium 4", 0, 0, 0, 614 0, 0, 0, 0, 615 0, 0, 0, 0, 616 0, 0, 0, 0, 617 "Pentium 4" /* Default */ 618 }, 619 intel686_p4_cpu_setup 620 } } 621 }, 622 { 623 "AuthenticAMD", 624 CPUVENDOR_AMD, 625 "AMD", 626 /* Family 4 */ 627 { { 628 CPUCLASS_486, 629 { 630 0, 0, 0, "Am486DX2 W/T", 631 0, 0, 0, "Am486DX2 W/B", 632 "Am486DX4 W/T or Am5x86 W/T 150", 633 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 634 0, 0, "Am5x86 W/T 133/160", 635 "Am5x86 W/B 133/160", 636 "Am486 or Am5x86" /* Default */ 637 }, 638 NULL 639 }, 640 /* Family 5 */ 641 { 642 CPUCLASS_586, 643 { 644 "K5", "K5", "K5", "K5", 0, 0, "K6", 645 "K6", "K6-2", "K6-III", 0, 0, 0, 646 "K6-2+/III+", 0, 0, 647 "K5 or K6" /* Default */ 648 }, 649 amd_family5_setup 650 }, 651 /* Family 6 */ 652 { 653 CPUCLASS_686, 654 { 655 0, "Athlon Model 1", "Athlon Model 2", 656 "Duron Model 3", 657 "Athlon Model 4", 658 0, "Athlon XP Model 6", 659 "Duron Model 7", 660 "Athlon XP Model 8", 661 0, "Athlon XP Model 10", 662 0, 0, 0, 0, 0, 663 "K7" /* Default */ 664 }, 665 amd_family6_setup 666 }, 667 /* Family 7 */ 668 { 669 CPUCLASS_686, 670 } , 671 /* Family 8 */ 672 { 673 CPUCLASS_686, 674 } , 675 /* Family 9 */ 676 { 677 CPUCLASS_686, 678 } , 679 /* Family A */ 680 { 681 CPUCLASS_686, 682 } , 683 /* Family B */ 684 { 685 CPUCLASS_686, 686 } , 687 /* Family C */ 688 { 689 CPUCLASS_686, 690 } , 691 /* Family D */ 692 { 693 CPUCLASS_686, 694 } , 695 /* Family E */ 696 { 697 CPUCLASS_686, 698 } , 699 /* Family F */ 700 { 701 CPUCLASS_686, 702 { 703 0, 0, 0, 0, "Athlon64", 704 "Opteron or Athlon64FX", 0, 0, 705 0, 0, 0, 0, 0, 0, 0, 0, 706 "AMD64" /* DEFAULT */ 707 }, 708 amd_family6_setup 709 } } 710 }, 711 { 712 "CyrixInstead", 713 CPUVENDOR_CYRIX, 714 "Cyrix", 715 /* Family 4 */ 716 { { 717 CPUCLASS_486, 718 { 719 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0, 720 0, 0, 0, 0, 721 "486 class" /* Default */ 722 }, 723 NULL 724 }, 725 /* Family 5 */ 726 { 727 CPUCLASS_586, 728 { 729 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0, 730 0, 0, 0, 0, 0, 0, 731 "586 class" /* Default */ 732 }, 733 cyrix6x86_cpu_setup 734 }, 735 /* Family 6 */ 736 { 737 CPUCLASS_686, 738 { 739 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 740 0, 0, 0, 0, 741 "686 class" /* Default */ 742 }, 743 NULL 744 } } 745 }, 746 { 747 "CentaurHauls", 748 CPUVENDOR_IDT, 749 "IDT", 750 /* Family 4, not available from IDT */ 751 { { 752 CPUCLASS_486, 753 { 754 0, 0, 0, 0, 0, 0, 0, 0, 755 0, 0, 0, 0, 0, 0, 0, 0, 756 "486 class" /* Default */ 757 }, 758 NULL 759 }, 760 /* Family 5 */ 761 { 762 CPUCLASS_586, 763 { 764 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 765 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 766 "WinChip" /* Default */ 767 }, 768 winchip_cpu_setup 769 }, 770 /* Family 6 */ 771 { 772 CPUCLASS_686, 773 { 774 0, 0, 0, 0, 0, 0, 775 "C3 Samuel", 776 "C3 Samuel 2/Ezra", 777 "C3 Ezra-T", 778 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0, 779 "C3" /* Default */ 780 }, 781 cyrix3_cpu_setup 782 } } 783 }, 784 { 785 "RiseRiseRise", 786 CPUVENDOR_RISE, 787 "Rise", 788 /* Family 4, not available from Rise */ 789 { { 790 CPUCLASS_486, 791 { 792 0, 0, 0, 0, 0, 0, 0, 0, 793 0, 0, 0, 0, 0, 0, 0, 0, 794 "486 class" /* Default */ 795 }, 796 NULL 797 }, 798 /* Family 5 */ 799 { 800 CPUCLASS_586, 801 { 802 "mP6", 0, "mP6", 0, 0, 0, 0, 0, 803 0, 0, 0, 0, 0, 0, 0, 0, 804 "mP6" /* Default */ 805 }, 806 NULL 807 }, 808 /* Family 6, not yet available from Rise */ 809 { 810 CPUCLASS_686, 811 { 812 0, 0, 0, 0, 0, 0, 0, 0, 813 0, 0, 0, 0, 0, 0, 0, 0, 814 "686 class" /* Default */ 815 }, 816 NULL 817 } } 818 }, 819 { 820 "GenuineTMx86", 821 CPUVENDOR_TRANSMETA, 822 "Transmeta", 823 /* Family 4, not available from Transmeta */ 824 { { 825 CPUCLASS_486, 826 { 827 0, 0, 0, 0, 0, 0, 0, 0, 828 0, 0, 0, 0, 0, 0, 0, 0, 829 "486 class" /* Default */ 830 }, 831 NULL 832 }, 833 /* Family 5 */ 834 { 835 CPUCLASS_586, 836 { 837 0, 0, 0, 0, "TMS5x00", 0, 0, 838 0, 0, 0, 0, 0, 0, 0, 0, 0, 839 "TMS5x00" /* Default */ 840 }, 841 tm86_cpu_setup 842 }, 843 /* Family 6, not yet available from Transmeta */ 844 { 845 CPUCLASS_686, 846 { 847 0, 0, 0, 0, 0, 0, 0, 0, 848 0, 0, 0, 0, 0, 0, 0, 0, 849 "686 class" /* Default */ 850 }, 851 NULL 852 }, 853 /* Family 7 */ 854 { 855 CPUCLASS_686, 856 } , 857 /* Family 8 */ 858 { 859 CPUCLASS_686, 860 } , 861 /* Family 9 */ 862 { 863 CPUCLASS_686, 864 } , 865 /* Family A */ 866 { 867 CPUCLASS_686, 868 } , 869 /* Family B */ 870 { 871 CPUCLASS_686, 872 } , 873 /* Family C */ 874 { 875 CPUCLASS_686, 876 } , 877 /* Family D */ 878 { 879 CPUCLASS_686, 880 } , 881 /* Family E */ 882 { 883 CPUCLASS_686, 884 } , 885 /* Family F */ 886 { 887 /* Extended processor family - Transmeta Efficeon */ 888 CPUCLASS_686, 889 { 890 0, 0, "TM8000", "TM8000", 891 0, 0, 0, 0, 892 0, 0, 0, 0, 893 0, 0, 0, 0, 894 "TM8000" /* Default */ 895 }, 896 tm86_cpu_setup 897 } } 898 }, 899 { 900 "Geode by NSC", 901 CPUVENDOR_NS, 902 "National Semiconductor", 903 /* Family 4, not available from National Semiconductor */ 904 { { 905 CPUCLASS_486, 906 { 907 0, 0, 0, 0, 0, 0, 0, 0, 908 0, 0, 0, 0, 0, 0, 0, 0, 909 "486 class" /* Default */ 910 }, 911 NULL 912 }, 913 /* Family 5 */ 914 { 915 CPUCLASS_586, 916 { 917 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0, 918 0, 0, 0, 0, 0, 0, 919 "586 class" /* Default */ 920 }, 921 natsem6x86_cpu_setup 922 } } 923 }, 924 { 925 "SiS SiS SiS ", 926 CPUVENDOR_SIS, 927 "SiS", 928 /* Family 4, not available from SiS */ 929 { { 930 CPUCLASS_486, 931 { 932 0, 0, 0, 0, 0, 0, 0, 0, 933 0, 0, 0, 0, 0, 0, 0, 0, 934 "486 class" /* Default */ 935 }, 936 NULL 937 }, 938 /* Family 5 */ 939 { 940 CPUCLASS_586, 941 { 942 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0, 943 0, 0, 0, 0, 0, 0, 944 "586 class" /* Default */ 945 }, 946 NULL 947 } } 948 } 949 }; 950 951 const struct cpu_cpuid_feature i386_cpuid_features[] = { 952 { CPUID_FPU, "FPU" }, 953 { CPUID_VME, "V86" }, 954 { CPUID_DE, "DE" }, 955 { CPUID_PSE, "PSE" }, 956 { CPUID_TSC, "TSC" }, 957 { CPUID_MSR, "MSR" }, 958 { CPUID_PAE, "PAE" }, 959 { CPUID_MCE, "MCE" }, 960 { CPUID_CX8, "CX8" }, 961 { CPUID_APIC, "APIC" }, 962 { CPUID_SYS1, "SYS" }, 963 { CPUID_SEP, "SEP" }, 964 { CPUID_MTRR, "MTRR" }, 965 { CPUID_PGE, "PGE" }, 966 { CPUID_MCA, "MCA" }, 967 { CPUID_CMOV, "CMOV" }, 968 { CPUID_PAT, "PAT" }, 969 { CPUID_PSE36, "PSE36" }, 970 { CPUID_PSN, "PSN" }, 971 { CPUID_CFLUSH, "CFLUSH" }, 972 { CPUID_DS, "DS" }, 973 { CPUID_ACPI, "ACPI" }, 974 { CPUID_MMX, "MMX" }, 975 { CPUID_FXSR, "FXSR" }, 976 { CPUID_SSE, "SSE" }, 977 { CPUID_SSE2, "SSE2" }, 978 { CPUID_SS, "SS" }, 979 { CPUID_HTT, "HTT" }, 980 { CPUID_TM, "TM" }, 981 { CPUID_PBE, "PBE" } 982 }; 983 984 const struct cpu_cpuid_feature i386_ecpuid_features[] = { 985 { CPUID_MPC, "MPC" }, 986 { CPUID_NXE, "NXE" }, 987 { CPUID_MMXX, "MMXX" }, 988 { CPUID_FFXSR, "FFXSR" }, 989 { CPUID_PAGE1GB, "PAGE1GB" }, 990 { CPUID_RDTSCP, "RDTSCP" }, 991 { CPUID_LONG, "LONG" }, 992 { CPUID_3DNOW2, "3DNOW2" }, 993 { CPUID_3DNOW, "3DNOW" } 994 }; 995 996 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = { 997 { CPUIDECX_SSE3, "SSE3" }, 998 { CPUIDECX_PCLMUL, "PCLMUL" }, 999 { CPUIDECX_DTES64, "DTES64" }, 1000 { CPUIDECX_MWAIT, "MWAIT" }, 1001 { CPUIDECX_DSCPL, "DS-CPL" }, 1002 { CPUIDECX_VMX, "VMX" }, 1003 { CPUIDECX_SMX, "SMX" }, 1004 { CPUIDECX_EST, "EST" }, 1005 { CPUIDECX_TM2, "TM2" }, 1006 { CPUIDECX_SSSE3, "SSSE3" }, 1007 { CPUIDECX_CNXTID, "CNXT-ID" }, 1008 { CPUIDECX_SDBG, "SDBG" }, 1009 { CPUIDECX_FMA3, "FMA3" }, 1010 { CPUIDECX_CX16, "CX16" }, 1011 { CPUIDECX_XTPR, "xTPR" }, 1012 { CPUIDECX_PDCM, "PDCM" }, 1013 { CPUIDECX_PCID, "PCID" }, 1014 { CPUIDECX_DCA, "DCA" }, 1015 { CPUIDECX_SSE41, "SSE4.1" }, 1016 { CPUIDECX_SSE42, "SSE4.2" }, 1017 { CPUIDECX_X2APIC, "x2APIC" }, 1018 { CPUIDECX_MOVBE, "MOVBE" }, 1019 { CPUIDECX_POPCNT, "POPCNT" }, 1020 { CPUIDECX_DEADLINE, "DEADLINE" }, 1021 { CPUIDECX_AES, "AES" }, 1022 { CPUIDECX_XSAVE, "XSAVE" }, 1023 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 1024 { CPUIDECX_AVX, "AVX" }, 1025 { CPUIDECX_F16C, "F16C" }, 1026 { CPUIDECX_RDRAND, "RDRAND" }, 1027 { CPUIDECX_HV, "HV" }, 1028 }; 1029 1030 const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = { 1031 { CPUIDECX_LAHF, "LAHF" }, 1032 { CPUIDECX_CMPLEG, "CMPLEG" }, 1033 { CPUIDECX_SVM, "SVM" }, 1034 { CPUIDECX_EAPICSP, "EAPICSP" }, 1035 { CPUIDECX_AMCR8, "AMCR8" }, 1036 { CPUIDECX_ABM, "ABM" }, 1037 { CPUIDECX_SSE4A, "SSE4A" }, 1038 { CPUIDECX_MASSE, "MASSE" }, 1039 { CPUIDECX_3DNOWP, "3DNOWP" }, 1040 { CPUIDECX_OSVW, "OSVW" }, 1041 { CPUIDECX_IBS, "IBS" }, 1042 { CPUIDECX_XOP, "XOP" }, 1043 { CPUIDECX_SKINIT, "SKINIT" }, 1044 { CPUIDECX_WDT, "WDT" }, 1045 { CPUIDECX_LWP, "LWP" }, 1046 { CPUIDECX_FMA4, "FMA4" }, 1047 { CPUIDECX_TCE, "TCE" }, 1048 { CPUIDECX_NODEID, "NODEID" }, 1049 { CPUIDECX_TBM, "TBM" }, 1050 { CPUIDECX_TOPEXT, "TOPEXT" }, 1051 { CPUIDECX_CPCTR, "CPCTR" }, 1052 { CPUIDECX_DBKP, "DBKP" }, 1053 { CPUIDECX_PERFTSC, "PERFTSC" }, 1054 { CPUIDECX_PCTRL3, "PCTRL3" }, 1055 { CPUIDECX_MWAITX, "MWAITX" }, 1056 }; 1057 1058 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { 1059 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 1060 { SEFF0EBX_TSC_ADJUST, "TSC_ADJUST" }, 1061 { SEFF0EBX_SGX, "SGX" }, 1062 { SEFF0EBX_BMI1, "BMI1" }, 1063 { SEFF0EBX_HLE, "HLE" }, 1064 { SEFF0EBX_AVX2, "AVX2" }, 1065 { SEFF0EBX_SMEP, "SMEP" }, 1066 { SEFF0EBX_BMI2, "BMI2" }, 1067 { SEFF0EBX_ERMS, "ERMS" }, 1068 { SEFF0EBX_INVPCID, "INVPCID" }, 1069 { SEFF0EBX_RTM, "RTM" }, 1070 { SEFF0EBX_PQM, "PQM" }, 1071 { SEFF0EBX_MPX, "MPX" }, 1072 { SEFF0EBX_AVX512F, "AVX512F" }, 1073 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 1074 { SEFF0EBX_RDSEED, "RDSEED" }, 1075 { SEFF0EBX_ADX, "ADX" }, 1076 { SEFF0EBX_SMAP, "SMAP" }, 1077 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 1078 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 1079 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 1080 { SEFF0EBX_CLWB, "CLWB" }, 1081 { SEFF0EBX_PT, "PT" }, 1082 { SEFF0EBX_AVX512PF, "AVX512PF" }, 1083 { SEFF0EBX_AVX512ER, "AVX512ER" }, 1084 { SEFF0EBX_AVX512CD, "AVX512CD" }, 1085 { SEFF0EBX_SHA, "SHA" }, 1086 { SEFF0EBX_AVX512BW, "AVX512BW" }, 1087 { SEFF0EBX_AVX512VL, "AVX512VL" }, 1088 }; 1089 1090 const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = { 1091 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 1092 { SEFF0ECX_UMIP, "UMIP" }, 1093 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 1094 { SEFF0ECX_PKU, "PKU" }, 1095 }; 1096 1097 const struct cpu_cpuid_feature cpu_seff0_edxfeatures[] = { 1098 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 1099 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 1100 { SEFF0EDX_SRBDS_CTRL, "SRBDS_CTRL" }, 1101 { SEFF0EDX_MD_CLEAR, "MD_CLEAR" }, 1102 { SEFF0EDX_TSXFA, "TSXFA" }, 1103 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 1104 { SEFF0EDX_STIBP, "STIBP" }, 1105 { SEFF0EDX_L1DF, "L1DF" }, 1106 /* SEFF0EDX_ARCH_CAP (not printed) */ 1107 { SEFF0EDX_SSBD, "SSBD" }, 1108 }; 1109 1110 const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = { 1111 { TPM_SENSOR, "SENSOR" }, 1112 { TPM_ARAT, "ARAT" }, 1113 }; 1114 1115 const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = { 1116 { CPUIDEAX_VERID, "PERF" }, 1117 }; 1118 1119 const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = { 1120 { CPUIDEDX_ITSC, "ITSC" }, 1121 }; 1122 1123 const struct cpu_cpuid_feature cpu_xsave_extfeatures[] = { 1124 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 1125 { XSAVE_XSAVEC, "XSAVEC" }, 1126 { XSAVE_XGETBV1, "XGETBV1" }, 1127 { XSAVE_XSAVES, "XSAVES" }, 1128 }; 1129 1130 void 1131 winchip_cpu_setup(struct cpu_info *ci) 1132 { 1133 1134 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1135 case 4: /* WinChip C6 */ 1136 ci->ci_feature_flags &= ~CPUID_TSC; 1137 /* Disable RDTSC instruction from user-level. */ 1138 lcr4(rcr4() | CR4_TSD); 1139 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1140 break; 1141 } 1142 } 1143 1144 #if !defined(SMALL_KERNEL) 1145 void 1146 cyrix3_setperf_setup(struct cpu_info *ci) 1147 { 1148 if (cpu_ecxfeature & CPUIDECX_EST) { 1149 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1150 est_init(ci, CPUVENDOR_VIA); 1151 else 1152 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1153 ci->ci_dev->dv_xname); 1154 } 1155 } 1156 #endif 1157 1158 void 1159 cyrix3_cpu_setup(struct cpu_info *ci) 1160 { 1161 int model = (ci->ci_signature >> 4) & 15; 1162 int step = ci->ci_signature & 15; 1163 1164 u_int64_t msreg; 1165 u_int32_t regs[4]; 1166 unsigned int val; 1167 #if !defined(SMALL_KERNEL) 1168 extern void (*pagezero)(void *, size_t); 1169 extern void i686_pagezero(void *, size_t); 1170 1171 pagezero = i686_pagezero; 1172 1173 setperf_setup = cyrix3_setperf_setup; 1174 #endif 1175 1176 switch (model) { 1177 /* Possible earlier models */ 1178 case 0: case 1: case 2: 1179 case 3: case 4: case 5: 1180 break; 1181 1182 case 6: /* C3 Samuel 1 */ 1183 case 7: /* C3 Samuel 2 or C3 Ezra */ 1184 case 8: /* C3 Ezra-T */ 1185 cpuid(0x80000001, regs); 1186 val = regs[3]; 1187 if (val & (1U << 31)) { 1188 cpu_feature |= CPUID_3DNOW; 1189 } else { 1190 cpu_feature &= ~CPUID_3DNOW; 1191 } 1192 break; 1193 1194 case 9: 1195 if (step < 3) 1196 break; 1197 /* 1198 * C3 Nehemiah & later: fall through. 1199 */ 1200 1201 case 10: /* C7-M Type A */ 1202 case 13: /* C7-M Type D */ 1203 case 15: /* Nano */ 1204 #if !defined(SMALL_KERNEL) 1205 if (CPU_IS_PRIMARY(ci) && 1206 (model == 10 || model == 13 || model == 15)) { 1207 /* Setup the sensors structures */ 1208 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1209 sizeof(ci->ci_sensordev.xname)); 1210 ci->ci_sensor.type = SENSOR_TEMP; 1211 sensor_task_register(ci, via_update_sensor, 5); 1212 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1213 sensordev_install(&ci->ci_sensordev); 1214 } 1215 #endif 1216 1217 default: 1218 /* 1219 * C3 Nehemiah/Esther & later models: 1220 * First we check for extended feature flags, and then 1221 * (if present) retrieve the ones at 0xC0000001. In this 1222 * bit 2 tells us if the RNG is present. Bit 3 tells us 1223 * if the RNG has been enabled. In order to use the RNG 1224 * we need 3 things: We need an RNG, we need the FXSR bit 1225 * enabled in cr4 (SSE/SSE2 stuff), and we need to have 1226 * Bit 6 of MSR 0x110B set to 1 (the default), which will 1227 * show up as bit 3 set here. 1228 */ 1229 cpuid(0xC0000000, regs); /* Check for RNG */ 1230 val = regs[0]; 1231 if (val >= 0xC0000001) { 1232 cpuid(0xC0000001, regs); 1233 val = regs[3]; 1234 } else 1235 val = 0; 1236 1237 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 1238 printf("%s:", ci->ci_dev->dv_xname); 1239 1240 /* Enable RNG if present and disabled */ 1241 if (val & C3_CPUID_HAS_RNG) { 1242 extern int viac3_rnd_present; 1243 1244 if (!(val & C3_CPUID_DO_RNG)) { 1245 msreg = rdmsr(0x110B); 1246 msreg |= 0x40; 1247 wrmsr(0x110B, msreg); 1248 } 1249 viac3_rnd_present = 1; 1250 printf(" RNG"); 1251 } 1252 1253 /* Enable AES engine if present and disabled */ 1254 if (val & C3_CPUID_HAS_ACE) { 1255 #ifdef CRYPTO 1256 if (!(val & C3_CPUID_DO_ACE)) { 1257 msreg = rdmsr(0x1107); 1258 msreg |= (0x01 << 28); 1259 wrmsr(0x1107, msreg); 1260 } 1261 i386_has_xcrypt |= C3_HAS_AES; 1262 #endif /* CRYPTO */ 1263 printf(" AES"); 1264 } 1265 1266 /* Enable ACE2 engine if present and disabled */ 1267 if (val & C3_CPUID_HAS_ACE2) { 1268 #ifdef CRYPTO 1269 if (!(val & C3_CPUID_DO_ACE2)) { 1270 msreg = rdmsr(0x1107); 1271 msreg |= (0x01 << 28); 1272 wrmsr(0x1107, msreg); 1273 } 1274 i386_has_xcrypt |= C3_HAS_AESCTR; 1275 #endif /* CRYPTO */ 1276 printf(" AES-CTR"); 1277 } 1278 1279 /* Enable SHA engine if present and disabled */ 1280 if (val & C3_CPUID_HAS_PHE) { 1281 #ifdef CRYPTO 1282 if (!(val & C3_CPUID_DO_PHE)) { 1283 msreg = rdmsr(0x1107); 1284 msreg |= (0x01 << 28/**/); 1285 wrmsr(0x1107, msreg); 1286 } 1287 i386_has_xcrypt |= C3_HAS_SHA; 1288 #endif /* CRYPTO */ 1289 printf(" SHA1 SHA256"); 1290 } 1291 1292 /* Enable MM engine if present and disabled */ 1293 if (val & C3_CPUID_HAS_PMM) { 1294 #ifdef CRYPTO 1295 if (!(val & C3_CPUID_DO_PMM)) { 1296 msreg = rdmsr(0x1107); 1297 msreg |= (0x01 << 28/**/); 1298 wrmsr(0x1107, msreg); 1299 } 1300 i386_has_xcrypt |= C3_HAS_MM; 1301 #endif /* CRYPTO */ 1302 printf(" RSA"); 1303 } 1304 1305 printf("\n"); 1306 break; 1307 } 1308 } 1309 1310 #if !defined(SMALL_KERNEL) 1311 void 1312 via_update_sensor(void *args) 1313 { 1314 struct cpu_info *ci = (struct cpu_info *) args; 1315 u_int64_t msr; 1316 1317 switch (ci->ci_model) { 1318 case 0xa: 1319 case 0xd: 1320 msr = rdmsr(MSR_C7M_TMTEMPERATURE); 1321 break; 1322 case 0xf: 1323 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 1324 break; 1325 } 1326 ci->ci_sensor.value = (msr & 0xffffff); 1327 /* micro degrees */ 1328 ci->ci_sensor.value *= 1000000; 1329 ci->ci_sensor.value += 273150000; 1330 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1331 } 1332 #endif 1333 1334 void 1335 cyrix6x86_cpu_setup(struct cpu_info *ci) 1336 { 1337 extern int clock_broken_latch; 1338 1339 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1340 case -1: /* M1 w/o cpuid */ 1341 case 2: /* M1 */ 1342 /* set up various cyrix registers */ 1343 /* Enable suspend on halt */ 1344 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 1345 /* enable access to ccr4/ccr5 */ 1346 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10); 1347 /* cyrix's workaround for the "coma bug" */ 1348 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 1349 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 1350 cyrix_read_reg(0x33); cyrix_write_reg(0x33, 0); 1351 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 1352 /* disable access to ccr4/ccr5 */ 1353 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10); 1354 1355 printf("%s: xchg bug workaround performed\n", 1356 ci->ci_dev->dv_xname); 1357 break; /* fallthrough? */ 1358 case 4: /* GXm */ 1359 /* Unset the TSC bit until calibrate_delay() gets fixed. */ 1360 clock_broken_latch = 1; 1361 curcpu()->ci_feature_flags &= ~CPUID_TSC; 1362 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1363 break; 1364 } 1365 } 1366 1367 void 1368 natsem6x86_cpu_setup(struct cpu_info *ci) 1369 { 1370 extern int clock_broken_latch; 1371 int model = (ci->ci_signature >> 4) & 15; 1372 1373 clock_broken_latch = 1; 1374 switch (model) { 1375 case 4: 1376 cpu_feature &= ~CPUID_TSC; 1377 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1378 break; 1379 } 1380 } 1381 1382 void 1383 intel586_cpu_setup(struct cpu_info *ci) 1384 { 1385 if (!cpu_f00f_bug) { 1386 fix_f00f(); 1387 printf("%s: F00F bug workaround installed\n", 1388 ci->ci_dev->dv_xname); 1389 } 1390 } 1391 1392 #if !defined(SMALL_KERNEL) 1393 void 1394 amd_family5_setperf_setup(struct cpu_info *ci) 1395 { 1396 k6_powernow_init(); 1397 } 1398 #endif 1399 1400 void 1401 amd_family5_setup(struct cpu_info *ci) 1402 { 1403 int model = (ci->ci_signature >> 4) & 15; 1404 1405 switch (model) { 1406 case 0: /* AMD-K5 Model 0 */ 1407 /* 1408 * According to the AMD Processor Recognition App Note, 1409 * the AMD-K5 Model 0 uses the wrong bit to indicate 1410 * support for global PTEs, instead using bit 9 (APIC) 1411 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1412 */ 1413 if (cpu_feature & CPUID_APIC) 1414 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE; 1415 /* 1416 * XXX But pmap_pg_g is already initialized -- need to kick 1417 * XXX the pmap somehow. How does the MP branch do this? 1418 */ 1419 break; 1420 case 12: 1421 case 13: 1422 #if !defined(SMALL_KERNEL) 1423 setperf_setup = amd_family5_setperf_setup; 1424 #endif 1425 break; 1426 } 1427 } 1428 1429 #if !defined(SMALL_KERNEL) 1430 void 1431 amd_family6_setperf_setup(struct cpu_info *ci) 1432 { 1433 int family = (ci->ci_signature >> 8) & 15; 1434 1435 switch (family) { 1436 case 6: 1437 k7_powernow_init(); 1438 break; 1439 case 15: 1440 k8_powernow_init(); 1441 break; 1442 } 1443 if (ci->ci_family >= 0x10) 1444 k1x_init(ci); 1445 } 1446 #endif 1447 1448 void 1449 amd_family6_setup(struct cpu_info *ci) 1450 { 1451 #if !defined(SMALL_KERNEL) 1452 int family = (ci->ci_signature >> 8) & 15; 1453 extern void (*pagezero)(void *, size_t); 1454 extern void sse2_pagezero(void *, size_t); 1455 extern void i686_pagezero(void *, size_t); 1456 1457 if (cpu_feature & CPUID_SSE2) 1458 pagezero = sse2_pagezero; 1459 else 1460 pagezero = i686_pagezero; 1461 1462 setperf_setup = amd_family6_setperf_setup; 1463 1464 if (family == 0xf) { 1465 amd64_errata(ci); 1466 } 1467 #endif 1468 } 1469 1470 #if !defined(SMALL_KERNEL) 1471 /* 1472 * Temperature read on the CPU is relative to the maximum 1473 * temperature supported by the CPU, Tj(Max). 1474 * Refer to: 1475 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 1476 * Section 35 and 1477 * http://www.intel.com/content/dam/www/public/us/en/documents/ 1478 * white-papers/cpu-monitoring-dts-peci-paper.pdf 1479 * 1480 * The temperature on Intel CPUs can be between 70 and 105 degC, since 1481 * Westmere we can read the TJmax from the die. For older CPUs we have 1482 * to guess or use undocumented MSRs. Then we subtract the temperature 1483 * portion of thermal status from max to get current temperature. 1484 */ 1485 void 1486 intelcore_update_sensor(void *args) 1487 { 1488 struct cpu_info *ci = (struct cpu_info *) args; 1489 u_int64_t msr; 1490 int max = 100; 1491 1492 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 1493 if (ci->ci_model == 0x0e && 1494 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 1495 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 1496 max = 85; 1497 1498 /* 1499 * Newer CPUs can tell you what their max temperature is. 1500 * See: '64-ia-32-architectures-software-developer- 1501 * vol-3c-part-3-manual.pdf' 1502 */ 1503 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 1504 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 1505 ci->ci_model != 0x35 && ci->ci_model != 0x36) 1506 max = MSR_TEMPERATURE_TARGET_TJMAX( 1507 rdmsr(MSR_TEMPERATURE_TARGET)); 1508 1509 msr = rdmsr(MSR_THERM_STATUS); 1510 if (msr & MSR_THERM_STATUS_VALID_BIT) { 1511 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 1512 /* micro degrees */ 1513 ci->ci_sensor.value *= 1000000; 1514 /* kelvin */ 1515 ci->ci_sensor.value += 273150000; 1516 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1517 } else { 1518 ci->ci_sensor.value = 0; 1519 ci->ci_sensor.flags |= SENSOR_FINVALID; 1520 } 1521 } 1522 1523 void 1524 intel686_cpusensors_setup(struct cpu_info *ci) 1525 { 1526 if (!CPU_IS_PRIMARY(ci) || (ci->ci_feature_tpmflags & TPM_SENSOR) == 0) 1527 return; 1528 1529 /* Setup the sensors structures */ 1530 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1531 sizeof(ci->ci_sensordev.xname)); 1532 ci->ci_sensor.type = SENSOR_TEMP; 1533 sensor_task_register(ci, intelcore_update_sensor, 5); 1534 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1535 sensordev_install(&ci->ci_sensordev); 1536 } 1537 #endif 1538 1539 #if !defined(SMALL_KERNEL) 1540 void 1541 intel686_setperf_setup(struct cpu_info *ci) 1542 { 1543 int family = (ci->ci_signature >> 8) & 15; 1544 int step = ci->ci_signature & 15; 1545 1546 if (cpu_ecxfeature & CPUIDECX_EST) { 1547 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1548 est_init(ci, CPUVENDOR_INTEL); 1549 else 1550 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1551 ci->ci_dev->dv_xname); 1552 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) == 1553 (CPUID_ACPI | CPUID_TM)) 1554 p4tcc_init(family, step); 1555 } 1556 #endif 1557 1558 void 1559 intel686_common_cpu_setup(struct cpu_info *ci) 1560 { 1561 1562 #if !defined(SMALL_KERNEL) 1563 setperf_setup = intel686_setperf_setup; 1564 cpusensors_setup = intel686_cpusensors_setup; 1565 { 1566 extern void (*pagezero)(void *, size_t); 1567 extern void sse2_pagezero(void *, size_t); 1568 extern void i686_pagezero(void *, size_t); 1569 1570 if (cpu_feature & CPUID_SSE2) 1571 pagezero = sse2_pagezero; 1572 else 1573 pagezero = i686_pagezero; 1574 } 1575 #endif 1576 /* 1577 * Make sure SYSENTER is disabled. 1578 */ 1579 if (cpu_feature & CPUID_SEP) 1580 wrmsr(MSR_SYSENTER_CS, 0); 1581 } 1582 1583 void 1584 intel686_cpu_setup(struct cpu_info *ci) 1585 { 1586 int model = (ci->ci_signature >> 4) & 15; 1587 int step = ci->ci_signature & 15; 1588 u_quad_t msr119; 1589 1590 intel686_common_cpu_setup(ci); 1591 1592 /* 1593 * Original PPro returns SYSCALL in CPUID but is non-functional. 1594 * From Intel Application Note #485. 1595 */ 1596 if ((model == 1) && (step < 3)) 1597 ci->ci_feature_flags &= ~CPUID_SEP; 1598 1599 /* 1600 * Disable the Pentium3 serial number. 1601 */ 1602 if ((model == 7) && (ci->ci_feature_flags & CPUID_PSN)) { 1603 msr119 = rdmsr(MSR_BBL_CR_CTL); 1604 msr119 |= 0x0000000000200000LL; 1605 wrmsr(MSR_BBL_CR_CTL, msr119); 1606 1607 printf("%s: disabling processor serial number\n", 1608 ci->ci_dev->dv_xname); 1609 ci->ci_feature_flags &= ~CPUID_PSN; 1610 ci->ci_level = 2; 1611 } 1612 1613 #if !defined(SMALL_KERNEL) 1614 p3_early = (model == 8 && step == 1) ? 1 : 0; 1615 update_cpuspeed = p3_update_cpuspeed; 1616 #endif 1617 } 1618 1619 void 1620 intel686_p4_cpu_setup(struct cpu_info *ci) 1621 { 1622 intel686_common_cpu_setup(ci); 1623 1624 #if !defined(SMALL_KERNEL) 1625 p4_model = (ci->ci_signature >> 4) & 15; 1626 update_cpuspeed = p4_update_cpuspeed; 1627 #endif 1628 } 1629 1630 void 1631 tm86_cpu_setup(struct cpu_info *ci) 1632 { 1633 #if !defined(SMALL_KERNEL) 1634 longrun_init(); 1635 #endif 1636 } 1637 1638 char * 1639 intel686_cpu_name(int model) 1640 { 1641 char *ret = NULL; 1642 1643 switch (model) { 1644 case 5: 1645 switch (cpu_cache_edx & 0xFF) { 1646 case 0x40: 1647 case 0x41: 1648 ret = "Celeron"; 1649 break; 1650 /* 0x42 should not exist in this model. */ 1651 case 0x43: 1652 ret = "Pentium II"; 1653 break; 1654 case 0x44: 1655 case 0x45: 1656 ret = "Pentium II Xeon"; 1657 break; 1658 } 1659 break; 1660 case 7: 1661 switch (cpu_cache_edx & 0xFF) { 1662 /* 0x40 - 0x42 should not exist in this model. */ 1663 case 0x43: 1664 ret = "Pentium III"; 1665 break; 1666 case 0x44: 1667 case 0x45: 1668 ret = "Pentium III Xeon"; 1669 break; 1670 } 1671 break; 1672 } 1673 1674 return (ret); 1675 } 1676 1677 char * 1678 cyrix3_cpu_name(int model, int step) 1679 { 1680 char *name = NULL; 1681 1682 switch (model) { 1683 case 7: 1684 if (step < 8) 1685 name = "C3 Samuel 2"; 1686 else 1687 name = "C3 Ezra"; 1688 break; 1689 } 1690 return name; 1691 } 1692 1693 /* 1694 * Print identification for the given CPU. 1695 * XXX XXX 1696 * This is not as clean as one might like, because it references 1697 * 1698 * the "cpuid_level" and "cpu_vendor" globals. 1699 * cpuid_level isn't so bad, since both CPU's will hopefully 1700 * be of the same level. 1701 * 1702 * The Intel multiprocessor spec doesn't give us the cpu_vendor 1703 * information; however, the chance of multi-vendor SMP actually 1704 * ever *working* is sufficiently low that it's probably safe to assume 1705 * all processors are of the same vendor. 1706 */ 1707 void 1708 identifycpu(struct cpu_info *ci) 1709 { 1710 const char *name, *modifier, *vendorname, *token; 1711 int class = CPUCLASS_386, vendor, i, max; 1712 int family, model, step, modif, cachesize; 1713 const struct cpu_cpuid_nameclass *cpup = NULL; 1714 char *brandstr_from, *brandstr_to; 1715 char *cpu_device = ci->ci_dev->dv_xname; 1716 int skipspace; 1717 extern uint32_t cpu_meltdown; 1718 1719 if (cpuid_level == -1) { 1720 #ifdef DIAGNOSTIC 1721 if (cpu < 0 || cpu >= 1722 (sizeof i386_nocpuid_cpus/sizeof(struct cpu_nocpuid_nameclass))) 1723 panic("unknown cpu type %d", cpu); 1724 #endif 1725 name = i386_nocpuid_cpus[cpu].cpu_name; 1726 vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1727 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1728 model = -1; 1729 step = -1; 1730 class = i386_nocpuid_cpus[cpu].cpu_class; 1731 ci->cpu_setup = i386_nocpuid_cpus[cpu].cpu_setup; 1732 modifier = ""; 1733 token = ""; 1734 } else { 1735 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1736 modif = (ci->ci_signature >> 12) & 3; 1737 family = (ci->ci_signature >> 8) & 15; 1738 ci->ci_family = family; 1739 model = (ci->ci_signature >> 4) & 15; 1740 ci->ci_model = model; 1741 step = ci->ci_signature & 15; 1742 #ifdef CPUDEBUG 1743 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n", 1744 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx, 1745 cpu_cache_ecx, cpu_cache_edx); 1746 #endif 1747 if (family < CPU_MINFAMILY) 1748 panic("identifycpu: strange family value"); 1749 1750 for (i = 0; i < max; i++) { 1751 if (!strncmp(cpu_vendor, 1752 i386_cpuid_cpus[i].cpu_id, 12)) { 1753 cpup = &i386_cpuid_cpus[i]; 1754 break; 1755 } 1756 } 1757 1758 if (cpup == NULL) { 1759 vendor = CPUVENDOR_UNKNOWN; 1760 if (cpu_vendor[0] != '\0') 1761 vendorname = &cpu_vendor[0]; 1762 else 1763 vendorname = "Unknown"; 1764 if (family > CPU_MAXFAMILY) 1765 family = CPU_MAXFAMILY; 1766 class = family - 3; 1767 if (class > CPUCLASS_686) 1768 class = CPUCLASS_686; 1769 modifier = ""; 1770 name = ""; 1771 token = ""; 1772 ci->cpu_setup = NULL; 1773 } else { 1774 token = cpup->cpu_id; 1775 vendor = cpup->cpu_vendor; 1776 vendorname = cpup->cpu_vendorname; 1777 /* 1778 * Special hack for the VIA C3 series. 1779 * 1780 * VIA bought Centaur Technology from IDT in Aug 1999 1781 * and marketed the processors as VIA Cyrix III/C3. 1782 */ 1783 if (vendor == CPUVENDOR_IDT && family >= 6) { 1784 vendor = CPUVENDOR_VIA; 1785 vendorname = "VIA"; 1786 } 1787 modifier = modifiers[modif]; 1788 if (family > CPU_MAXFAMILY) { 1789 family = CPU_MAXFAMILY; 1790 model = CPU_DEFMODEL; 1791 } else if (model > CPU_MAXMODEL) 1792 model = CPU_DEFMODEL; 1793 i = family - CPU_MINFAMILY; 1794 1795 /* store extended family/model values for later use */ 1796 if ((vendor == CPUVENDOR_INTEL && 1797 (family == 0x6 || family == 0xf)) || 1798 (vendor == CPUVENDOR_AMD && family == 0xf)) { 1799 ci->ci_family += (ci->ci_signature >> 20) & 1800 0xff; 1801 ci->ci_model += ((ci->ci_signature >> 16) & 1802 0x0f) << 4; 1803 } 1804 1805 /* Special hack for the PentiumII/III series. */ 1806 if (vendor == CPUVENDOR_INTEL && family == 6 && 1807 (model == 5 || model == 7)) { 1808 name = intel686_cpu_name(model); 1809 /* Special hack for the VIA C3 series. */ 1810 } else if (vendor == CPUVENDOR_VIA && family == 6 && 1811 model == 7) { 1812 name = cyrix3_cpu_name(model, step); 1813 /* Special hack for the TMS5x00 series. */ 1814 } else if (vendor == CPUVENDOR_TRANSMETA && 1815 family == 5 && model == 4) { 1816 name = tm86_cpu_name(model); 1817 } else 1818 name = cpup->cpu_family[i].cpu_models[model]; 1819 if (name == NULL) { 1820 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL]; 1821 if (name == NULL) 1822 name = ""; 1823 } 1824 class = cpup->cpu_family[i].cpu_class; 1825 ci->cpu_setup = cpup->cpu_family[i].cpu_setup; 1826 } 1827 } 1828 1829 /* Find the amount of on-chip L2 cache. */ 1830 cachesize = -1; 1831 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) { 1832 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 }; 1833 1834 if ((cpu_cache_edx & 0xFF) >= 0x40 && 1835 (cpu_cache_edx & 0xFF) <= 0x45) 1836 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40]; 1837 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) { 1838 u_int regs[4]; 1839 cpuid(0x80000000, regs); 1840 1841 if (regs[0] >= 0x80000005) 1842 cpuid(0x80000005, ci->ci_amdcacheinfo); 1843 1844 if (regs[0] >= 0x80000006) { 1845 cpuid(0x80000006, ci->ci_extcacheinfo); 1846 cachesize = (ci->ci_extcacheinfo[2] >> 16); 1847 } 1848 } 1849 1850 if (ci->ci_feature_flags & CPUID_CFLUSH) { 1851 u_int regs[4]; 1852 1853 /* to get the cacheline size you must do cpuid 1854 * with eax 0x01 1855 */ 1856 1857 cpuid(0x01, regs); 1858 ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; 1859 } 1860 1861 if (vendor == CPUVENDOR_INTEL) { 1862 u_int regs[4]; 1863 /* 1864 * PIII, Core Solo and Core Duo CPUs have known 1865 * errata stating: 1866 * "Page with PAT set to WC while associated MTRR is UC 1867 * may consolidate to UC". 1868 * Because of this it is best we just fallback to mtrrs 1869 * in this case. 1870 */ 1871 if (ci->ci_family == 6 && ci->ci_model < 15) 1872 ci->ci_feature_flags &= ~CPUID_PAT; 1873 1874 if (cpuid_level >= 0x1) { 1875 cpuid(0x80000000, regs); 1876 if (regs[0] >= 0x80000006) 1877 cpuid(0x80000006, ci->ci_extcacheinfo); 1878 } 1879 } 1880 1881 /* Remove leading, trailing and duplicated spaces from cpu_brandstr */ 1882 brandstr_from = brandstr_to = cpu_brandstr; 1883 skipspace = 1; 1884 while (*brandstr_from != '\0') { 1885 if (!skipspace || *brandstr_from != ' ') { 1886 skipspace = 0; 1887 *(brandstr_to++) = *brandstr_from; 1888 } 1889 if (*brandstr_from == ' ') 1890 skipspace = 1; 1891 brandstr_from++; 1892 } 1893 if (skipspace && brandstr_to > cpu_brandstr) 1894 brandstr_to--; 1895 *brandstr_to = '\0'; 1896 1897 if (cpu_brandstr[0] == '\0') { 1898 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */, 1899 "%s %s%s", vendorname, modifier, name); 1900 } 1901 1902 if (cachesize > -1) { 1903 snprintf(cpu_model, sizeof(cpu_model), 1904 "%s (%s%s%s%s-class, %dKB L2 cache)", 1905 cpu_brandstr, 1906 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1907 ((*token) ? "\" " : ""), classnames[class], cachesize); 1908 } else { 1909 snprintf(cpu_model, sizeof(cpu_model), 1910 "%s (%s%s%s%s-class)", 1911 cpu_brandstr, 1912 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1913 ((*token) ? "\" " : ""), classnames[class]); 1914 } 1915 1916 printf("%s: %s", cpu_device, cpu_model); 1917 1918 if (ci->ci_feature_flags && (ci->ci_feature_flags & CPUID_TSC)) { 1919 /* Has TSC, check if it's constant */ 1920 switch (vendor) { 1921 case CPUVENDOR_INTEL: 1922 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 1923 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 1924 ci->ci_flags |= CPUF_CONST_TSC; 1925 } 1926 break; 1927 case CPUVENDOR_VIA: 1928 if (ci->ci_model >= 0x0f) { 1929 ci->ci_flags |= CPUF_CONST_TSC; 1930 } 1931 break; 1932 } 1933 calibrate_cyclecounter(); 1934 if (cpuspeed > 994) { 1935 int ghz, fr; 1936 1937 ghz = (cpuspeed + 9) / 1000; 1938 fr = ((cpuspeed + 9) / 10 ) % 100; 1939 if (fr) 1940 printf(" %d.%02d GHz", ghz, fr); 1941 else 1942 printf(" %d GHz", ghz); 1943 } else { 1944 printf(" %d MHz", cpuspeed); 1945 } 1946 } 1947 1948 if (cpuid_level != -1) 1949 printf(", %02x-%02x-%02x", ci->ci_family, ci->ci_model, 1950 step); 1951 1952 printf("\n"); 1953 1954 if (ci->ci_feature_flags) { 1955 int numbits = 0; 1956 1957 printf("%s: ", cpu_device); 1958 max = sizeof(i386_cpuid_features) / 1959 sizeof(i386_cpuid_features[0]); 1960 for (i = 0; i < max; i++) { 1961 if (ci->ci_feature_flags & 1962 i386_cpuid_features[i].feature_bit) { 1963 printf("%s%s", (numbits == 0 ? "" : ","), 1964 i386_cpuid_features[i].feature_name); 1965 numbits++; 1966 } 1967 } 1968 max = sizeof(i386_cpuid_ecxfeatures) 1969 / sizeof(i386_cpuid_ecxfeatures[0]); 1970 for (i = 0; i < max; i++) { 1971 if (cpu_ecxfeature & 1972 i386_cpuid_ecxfeatures[i].feature_bit) { 1973 printf("%s%s", (numbits == 0 ? "" : ","), 1974 i386_cpuid_ecxfeatures[i].feature_name); 1975 numbits++; 1976 } 1977 } 1978 for (i = 0; i < nitems(i386_ecpuid_features); i++) { 1979 if (ecpu_feature & 1980 i386_ecpuid_features[i].feature_bit) { 1981 printf("%s%s", (numbits == 0 ? "" : ","), 1982 i386_ecpuid_features[i].feature_name); 1983 numbits++; 1984 } 1985 } 1986 for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) { 1987 if (ecpu_ecxfeature & 1988 i386_ecpuid_ecxfeatures[i].feature_bit) { 1989 printf("%s%s", (numbits == 0 ? "" : ","), 1990 i386_ecpuid_ecxfeatures[i].feature_name); 1991 numbits++; 1992 } 1993 } 1994 for (i = 0; i < nitems(i386_cpuid_eaxperf); i++) { 1995 if (cpu_perf_eax & 1996 i386_cpuid_eaxperf[i].feature_bit) { 1997 printf("%s%s", (numbits == 0 ? "" : ","), 1998 i386_cpuid_eaxperf[i].feature_name); 1999 numbits++; 2000 } 2001 } 2002 for (i = 0; i < nitems(i386_cpuid_edxapmi); i++) { 2003 if (cpu_apmi_edx & 2004 i386_cpuid_edxapmi[i].feature_bit) { 2005 printf("%s%s", (numbits == 0 ? "" : ","), 2006 i386_cpuid_edxapmi[i].feature_name); 2007 numbits++; 2008 } 2009 } 2010 2011 if (cpuid_level >= 0x07) { 2012 u_int dummy; 2013 2014 /* "Structured Extended Feature Flags" */ 2015 CPUID_LEAF(0x7, 0, dummy, 2016 ci->ci_feature_sefflags_ebx, 2017 ci->ci_feature_sefflags_ecx, 2018 ci->ci_feature_sefflags_edx); 2019 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 2020 if (ci->ci_feature_sefflags_ebx & 2021 cpu_seff0_ebxfeatures[i].feature_bit) 2022 printf("%s%s", 2023 (numbits == 0 ? "" : ","), 2024 cpu_seff0_ebxfeatures[i].feature_name); 2025 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 2026 if (ci->ci_feature_sefflags_ecx & 2027 cpu_seff0_ecxfeatures[i].feature_bit) 2028 printf("%s%s", 2029 (numbits == 0 ? "" : ","), 2030 cpu_seff0_ecxfeatures[i].feature_name); 2031 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 2032 if (ci->ci_feature_sefflags_edx & 2033 cpu_seff0_edxfeatures[i].feature_bit) 2034 printf("%s%s", 2035 (numbits == 0 ? "" : ","), 2036 cpu_seff0_edxfeatures[i].feature_name); 2037 } 2038 2039 if (!strcmp(cpu_vendor, "GenuineIntel") && 2040 cpuid_level >= 0x06 ) { 2041 u_int dummy; 2042 2043 CPUID(0x06, ci->ci_feature_tpmflags, dummy, 2044 dummy, dummy); 2045 max = nitems(cpu_tpm_eaxfeatures); 2046 for (i = 0; i < max; i++) 2047 if (ci->ci_feature_tpmflags & 2048 cpu_tpm_eaxfeatures[i].feature_bit) 2049 printf(",%s", cpu_tpm_eaxfeatures[i].feature_name); 2050 } 2051 2052 /* xsave subfeatures */ 2053 if (cpuid_level >= 0xd) { 2054 uint32_t dummy, val; 2055 2056 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 2057 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 2058 if (val & cpu_xsave_extfeatures[i].feature_bit) 2059 printf(",%s", 2060 cpu_xsave_extfeatures[i].feature_name); 2061 } 2062 2063 if (cpu_meltdown) 2064 printf(",MELTDOWN"); 2065 2066 printf("\n"); 2067 } 2068 2069 /* 2070 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques 2071 * for Managing Speculation on AMD Processors" 2072 * 2073 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch 2074 * serializing instruction. 2075 * 2076 * This MSR is available on all AMD families >= 10h, except 11h 2077 * where LFENCE is always serializing. 2078 */ 2079 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 2080 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) { 2081 uint64_t msr; 2082 2083 msr = rdmsr(MSR_DE_CFG); 2084 if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { 2085 msr |= DE_CFG_SERIALIZE_LFENCE; 2086 wrmsr(MSR_DE_CFG, msr); 2087 } 2088 } 2089 } 2090 2091 /* 2092 * Attempt to disable Silicon Debug and lock the configuration 2093 * if it's enabled and unlocked. 2094 */ 2095 if (!strcmp(cpu_vendor, "GenuineIntel") && 2096 (cpu_ecxfeature & CPUIDECX_SDBG)) { 2097 uint64_t msr; 2098 2099 msr = rdmsr(IA32_DEBUG_INTERFACE); 2100 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 2101 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 2102 msr &= IA32_DEBUG_INTERFACE_MASK; 2103 msr |= IA32_DEBUG_INTERFACE_LOCK; 2104 wrmsr(IA32_DEBUG_INTERFACE, msr); 2105 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 2106 printf("%s: cannot disable silicon debug\n", 2107 cpu_device); 2108 } 2109 2110 if (CPU_IS_PRIMARY(ci)) { 2111 if (cpu_ecxfeature & CPUIDECX_RDRAND) 2112 has_rdrand = 1; 2113 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 2114 has_rdseed = 1; 2115 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 2116 replacesmap(); 2117 } 2118 2119 #ifndef SMALL_KERNEL 2120 if (cpuspeed != 0 && cpu_cpuspeed == NULL) 2121 cpu_cpuspeed = pentium_cpuspeed; 2122 #endif 2123 2124 cpu_class = class; 2125 2126 if (cpu_class == CPUCLASS_386) { 2127 printf("WARNING: 386 (possibly unknown?) cpu class, assuming 486\n"); 2128 cpu_class = CPUCLASS_486; 2129 } 2130 2131 ci->cpu_class = class; 2132 2133 if (cpu == CPU_486DLC) 2134 printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2135 2136 /* 2137 * Enable ring 0 write protection (486 or above, but 386 2138 * no longer supported). 2139 */ 2140 lcr0(rcr0() | CR0_WP); 2141 2142 /* 2143 * If we have FXSAVE/FXRESTOR, use them. 2144 */ 2145 if (cpu_feature & CPUID_FXSR) { 2146 i386_use_fxsave = 1; 2147 lcr4(rcr4() | CR4_OSFXSR); 2148 2149 /* 2150 * If we have SSE/SSE2, enable XMM exceptions, and 2151 * notify userland. 2152 */ 2153 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) { 2154 if (cpu_feature & CPUID_SSE) 2155 i386_has_sse = 1; 2156 if (cpu_feature & CPUID_SSE2) 2157 i386_has_sse2 = 1; 2158 lcr4(rcr4() | CR4_OSXMMEXCPT); 2159 } 2160 } else 2161 i386_use_fxsave = 0; 2162 2163 } 2164 2165 char * 2166 tm86_cpu_name(int model) 2167 { 2168 u_int32_t regs[4]; 2169 char *name = NULL; 2170 2171 cpuid(0x80860001, regs); 2172 2173 switch (model) { 2174 case 4: 2175 if (((regs[1] >> 16) & 0xff) >= 0x3) 2176 name = "TMS5800"; 2177 else 2178 name = "TMS5600"; 2179 } 2180 2181 return name; 2182 } 2183 2184 #ifndef SMALL_KERNEL 2185 void 2186 cyrix3_get_bus_clock(struct cpu_info *ci) 2187 { 2188 u_int64_t msr; 2189 int bus; 2190 2191 msr = rdmsr(MSR_EBL_CR_POWERON); 2192 bus = (msr >> 18) & 0x3; 2193 switch (bus) { 2194 case 0: 2195 bus_clock = BUS100; 2196 break; 2197 case 1: 2198 bus_clock = BUS133; 2199 break; 2200 case 2: 2201 bus_clock = BUS200; 2202 break; 2203 case 3: 2204 bus_clock = BUS166; 2205 break; 2206 } 2207 } 2208 2209 void 2210 p4_get_bus_clock(struct cpu_info *ci) 2211 { 2212 u_int64_t msr; 2213 int model, bus; 2214 2215 model = (ci->ci_signature >> 4) & 15; 2216 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2217 if (model < 2) { 2218 bus = (msr >> 21) & 0x7; 2219 switch (bus) { 2220 case 0: 2221 bus_clock = BUS100; 2222 break; 2223 case 1: 2224 bus_clock = BUS133; 2225 break; 2226 default: 2227 printf("%s: unknown Pentium 4 (model %d) " 2228 "EBC_FREQUENCY_ID value %d\n", 2229 ci->ci_dev->dv_xname, model, bus); 2230 break; 2231 } 2232 } else { 2233 bus = (msr >> 16) & 0x7; 2234 switch (bus) { 2235 case 0: 2236 bus_clock = (model == 2) ? BUS100 : BUS266; 2237 break; 2238 case 1: 2239 bus_clock = BUS133; 2240 break; 2241 case 2: 2242 bus_clock = BUS200; 2243 break; 2244 case 3: 2245 bus_clock = BUS166; 2246 break; 2247 default: 2248 printf("%s: unknown Pentium 4 (model %d) " 2249 "EBC_FREQUENCY_ID value %d\n", 2250 ci->ci_dev->dv_xname, model, bus); 2251 break; 2252 } 2253 } 2254 } 2255 2256 void 2257 p3_get_bus_clock(struct cpu_info *ci) 2258 { 2259 u_int64_t msr; 2260 int bus; 2261 2262 switch (ci->ci_model) { 2263 case 0x9: /* Pentium M (130 nm, Banias) */ 2264 bus_clock = BUS100; 2265 break; 2266 case 0xd: /* Pentium M (90 nm, Dothan) */ 2267 msr = rdmsr(MSR_FSB_FREQ); 2268 bus = (msr >> 0) & 0x7; 2269 switch (bus) { 2270 case 0: 2271 bus_clock = BUS100; 2272 break; 2273 case 1: 2274 bus_clock = BUS133; 2275 break; 2276 default: 2277 printf("%s: unknown Pentium M FSB_FREQ value %d", 2278 ci->ci_dev->dv_xname, bus); 2279 goto print_msr; 2280 } 2281 break; 2282 case 0x15: /* EP80579 no FSB */ 2283 break; 2284 case 0xe: /* Core Duo/Solo */ 2285 case 0xf: /* Core Xeon */ 2286 case 0x16: /* 65nm Celeron */ 2287 case 0x17: /* Core 2 Extreme/45nm Xeon */ 2288 case 0x1d: /* Xeon MP 7400 */ 2289 msr = rdmsr(MSR_FSB_FREQ); 2290 bus = (msr >> 0) & 0x7; 2291 switch (bus) { 2292 case 5: 2293 bus_clock = BUS100; 2294 break; 2295 case 1: 2296 bus_clock = BUS133; 2297 break; 2298 case 3: 2299 bus_clock = BUS166; 2300 break; 2301 case 2: 2302 bus_clock = BUS200; 2303 break; 2304 case 0: 2305 bus_clock = BUS266; 2306 break; 2307 case 4: 2308 bus_clock = BUS333; 2309 break; 2310 default: 2311 printf("%s: unknown Core FSB_FREQ value %d", 2312 ci->ci_dev->dv_xname, bus); 2313 goto print_msr; 2314 } 2315 break; 2316 case 0x1c: /* Atom */ 2317 case 0x26: /* Atom Z6xx */ 2318 case 0x36: /* Atom [DN]2xxx */ 2319 msr = rdmsr(MSR_FSB_FREQ); 2320 bus = (msr >> 0) & 0x7; 2321 switch (bus) { 2322 case 5: 2323 bus_clock = BUS100; 2324 break; 2325 case 1: 2326 bus_clock = BUS133; 2327 break; 2328 case 3: 2329 bus_clock = BUS166; 2330 break; 2331 case 2: 2332 bus_clock = BUS200; 2333 break; 2334 default: 2335 printf("%s: unknown Atom FSB_FREQ value %d", 2336 ci->ci_dev->dv_xname, bus); 2337 goto print_msr; 2338 } 2339 break; 2340 case 0x1: /* Pentium Pro, model 1 */ 2341 case 0x3: /* Pentium II, model 3 */ 2342 case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */ 2343 case 0x6: /* Celeron, model 6 */ 2344 case 0x7: /* Pentium III, III Xeon, model 7 */ 2345 case 0x8: /* Pentium III, III Xeon, Celeron, model 8 */ 2346 case 0xa: /* Pentium III Xeon, model A */ 2347 case 0xb: /* Pentium III, model B */ 2348 msr = rdmsr(MSR_EBL_CR_POWERON); 2349 bus = (msr >> 18) & 0x3; 2350 switch (bus) { 2351 case 0: 2352 bus_clock = BUS66; 2353 break; 2354 case 1: 2355 bus_clock = BUS133; 2356 break; 2357 case 2: 2358 bus_clock = BUS100; 2359 break; 2360 default: 2361 printf("%s: unknown i686 EBL_CR_POWERON value %d", 2362 ci->ci_dev->dv_xname, bus); 2363 goto print_msr; 2364 } 2365 break; 2366 default: 2367 /* no FSB on modern Intel processors */ 2368 break; 2369 } 2370 return; 2371 print_msr: 2372 /* 2373 * Show the EBL_CR_POWERON MSR, so we'll at least have 2374 * some extra information, such as clock ratio, etc. 2375 */ 2376 printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON)); 2377 } 2378 2379 void 2380 p4_update_cpuspeed(void) 2381 { 2382 struct cpu_info *ci; 2383 u_int64_t msr; 2384 int mult; 2385 2386 ci = curcpu(); 2387 p4_get_bus_clock(ci); 2388 2389 if (bus_clock == 0) { 2390 printf("p4_update_cpuspeed: unknown bus clock\n"); 2391 return; 2392 } 2393 2394 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2395 mult = ((msr >> 24) & 0xff); 2396 2397 cpuspeed = (bus_clock * mult) / 100; 2398 } 2399 2400 void 2401 p3_update_cpuspeed(void) 2402 { 2403 struct cpu_info *ci; 2404 u_int64_t msr; 2405 int mult; 2406 const u_int8_t mult_code[] = { 2407 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 }; 2408 2409 ci = curcpu(); 2410 p3_get_bus_clock(ci); 2411 2412 if (bus_clock == 0) { 2413 printf("p3_update_cpuspeed: unknown bus clock\n"); 2414 return; 2415 } 2416 2417 msr = rdmsr(MSR_EBL_CR_POWERON); 2418 mult = (msr >> 22) & 0xf; 2419 mult = mult_code[mult]; 2420 if (!p3_early) 2421 mult += ((msr >> 27) & 0x1) * 40; 2422 2423 cpuspeed = (bus_clock * mult) / 1000; 2424 } 2425 2426 int 2427 pentium_cpuspeed(int *freq) 2428 { 2429 *freq = cpuspeed; 2430 return (0); 2431 } 2432 #endif /* !SMALL_KERNEL */ 2433 2434 /* 2435 * Send an interrupt to process. 2436 * 2437 * Stack is set up to allow sigcode stored 2438 * in u. to call routine, followed by kcall 2439 * to sigreturn routine below. After sigreturn 2440 * resets the signal mask, the stack, and the 2441 * frame pointer, it returns to the user 2442 * specified pc, psl. 2443 */ 2444 int 2445 sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip, 2446 int info, int onstack) 2447 { 2448 struct proc *p = curproc; 2449 struct trapframe *tf = p->p_md.md_regs; 2450 struct sigframe *fp, frame; 2451 register_t sp; 2452 2453 /* 2454 * Build the argument list for the signal handler. 2455 */ 2456 bzero(&frame, sizeof(frame)); 2457 frame.sf_signum = sig; 2458 2459 /* 2460 * Allocate space for the signal handler context. 2461 */ 2462 if ((p->p_sigstk.ss_flags & SS_DISABLE) == 0 && 2463 !sigonstack(tf->tf_esp) && onstack) 2464 sp = trunc_page((vaddr_t)p->p_sigstk.ss_sp + p->p_sigstk.ss_size); 2465 else 2466 sp = tf->tf_esp; 2467 2468 frame.sf_sc.sc_fpstate = NULL; 2469 if (p->p_md.md_flags & MDP_USEDFPU) { 2470 npxsave_proc(p, 1); 2471 sp -= sizeof(union savefpu); 2472 sp &= ~0xf; /* for XMM regs */ 2473 frame.sf_sc.sc_fpstate = (void *)sp; 2474 if (copyout(&p->p_addr->u_pcb.pcb_savefpu, 2475 (void *)sp, sizeof(union savefpu))) 2476 return 1; 2477 2478 /* Signal handlers get a completely clean FP state */ 2479 p->p_md.md_flags &= ~MDP_USEDFPU; 2480 } 2481 2482 fp = (struct sigframe *)sp - 1; 2483 frame.sf_scp = &fp->sf_sc; 2484 frame.sf_sip = NULL; 2485 frame.sf_handler = catcher; 2486 2487 /* 2488 * Build the signal context to be used by sigreturn. 2489 */ 2490 frame.sf_sc.sc_err = tf->tf_err; 2491 frame.sf_sc.sc_trapno = tf->tf_trapno; 2492 frame.sf_sc.sc_mask = mask; 2493 frame.sf_sc.sc_fs = tf->tf_fs; 2494 frame.sf_sc.sc_gs = tf->tf_gs; 2495 frame.sf_sc.sc_es = tf->tf_es; 2496 frame.sf_sc.sc_ds = tf->tf_ds; 2497 frame.sf_sc.sc_eflags = tf->tf_eflags; 2498 frame.sf_sc.sc_edi = tf->tf_edi; 2499 frame.sf_sc.sc_esi = tf->tf_esi; 2500 frame.sf_sc.sc_ebp = tf->tf_ebp; 2501 frame.sf_sc.sc_ebx = tf->tf_ebx; 2502 frame.sf_sc.sc_edx = tf->tf_edx; 2503 frame.sf_sc.sc_ecx = tf->tf_ecx; 2504 frame.sf_sc.sc_eax = tf->tf_eax; 2505 frame.sf_sc.sc_eip = tf->tf_eip; 2506 frame.sf_sc.sc_cs = tf->tf_cs; 2507 frame.sf_sc.sc_esp = tf->tf_esp; 2508 frame.sf_sc.sc_ss = tf->tf_ss; 2509 2510 if (info) { 2511 frame.sf_sip = &fp->sf_si; 2512 frame.sf_si = *ksip; 2513 } 2514 2515 /* XXX don't copyout siginfo if not needed? */ 2516 frame.sf_sc.sc_cookie = (long)&fp->sf_sc ^ p->p_p->ps_sigcookie; 2517 if (copyout(&frame, fp, sizeof(frame)) != 0) 2518 return 1; 2519 2520 /* 2521 * Build context to run handler in. 2522 */ 2523 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2524 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2525 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2526 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2527 tf->tf_eip = p->p_p->ps_sigcode; 2528 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2529 tf->tf_eflags &= ~(PSL_T|PSL_D|PSL_VM|PSL_AC); 2530 tf->tf_esp = (int)fp; 2531 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2532 2533 return 0; 2534 } 2535 2536 /* 2537 * System call to cleanup state after a signal 2538 * has been taken. Reset signal mask and 2539 * stack state from context left by sendsig (above). 2540 * Return to previous pc and psl as specified by 2541 * context left by sendsig. Check carefully to 2542 * make sure that the user has not modified the 2543 * psl to gain improper privileges or to cause 2544 * a machine fault. 2545 */ 2546 int 2547 sys_sigreturn(struct proc *p, void *v, register_t *retval) 2548 { 2549 struct sys_sigreturn_args /* { 2550 syscallarg(struct sigcontext *) sigcntxp; 2551 } */ *uap = v; 2552 struct sigcontext ksc, *scp = SCARG(uap, sigcntxp); 2553 struct trapframe *tf = p->p_md.md_regs; 2554 int error; 2555 2556 if (PROC_PC(p) != p->p_p->ps_sigcoderet) { 2557 sigexit(p, SIGILL); 2558 return (EPERM); 2559 } 2560 2561 if ((error = copyin((caddr_t)scp, &ksc, sizeof(*scp)))) 2562 return (error); 2563 2564 if (ksc.sc_cookie != ((long)scp ^ p->p_p->ps_sigcookie)) { 2565 sigexit(p, SIGILL); 2566 return (EFAULT); 2567 } 2568 2569 /* Prevent reuse of the sigcontext cookie */ 2570 ksc.sc_cookie = 0; 2571 (void)copyout(&ksc.sc_cookie, (caddr_t)scp + 2572 offsetof(struct sigcontext, sc_cookie), sizeof (ksc.sc_cookie)); 2573 2574 /* 2575 * Restore signal ksc. 2576 */ 2577 /* 2578 * Check for security violations. If we're returning to 2579 * protected mode, the CPU will validate the segment registers 2580 * automatically and generate a trap on violations. We handle 2581 * the trap, rather than doing all of the checking here. 2582 */ 2583 if (((ksc.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 || 2584 !USERMODE(ksc.sc_cs, ksc.sc_eflags)) 2585 return (EINVAL); 2586 2587 tf->tf_fs = ksc.sc_fs; 2588 tf->tf_gs = ksc.sc_gs; 2589 tf->tf_es = ksc.sc_es; 2590 tf->tf_ds = ksc.sc_ds; 2591 tf->tf_eflags = ksc.sc_eflags; 2592 tf->tf_edi = ksc.sc_edi; 2593 tf->tf_esi = ksc.sc_esi; 2594 tf->tf_ebp = ksc.sc_ebp; 2595 tf->tf_ebx = ksc.sc_ebx; 2596 tf->tf_edx = ksc.sc_edx; 2597 tf->tf_ecx = ksc.sc_ecx; 2598 tf->tf_eax = ksc.sc_eax; 2599 tf->tf_eip = ksc.sc_eip; 2600 tf->tf_cs = ksc.sc_cs; 2601 tf->tf_esp = ksc.sc_esp; 2602 tf->tf_ss = ksc.sc_ss; 2603 2604 if (p->p_md.md_flags & MDP_USEDFPU) 2605 npxsave_proc(p, 0); 2606 2607 if (ksc.sc_fpstate) { 2608 union savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu; 2609 2610 if ((error = copyin(ksc.sc_fpstate, sfp, sizeof(*sfp)))) 2611 return (error); 2612 if (i386_use_fxsave) 2613 sfp->sv_xmm.sv_env.en_mxcsr &= fpu_mxcsr_mask; 2614 p->p_md.md_flags |= MDP_USEDFPU; 2615 } 2616 2617 p->p_sigmask = ksc.sc_mask & ~sigcantmask; 2618 2619 return (EJUSTRETURN); 2620 } 2621 2622 #ifdef MULTIPROCESSOR 2623 /* force a CPU into the kernel, whether or not it's idle */ 2624 void 2625 cpu_kick(struct cpu_info *ci) 2626 { 2627 /* only need to kick other CPUs */ 2628 if (ci != curcpu()) { 2629 if (cpu_mwait_size > 0) { 2630 /* 2631 * If not idling, then send an IPI, else 2632 * just clear the "keep idling" bit. 2633 */ 2634 if ((ci->ci_mwait & MWAIT_IN_IDLE) == 0) 2635 i386_send_ipi(ci, I386_IPI_NOP); 2636 else 2637 atomic_clearbits_int(&ci->ci_mwait, 2638 MWAIT_KEEP_IDLING); 2639 } else { 2640 /* no mwait, so need an IPI */ 2641 i386_send_ipi(ci, I386_IPI_NOP); 2642 } 2643 } 2644 } 2645 #endif 2646 2647 /* 2648 * Notify the current process (p) that it has a signal pending, 2649 * process as soon as possible. 2650 */ 2651 void 2652 signotify(struct proc *p) 2653 { 2654 aston(p); 2655 cpu_kick(p->p_cpu); 2656 } 2657 2658 #ifdef MULTIPROCESSOR 2659 void 2660 cpu_unidle(struct cpu_info *ci) 2661 { 2662 if (cpu_mwait_size > 0 && (ci->ci_mwait & MWAIT_ONLY)) { 2663 /* 2664 * Just clear the "keep idling" bit; if it wasn't 2665 * idling then we didn't need to do anything anyway. 2666 */ 2667 atomic_clearbits_int(&ci->ci_mwait, MWAIT_KEEP_IDLING); 2668 return; 2669 } 2670 2671 if (ci != curcpu()) 2672 i386_send_ipi(ci, I386_IPI_NOP); 2673 } 2674 #endif 2675 2676 int waittime = -1; 2677 struct pcb dumppcb; 2678 2679 __dead void 2680 boot(int howto) 2681 { 2682 if ((howto & RB_POWERDOWN) != 0) 2683 lid_action = 0; 2684 2685 if ((howto & RB_RESET) != 0) 2686 goto doreset; 2687 2688 if (cold) { 2689 if ((howto & RB_USERREQ) == 0) 2690 howto |= RB_HALT; 2691 goto haltsys; 2692 } 2693 2694 boothowto = howto; 2695 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 2696 waittime = 0; 2697 vfs_shutdown(curproc); 2698 2699 if ((howto & RB_TIMEBAD) == 0) { 2700 resettodr(); 2701 } else { 2702 printf("WARNING: not updating battery clock\n"); 2703 } 2704 } 2705 if_downall(); 2706 2707 uvm_shutdown(); 2708 splhigh(); 2709 cold = 1; 2710 2711 if ((howto & RB_DUMP) != 0) 2712 dumpsys(); 2713 2714 haltsys: 2715 config_suspend_all(DVACT_POWERDOWN); 2716 2717 #ifdef MULTIPROCESSOR 2718 i386_broadcast_ipi(I386_IPI_HALT); 2719 #endif 2720 2721 if ((howto & RB_HALT) != 0) { 2722 #if NACPI > 0 && !defined(SMALL_KERNEL) 2723 extern int acpi_enabled; 2724 2725 if (acpi_enabled) { 2726 delay(500000); 2727 if ((howto & RB_POWERDOWN) != 0) 2728 acpi_powerdown(); 2729 } 2730 #endif 2731 2732 #if NAPM > 0 2733 if ((howto & RB_POWERDOWN) != 0) { 2734 int rv; 2735 2736 printf("\nAttempting to power down...\n"); 2737 /* 2738 * Turn off, if we can. But try to turn disk off and 2739 * wait a bit first--some disk drives are slow to 2740 * clean up and users have reported disk corruption. 2741 * 2742 * If apm_set_powstate() fails the first time, don't 2743 * try to turn the system off. 2744 */ 2745 delay(500000); 2746 apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2747 delay(500000); 2748 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2749 if (rv == 0 || rv == ENXIO) { 2750 delay(500000); 2751 (void) apm_set_powstate(APM_DEV_ALLDEVS, 2752 APM_SYS_OFF); 2753 } 2754 } 2755 #endif 2756 printf("\n"); 2757 printf("The operating system has halted.\n"); 2758 printf("Please press any key to reboot.\n\n"); 2759 cnpollc(1); /* for proper keyboard command handling */ 2760 cngetc(); 2761 cnpollc(0); 2762 } 2763 2764 doreset: 2765 printf("rebooting...\n"); 2766 cpu_reset(); 2767 for (;;) 2768 continue; 2769 /* NOTREACHED */ 2770 } 2771 2772 /* 2773 * This is called by configure to set dumplo and dumpsize. 2774 * Dumps always skip the first block of disk space 2775 * in case there might be a disk label stored there. 2776 * If there is extra space, put dump at the end to 2777 * reduce the chance that swapping trashes it. 2778 */ 2779 void 2780 dumpconf(void) 2781 { 2782 int nblks; /* size of dump area */ 2783 int i; 2784 2785 if (dumpdev == NODEV || 2786 (nblks = (bdevsw[major(dumpdev)].d_psize)(dumpdev)) == 0) 2787 return; 2788 if (nblks <= ctod(1)) 2789 return; 2790 2791 /* Always skip the first block, in case there is a label there. */ 2792 if (dumplo < ctod(1)) 2793 dumplo = ctod(1); 2794 2795 for (i = 0; i < ndumpmem; i++) 2796 dumpsize = max(dumpsize, dumpmem[i].end); 2797 2798 /* Put dump at end of partition, and make it fit. */ 2799 if (dumpsize > dtoc(nblks - dumplo - 1)) 2800 dumpsize = dtoc(nblks - dumplo - 1); 2801 if (dumplo < nblks - ctod(dumpsize) - 1) 2802 dumplo = nblks - ctod(dumpsize) - 1; 2803 } 2804 2805 /* 2806 * cpu_dump: dump machine-dependent kernel core dump headers. 2807 */ 2808 int 2809 cpu_dump(void) 2810 { 2811 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2812 long buf[dbtob(1) / sizeof (long)]; 2813 kcore_seg_t *segp; 2814 2815 dump = bdevsw[major(dumpdev)].d_dump; 2816 2817 segp = (kcore_seg_t *)buf; 2818 2819 /* 2820 * Generate a segment header. 2821 */ 2822 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 2823 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); 2824 2825 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1))); 2826 } 2827 2828 /* 2829 * Doadump comes here after turning off memory management and 2830 * getting on the dump stack, either when called above, or by 2831 * the auto-restart code. 2832 */ 2833 static vaddr_t dumpspace; 2834 2835 vaddr_t 2836 reserve_dumppages(vaddr_t p) 2837 { 2838 2839 dumpspace = p; 2840 return (p + PAGE_SIZE); 2841 } 2842 2843 void 2844 dumpsys(void) 2845 { 2846 u_int i, j, npg; 2847 int maddr; 2848 daddr_t blkno; 2849 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2850 int error; 2851 char *str; 2852 extern int msgbufmapped; 2853 2854 /* Save registers. */ 2855 savectx(&dumppcb); 2856 2857 msgbufmapped = 0; /* don't record dump msgs in msgbuf */ 2858 if (dumpdev == NODEV) 2859 return; 2860 2861 /* 2862 * For dumps during autoconfiguration, 2863 * if dump device has already configured... 2864 */ 2865 if (dumpsize == 0) 2866 dumpconf(); 2867 if (dumplo < 0) 2868 return; 2869 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo); 2870 2871 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); 2872 printf("dump "); 2873 if (error == -1) { 2874 printf("area unavailable\n"); 2875 return; 2876 } 2877 2878 #if 0 /* XXX this doesn't work. grr. */ 2879 /* toss any characters present prior to dump */ 2880 while (sget() != NULL); /*syscons and pccons differ */ 2881 #endif 2882 2883 /* scan through the dumpmem list */ 2884 dump = bdevsw[major(dumpdev)].d_dump; 2885 error = cpu_dump(); 2886 for (i = 0; !error && i < ndumpmem; i++) { 2887 2888 npg = dumpmem[i].end - dumpmem[i].start; 2889 maddr = ptoa(dumpmem[i].start); 2890 blkno = dumplo + btodb(maddr) + 1; 2891 #if 0 2892 printf("(%d %lld %d) ", maddr, (long long)blkno, npg); 2893 #endif 2894 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) { 2895 2896 /* Print out how many MBs we have more to go. */ 2897 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG) 2898 printf("%ld ", 2899 (ptoa(dumpsize) - maddr) / (1024 * 1024)); 2900 #if 0 2901 printf("(%x %lld) ", maddr, (long long)blkno); 2902 #endif 2903 pmap_enter(pmap_kernel(), dumpspace, maddr, 2904 PROT_READ, PMAP_WIRED); 2905 if ((error = (*dump)(dumpdev, blkno, 2906 (caddr_t)dumpspace, NBPG))) 2907 break; 2908 2909 #if 0 /* XXX this doesn't work. grr. */ 2910 /* operator aborting dump? */ 2911 if (sget() != NULL) { 2912 error = EINTR; 2913 break; 2914 } 2915 #endif 2916 } 2917 } 2918 2919 switch (error) { 2920 2921 case 0: str = "succeeded\n\n"; break; 2922 case ENXIO: str = "device bad\n\n"; break; 2923 case EFAULT: str = "device not ready\n\n"; break; 2924 case EINVAL: str = "area improper\n\n"; break; 2925 case EIO: str = "i/o error\n\n"; break; 2926 case EINTR: str = "aborted from console\n\n"; break; 2927 default: str = "error %d\n\n"; break; 2928 } 2929 printf(str, error); 2930 2931 delay(5000000); /* 5 seconds */ 2932 } 2933 2934 /* 2935 * Clear registers on exec 2936 */ 2937 void 2938 setregs(struct proc *p, struct exec_package *pack, u_long stack, 2939 register_t *retval) 2940 { 2941 struct pcb *pcb = &p->p_addr->u_pcb; 2942 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map); 2943 struct trapframe *tf = p->p_md.md_regs; 2944 2945 #if NNPX > 0 2946 /* If we were using the FPU, forget about it. */ 2947 if (pcb->pcb_fpcpu != NULL) 2948 npxsave_proc(p, 0); 2949 p->p_md.md_flags &= ~MDP_USEDFPU; 2950 #endif 2951 2952 initcodesegment(&pmap->pm_codeseg); 2953 setsegment(&pcb->pcb_threadsegs[TSEG_FS], 0, 2954 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2955 setsegment(&pcb->pcb_threadsegs[TSEG_GS], 0, 2956 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2957 2958 /* 2959 * And update the GDT since we return to the user process 2960 * by leaving the syscall (we don't do another pmap_activate()). 2961 */ 2962 curcpu()->ci_gdt[GUCODE_SEL].sd = pmap->pm_codeseg; 2963 curcpu()->ci_gdt[GUFS_SEL].sd = pcb->pcb_threadsegs[TSEG_FS]; 2964 curcpu()->ci_gdt[GUGS_SEL].sd = pcb->pcb_threadsegs[TSEG_GS]; 2965 2966 /* 2967 * And reset the hiexec marker in the pmap. 2968 */ 2969 pmap->pm_hiexec = 0; 2970 2971 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2972 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2973 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2974 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2975 tf->tf_edi = 0; 2976 tf->tf_esi = 0; 2977 tf->tf_ebp = 0; 2978 tf->tf_ebx = (int)p->p_p->ps_strings; 2979 tf->tf_edx = 0; 2980 tf->tf_ecx = 0; 2981 tf->tf_eax = 0; 2982 tf->tf_eip = pack->ep_entry; 2983 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2984 tf->tf_eflags = PSL_USERSET; 2985 tf->tf_esp = stack; 2986 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2987 2988 retval[1] = 0; 2989 } 2990 2991 /* 2992 * Initialize segments and descriptor tables 2993 */ 2994 2995 /* IDT is now a full page, so we can map it in u-k */ 2996 union { 2997 struct gate_descriptor idt[NIDT]; 2998 char align[PAGE_SIZE]; 2999 } _idt_region __aligned(PAGE_SIZE); 3000 #define idt_region _idt_region.idt 3001 struct gate_descriptor *idt = idt_region; 3002 3003 extern struct user *proc0paddr; 3004 3005 void 3006 setgate(struct gate_descriptor *gd, void *func, int args, int type, int dpl, 3007 int seg) 3008 { 3009 3010 gd->gd_looffset = (int)func; 3011 gd->gd_selector = GSEL(seg, SEL_KPL); 3012 gd->gd_stkcpy = args; 3013 gd->gd_xx = 0; 3014 gd->gd_type = type; 3015 gd->gd_dpl = dpl; 3016 gd->gd_p = 1; 3017 gd->gd_hioffset = (int)func >> 16; 3018 } 3019 3020 void 3021 unsetgate(struct gate_descriptor *gd) 3022 { 3023 gd->gd_p = 0; 3024 gd->gd_hioffset = 0; 3025 gd->gd_looffset = 0; 3026 gd->gd_selector = 0; 3027 gd->gd_xx = 0; 3028 gd->gd_stkcpy = 0; 3029 gd->gd_type = 0; 3030 gd->gd_dpl = 0; 3031 } 3032 3033 void 3034 setregion(struct region_descriptor *rd, void *base, size_t limit) 3035 { 3036 rd->rd_limit = (int)limit; 3037 rd->rd_base = (int)base; 3038 } 3039 3040 void 3041 initcodesegment(struct segment_descriptor *cs) 3042 { 3043 if (cpu_pae) { 3044 /* 3045 * When code execution is managed using NX feature 3046 * in pmapae.c, GUCODE_SEL should cover userland. 3047 */ 3048 setsegment(cs, 0, atop(VM_MAXUSER_ADDRESS - 1), 3049 SDT_MEMERA, SEL_UPL, 1, 1); 3050 } else { 3051 /* 3052 * For pmap.c's non-PAE/NX line-in-the-sand execution, reset 3053 * the code segment limit to I386_MAX_EXE_ADDR in the pmap; 3054 * this gets copied into the GDT for GUCODE_SEL by 3055 * pmap_activate(). Similarly, reset the base of each of 3056 * the two thread data segments to zero in the pcb; they'll 3057 * get copied into the GDT for GUFS_SEL and GUGS_SEL. 3058 */ 3059 setsegment(cs, 0, atop(I386_MAX_EXE_ADDR - 1), 3060 SDT_MEMERA, SEL_UPL, 1, 1); 3061 } 3062 } 3063 3064 void 3065 setsegment(struct segment_descriptor *sd, void *base, size_t limit, int type, 3066 int dpl, int def32, int gran) 3067 { 3068 3069 sd->sd_lolimit = (int)limit; 3070 sd->sd_lobase = (int)base; 3071 sd->sd_type = type; 3072 sd->sd_dpl = dpl; 3073 sd->sd_p = 1; 3074 sd->sd_hilimit = (int)limit >> 16; 3075 sd->sd_xx = 0; 3076 sd->sd_def32 = def32; 3077 sd->sd_gran = gran; 3078 sd->sd_hibase = (int)base >> 24; 3079 } 3080 3081 #define IDTVEC(name) __CONCAT(X, name) 3082 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 3083 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm), 3084 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page), 3085 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall), IDTVEC(mchk), 3086 IDTVEC(simd); 3087 3088 extern int IDTVEC(f00f_redirect); 3089 3090 int cpu_f00f_bug = 0; 3091 3092 void 3093 fix_f00f(void) 3094 { 3095 struct region_descriptor region; 3096 vaddr_t va; 3097 paddr_t pa; 3098 void *p; 3099 3100 /* Allocate two new pages */ 3101 va = (vaddr_t)km_alloc(NBPG*2, &kv_any, &kp_zero, &kd_waitok); 3102 p = (void *)(va + NBPG - 7*sizeof(*idt)); 3103 3104 /* Copy over old IDT */ 3105 bcopy(idt, p, sizeof(idt_region)); 3106 idt = p; 3107 3108 /* Fix up paging redirect */ 3109 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386IGT, SEL_KPL, 3110 GCODE_SEL); 3111 3112 /* Map first page RO */ 3113 pmap_pte_setbits(va, 0, PG_RW); 3114 3115 /* add k-u read-only mappings XXX old IDT stays in place */ 3116 /* XXX hshoexer: are f00f affected CPUs affected by meltdown? */ 3117 pmap_extract(pmap_kernel(), va, &pa); 3118 pmap_enter_special(va, pa, PROT_READ, 0); 3119 pmap_extract(pmap_kernel(), va + PAGE_SIZE, &pa); 3120 pmap_enter_special(va + PAGE_SIZE, pa, PROT_READ, 0); 3121 3122 /* Reload idtr */ 3123 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3124 lidt(®ion); 3125 3126 /* Tell the rest of the world */ 3127 cpu_f00f_bug = 1; 3128 } 3129 3130 #ifdef MULTIPROCESSOR 3131 void 3132 cpu_init_idt(void) 3133 { 3134 struct region_descriptor region; 3135 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3136 lidt(®ion); 3137 } 3138 #endif /* MULTIPROCESSOR */ 3139 3140 void 3141 init386(paddr_t first_avail) 3142 { 3143 int i, kb; 3144 struct region_descriptor region; 3145 bios_memmap_t *im; 3146 3147 proc0.p_addr = proc0paddr; 3148 cpu_info_primary.ci_self = &cpu_info_primary; 3149 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb; 3150 cpu_info_primary.ci_tss = &cpu_info_full_primary.cif_tss; 3151 cpu_info_primary.ci_nmi_tss = &cpu_info_full_primary.cif_nmi_tss; 3152 cpu_info_primary.ci_gdt = (void *)&cpu_info_full_primary.cif_gdt; 3153 3154 /* make bootstrap gdt gates and memory segments */ 3155 setsegment(&cpu_info_primary.ci_gdt[GCODE_SEL].sd, 0, 0xfffff, 3156 SDT_MEMERA, SEL_KPL, 1, 1); 3157 setsegment(&cpu_info_primary.ci_gdt[GICODE_SEL].sd, 0, 0xfffff, 3158 SDT_MEMERA, SEL_KPL, 1, 1); 3159 setsegment(&cpu_info_primary.ci_gdt[GDATA_SEL].sd, 0, 0xfffff, 3160 SDT_MEMRWA, SEL_KPL, 1, 1); 3161 setsegment(&cpu_info_primary.ci_gdt[GUCODE_SEL].sd, 0, 3162 atop(I386_MAX_EXE_ADDR) - 1, SDT_MEMERA, SEL_UPL, 1, 1); 3163 setsegment(&cpu_info_primary.ci_gdt[GUDATA_SEL].sd, 0, 3164 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3165 setsegment(&cpu_info_primary.ci_gdt[GCPU_SEL].sd, &cpu_info_primary, 3166 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 0, 0); 3167 setsegment(&cpu_info_primary.ci_gdt[GUFS_SEL].sd, 0, 3168 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3169 setsegment(&cpu_info_primary.ci_gdt[GUGS_SEL].sd, 0, 3170 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3171 setsegment(&cpu_info_primary.ci_gdt[GTSS_SEL].sd, 3172 cpu_info_primary.ci_tss, sizeof(struct i386tss)-1, 3173 SDT_SYS386TSS, SEL_KPL, 0, 0); 3174 setsegment(&cpu_info_primary.ci_gdt[GNMITSS_SEL].sd, 3175 cpu_info_primary.ci_nmi_tss, sizeof(struct i386tss)-1, 3176 SDT_SYS386TSS, SEL_KPL, 0, 0); 3177 3178 /* exceptions */ 3179 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3180 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3181 setgate(&idt[ 2], NULL, 0, SDT_SYSTASKGT, SEL_KPL, GNMITSS_SEL); 3182 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3183 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3184 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3185 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3186 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3187 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3188 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3189 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3190 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3191 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3192 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3193 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3194 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3195 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3196 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3197 setgate(&idt[ 18], &IDTVEC(mchk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3198 setgate(&idt[ 19], &IDTVEC(simd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3199 for (i = 20; i < NRSVIDT; i++) 3200 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3201 for (i = NRSVIDT; i < NIDT; i++) 3202 unsetgate(&idt[i]); 3203 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3204 3205 setregion(®ion, cpu_info_primary.ci_gdt, GDT_SIZE - 1); 3206 lgdt(®ion); 3207 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3208 lidt(®ion); 3209 3210 /* 3211 * Initialize the I/O port and I/O mem extent maps. 3212 * Note: we don't have to check the return value since 3213 * creation of a fixed extent map will never fail (since 3214 * descriptor storage has already been allocated). 3215 * 3216 * N.B. The iomem extent manages _all_ physical addresses 3217 * on the machine. When the amount of RAM is found, the two 3218 * extents of RAM are allocated from the map (0 -> ISA hole 3219 * and end of ISA hole -> end of RAM). 3220 */ 3221 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF, 3222 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage), 3223 EX_NOCOALESCE|EX_NOWAIT); 3224 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF, 3225 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage), 3226 EX_NOCOALESCE|EX_NOWAIT); 3227 3228 #if NISA > 0 3229 isa_defaultirq(); 3230 #endif 3231 3232 /* 3233 * Attach the glass console early in case we need to display a panic. 3234 */ 3235 cninit(); 3236 3237 /* 3238 * Saving SSE registers won't work if the save area isn't 3239 * 16-byte aligned. 3240 */ 3241 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf) 3242 panic("init386: pcb_savefpu not 16-byte aligned"); 3243 3244 /* call pmap initialization to make new kernel address space */ 3245 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE); 3246 3247 /* 3248 * Boot arguments are in a single page specified by /boot. 3249 * 3250 * We require the "new" vector form, as well as memory ranges 3251 * to be given in bytes rather than KB. 3252 */ 3253 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) == 3254 (BAPIV_VECTOR | BAPIV_BMEMMAP)) { 3255 if (bootargc > NBPG) 3256 panic("too many boot args"); 3257 3258 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc, 3259 EX_NOWAIT)) 3260 panic("cannot reserve /boot args memory"); 3261 3262 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv, 3263 PROT_READ | PROT_WRITE, 3264 PROT_READ | PROT_WRITE | PMAP_WIRED); 3265 3266 bios_getopt(); 3267 3268 } else 3269 panic("/boot too old: upgrade!"); 3270 3271 #ifdef DIAGNOSTIC 3272 if (bios_memmap == NULL) 3273 panic("no BIOS memory map supplied"); 3274 #endif 3275 3276 /* 3277 * account all the memory passed in the map from /boot 3278 * calculate avail_end and count the physmem. 3279 */ 3280 avail_end = 0; 3281 physmem = 0; 3282 #ifdef DEBUG 3283 printf("memmap:"); 3284 #endif 3285 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++) 3286 if (im->type == BIOS_MAP_FREE) { 3287 paddr_t a, e; 3288 #ifdef DEBUG 3289 printf(" %llx-%llx", im->addr, im->addr + im->size); 3290 #endif 3291 3292 if (im->addr >= 0x100000000ULL) { 3293 #ifdef DEBUG 3294 printf("-H"); 3295 #endif 3296 continue; 3297 } 3298 3299 a = round_page(im->addr); 3300 if (im->addr + im->size <= 0xfffff000ULL) 3301 e = trunc_page(im->addr + im->size); 3302 else { 3303 #ifdef DEBUG 3304 printf("-T"); 3305 #endif 3306 e = 0xfffff000; 3307 } 3308 3309 /* skip first 16 pages due to SMI corruption */ 3310 if (a < 16 * NBPG) 3311 a = 16 * NBPG; 3312 3313 #ifdef MULTIPROCESSOR 3314 /* skip MP trampoline code page */ 3315 if (a < MP_TRAMPOLINE + NBPG) 3316 a = MP_TRAMPOLINE + NBPG; 3317 3318 /* skip MP trampoline data page */ 3319 if (a < MP_TRAMP_DATA + NBPG) 3320 a = MP_TRAMP_DATA + NBPG; 3321 #endif /* MULTIPROCESSOR */ 3322 3323 #if NACPI > 0 && !defined(SMALL_KERNEL) 3324 /* skip ACPI resume trampoline code page */ 3325 if (a < ACPI_TRAMPOLINE + NBPG) 3326 a = ACPI_TRAMPOLINE + NBPG; 3327 3328 /* skip ACPI resume trampoline data page */ 3329 if (a < ACPI_TRAMP_DATA + NBPG) 3330 a = ACPI_TRAMP_DATA + NBPG; 3331 #endif /* ACPI */ 3332 3333 #ifdef HIBERNATE 3334 /* skip hibernate reserved pages */ 3335 if (a < HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE) 3336 a = HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE; 3337 #endif /* HIBERNATE */ 3338 3339 /* skip shorter than page regions */ 3340 if (a >= e || (e - a) < NBPG) { 3341 #ifdef DEBUG 3342 printf("-S"); 3343 #endif 3344 continue; 3345 } 3346 3347 /* 3348 * XXX Some buggy ACPI BIOSes use memory that 3349 * they declare as free. Current worst offender 3350 * is Supermicro 5019D-FTN4. Typically the 3351 * affected memory areas are small blocks 3352 * between areas reserved for ACPI and other 3353 * BIOS goo. So skip areas smaller than 32 MB 3354 * above the 16 MB boundary (to avoid 3355 * affecting legacy stuff). 3356 */ 3357 if (a > 16*1024*1024 && (e - a) < 32*1024*1024) { 3358 #ifdef DEBUG 3359 printf("-X"); 3360 #endif 3361 continue; 3362 } 3363 3364 /* skip legacy IO region */ 3365 if ((a > IOM_BEGIN && a < IOM_END) || 3366 (e > IOM_BEGIN && e < IOM_END)) { 3367 #ifdef DEBUG 3368 printf("-I"); 3369 #endif 3370 continue; 3371 } 3372 3373 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT)) 3374 /* XXX What should we do? */ 3375 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)" 3376 " FROM IOMEM EXTENT MAP!\n", a, e); 3377 3378 physmem += atop(e - a); 3379 dumpmem[i].start = atop(a); 3380 dumpmem[i].end = atop(e); 3381 i++; 3382 avail_end = max(avail_end, e); 3383 } 3384 3385 ndumpmem = i; 3386 avail_end -= round_page(MSGBUFSIZE); 3387 3388 #ifdef DEBUG 3389 printf(": %lx\n", avail_end); 3390 #endif 3391 if (physmem < atop(4 * 1024 * 1024)) { 3392 printf("\awarning: too little memory available;" 3393 "running in degraded mode\npress a key to confirm\n\n"); 3394 cnpollc(1); 3395 cngetc(); 3396 cnpollc(0); 3397 } 3398 3399 #ifdef DEBUG 3400 printf("physload: "); 3401 #endif 3402 kb = atop(KERNTEXTOFF - KERNBASE); 3403 if (kb > atop(IOM_END)) { 3404 paddr_t lim = atop(IOM_END); 3405 #ifdef DEBUG 3406 printf(" %lx-%x (<16M)", lim, kb); 3407 #endif 3408 uvm_page_physload(lim, kb, lim, kb, 0); 3409 } 3410 3411 for (i = 0; i < ndumpmem; i++) { 3412 paddr_t a, e; 3413 3414 a = dumpmem[i].start; 3415 e = dumpmem[i].end; 3416 if (a < atop(first_avail) && e > atop(first_avail)) 3417 a = atop(first_avail); 3418 if (e > atop(avail_end)) 3419 e = atop(avail_end); 3420 3421 if (a < e) { 3422 #ifdef DEBUG 3423 printf(" %lx-%lx", a, e); 3424 #endif 3425 uvm_page_physload(a, e, a, e, 0); 3426 } 3427 } 3428 #ifdef DEBUG 3429 printf("\n"); 3430 #endif 3431 3432 tlbflush(); 3433 #if 0 3434 #if NISADMA > 0 3435 /* 3436 * Some motherboards/BIOSes remap the 384K of RAM that would 3437 * normally be covered by the ISA hole to the end of memory 3438 * so that it can be used. However, on a 16M system, this 3439 * would cause bounce buffers to be allocated and used. 3440 * This is not desirable behaviour, as more than 384K of 3441 * bounce buffers might be allocated. As a work-around, 3442 * we round memory down to the nearest 1M boundary if 3443 * we're using any isadma devices and the remapped memory 3444 * is what puts us over 16M. 3445 */ 3446 if (extmem > (15*1024) && extmem < (16*1024)) { 3447 printf("Warning: ignoring %dk of remapped memory\n", 3448 extmem - (15*1024)); 3449 extmem = (15*1024); 3450 } 3451 #endif 3452 #endif 3453 3454 #ifdef DDB 3455 db_machine_init(); 3456 ddb_init(); 3457 if (boothowto & RB_KDB) 3458 db_enter(); 3459 #endif 3460 3461 softintr_init(); 3462 } 3463 3464 /* 3465 * consinit: 3466 * initialize the system console. 3467 */ 3468 void 3469 consinit(void) 3470 { 3471 /* Already done in init386(). */ 3472 } 3473 3474 void 3475 cpu_reset(void) 3476 { 3477 struct region_descriptor region; 3478 3479 intr_disable(); 3480 3481 if (cpuresetfn) 3482 (*cpuresetfn)(); 3483 3484 /* 3485 * The keyboard controller has 4 random output pins, one of which is 3486 * connected to the RESET pin on the CPU in many PCs. We tell the 3487 * keyboard controller to pulse this line a couple of times. 3488 */ 3489 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3490 delay(100000); 3491 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3492 delay(100000); 3493 3494 /* 3495 * Try to cause a triple fault and watchdog reset by setting the 3496 * IDT to point to nothing. 3497 */ 3498 bzero((caddr_t)idt, sizeof(idt_region)); 3499 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3500 lidt(®ion); 3501 __asm volatile("divl %0,%1" : : "q" (0), "a" (0)); 3502 3503 /* 3504 * Try to cause a triple fault and watchdog reset by unmapping the 3505 * entire address space. 3506 */ 3507 bzero((caddr_t)PTD, NBPG); 3508 tlbflush(); 3509 3510 for (;;) 3511 continue; 3512 /* NOTREACHED */ 3513 } 3514 3515 void 3516 cpu_initclocks(void) 3517 { 3518 (*initclock_func)(); /* lapic or i8254 */ 3519 } 3520 3521 void 3522 need_resched(struct cpu_info *ci) 3523 { 3524 ci->ci_want_resched = 1; 3525 3526 /* There's a risk we'll be called before the idle threads start */ 3527 if (ci->ci_curproc) { 3528 aston(ci->ci_curproc); 3529 cpu_kick(ci); 3530 } 3531 } 3532 3533 /* Allocate an IDT vector slot within the given range. 3534 * XXX needs locking to avoid MP allocation races. 3535 */ 3536 3537 int 3538 idt_vec_alloc(int low, int high) 3539 { 3540 int vec; 3541 3542 for (vec = low; vec <= high; vec++) 3543 if (idt[vec].gd_p == 0) 3544 return (vec); 3545 return (0); 3546 } 3547 3548 void 3549 idt_vec_set(int vec, void (*function)(void)) 3550 { 3551 setgate(&idt[vec], function, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL); 3552 } 3553 3554 void 3555 idt_vec_free(int vec) 3556 { 3557 unsetgate(&idt[vec]); 3558 } 3559 3560 const struct sysctl_bounded_args cpuctl_vars[] = { 3561 { CPU_LIDACTION, &lid_action, 0, 2 }, 3562 { CPU_CPUID, &cpu_id, SYSCTL_INT_READONLY }, 3563 { CPU_OSFXSR, &i386_use_fxsave, SYSCTL_INT_READONLY }, 3564 { CPU_SSE, &i386_has_sse, SYSCTL_INT_READONLY }, 3565 { CPU_SSE2, &i386_has_sse2, SYSCTL_INT_READONLY }, 3566 { CPU_XCRYPT, &i386_has_xcrypt, SYSCTL_INT_READONLY }, 3567 }; 3568 3569 /* 3570 * machine dependent system variables. 3571 */ 3572 int 3573 cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 3574 size_t newlen, struct proc *p) 3575 { 3576 dev_t dev; 3577 3578 switch (name[0]) { 3579 case CPU_CONSDEV: 3580 if (namelen != 1) 3581 return (ENOTDIR); /* overloaded */ 3582 3583 if (cn_tab != NULL) 3584 dev = cn_tab->cn_dev; 3585 else 3586 dev = NODEV; 3587 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3588 #if NBIOS > 0 3589 case CPU_BIOS: 3590 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp, 3591 newp, newlen, p); 3592 #endif 3593 case CPU_BLK2CHR: 3594 if (namelen != 2) 3595 return (ENOTDIR); /* overloaded */ 3596 dev = blktochr((dev_t)name[1]); 3597 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3598 case CPU_CHR2BLK: 3599 if (namelen != 2) 3600 return (ENOTDIR); /* overloaded */ 3601 dev = chrtoblk((dev_t)name[1]); 3602 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3603 case CPU_ALLOWAPERTURE: 3604 #ifdef APERTURE 3605 if (securelevel > 0) 3606 return (sysctl_int_lower(oldp, oldlenp, newp, newlen, 3607 &allowaperture)); 3608 else 3609 return (sysctl_int(oldp, oldlenp, newp, newlen, 3610 &allowaperture)); 3611 #else 3612 return (sysctl_rdint(oldp, oldlenp, newp, 0)); 3613 #endif 3614 case CPU_CPUVENDOR: 3615 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor)); 3616 case CPU_CPUFEATURE: 3617 return (sysctl_rdint(oldp, oldlenp, newp, curcpu()->ci_feature_flags)); 3618 case CPU_KBDRESET: 3619 return (sysctl_securelevel_int(oldp, oldlenp, newp, newlen, 3620 &kbd_reset)); 3621 #if NPCKBC > 0 && NUKBD > 0 3622 case CPU_FORCEUKBD: 3623 { 3624 int error; 3625 3626 if (forceukbd) 3627 return (sysctl_rdint(oldp, oldlenp, newp, forceukbd)); 3628 3629 error = sysctl_int(oldp, oldlenp, newp, newlen, &forceukbd); 3630 if (forceukbd) 3631 pckbc_release_console(); 3632 return (error); 3633 } 3634 #endif 3635 default: 3636 return (sysctl_bounded_arr(cpuctl_vars, nitems(cpuctl_vars), 3637 name, namelen, oldp, oldlenp, newp, newlen)); 3638 } 3639 /* NOTREACHED */ 3640 } 3641 3642 int 3643 bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, 3644 bus_space_handle_t *bshp) 3645 { 3646 int error; 3647 struct extent *ex; 3648 3649 /* 3650 * Pick the appropriate extent map. 3651 */ 3652 if (t == I386_BUS_SPACE_IO) { 3653 ex = ioport_ex; 3654 if (flags & BUS_SPACE_MAP_LINEAR) 3655 return (EINVAL); 3656 } else if (t == I386_BUS_SPACE_MEM) { 3657 ex = iomem_ex; 3658 } else { 3659 panic("bus_space_map: bad bus space tag"); 3660 } 3661 3662 /* 3663 * Before we go any further, let's make sure that this 3664 * region is available. 3665 */ 3666 error = extent_alloc_region(ex, bpa, size, 3667 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0)); 3668 if (error) 3669 return (error); 3670 3671 /* 3672 * For I/O space, that's all she wrote. 3673 */ 3674 if (t == I386_BUS_SPACE_IO) { 3675 *bshp = bpa; 3676 return (0); 3677 } 3678 3679 if (IOM_BEGIN <= bpa && bpa <= IOM_END) { 3680 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa); 3681 return (0); 3682 } 3683 3684 /* 3685 * For memory space, map the bus physical address to 3686 * a kernel virtual address. 3687 */ 3688 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3689 if (error) { 3690 if (extent_free(ex, bpa, size, EX_NOWAIT | 3691 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3692 printf("bus_space_map: pa 0x%lx, size 0x%lx\n", 3693 bpa, size); 3694 printf("bus_space_map: can't free region\n"); 3695 } 3696 } 3697 3698 return (error); 3699 } 3700 3701 int 3702 _bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, 3703 int flags, bus_space_handle_t *bshp) 3704 { 3705 /* 3706 * For I/O space, that's all she wrote. 3707 */ 3708 if (t == I386_BUS_SPACE_IO) { 3709 *bshp = bpa; 3710 return (0); 3711 } 3712 3713 /* 3714 * For memory space, map the bus physical address to 3715 * a kernel virtual address. 3716 */ 3717 return (bus_mem_add_mapping(bpa, size, flags, bshp)); 3718 } 3719 3720 int 3721 bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, 3722 bus_size_t size, bus_size_t alignment, bus_size_t boundary, 3723 int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) 3724 { 3725 struct extent *ex; 3726 u_long bpa; 3727 int error; 3728 3729 /* 3730 * Pick the appropriate extent map. 3731 */ 3732 if (t == I386_BUS_SPACE_IO) { 3733 ex = ioport_ex; 3734 } else if (t == I386_BUS_SPACE_MEM) { 3735 ex = iomem_ex; 3736 } else { 3737 panic("bus_space_alloc: bad bus space tag"); 3738 } 3739 3740 /* 3741 * Sanity check the allocation against the extent's boundaries. 3742 */ 3743 if (rstart < ex->ex_start || rend > ex->ex_end) 3744 panic("bus_space_alloc: bad region start/end"); 3745 3746 /* 3747 * Do the requested allocation. 3748 */ 3749 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0, 3750 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0), 3751 &bpa); 3752 3753 if (error) 3754 return (error); 3755 3756 /* 3757 * For I/O space, that's all she wrote. 3758 */ 3759 if (t == I386_BUS_SPACE_IO) { 3760 *bshp = *bpap = bpa; 3761 return (0); 3762 } 3763 3764 /* 3765 * For memory space, map the bus physical address to 3766 * a kernel virtual address. 3767 */ 3768 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3769 if (error) { 3770 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT | 3771 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3772 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n", 3773 bpa, size); 3774 printf("bus_space_alloc: can't free region\n"); 3775 } 3776 } 3777 3778 *bpap = bpa; 3779 3780 return (error); 3781 } 3782 3783 int 3784 bus_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int flags, 3785 bus_space_handle_t *bshp) 3786 { 3787 paddr_t pa, endpa; 3788 vaddr_t va; 3789 bus_size_t map_size; 3790 int pmap_flags = PMAP_NOCACHE; 3791 3792 pa = trunc_page(bpa); 3793 endpa = round_page(bpa + size); 3794 3795 #ifdef DIAGNOSTIC 3796 if (endpa <= pa && endpa != 0) 3797 panic("bus_mem_add_mapping: overflow"); 3798 #endif 3799 3800 map_size = endpa - pa; 3801 3802 va = (vaddr_t)km_alloc(map_size, &kv_any, &kp_none, &kd_nowait); 3803 if (va == 0) 3804 return (ENOMEM); 3805 3806 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 3807 3808 if (flags & BUS_SPACE_MAP_CACHEABLE) 3809 pmap_flags = 0; 3810 else if (flags & BUS_SPACE_MAP_PREFETCHABLE) 3811 pmap_flags = PMAP_WC; 3812 3813 for (; map_size > 0; 3814 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE) 3815 pmap_kenter_pa(va, pa | pmap_flags, 3816 PROT_READ | PROT_WRITE); 3817 pmap_update(pmap_kernel()); 3818 3819 return 0; 3820 } 3821 3822 void 3823 bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3824 { 3825 struct extent *ex; 3826 u_long va, endva; 3827 bus_addr_t bpa; 3828 3829 /* 3830 * Find the correct extent and bus physical address. 3831 */ 3832 if (t == I386_BUS_SPACE_IO) { 3833 ex = ioport_ex; 3834 bpa = bsh; 3835 } else if (t == I386_BUS_SPACE_MEM) { 3836 ex = iomem_ex; 3837 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3838 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3839 goto ok; 3840 3841 va = trunc_page(bsh); 3842 endva = round_page(bsh + size); 3843 3844 #ifdef DIAGNOSTIC 3845 if (endva <= va) 3846 panic("bus_space_unmap: overflow"); 3847 #endif 3848 3849 (void) pmap_extract(pmap_kernel(), va, &bpa); 3850 bpa += (bsh & PGOFSET); 3851 3852 pmap_kremove(va, endva - va); 3853 pmap_update(pmap_kernel()); 3854 3855 /* 3856 * Free the kernel virtual mapping. 3857 */ 3858 km_free((void *)va, endva - va, &kv_any, &kp_none); 3859 } else 3860 panic("bus_space_unmap: bad bus space tag"); 3861 3862 ok: 3863 if (extent_free(ex, bpa, size, 3864 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3865 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n", 3866 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size); 3867 printf("bus_space_unmap: can't free region\n"); 3868 } 3869 } 3870 3871 void 3872 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size, 3873 bus_addr_t *adrp) 3874 { 3875 u_long va, endva; 3876 bus_addr_t bpa; 3877 3878 /* 3879 * Find the correct bus physical address. 3880 */ 3881 if (t == I386_BUS_SPACE_IO) { 3882 bpa = bsh; 3883 } else if (t == I386_BUS_SPACE_MEM) { 3884 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3885 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3886 goto ok; 3887 3888 va = trunc_page(bsh); 3889 endva = round_page(bsh + size); 3890 3891 #ifdef DIAGNOSTIC 3892 if (endva <= va) 3893 panic("_bus_space_unmap: overflow"); 3894 #endif 3895 3896 (void) pmap_extract(pmap_kernel(), va, &bpa); 3897 bpa += (bsh & PGOFSET); 3898 3899 pmap_kremove(va, endva - va); 3900 pmap_update(pmap_kernel()); 3901 3902 /* 3903 * Free the kernel virtual mapping. 3904 */ 3905 km_free((void *)va, endva - va, &kv_any, &kp_none); 3906 } else 3907 panic("bus_space_unmap: bad bus space tag"); 3908 3909 ok: 3910 if (adrp != NULL) 3911 *adrp = bpa; 3912 } 3913 3914 void 3915 bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3916 { 3917 3918 /* bus_space_unmap() does all that we need to do. */ 3919 bus_space_unmap(t, bsh, size); 3920 } 3921 3922 int 3923 bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 3924 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 3925 { 3926 *nbshp = bsh + offset; 3927 return (0); 3928 } 3929 3930 paddr_t 3931 bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags) 3932 { 3933 /* Can't mmap I/O space. */ 3934 if (t == I386_BUS_SPACE_IO) 3935 return (-1); 3936 3937 return (addr + off); 3938 } 3939 3940 #ifdef DIAGNOSTIC 3941 void 3942 splassert_check(int wantipl, const char *func) 3943 { 3944 if (lapic_tpr < wantipl) 3945 splassert_fail(wantipl, lapic_tpr, func); 3946 if (wantipl == IPL_NONE && curcpu()->ci_idepth != 0) 3947 splassert_fail(-1, curcpu()->ci_idepth, func); 3948 } 3949 #endif 3950 3951 int 3952 copyin32(const uint32_t *uaddr, uint32_t *kaddr) 3953 { 3954 if ((vaddr_t)uaddr & 0x3) 3955 return EFAULT; 3956 3957 /* copyin(9) is atomic */ 3958 return copyin(uaddr, kaddr, sizeof(uint32_t)); 3959 } 3960 3961 /* 3962 * True if the system has any non-level interrupts which are shared 3963 * on the same pin. 3964 */ 3965 int intr_shared_edge; 3966 3967 /* 3968 * Software interrupt registration 3969 * 3970 * We hand-code this to ensure that it's atomic. 3971 */ 3972 void 3973 softintr(int sir) 3974 { 3975 struct cpu_info *ci = curcpu(); 3976 3977 __asm volatile("orl %1, %0" : 3978 "=m" (ci->ci_ipending) : "ir" (1 << sir)); 3979 } 3980 3981 /* 3982 * Raise current interrupt priority level, and return the old one. 3983 */ 3984 int 3985 splraise(int ncpl) 3986 { 3987 int ocpl; 3988 3989 KASSERT(ncpl >= IPL_NONE); 3990 3991 _SPLRAISE(ocpl, ncpl); 3992 return (ocpl); 3993 } 3994 3995 /* 3996 * Restore an old interrupt priority level. If any thereby unmasked 3997 * interrupts are pending, call Xspllower() to process them. 3998 */ 3999 void 4000 splx(int ncpl) 4001 { 4002 _SPLX(ncpl); 4003 } 4004 4005 /* 4006 * Same as splx(), but we return the old value of spl, for the 4007 * benefit of some splsoftclock() callers. 4008 */ 4009 int 4010 spllower(int ncpl) 4011 { 4012 int ocpl = lapic_tpr; 4013 4014 splx(ncpl); 4015 return (ocpl); 4016 } 4017 4018 int 4019 intr_handler(struct intrframe *frame, struct intrhand *ih) 4020 { 4021 int rc; 4022 #ifdef MULTIPROCESSOR 4023 int need_lock; 4024 4025 if (ih->ih_flags & IPL_MPSAFE) 4026 need_lock = 0; 4027 else 4028 need_lock = 1; 4029 4030 if (need_lock) 4031 __mp_lock(&kernel_lock); 4032 #endif 4033 rc = (*ih->ih_fun)(ih->ih_arg ? ih->ih_arg : frame); 4034 #ifdef MULTIPROCESSOR 4035 if (need_lock) 4036 __mp_unlock(&kernel_lock); 4037 #endif 4038 return rc; 4039 } 4040 4041 void 4042 intr_barrier(void *ih) 4043 { 4044 sched_barrier(NULL); 4045 } 4046 4047 unsigned int 4048 cpu_rnd_messybits(void) 4049 { 4050 struct timespec ts; 4051 4052 nanotime(&ts); 4053 return (ts.tv_nsec ^ (ts.tv_sec << 20)); 4054 } 4055