1 /* $OpenBSD: machdep.c,v 1.534 2014/03/22 06:05:45 guenther Exp $ */ 2 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 36 * Copyright (c) 1992 Terrence R. Lambert. 37 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to Berkeley by 41 * William Jolitz. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/signalvar.h> 73 #include <sys/kernel.h> 74 #include <sys/proc.h> 75 #include <sys/user.h> 76 #include <sys/exec.h> 77 #include <sys/buf.h> 78 #include <sys/reboot.h> 79 #include <sys/conf.h> 80 #include <sys/file.h> 81 #include <sys/timeout.h> 82 #include <sys/malloc.h> 83 #include <sys/mbuf.h> 84 #include <sys/msgbuf.h> 85 #include <sys/mount.h> 86 #include <sys/vnode.h> 87 #include <sys/device.h> 88 #include <sys/extent.h> 89 #include <sys/sysctl.h> 90 #include <sys/syscallargs.h> 91 #include <sys/core.h> 92 #include <sys/kcore.h> 93 #include <sys/sensors.h> 94 95 #ifdef KGDB 96 #include <sys/kgdb.h> 97 #endif 98 99 #include <dev/cons.h> 100 #include <stand/boot/bootarg.h> 101 102 #include <net/if.h> 103 #include <uvm/uvm_extern.h> 104 #include <uvm/uvm_swap.h> 105 106 #include <machine/bus.h> 107 108 #include <machine/cpu.h> 109 #include <machine/cpufunc.h> 110 #include <machine/cpuvar.h> 111 #include <machine/gdt.h> 112 #include <machine/kcore.h> 113 #include <machine/pio.h> 114 #include <machine/bus.h> 115 #include <machine/psl.h> 116 #include <machine/reg.h> 117 #include <machine/specialreg.h> 118 #include <machine/biosvar.h> 119 #ifdef MULTIPROCESSOR 120 #include <machine/mpbiosvar.h> 121 #endif /* MULTIPROCESSOR */ 122 123 #include <dev/rndvar.h> 124 #include <dev/isa/isareg.h> 125 #include <dev/isa/isavar.h> 126 #include <dev/ic/i8042reg.h> 127 #include <dev/ic/mc146818reg.h> 128 #include <i386/isa/isa_machdep.h> 129 #include <i386/isa/nvram.h> 130 131 #include "acpi.h" 132 #if NACPI > 0 133 #include <dev/acpi/acpivar.h> 134 #endif 135 136 #include "apm.h" 137 #if NAPM > 0 138 #include <machine/apmvar.h> 139 #endif 140 141 #ifdef DDB 142 #include <machine/db_machdep.h> 143 #include <ddb/db_access.h> 144 #include <ddb/db_sym.h> 145 #include <ddb/db_extern.h> 146 #endif 147 148 #ifdef VM86 149 #include <machine/vm86.h> 150 #endif 151 152 #include "isa.h" 153 #include "isadma.h" 154 #include "npx.h" 155 #if NNPX > 0 156 extern struct proc *npxproc; 157 #endif 158 159 #include "bios.h" 160 #include "com.h" 161 162 #if NCOM > 0 163 #include <sys/termios.h> 164 #include <dev/ic/comreg.h> 165 #include <dev/ic/comvar.h> 166 #endif /* NCOM > 0 */ 167 168 #ifdef HIBERNATE 169 #include <machine/hibernate_var.h> 170 #endif /* HIBERNATE */ 171 172 173 void replacesmap(void); 174 int intr_handler(struct intrframe *, struct intrhand *); 175 176 /* the following is used externally (sysctl_hw) */ 177 char machine[] = MACHINE; 178 179 /* 180 * switchto vectors 181 */ 182 void (*cpu_idle_leave_fcn)(void) = NULL; 183 void (*cpu_idle_cycle_fcn)(void) = NULL; 184 void (*cpu_idle_enter_fcn)(void) = NULL; 185 186 /* 187 * Declare these as initialized data so we can patch them. 188 */ 189 #if NAPM > 0 190 int cpu_apmhalt = 0; /* sysctl'd to 1 for halt -p hack */ 191 #endif 192 193 #ifdef USER_LDT 194 int user_ldt_enable = 0; /* sysctl'd to 1 to enable */ 195 #endif 196 197 struct uvm_constraint_range isa_constraint = { 0x0, 0x00ffffffUL }; 198 struct uvm_constraint_range dma_constraint = { 0x0, 0xffffffffUL }; 199 struct uvm_constraint_range *uvm_md_constraints[] = { 200 &isa_constraint, 201 &dma_constraint, 202 NULL 203 }; 204 205 extern int boothowto; 206 int physmem; 207 208 struct dumpmem dumpmem[VM_PHYSSEG_MAX]; 209 u_int ndumpmem; 210 211 /* 212 * These variables are needed by /sbin/savecore 213 */ 214 u_long dumpmag = 0x8fca0101; /* magic number */ 215 int dumpsize = 0; /* pages */ 216 long dumplo = 0; /* blocks */ 217 218 int cpu_class; 219 int i386_fpu_present; 220 int i386_fpu_exception; 221 int i386_fpu_fdivbug; 222 223 int i386_use_fxsave; 224 int i386_has_sse; 225 int i386_has_sse2; 226 int i386_has_xcrypt; 227 228 bootarg_t *bootargp; 229 paddr_t avail_end; 230 231 struct vm_map *exec_map = NULL; 232 struct vm_map *phys_map = NULL; 233 234 #if !defined(SMALL_KERNEL) 235 int p4_model; 236 int p3_early; 237 void (*update_cpuspeed)(void) = NULL; 238 void via_update_sensor(void *args); 239 #endif 240 int kbd_reset; 241 int lid_suspend; 242 243 /* 244 * safepri is a safe priority for sleep to set for a spin-wait 245 * during autoconfiguration or after a panic. 246 */ 247 int safepri = 0; 248 249 #if !defined(SMALL_KERNEL) 250 int bus_clock; 251 #endif 252 void (*setperf_setup)(struct cpu_info *); 253 int setperf_prio = 0; /* for concurrent handlers */ 254 255 void (*cpusensors_setup)(struct cpu_info *); 256 257 void (*delay_func)(int) = i8254_delay; 258 void (*initclock_func)(void) = i8254_initclocks; 259 260 /* 261 * Extent maps to manage I/O and ISA memory hole space. Allocate 262 * storage for 16 regions in each, initially. Later, ioport_malloc_safe 263 * will indicate that it's safe to use malloc() to dynamically allocate 264 * region descriptors. 265 * 266 * N.B. At least two regions are _always_ allocated from the iomem 267 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM). 268 * 269 * The extent maps are not static! Machine-dependent ISA and EISA 270 * routines need access to them for bus address space allocation. 271 */ 272 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 273 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 274 struct extent *ioport_ex; 275 struct extent *iomem_ex; 276 static int ioport_malloc_safe; 277 278 void dumpsys(void); 279 int cpu_dump(void); 280 void init386(paddr_t); 281 void consinit(void); 282 void (*cpuresetfn)(void); 283 284 int bus_mem_add_mapping(bus_addr_t, bus_size_t, 285 int, bus_space_handle_t *); 286 287 #ifdef KGDB 288 #ifndef KGDB_DEVNAME 289 #define KGDB_DEVNAME "com" 290 #endif /* KGDB_DEVNAME */ 291 char kgdb_devname[] = KGDB_DEVNAME; 292 #if NCOM > 0 293 #ifndef KGDBADDR 294 #define KGDBADDR 0x3f8 295 #endif 296 int comkgdbaddr = KGDBADDR; 297 #ifndef KGDBRATE 298 #define KGDBRATE TTYDEF_SPEED 299 #endif 300 int comkgdbrate = KGDBRATE; 301 #ifndef KGDBMODE 302 #define KGDBMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 303 #endif 304 int comkgdbmode = KGDBMODE; 305 #endif /* NCOM > 0 */ 306 void kgdb_port_init(void); 307 #endif /* KGDB */ 308 309 #ifdef APERTURE 310 #ifdef INSECURE 311 int allowaperture = 1; 312 #else 313 int allowaperture = 0; 314 #endif 315 #endif 316 317 int has_rdrand; 318 319 void winchip_cpu_setup(struct cpu_info *); 320 void amd_family5_setperf_setup(struct cpu_info *); 321 void amd_family5_setup(struct cpu_info *); 322 void amd_family6_setperf_setup(struct cpu_info *); 323 void amd_family6_setup(struct cpu_info *); 324 void cyrix3_setperf_setup(struct cpu_info *); 325 void cyrix3_cpu_setup(struct cpu_info *); 326 void cyrix6x86_cpu_setup(struct cpu_info *); 327 void natsem6x86_cpu_setup(struct cpu_info *); 328 void intel586_cpu_setup(struct cpu_info *); 329 void intel686_cpusensors_setup(struct cpu_info *); 330 void intel686_setperf_setup(struct cpu_info *); 331 void intel686_common_cpu_setup(struct cpu_info *); 332 void intel686_cpu_setup(struct cpu_info *); 333 void intel686_p4_cpu_setup(struct cpu_info *); 334 void intelcore_update_sensor(void *); 335 void tm86_cpu_setup(struct cpu_info *); 336 char * intel686_cpu_name(int); 337 char * cyrix3_cpu_name(int, int); 338 char * tm86_cpu_name(int); 339 void cyrix3_get_bus_clock(struct cpu_info *); 340 void p4_get_bus_clock(struct cpu_info *); 341 void p3_get_bus_clock(struct cpu_info *); 342 void p4_update_cpuspeed(void); 343 void p3_update_cpuspeed(void); 344 int pentium_cpuspeed(int *); 345 346 static __inline u_char 347 cyrix_read_reg(u_char reg) 348 { 349 outb(0x22, reg); 350 return inb(0x23); 351 } 352 353 static __inline void 354 cyrix_write_reg(u_char reg, u_char data) 355 { 356 outb(0x22, reg); 357 outb(0x23, data); 358 } 359 360 /* 361 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx. 362 * requires caller to provide u_int32_t regs[4] array. 363 */ 364 void 365 cpuid(u_int32_t ax, u_int32_t *regs) 366 { 367 __asm __volatile( 368 "cpuid\n\t" 369 "movl %%eax, 0(%2)\n\t" 370 "movl %%ebx, 4(%2)\n\t" 371 "movl %%ecx, 8(%2)\n\t" 372 "movl %%edx, 12(%2)\n\t" 373 :"=a" (ax) 374 :"0" (ax), "S" (regs) 375 :"bx", "cx", "dx"); 376 } 377 378 /* 379 * Machine-dependent startup code 380 */ 381 void 382 cpu_startup() 383 { 384 unsigned i; 385 vaddr_t minaddr, maxaddr, va; 386 paddr_t pa; 387 388 /* 389 * Initialize error message buffer (at end of core). 390 * (space reserved in pmap_bootstrap) 391 */ 392 pa = avail_end; 393 va = (vaddr_t)msgbufp; 394 for (i = 0; i < atop(MSGBUFSIZE); i++) { 395 pmap_kenter_pa(va, pa, VM_PROT_READ|VM_PROT_WRITE); 396 va += PAGE_SIZE; 397 pa += PAGE_SIZE; 398 } 399 pmap_update(pmap_kernel()); 400 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); 401 402 printf("%s", version); 403 startclocks(); 404 405 /* 406 * We need to call identifycpu here early, so users have at least some 407 * basic information, if booting hangs later on. 408 */ 409 strlcpy(curcpu()->ci_dev.dv_xname, "cpu0", 410 sizeof(curcpu()->ci_dev.dv_xname)); 411 curcpu()->ci_signature = cpu_id; 412 curcpu()->ci_feature_flags = cpu_feature; 413 identifycpu(curcpu()); 414 415 printf("real mem = %llu (%lluMB)\n", 416 (unsigned long long)ptoa((psize_t)physmem), 417 (unsigned long long)ptoa((psize_t)physmem)/1024U/1024U); 418 419 /* 420 * Allocate a submap for exec arguments. This map effectively 421 * limits the number of processes exec'ing at any time. 422 */ 423 minaddr = vm_map_min(kernel_map); 424 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 425 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 426 427 /* 428 * Allocate a submap for physio 429 */ 430 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 431 VM_PHYS_SIZE, 0, FALSE, NULL); 432 433 printf("avail mem = %llu (%lluMB)\n", 434 (unsigned long long)ptoa((psize_t)uvmexp.free), 435 (unsigned long long)ptoa((psize_t)uvmexp.free)/1024U/1024U); 436 437 /* 438 * Set up buffers, so they can be used to read disk labels. 439 */ 440 bufinit(); 441 442 /* 443 * Configure the system. 444 */ 445 if (boothowto & RB_CONFIG) { 446 #ifdef BOOT_CONFIG 447 user_config(); 448 #else 449 printf("kernel does not support -c; continuing..\n"); 450 #endif 451 } 452 ioport_malloc_safe = 1; 453 } 454 455 /* 456 * Set up proc0's TSS and LDT. 457 */ 458 void 459 i386_proc0_tss_ldt_init() 460 { 461 int x; 462 struct pcb *pcb; 463 464 curpcb = pcb = &proc0.p_addr->u_pcb; 465 466 pcb->pcb_tss.tss_ioopt = 467 ((caddr_t)pcb->pcb_iomap - (caddr_t)&pcb->pcb_tss) << 16; 468 for (x = 0; x < sizeof(pcb->pcb_iomap) / 4; x++) 469 pcb->pcb_iomap[x] = 0xffffffff; 470 pcb->pcb_iomap_pad = 0xff; 471 472 pcb->pcb_ldt_sel = pmap_kernel()->pm_ldt_sel = GSEL(GLDT_SEL, SEL_KPL); 473 pcb->pcb_ldt = ldt; 474 pcb->pcb_cr0 = rcr0(); 475 pcb->pcb_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL); 476 pcb->pcb_tss.tss_esp0 = (int)proc0.p_addr + USPACE - 16; 477 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_tss.tss_esp0 - 1; 478 proc0.p_md.md_tss_sel = tss_alloc(pcb); 479 480 ltr(proc0.p_md.md_tss_sel); 481 lldt(pcb->pcb_ldt_sel); 482 } 483 484 #ifdef MULTIPROCESSOR 485 void 486 i386_init_pcb_tss_ldt(struct cpu_info *ci) 487 { 488 int x; 489 struct pcb *pcb = ci->ci_idle_pcb; 490 491 pcb->pcb_tss.tss_ioopt = 492 ((caddr_t)pcb->pcb_iomap - (caddr_t)&pcb->pcb_tss) << 16; 493 for (x = 0; x < sizeof(pcb->pcb_iomap) / 4; x++) 494 pcb->pcb_iomap[x] = 0xffffffff; 495 pcb->pcb_iomap_pad = 0xff; 496 497 pcb->pcb_ldt_sel = pmap_kernel()->pm_ldt_sel = GSEL(GLDT_SEL, SEL_KPL); 498 pcb->pcb_ldt = ci->ci_ldt; 499 pcb->pcb_cr0 = rcr0(); 500 ci->ci_idle_tss_sel = tss_alloc(pcb); 501 } 502 #endif /* MULTIPROCESSOR */ 503 504 /* 505 * Info for CTL_HW 506 */ 507 char cpu_model[120]; 508 509 /* 510 * Note: these are just the ones that may not have a cpuid instruction. 511 * We deal with the rest in a different way. 512 */ 513 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 514 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 515 NULL}, /* CPU_386SX */ 516 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 517 NULL}, /* CPU_386 */ 518 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 519 NULL}, /* CPU_486SX */ 520 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 521 NULL}, /* CPU_486 */ 522 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 523 NULL}, /* CPU_486DLC */ 524 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 525 cyrix6x86_cpu_setup}, /* CPU_6x86 */ 526 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 527 NULL}, /* CPU_NX586 */ 528 }; 529 530 const char *classnames[] = { 531 "386", 532 "486", 533 "586", 534 "686" 535 }; 536 537 const char *modifiers[] = { 538 "", 539 "OverDrive ", 540 "Dual ", 541 "" 542 }; 543 544 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 545 { 546 "GenuineIntel", 547 CPUVENDOR_INTEL, 548 "Intel", 549 /* Family 4 */ 550 { { 551 CPUCLASS_486, 552 { 553 "486DX", "486DX", "486SX", "486DX2", "486SL", 554 "486SX2", 0, "486DX2 W/B", 555 "486DX4", 0, 0, 0, 0, 0, 0, 0, 556 "486" /* Default */ 557 }, 558 NULL 559 }, 560 /* Family 5 */ 561 { 562 CPUCLASS_586, 563 { 564 "Pentium (A-step)", "Pentium (P5)", 565 "Pentium (P54C)", "Pentium (P24T)", 566 "Pentium/MMX", "Pentium", 0, 567 "Pentium (P54C)", "Pentium/MMX", 568 0, 0, 0, 0, 0, 0, 0, 569 "Pentium" /* Default */ 570 }, 571 intel586_cpu_setup 572 }, 573 /* Family 6 */ 574 { 575 CPUCLASS_686, 576 { 577 "Pentium Pro", "Pentium Pro", 0, 578 "Pentium II", "Pentium Pro", 579 "Pentium II/Celeron", 580 "Celeron", 581 "Pentium III", 582 "Pentium III", 583 "Pentium M", 584 "Pentium III Xeon", 585 "Pentium III", 0, 586 "Pentium M", 587 "Core Duo/Solo", 0, 588 "Pentium Pro, II or III" /* Default */ 589 }, 590 intel686_cpu_setup 591 }, 592 /* Family 7 */ 593 { 594 CPUCLASS_686, 595 } , 596 /* Family 8 */ 597 { 598 CPUCLASS_686, 599 } , 600 /* Family 9 */ 601 { 602 CPUCLASS_686, 603 } , 604 /* Family A */ 605 { 606 CPUCLASS_686, 607 } , 608 /* Family B */ 609 { 610 CPUCLASS_686, 611 } , 612 /* Family C */ 613 { 614 CPUCLASS_686, 615 } , 616 /* Family D */ 617 { 618 CPUCLASS_686, 619 } , 620 /* Family E */ 621 { 622 CPUCLASS_686, 623 } , 624 /* Family F */ 625 { 626 CPUCLASS_686, 627 { 628 "Pentium 4", 0, 0, 0, 629 0, 0, 0, 0, 630 0, 0, 0, 0, 631 0, 0, 0, 0, 632 "Pentium 4" /* Default */ 633 }, 634 intel686_p4_cpu_setup 635 } } 636 }, 637 { 638 "AuthenticAMD", 639 CPUVENDOR_AMD, 640 "AMD", 641 /* Family 4 */ 642 { { 643 CPUCLASS_486, 644 { 645 0, 0, 0, "Am486DX2 W/T", 646 0, 0, 0, "Am486DX2 W/B", 647 "Am486DX4 W/T or Am5x86 W/T 150", 648 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 649 0, 0, "Am5x86 W/T 133/160", 650 "Am5x86 W/B 133/160", 651 "Am486 or Am5x86" /* Default */ 652 }, 653 NULL 654 }, 655 /* Family 5 */ 656 { 657 CPUCLASS_586, 658 { 659 "K5", "K5", "K5", "K5", 0, 0, "K6", 660 "K6", "K6-2", "K6-III", 0, 0, 0, 661 "K6-2+/III+", 0, 0, 662 "K5 or K6" /* Default */ 663 }, 664 amd_family5_setup 665 }, 666 /* Family 6 */ 667 { 668 CPUCLASS_686, 669 { 670 0, "Athlon Model 1", "Athlon Model 2", 671 "Duron Model 3", 672 "Athlon Model 4", 673 0, "Athlon XP Model 6", 674 "Duron Model 7", 675 "Athlon XP Model 8", 676 0, "Athlon XP Model 10", 677 0, 0, 0, 0, 0, 678 "K7" /* Default */ 679 }, 680 amd_family6_setup 681 }, 682 /* Family 7 */ 683 { 684 CPUCLASS_686, 685 } , 686 /* Family 8 */ 687 { 688 CPUCLASS_686, 689 } , 690 /* Family 9 */ 691 { 692 CPUCLASS_686, 693 } , 694 /* Family A */ 695 { 696 CPUCLASS_686, 697 } , 698 /* Family B */ 699 { 700 CPUCLASS_686, 701 } , 702 /* Family C */ 703 { 704 CPUCLASS_686, 705 } , 706 /* Family D */ 707 { 708 CPUCLASS_686, 709 } , 710 /* Family E */ 711 { 712 CPUCLASS_686, 713 } , 714 /* Family F */ 715 { 716 CPUCLASS_686, 717 { 718 0, 0, 0, 0, "Athlon64", 719 "Opteron or Athlon64FX", 0, 0, 720 0, 0, 0, 0, 0, 0, 0, 0, 721 "AMD64" /* DEFAULT */ 722 }, 723 amd_family6_setup 724 } } 725 }, 726 { 727 "CyrixInstead", 728 CPUVENDOR_CYRIX, 729 "Cyrix", 730 /* Family 4 */ 731 { { 732 CPUCLASS_486, 733 { 734 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0, 735 0, 0, 0, 0, 736 "486 class" /* Default */ 737 }, 738 NULL 739 }, 740 /* Family 5 */ 741 { 742 CPUCLASS_586, 743 { 744 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0, 745 0, 0, 0, 0, 0, 0, 746 "586 class" /* Default */ 747 }, 748 cyrix6x86_cpu_setup 749 }, 750 /* Family 6 */ 751 { 752 CPUCLASS_686, 753 { 754 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 755 0, 0, 0, 0, 756 "686 class" /* Default */ 757 }, 758 NULL 759 } } 760 }, 761 { 762 "CentaurHauls", 763 CPUVENDOR_IDT, 764 "IDT", 765 /* Family 4, not available from IDT */ 766 { { 767 CPUCLASS_486, 768 { 769 0, 0, 0, 0, 0, 0, 0, 0, 770 0, 0, 0, 0, 0, 0, 0, 0, 771 "486 class" /* Default */ 772 }, 773 NULL 774 }, 775 /* Family 5 */ 776 { 777 CPUCLASS_586, 778 { 779 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 780 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 781 "WinChip" /* Default */ 782 }, 783 winchip_cpu_setup 784 }, 785 /* Family 6 */ 786 { 787 CPUCLASS_686, 788 { 789 0, 0, 0, 0, 0, 0, 790 "C3 Samuel", 791 "C3 Samuel 2/Ezra", 792 "C3 Ezra-T", 793 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0, 794 "C3" /* Default */ 795 }, 796 cyrix3_cpu_setup 797 } } 798 }, 799 { 800 "RiseRiseRise", 801 CPUVENDOR_RISE, 802 "Rise", 803 /* Family 4, not available from Rise */ 804 { { 805 CPUCLASS_486, 806 { 807 0, 0, 0, 0, 0, 0, 0, 0, 808 0, 0, 0, 0, 0, 0, 0, 0, 809 "486 class" /* Default */ 810 }, 811 NULL 812 }, 813 /* Family 5 */ 814 { 815 CPUCLASS_586, 816 { 817 "mP6", 0, "mP6", 0, 0, 0, 0, 0, 818 0, 0, 0, 0, 0, 0, 0, 0, 819 "mP6" /* Default */ 820 }, 821 NULL 822 }, 823 /* Family 6, not yet available from Rise */ 824 { 825 CPUCLASS_686, 826 { 827 0, 0, 0, 0, 0, 0, 0, 0, 828 0, 0, 0, 0, 0, 0, 0, 0, 829 "686 class" /* Default */ 830 }, 831 NULL 832 } } 833 }, 834 { 835 "GenuineTMx86", 836 CPUVENDOR_TRANSMETA, 837 "Transmeta", 838 /* Family 4, not available from Transmeta */ 839 { { 840 CPUCLASS_486, 841 { 842 0, 0, 0, 0, 0, 0, 0, 0, 843 0, 0, 0, 0, 0, 0, 0, 0, 844 "486 class" /* Default */ 845 }, 846 NULL 847 }, 848 /* Family 5 */ 849 { 850 CPUCLASS_586, 851 { 852 0, 0, 0, 0, "TMS5x00", 0, 0, 853 0, 0, 0, 0, 0, 0, 0, 0, 0, 854 "TMS5x00" /* Default */ 855 }, 856 tm86_cpu_setup 857 }, 858 /* Family 6, not yet available from Transmeta */ 859 { 860 CPUCLASS_686, 861 { 862 0, 0, 0, 0, 0, 0, 0, 0, 863 0, 0, 0, 0, 0, 0, 0, 0, 864 "686 class" /* Default */ 865 }, 866 NULL 867 }, 868 /* Family 7 */ 869 { 870 CPUCLASS_686, 871 } , 872 /* Family 8 */ 873 { 874 CPUCLASS_686, 875 } , 876 /* Family 9 */ 877 { 878 CPUCLASS_686, 879 } , 880 /* Family A */ 881 { 882 CPUCLASS_686, 883 } , 884 /* Family B */ 885 { 886 CPUCLASS_686, 887 } , 888 /* Family C */ 889 { 890 CPUCLASS_686, 891 } , 892 /* Family D */ 893 { 894 CPUCLASS_686, 895 } , 896 /* Family E */ 897 { 898 CPUCLASS_686, 899 } , 900 /* Family F */ 901 { 902 /* Extended processor family - Transmeta Efficeon */ 903 CPUCLASS_686, 904 { 905 0, 0, "TM8000", "TM8000", 906 0, 0, 0, 0, 907 0, 0, 0, 0, 908 0, 0, 0, 0, 909 "TM8000" /* Default */ 910 }, 911 tm86_cpu_setup 912 } } 913 }, 914 { 915 "Geode by NSC", 916 CPUVENDOR_NS, 917 "National Semiconductor", 918 /* Family 4, not available from National Semiconductor */ 919 { { 920 CPUCLASS_486, 921 { 922 0, 0, 0, 0, 0, 0, 0, 0, 923 0, 0, 0, 0, 0, 0, 0, 0, 924 "486 class" /* Default */ 925 }, 926 NULL 927 }, 928 /* Family 5 */ 929 { 930 CPUCLASS_586, 931 { 932 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0, 933 0, 0, 0, 0, 0, 0, 934 "586 class" /* Default */ 935 }, 936 natsem6x86_cpu_setup 937 } } 938 }, 939 { 940 "SiS SiS SiS ", 941 CPUVENDOR_SIS, 942 "SiS", 943 /* Family 4, not available from SiS */ 944 { { 945 CPUCLASS_486, 946 { 947 0, 0, 0, 0, 0, 0, 0, 0, 948 0, 0, 0, 0, 0, 0, 0, 0, 949 "486 class" /* Default */ 950 }, 951 NULL 952 }, 953 /* Family 5 */ 954 { 955 CPUCLASS_586, 956 { 957 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0, 958 0, 0, 0, 0, 0, 0, 959 "586 class" /* Default */ 960 }, 961 NULL 962 } } 963 } 964 }; 965 966 const struct cpu_cpuid_feature i386_cpuid_features[] = { 967 { CPUID_FPU, "FPU" }, 968 { CPUID_VME, "V86" }, 969 { CPUID_DE, "DE" }, 970 { CPUID_PSE, "PSE" }, 971 { CPUID_TSC, "TSC" }, 972 { CPUID_MSR, "MSR" }, 973 { CPUID_PAE, "PAE" }, 974 { CPUID_MCE, "MCE" }, 975 { CPUID_CX8, "CX8" }, 976 { CPUID_APIC, "APIC" }, 977 { CPUID_SYS1, "SYS" }, 978 { CPUID_SEP, "SEP" }, 979 { CPUID_MTRR, "MTRR" }, 980 { CPUID_PGE, "PGE" }, 981 { CPUID_MCA, "MCA" }, 982 { CPUID_CMOV, "CMOV" }, 983 { CPUID_PAT, "PAT" }, 984 { CPUID_PSE36, "PSE36" }, 985 { CPUID_PSN, "PSN" }, 986 { CPUID_CFLUSH, "CFLUSH" }, 987 { CPUID_DS, "DS" }, 988 { CPUID_ACPI, "ACPI" }, 989 { CPUID_MMX, "MMX" }, 990 { CPUID_FXSR, "FXSR" }, 991 { CPUID_SSE, "SSE" }, 992 { CPUID_SSE2, "SSE2" }, 993 { CPUID_SS, "SS" }, 994 { CPUID_HTT, "HTT" }, 995 { CPUID_TM, "TM" }, 996 { CPUID_PBE, "PBE" } 997 }; 998 999 const struct cpu_cpuid_feature i386_ecpuid_features[] = { 1000 { CPUID_MPC, "MPC" }, 1001 { CPUID_NXE, "NXE" }, 1002 { CPUID_MMXX, "MMXX" }, 1003 { CPUID_FFXSR, "FFXSR" }, 1004 { CPUID_LONG, "LONG" }, 1005 { CPUID_3DNOW2, "3DNOW2" }, 1006 { CPUID_3DNOW, "3DNOW" } 1007 }; 1008 1009 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = { 1010 { CPUIDECX_SSE3, "SSE3" }, 1011 { CPUIDECX_PCLMUL, "PCLMUL" }, 1012 { CPUIDECX_DTES64, "DTES64" }, 1013 { CPUIDECX_MWAIT, "MWAIT" }, 1014 { CPUIDECX_DSCPL, "DS-CPL" }, 1015 { CPUIDECX_VMX, "VMX" }, 1016 { CPUIDECX_SMX, "SMX" }, 1017 { CPUIDECX_EST, "EST" }, 1018 { CPUIDECX_TM2, "TM2" }, 1019 { CPUIDECX_SSSE3, "SSSE3" }, 1020 { CPUIDECX_CNXTID, "CNXT-ID" }, 1021 { CPUIDECX_FMA3, "FMA3" }, 1022 { CPUIDECX_CX16, "CX16" }, 1023 { CPUIDECX_XTPR, "xTPR" }, 1024 { CPUIDECX_PDCM, "PDCM" }, 1025 { CPUIDECX_PCID, "PCID" }, 1026 { CPUIDECX_DCA, "DCA" }, 1027 { CPUIDECX_SSE41, "SSE4.1" }, 1028 { CPUIDECX_SSE42, "SSE4.2" }, 1029 { CPUIDECX_X2APIC, "x2APIC" }, 1030 { CPUIDECX_MOVBE, "MOVBE" }, 1031 { CPUIDECX_POPCNT, "POPCNT" }, 1032 { CPUIDECX_DEADLINE, "DEADLINE" }, 1033 { CPUIDECX_AES, "AES" }, 1034 { CPUIDECX_XSAVE, "XSAVE" }, 1035 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 1036 { CPUIDECX_AVX, "AVX" }, 1037 { CPUIDECX_F16C, "F16C" }, 1038 { CPUIDECX_RDRAND, "RDRAND" }, 1039 }; 1040 1041 const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = { 1042 { CPUIDECX_LAHF, "LAHF" }, 1043 { CPUIDECX_CMPLEG, "CMPLEG" }, 1044 { CPUIDECX_SVM, "SVM" }, 1045 { CPUIDECX_EAPICSP, "EAPICSP" }, 1046 { CPUIDECX_AMCR8, "AMCR8" }, 1047 { CPUIDECX_ABM, "ABM" }, 1048 { CPUIDECX_SSE4A, "SSE4A" }, 1049 { CPUIDECX_MASSE, "MASSE" }, 1050 { CPUIDECX_3DNOWP, "3DNOWP" }, 1051 { CPUIDECX_OSVW, "OSVW" }, 1052 { CPUIDECX_IBS, "IBS" }, 1053 { CPUIDECX_XOP, "XOP" }, 1054 { CPUIDECX_SKINIT, "SKINIT" }, 1055 { CPUIDECX_WDT, "WDT" }, 1056 { CPUIDECX_LWP, "LWP" }, 1057 { CPUIDECX_FMA4, "FMA4" }, 1058 { CPUIDECX_NODEID, "NODEID" }, 1059 { CPUIDECX_TBM, "TBM" }, 1060 { CPUIDECX_TOPEXT, "TOPEXT" }, 1061 }; 1062 1063 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { 1064 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 1065 { SEFF0EBX_BMI1, "BMI1" }, 1066 { SEFF0EBX_HLE, "HLE" }, 1067 { SEFF0EBX_AVX2, "AVX2" }, 1068 { SEFF0EBX_SMEP, "SMEP" }, 1069 { SEFF0EBX_BMI2, "BMI2" }, 1070 { SEFF0EBX_ERMS, "ERMS" }, 1071 { SEFF0EBX_INVPCID, "INVPCID" }, 1072 { SEFF0EBX_RTM, "RTM" }, 1073 { SEFF0EBX_RDSEED, "RDSEED" }, 1074 { SEFF0EBX_ADX, "ADX" }, 1075 { SEFF0EBX_SMAP, "SMAP" }, 1076 }; 1077 1078 const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = { 1079 { CPUIDEAX_VERID, "PERF" }, 1080 }; 1081 1082 const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = { 1083 { CPUIDEDX_ITSC, "ITSC" }, 1084 }; 1085 1086 void 1087 winchip_cpu_setup(struct cpu_info *ci) 1088 { 1089 1090 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1091 case 4: /* WinChip C6 */ 1092 ci->ci_feature_flags &= ~CPUID_TSC; 1093 /* Disable RDTSC instruction from user-level. */ 1094 lcr4(rcr4() | CR4_TSD); 1095 printf("%s: TSC disabled\n", ci->ci_dev.dv_xname); 1096 break; 1097 } 1098 } 1099 1100 #if !defined(SMALL_KERNEL) 1101 void 1102 cyrix3_setperf_setup(struct cpu_info *ci) 1103 { 1104 if (cpu_ecxfeature & CPUIDECX_EST) { 1105 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1106 est_init(ci, CPUVENDOR_VIA); 1107 else 1108 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1109 ci->ci_dev.dv_xname); 1110 } 1111 } 1112 #endif 1113 1114 void 1115 cyrix3_cpu_setup(struct cpu_info *ci) 1116 { 1117 int model = (ci->ci_signature >> 4) & 15; 1118 int step = ci->ci_signature & 15; 1119 1120 u_int64_t msreg; 1121 u_int32_t regs[4]; 1122 unsigned int val; 1123 #if !defined(SMALL_KERNEL) 1124 extern void (*pagezero)(void *, size_t); 1125 extern void i686_pagezero(void *, size_t); 1126 1127 pagezero = i686_pagezero; 1128 1129 setperf_setup = cyrix3_setperf_setup; 1130 #endif 1131 1132 switch (model) { 1133 /* Possible earlier models */ 1134 case 0: case 1: case 2: 1135 case 3: case 4: case 5: 1136 break; 1137 1138 case 6: /* C3 Samuel 1 */ 1139 case 7: /* C3 Samuel 2 or C3 Ezra */ 1140 case 8: /* C3 Ezra-T */ 1141 cpuid(0x80000001, regs); 1142 val = regs[3]; 1143 if (val & (1U << 31)) { 1144 cpu_feature |= CPUID_3DNOW; 1145 } else { 1146 cpu_feature &= ~CPUID_3DNOW; 1147 } 1148 break; 1149 1150 case 9: 1151 if (step < 3) 1152 break; 1153 /* 1154 * C3 Nehemiah & later: fall through. 1155 */ 1156 1157 case 10: /* C7-M Type A */ 1158 case 13: /* C7-M Type D */ 1159 case 15: /* Nano */ 1160 #if !defined(SMALL_KERNEL) 1161 if (model == 10 || model == 13 || model == 15) { 1162 /* Setup the sensors structures */ 1163 strlcpy(ci->ci_sensordev.xname, ci->ci_dev.dv_xname, 1164 sizeof(ci->ci_sensordev.xname)); 1165 ci->ci_sensor.type = SENSOR_TEMP; 1166 sensor_task_register(ci, via_update_sensor, 5); 1167 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1168 sensordev_install(&ci->ci_sensordev); 1169 } 1170 #endif 1171 1172 default: 1173 /* 1174 * C3 Nehemiah/Esther & later models: 1175 * First we check for extended feature flags, and then 1176 * (if present) retrieve the ones at 0xC0000001. In this 1177 * bit 2 tells us if the RNG is present. Bit 3 tells us 1178 * if the RNG has been enabled. In order to use the RNG 1179 * we need 3 things: We need an RNG, we need the FXSR bit 1180 * enabled in cr4 (SSE/SSE2 stuff), and we need to have 1181 * Bit 6 of MSR 0x110B set to 1 (the default), which will 1182 * show up as bit 3 set here. 1183 */ 1184 cpuid(0xC0000000, regs); /* Check for RNG */ 1185 val = regs[0]; 1186 if (val >= 0xC0000001) { 1187 cpuid(0xC0000001, regs); 1188 val = regs[3]; 1189 } else 1190 val = 0; 1191 1192 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 1193 printf("%s:", ci->ci_dev.dv_xname); 1194 1195 /* Enable RNG if present and disabled */ 1196 if (val & C3_CPUID_HAS_RNG) { 1197 extern int viac3_rnd_present; 1198 1199 if (!(val & C3_CPUID_DO_RNG)) { 1200 msreg = rdmsr(0x110B); 1201 msreg |= 0x40; 1202 wrmsr(0x110B, msreg); 1203 } 1204 viac3_rnd_present = 1; 1205 printf(" RNG"); 1206 } 1207 1208 /* Enable AES engine if present and disabled */ 1209 if (val & C3_CPUID_HAS_ACE) { 1210 #ifdef CRYPTO 1211 if (!(val & C3_CPUID_DO_ACE)) { 1212 msreg = rdmsr(0x1107); 1213 msreg |= (0x01 << 28); 1214 wrmsr(0x1107, msreg); 1215 } 1216 i386_has_xcrypt |= C3_HAS_AES; 1217 #endif /* CRYPTO */ 1218 printf(" AES"); 1219 } 1220 1221 /* Enable ACE2 engine if present and disabled */ 1222 if (val & C3_CPUID_HAS_ACE2) { 1223 #ifdef CRYPTO 1224 if (!(val & C3_CPUID_DO_ACE2)) { 1225 msreg = rdmsr(0x1107); 1226 msreg |= (0x01 << 28); 1227 wrmsr(0x1107, msreg); 1228 } 1229 i386_has_xcrypt |= C3_HAS_AESCTR; 1230 #endif /* CRYPTO */ 1231 printf(" AES-CTR"); 1232 } 1233 1234 /* Enable SHA engine if present and disabled */ 1235 if (val & C3_CPUID_HAS_PHE) { 1236 #ifdef CRYPTO 1237 if (!(val & C3_CPUID_DO_PHE)) { 1238 msreg = rdmsr(0x1107); 1239 msreg |= (0x01 << 28/**/); 1240 wrmsr(0x1107, msreg); 1241 } 1242 i386_has_xcrypt |= C3_HAS_SHA; 1243 #endif /* CRYPTO */ 1244 printf(" SHA1 SHA256"); 1245 } 1246 1247 /* Enable MM engine if present and disabled */ 1248 if (val & C3_CPUID_HAS_PMM) { 1249 #ifdef CRYPTO 1250 if (!(val & C3_CPUID_DO_PMM)) { 1251 msreg = rdmsr(0x1107); 1252 msreg |= (0x01 << 28/**/); 1253 wrmsr(0x1107, msreg); 1254 } 1255 i386_has_xcrypt |= C3_HAS_MM; 1256 #endif /* CRYPTO */ 1257 printf(" RSA"); 1258 } 1259 1260 printf("\n"); 1261 break; 1262 } 1263 } 1264 1265 #if !defined(SMALL_KERNEL) 1266 void 1267 via_update_sensor(void *args) 1268 { 1269 struct cpu_info *ci = (struct cpu_info *) args; 1270 u_int64_t msr; 1271 1272 switch (ci->ci_model) { 1273 case 0xa: 1274 case 0xd: 1275 msr = rdmsr(MSR_C7M_TMTEMPERATURE); 1276 break; 1277 case 0xf: 1278 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 1279 break; 1280 } 1281 ci->ci_sensor.value = (msr & 0xffffff); 1282 /* micro degrees */ 1283 ci->ci_sensor.value *= 1000000; 1284 ci->ci_sensor.value += 273150000; 1285 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1286 } 1287 #endif 1288 1289 void 1290 cyrix6x86_cpu_setup(struct cpu_info *ci) 1291 { 1292 extern int clock_broken_latch; 1293 1294 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1295 case -1: /* M1 w/o cpuid */ 1296 case 2: /* M1 */ 1297 /* set up various cyrix registers */ 1298 /* Enable suspend on halt */ 1299 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 1300 /* enable access to ccr4/ccr5 */ 1301 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10); 1302 /* cyrix's workaround for the "coma bug" */ 1303 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 1304 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 1305 cyrix_read_reg(0x33); cyrix_write_reg(0x33, 0); 1306 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 1307 /* disable access to ccr4/ccr5 */ 1308 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10); 1309 1310 printf("%s: xchg bug workaround performed\n", 1311 ci->ci_dev.dv_xname); 1312 break; /* fallthrough? */ 1313 case 4: /* GXm */ 1314 /* Unset the TSC bit until calibrate_delay() gets fixed. */ 1315 clock_broken_latch = 1; 1316 curcpu()->ci_feature_flags &= ~CPUID_TSC; 1317 printf("%s: TSC disabled\n", ci->ci_dev.dv_xname); 1318 break; 1319 } 1320 } 1321 1322 void 1323 natsem6x86_cpu_setup(struct cpu_info *ci) 1324 { 1325 extern int clock_broken_latch; 1326 int model = (ci->ci_signature >> 4) & 15; 1327 1328 clock_broken_latch = 1; 1329 switch (model) { 1330 case 4: 1331 cpu_feature &= ~CPUID_TSC; 1332 printf("%s: TSC disabled\n", ci->ci_dev.dv_xname); 1333 break; 1334 } 1335 } 1336 1337 void 1338 intel586_cpu_setup(struct cpu_info *ci) 1339 { 1340 if (!cpu_f00f_bug) { 1341 fix_f00f(); 1342 printf("%s: F00F bug workaround installed\n", 1343 ci->ci_dev.dv_xname); 1344 } 1345 } 1346 1347 #if !defined(SMALL_KERNEL) 1348 void 1349 amd_family5_setperf_setup(struct cpu_info *ci) 1350 { 1351 k6_powernow_init(); 1352 } 1353 #endif 1354 1355 void 1356 amd_family5_setup(struct cpu_info *ci) 1357 { 1358 int model = (ci->ci_signature >> 4) & 15; 1359 1360 switch (model) { 1361 case 0: /* AMD-K5 Model 0 */ 1362 /* 1363 * According to the AMD Processor Recognition App Note, 1364 * the AMD-K5 Model 0 uses the wrong bit to indicate 1365 * support for global PTEs, instead using bit 9 (APIC) 1366 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1367 */ 1368 if (cpu_feature & CPUID_APIC) 1369 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE; 1370 /* 1371 * XXX But pmap_pg_g is already initialized -- need to kick 1372 * XXX the pmap somehow. How does the MP branch do this? 1373 */ 1374 break; 1375 case 12: 1376 case 13: 1377 #if !defined(SMALL_KERNEL) 1378 setperf_setup = amd_family5_setperf_setup; 1379 #endif 1380 break; 1381 } 1382 } 1383 1384 #if !defined(SMALL_KERNEL) 1385 void 1386 amd_family6_setperf_setup(struct cpu_info *ci) 1387 { 1388 int family = (ci->ci_signature >> 8) & 15; 1389 1390 switch (family) { 1391 case 6: 1392 k7_powernow_init(); 1393 break; 1394 case 15: 1395 k8_powernow_init(); 1396 break; 1397 } 1398 if (ci->ci_family >= 0x10) 1399 k1x_init(ci); 1400 } 1401 #endif 1402 1403 void 1404 amd_family6_setup(struct cpu_info *ci) 1405 { 1406 #if !defined(SMALL_KERNEL) 1407 int family = (ci->ci_signature >> 8) & 15; 1408 extern void (*pagezero)(void *, size_t); 1409 extern void sse2_pagezero(void *, size_t); 1410 extern void i686_pagezero(void *, size_t); 1411 1412 if (cpu_feature & CPUID_SSE2) 1413 pagezero = sse2_pagezero; 1414 else 1415 pagezero = i686_pagezero; 1416 1417 setperf_setup = amd_family6_setperf_setup; 1418 1419 if (family == 0xf) { 1420 amd64_errata(ci); 1421 } 1422 #endif 1423 } 1424 1425 #if !defined(SMALL_KERNEL) 1426 /* 1427 * Temperature read on the CPU is relative to the maximum 1428 * temperature supported by the CPU, Tj(Max). 1429 * Poorly documented, refer to: 1430 * http://softwarecommunity.intel.com/isn/Community/ 1431 * en-US/forums/thread/30228638.aspx 1432 * Basically, depending on a bit in one msr, the max is either 85 or 100. 1433 * Then we subtract the temperature portion of thermal status from 1434 * max to get current temperature. 1435 */ 1436 void 1437 intelcore_update_sensor(void *args) 1438 { 1439 struct cpu_info *ci = (struct cpu_info *) args; 1440 u_int64_t msr; 1441 int max = 100; 1442 1443 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 1444 if (ci->ci_model == 0xe && 1445 (rdmsr(MSR_TEMPERATURE_TARGET) & MSR_TEMPERATURE_TARGET_LOW_BIT)) 1446 max = 85; 1447 1448 msr = rdmsr(MSR_THERM_STATUS); 1449 if (msr & MSR_THERM_STATUS_VALID_BIT) { 1450 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 1451 /* micro degrees */ 1452 ci->ci_sensor.value *= 1000000; 1453 /* kelvin */ 1454 ci->ci_sensor.value += 273150000; 1455 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1456 } else { 1457 ci->ci_sensor.value = 0; 1458 ci->ci_sensor.flags |= SENSOR_FINVALID; 1459 } 1460 } 1461 1462 void 1463 intel686_cpusensors_setup(struct cpu_info *ci) 1464 { 1465 u_int regs[4]; 1466 1467 if (cpuid_level < 0x06) 1468 return; 1469 1470 /* CPUID.06H.EAX[0] = 1 tells us if we have on-die sensor */ 1471 cpuid(0x06, regs); 1472 if ((regs[0] & 0x01) != 1) 1473 return; 1474 1475 /* Setup the sensors structures */ 1476 strlcpy(ci->ci_sensordev.xname, ci->ci_dev.dv_xname, 1477 sizeof(ci->ci_sensordev.xname)); 1478 ci->ci_sensor.type = SENSOR_TEMP; 1479 sensor_task_register(ci, intelcore_update_sensor, 5); 1480 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1481 sensordev_install(&ci->ci_sensordev); 1482 } 1483 #endif 1484 1485 #if !defined(SMALL_KERNEL) 1486 void 1487 intel686_setperf_setup(struct cpu_info *ci) 1488 { 1489 int family = (ci->ci_signature >> 8) & 15; 1490 int step = ci->ci_signature & 15; 1491 1492 if (cpu_ecxfeature & CPUIDECX_EST) { 1493 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1494 est_init(ci, CPUVENDOR_INTEL); 1495 else 1496 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1497 ci->ci_dev.dv_xname); 1498 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) == 1499 (CPUID_ACPI | CPUID_TM)) 1500 p4tcc_init(family, step); 1501 } 1502 #endif 1503 1504 void 1505 intel686_common_cpu_setup(struct cpu_info *ci) 1506 { 1507 1508 #if !defined(SMALL_KERNEL) 1509 setperf_setup = intel686_setperf_setup; 1510 cpusensors_setup = intel686_cpusensors_setup; 1511 { 1512 extern void (*pagezero)(void *, size_t); 1513 extern void sse2_pagezero(void *, size_t); 1514 extern void i686_pagezero(void *, size_t); 1515 1516 if (cpu_feature & CPUID_SSE2) 1517 pagezero = sse2_pagezero; 1518 else 1519 pagezero = i686_pagezero; 1520 } 1521 #endif 1522 /* 1523 * Make sure SYSENTER is disabled. 1524 */ 1525 if (cpu_feature & CPUID_SEP) 1526 wrmsr(MSR_SYSENTER_CS, 0); 1527 } 1528 1529 void 1530 intel686_cpu_setup(struct cpu_info *ci) 1531 { 1532 int model = (ci->ci_signature >> 4) & 15; 1533 int step = ci->ci_signature & 15; 1534 u_quad_t msr119; 1535 1536 intel686_common_cpu_setup(ci); 1537 1538 /* 1539 * Original PPro returns SYSCALL in CPUID but is non-functional. 1540 * From Intel Application Note #485. 1541 */ 1542 if ((model == 1) && (step < 3)) 1543 ci->ci_feature_flags &= ~CPUID_SEP; 1544 1545 /* 1546 * Disable the Pentium3 serial number. 1547 */ 1548 if ((model == 7) && (ci->ci_feature_flags & CPUID_PSN)) { 1549 msr119 = rdmsr(MSR_BBL_CR_CTL); 1550 msr119 |= 0x0000000000200000LL; 1551 wrmsr(MSR_BBL_CR_CTL, msr119); 1552 1553 printf("%s: disabling processor serial number\n", 1554 ci->ci_dev.dv_xname); 1555 ci->ci_feature_flags &= ~CPUID_PSN; 1556 ci->ci_level = 2; 1557 } 1558 1559 #if !defined(SMALL_KERNEL) 1560 p3_early = (model == 8 && step == 1) ? 1 : 0; 1561 update_cpuspeed = p3_update_cpuspeed; 1562 #endif 1563 } 1564 1565 void 1566 intel686_p4_cpu_setup(struct cpu_info *ci) 1567 { 1568 intel686_common_cpu_setup(ci); 1569 1570 #if !defined(SMALL_KERNEL) 1571 p4_model = (ci->ci_signature >> 4) & 15; 1572 update_cpuspeed = p4_update_cpuspeed; 1573 #endif 1574 } 1575 1576 void 1577 tm86_cpu_setup(struct cpu_info *ci) 1578 { 1579 #if !defined(SMALL_KERNEL) 1580 longrun_init(); 1581 #endif 1582 } 1583 1584 char * 1585 intel686_cpu_name(int model) 1586 { 1587 char *ret = NULL; 1588 1589 switch (model) { 1590 case 5: 1591 switch (cpu_cache_edx & 0xFF) { 1592 case 0x40: 1593 case 0x41: 1594 ret = "Celeron"; 1595 break; 1596 /* 0x42 should not exist in this model. */ 1597 case 0x43: 1598 ret = "Pentium II"; 1599 break; 1600 case 0x44: 1601 case 0x45: 1602 ret = "Pentium II Xeon"; 1603 break; 1604 } 1605 break; 1606 case 7: 1607 switch (cpu_cache_edx & 0xFF) { 1608 /* 0x40 - 0x42 should not exist in this model. */ 1609 case 0x43: 1610 ret = "Pentium III"; 1611 break; 1612 case 0x44: 1613 case 0x45: 1614 ret = "Pentium III Xeon"; 1615 break; 1616 } 1617 break; 1618 } 1619 1620 return (ret); 1621 } 1622 1623 char * 1624 cyrix3_cpu_name(int model, int step) 1625 { 1626 char *name = NULL; 1627 1628 switch (model) { 1629 case 7: 1630 if (step < 8) 1631 name = "C3 Samuel 2"; 1632 else 1633 name = "C3 Ezra"; 1634 break; 1635 } 1636 return name; 1637 } 1638 1639 /* 1640 * Print identification for the given CPU. 1641 * XXX XXX 1642 * This is not as clean as one might like, because it references 1643 * 1644 * the "cpuid_level" and "cpu_vendor" globals. 1645 * cpuid_level isn't so bad, since both CPU's will hopefully 1646 * be of the same level. 1647 * 1648 * The Intel multiprocessor spec doesn't give us the cpu_vendor 1649 * information; however, the chance of multi-vendor SMP actually 1650 * ever *working* is sufficiently low that it's probably safe to assume 1651 * all processors are of the same vendor. 1652 */ 1653 1654 void 1655 identifycpu(struct cpu_info *ci) 1656 { 1657 const char *name, *modifier, *vendorname, *token; 1658 int class = CPUCLASS_386, vendor, i, max; 1659 int family, model, step, modif, cachesize; 1660 const struct cpu_cpuid_nameclass *cpup = NULL; 1661 char *brandstr_from, *brandstr_to; 1662 char *cpu_device = ci->ci_dev.dv_xname; 1663 int skipspace; 1664 1665 if (cpuid_level == -1) { 1666 #ifdef DIAGNOSTIC 1667 if (cpu < 0 || cpu >= 1668 (sizeof i386_nocpuid_cpus/sizeof(struct cpu_nocpuid_nameclass))) 1669 panic("unknown cpu type %d", cpu); 1670 #endif 1671 name = i386_nocpuid_cpus[cpu].cpu_name; 1672 vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1673 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1674 model = -1; 1675 step = -1; 1676 class = i386_nocpuid_cpus[cpu].cpu_class; 1677 ci->cpu_setup = i386_nocpuid_cpus[cpu].cpu_setup; 1678 modifier = ""; 1679 token = ""; 1680 } else { 1681 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1682 modif = (ci->ci_signature >> 12) & 3; 1683 family = (ci->ci_signature >> 8) & 15; 1684 ci->ci_family = family; 1685 model = (ci->ci_signature >> 4) & 15; 1686 ci->ci_model = model; 1687 step = ci->ci_signature & 15; 1688 #ifdef CPUDEBUG 1689 printf("%s: family %x model %x step %x\n", cpu_device, family, 1690 model, step); 1691 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n", 1692 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx, 1693 cpu_cache_ecx, cpu_cache_edx); 1694 #endif 1695 if (family < CPU_MINFAMILY) 1696 panic("identifycpu: strange family value"); 1697 1698 for (i = 0; i < max; i++) { 1699 if (!strncmp(cpu_vendor, 1700 i386_cpuid_cpus[i].cpu_id, 12)) { 1701 cpup = &i386_cpuid_cpus[i]; 1702 break; 1703 } 1704 } 1705 1706 if (cpup == NULL) { 1707 vendor = CPUVENDOR_UNKNOWN; 1708 if (cpu_vendor[0] != '\0') 1709 vendorname = &cpu_vendor[0]; 1710 else 1711 vendorname = "Unknown"; 1712 if (family > CPU_MAXFAMILY) 1713 family = CPU_MAXFAMILY; 1714 class = family - 3; 1715 if (class > CPUCLASS_686) 1716 class = CPUCLASS_686; 1717 modifier = ""; 1718 name = ""; 1719 token = ""; 1720 ci->cpu_setup = NULL; 1721 } else { 1722 token = cpup->cpu_id; 1723 vendor = cpup->cpu_vendor; 1724 vendorname = cpup->cpu_vendorname; 1725 /* 1726 * Special hack for the VIA C3 series. 1727 * 1728 * VIA bought Centaur Technology from IDT in Aug 1999 1729 * and marketed the processors as VIA Cyrix III/C3. 1730 */ 1731 if (vendor == CPUVENDOR_IDT && family >= 6) { 1732 vendor = CPUVENDOR_VIA; 1733 vendorname = "VIA"; 1734 } 1735 modifier = modifiers[modif]; 1736 if (family > CPU_MAXFAMILY) { 1737 family = CPU_MAXFAMILY; 1738 model = CPU_DEFMODEL; 1739 } else if (model > CPU_MAXMODEL) 1740 model = CPU_DEFMODEL; 1741 i = family - CPU_MINFAMILY; 1742 1743 /* store extended family/model values for later use */ 1744 if ((vendor == CPUVENDOR_INTEL && 1745 (family == 0x6 || family == 0xf)) || 1746 (vendor == CPUVENDOR_AMD && family == 0xf)) { 1747 ci->ci_family += (ci->ci_signature >> 20) & 1748 0xff; 1749 ci->ci_model += ((ci->ci_signature >> 16) & 1750 0x0f) << 4; 1751 } 1752 1753 /* Special hack for the PentiumII/III series. */ 1754 if (vendor == CPUVENDOR_INTEL && family == 6 && 1755 (model == 5 || model == 7)) { 1756 name = intel686_cpu_name(model); 1757 /* Special hack for the VIA C3 series. */ 1758 } else if (vendor == CPUVENDOR_VIA && family == 6 && 1759 model == 7) { 1760 name = cyrix3_cpu_name(model, step); 1761 /* Special hack for the TMS5x00 series. */ 1762 } else if (vendor == CPUVENDOR_TRANSMETA && 1763 family == 5 && model == 4) { 1764 name = tm86_cpu_name(model); 1765 } else 1766 name = cpup->cpu_family[i].cpu_models[model]; 1767 if (name == NULL) { 1768 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL]; 1769 if (name == NULL) 1770 name = ""; 1771 } 1772 class = cpup->cpu_family[i].cpu_class; 1773 ci->cpu_setup = cpup->cpu_family[i].cpu_setup; 1774 } 1775 } 1776 1777 /* Find the amount of on-chip L2 cache. */ 1778 cachesize = -1; 1779 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) { 1780 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 }; 1781 1782 if ((cpu_cache_edx & 0xFF) >= 0x40 && 1783 (cpu_cache_edx & 0xFF) <= 0x45) 1784 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40]; 1785 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) { 1786 u_int regs[4]; 1787 cpuid(0x80000000, regs); 1788 if (regs[0] >= 0x80000006) { 1789 cpuid(0x80000006, regs); 1790 cachesize = (regs[2] >> 16); 1791 } 1792 } 1793 1794 if (vendor == CPUVENDOR_INTEL) { 1795 /* 1796 * PIII, Core Solo and Core Duo CPUs have known 1797 * errata stating: 1798 * "Page with PAT set to WC while associated MTRR is UC 1799 * may consolidate to UC". 1800 * Because of this it is best we just fallback to mtrrs 1801 * in this case. 1802 */ 1803 if (ci->ci_family == 6 && ci->ci_model < 15) 1804 ci->ci_feature_flags &= ~CPUID_PAT; 1805 1806 if (ci->ci_feature_flags & CPUID_CFLUSH) { 1807 /* to get the cacheline size you must do cpuid 1808 * with eax 0x01 1809 */ 1810 u_int regs[4]; 1811 1812 cpuid(0x01, regs); 1813 ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; 1814 } 1815 } 1816 1817 /* Remove leading and duplicated spaces from cpu_brandstr */ 1818 brandstr_from = brandstr_to = cpu_brandstr; 1819 skipspace = 1; 1820 while (*brandstr_from != '\0') { 1821 if (!skipspace || *brandstr_from != ' ') { 1822 skipspace = 0; 1823 *(brandstr_to++) = *brandstr_from; 1824 } 1825 if (*brandstr_from == ' ') 1826 skipspace = 1; 1827 brandstr_from++; 1828 } 1829 *brandstr_to = '\0'; 1830 1831 if (cpu_brandstr[0] == '\0') { 1832 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */, 1833 "%s %s%s", vendorname, modifier, name); 1834 } 1835 1836 if ((ci->ci_flags & CPUF_PRIMARY) == 0) { 1837 if (cachesize > -1) { 1838 snprintf(cpu_model, sizeof(cpu_model), 1839 "%s (%s%s%s%s-class, %dKB L2 cache)", 1840 cpu_brandstr, 1841 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1842 ((*token) ? "\" " : ""), classnames[class], cachesize); 1843 } else { 1844 snprintf(cpu_model, sizeof(cpu_model), 1845 "%s (%s%s%s%s-class)", 1846 cpu_brandstr, 1847 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1848 ((*token) ? "\" " : ""), classnames[class]); 1849 } 1850 1851 printf("%s: %s", cpu_device, cpu_model); 1852 } 1853 1854 if (ci->ci_feature_flags && (ci->ci_feature_flags & CPUID_TSC)) { 1855 /* Has TSC, check if it's constant */ 1856 switch (vendor) { 1857 case CPUVENDOR_INTEL: 1858 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 1859 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 1860 ci->ci_flags |= CPUF_CONST_TSC; 1861 } 1862 break; 1863 case CPUVENDOR_VIA: 1864 if (ci->ci_model >= 0x0f) { 1865 ci->ci_flags |= CPUF_CONST_TSC; 1866 } 1867 break; 1868 } 1869 calibrate_cyclecounter(); 1870 if (cpuspeed > 994) { 1871 int ghz, fr; 1872 1873 ghz = (cpuspeed + 9) / 1000; 1874 fr = ((cpuspeed + 9) / 10 ) % 100; 1875 if ((ci->ci_flags & CPUF_PRIMARY) == 0) { 1876 if (fr) 1877 printf(" %d.%02d GHz", ghz, fr); 1878 else 1879 printf(" %d GHz", ghz); 1880 } 1881 } else { 1882 if ((ci->ci_flags & CPUF_PRIMARY) == 0) { 1883 printf(" %d MHz", cpuspeed); 1884 } 1885 } 1886 } 1887 if ((ci->ci_flags & CPUF_PRIMARY) == 0) { 1888 printf("\n"); 1889 1890 if (ci->ci_feature_flags) { 1891 int numbits = 0; 1892 1893 printf("%s: ", cpu_device); 1894 max = sizeof(i386_cpuid_features) / 1895 sizeof(i386_cpuid_features[0]); 1896 for (i = 0; i < max; i++) { 1897 if (ci->ci_feature_flags & 1898 i386_cpuid_features[i].feature_bit) { 1899 printf("%s%s", (numbits == 0 ? "" : ","), 1900 i386_cpuid_features[i].feature_name); 1901 numbits++; 1902 } 1903 } 1904 for (i = 0; i < nitems(i386_ecpuid_features); i++) { 1905 if (ecpu_feature & 1906 i386_ecpuid_features[i].feature_bit) { 1907 printf("%s%s", (numbits == 0 ? "" : ","), 1908 i386_ecpuid_features[i].feature_name); 1909 numbits++; 1910 } 1911 } 1912 max = sizeof(i386_cpuid_ecxfeatures) 1913 / sizeof(i386_cpuid_ecxfeatures[0]); 1914 for (i = 0; i < max; i++) { 1915 if (cpu_ecxfeature & 1916 i386_cpuid_ecxfeatures[i].feature_bit) { 1917 printf("%s%s", (numbits == 0 ? "" : ","), 1918 i386_cpuid_ecxfeatures[i].feature_name); 1919 numbits++; 1920 } 1921 } 1922 for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) { 1923 if (ecpu_ecxfeature & 1924 i386_ecpuid_ecxfeatures[i].feature_bit) { 1925 printf("%s%s", (numbits == 0 ? "" : ","), 1926 i386_ecpuid_ecxfeatures[i].feature_name); 1927 numbits++; 1928 } 1929 } 1930 for (i = 0; i < nitems(i386_cpuid_eaxperf); i++) { 1931 if (cpu_perf_eax & 1932 i386_cpuid_eaxperf[i].feature_bit) { 1933 printf("%s%s", (numbits == 0 ? "" : ","), 1934 i386_cpuid_eaxperf[i].feature_name); 1935 numbits++; 1936 } 1937 } 1938 for (i = 0; i < nitems(i386_cpuid_edxapmi); i++) { 1939 if (cpu_apmi_edx & 1940 i386_cpuid_edxapmi[i].feature_bit) { 1941 printf("%s%s", (numbits == 0 ? "" : ","), 1942 i386_cpuid_edxapmi[i].feature_name); 1943 numbits++; 1944 } 1945 } 1946 1947 if (cpuid_level >= 0x07) { 1948 u_int dummy; 1949 1950 /* "Structured Extended Feature Flags" */ 1951 CPUID_LEAF(0x7, 0, dummy, 1952 ci->ci_feature_sefflags, dummy, dummy); 1953 max = sizeof(cpu_seff0_ebxfeatures) / 1954 sizeof(cpu_seff0_ebxfeatures[0]); 1955 for (i = 0; i < max; i++) 1956 if (ci->ci_feature_sefflags & 1957 cpu_seff0_ebxfeatures[i].feature_bit) 1958 printf("%s%s", 1959 (numbits == 0 ? "" : ","), 1960 cpu_seff0_ebxfeatures[i].feature_name); 1961 } 1962 printf("\n"); 1963 } 1964 } 1965 1966 if (ci->ci_flags & CPUF_PRIMARY) { 1967 if (cpu_ecxfeature & CPUIDECX_RDRAND) 1968 has_rdrand = 1; 1969 #ifndef SMALL_KERNEL 1970 if (ci->ci_feature_sefflags & SEFF0EBX_SMAP) 1971 replacesmap(); 1972 #endif 1973 } 1974 1975 #ifndef SMALL_KERNEL 1976 if (cpuspeed != 0 && cpu_cpuspeed == NULL) 1977 cpu_cpuspeed = pentium_cpuspeed; 1978 #endif 1979 1980 cpu_class = class; 1981 1982 if (cpu_class == CPUCLASS_386) { 1983 printf("WARNING: 386 (possibly unknown?) cpu class, assuming 486\n"); 1984 cpu_class = CPUCLASS_486; 1985 } 1986 1987 ci->cpu_class = class; 1988 1989 if (cpu == CPU_486DLC) 1990 printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 1991 1992 /* 1993 * Enable ring 0 write protection (486 or above, but 386 1994 * no longer supported). 1995 */ 1996 lcr0(rcr0() | CR0_WP); 1997 1998 /* 1999 * If we have FXSAVE/FXRESTOR, use them. 2000 */ 2001 if (cpu_feature & CPUID_FXSR) { 2002 i386_use_fxsave = 1; 2003 lcr4(rcr4() | CR4_OSFXSR); 2004 2005 /* 2006 * If we have SSE/SSE2, enable XMM exceptions, and 2007 * notify userland. 2008 */ 2009 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) { 2010 if (cpu_feature & CPUID_SSE) 2011 i386_has_sse = 1; 2012 if (cpu_feature & CPUID_SSE2) 2013 i386_has_sse2 = 1; 2014 lcr4(rcr4() | CR4_OSXMMEXCPT); 2015 } 2016 } else 2017 i386_use_fxsave = 0; 2018 2019 } 2020 2021 char * 2022 tm86_cpu_name(int model) 2023 { 2024 u_int32_t regs[4]; 2025 char *name = NULL; 2026 2027 cpuid(0x80860001, regs); 2028 2029 switch (model) { 2030 case 4: 2031 if (((regs[1] >> 16) & 0xff) >= 0x3) 2032 name = "TMS5800"; 2033 else 2034 name = "TMS5600"; 2035 } 2036 2037 return name; 2038 } 2039 2040 #ifndef SMALL_KERNEL 2041 void 2042 cyrix3_get_bus_clock(struct cpu_info *ci) 2043 { 2044 u_int64_t msr; 2045 int bus; 2046 2047 msr = rdmsr(MSR_EBL_CR_POWERON); 2048 bus = (msr >> 18) & 0x3; 2049 switch (bus) { 2050 case 0: 2051 bus_clock = BUS100; 2052 break; 2053 case 1: 2054 bus_clock = BUS133; 2055 break; 2056 case 2: 2057 bus_clock = BUS200; 2058 break; 2059 case 3: 2060 bus_clock = BUS166; 2061 break; 2062 } 2063 } 2064 2065 void 2066 p4_get_bus_clock(struct cpu_info *ci) 2067 { 2068 u_int64_t msr; 2069 int model, bus; 2070 2071 model = (ci->ci_signature >> 4) & 15; 2072 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2073 if (model < 2) { 2074 bus = (msr >> 21) & 0x7; 2075 switch (bus) { 2076 case 0: 2077 bus_clock = BUS100; 2078 break; 2079 case 1: 2080 bus_clock = BUS133; 2081 break; 2082 default: 2083 printf("%s: unknown Pentium 4 (model %d) " 2084 "EBC_FREQUENCY_ID value %d\n", 2085 ci->ci_dev.dv_xname, model, bus); 2086 break; 2087 } 2088 } else { 2089 bus = (msr >> 16) & 0x7; 2090 switch (bus) { 2091 case 0: 2092 bus_clock = (model == 2) ? BUS100 : BUS266; 2093 break; 2094 case 1: 2095 bus_clock = BUS133; 2096 break; 2097 case 2: 2098 bus_clock = BUS200; 2099 break; 2100 case 3: 2101 bus_clock = BUS166; 2102 break; 2103 default: 2104 printf("%s: unknown Pentium 4 (model %d) " 2105 "EBC_FREQUENCY_ID value %d\n", 2106 ci->ci_dev.dv_xname, model, bus); 2107 break; 2108 } 2109 } 2110 } 2111 2112 void 2113 p3_get_bus_clock(struct cpu_info *ci) 2114 { 2115 u_int64_t msr; 2116 int bus; 2117 2118 switch (ci->ci_model) { 2119 case 0x9: /* Pentium M (130 nm, Banias) */ 2120 bus_clock = BUS100; 2121 break; 2122 case 0xd: /* Pentium M (90 nm, Dothan) */ 2123 msr = rdmsr(MSR_FSB_FREQ); 2124 bus = (msr >> 0) & 0x7; 2125 switch (bus) { 2126 case 0: 2127 bus_clock = BUS100; 2128 break; 2129 case 1: 2130 bus_clock = BUS133; 2131 break; 2132 default: 2133 printf("%s: unknown Pentium M FSB_FREQ value %d", 2134 ci->ci_dev.dv_xname, bus); 2135 goto print_msr; 2136 } 2137 break; 2138 case 0x15: /* EP80579 no FSB */ 2139 break; 2140 case 0xe: /* Core Duo/Solo */ 2141 case 0xf: /* Core Xeon */ 2142 case 0x16: /* 65nm Celeron */ 2143 case 0x17: /* Core 2 Extreme/45nm Xeon */ 2144 case 0x1d: /* Xeon MP 7400 */ 2145 msr = rdmsr(MSR_FSB_FREQ); 2146 bus = (msr >> 0) & 0x7; 2147 switch (bus) { 2148 case 5: 2149 bus_clock = BUS100; 2150 break; 2151 case 1: 2152 bus_clock = BUS133; 2153 break; 2154 case 3: 2155 bus_clock = BUS166; 2156 break; 2157 case 2: 2158 bus_clock = BUS200; 2159 break; 2160 case 0: 2161 bus_clock = BUS266; 2162 break; 2163 case 4: 2164 bus_clock = BUS333; 2165 break; 2166 default: 2167 printf("%s: unknown Core FSB_FREQ value %d", 2168 ci->ci_dev.dv_xname, bus); 2169 goto print_msr; 2170 } 2171 break; 2172 case 0x1c: /* Atom */ 2173 case 0x26: /* Atom Z6xx */ 2174 case 0x36: /* Atom [DN]2xxx */ 2175 msr = rdmsr(MSR_FSB_FREQ); 2176 bus = (msr >> 0) & 0x7; 2177 switch (bus) { 2178 case 5: 2179 bus_clock = BUS100; 2180 break; 2181 case 1: 2182 bus_clock = BUS133; 2183 break; 2184 case 3: 2185 bus_clock = BUS166; 2186 break; 2187 case 2: 2188 bus_clock = BUS200; 2189 break; 2190 default: 2191 printf("%s: unknown Atom FSB_FREQ value %d", 2192 ci->ci_dev.dv_xname, bus); 2193 goto print_msr; 2194 } 2195 break; 2196 case 0x1: /* Pentium Pro, model 1 */ 2197 case 0x3: /* Pentium II, model 3 */ 2198 case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */ 2199 case 0x6: /* Celeron, model 6 */ 2200 case 0x7: /* Pentium III, III Xeon, model 7 */ 2201 case 0x8: /* Pentium III, III Xeon, Celeron, model 8 */ 2202 case 0xa: /* Pentium III Xeon, model A */ 2203 case 0xb: /* Pentium III, model B */ 2204 msr = rdmsr(MSR_EBL_CR_POWERON); 2205 bus = (msr >> 18) & 0x3; 2206 switch (bus) { 2207 case 0: 2208 bus_clock = BUS66; 2209 break; 2210 case 1: 2211 bus_clock = BUS133; 2212 break; 2213 case 2: 2214 bus_clock = BUS100; 2215 break; 2216 default: 2217 printf("%s: unknown i686 EBL_CR_POWERON value %d", 2218 ci->ci_dev.dv_xname, bus); 2219 goto print_msr; 2220 } 2221 break; 2222 default: 2223 /* no FSB on modern Intel processors */ 2224 break; 2225 } 2226 return; 2227 print_msr: 2228 /* 2229 * Show the EBL_CR_POWERON MSR, so we'll at least have 2230 * some extra information, such as clock ratio, etc. 2231 */ 2232 printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON)); 2233 } 2234 2235 void 2236 p4_update_cpuspeed(void) 2237 { 2238 struct cpu_info *ci; 2239 u_int64_t msr; 2240 int mult; 2241 2242 ci = curcpu(); 2243 p4_get_bus_clock(ci); 2244 2245 if (bus_clock == 0) { 2246 printf("p4_update_cpuspeed: unknown bus clock\n"); 2247 return; 2248 } 2249 2250 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2251 mult = ((msr >> 24) & 0xff); 2252 2253 cpuspeed = (bus_clock * mult) / 100; 2254 } 2255 2256 void 2257 p3_update_cpuspeed(void) 2258 { 2259 struct cpu_info *ci; 2260 u_int64_t msr; 2261 int mult; 2262 const u_int8_t mult_code[] = { 2263 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 }; 2264 2265 ci = curcpu(); 2266 p3_get_bus_clock(ci); 2267 2268 if (bus_clock == 0) { 2269 printf("p3_update_cpuspeed: unknown bus clock\n"); 2270 return; 2271 } 2272 2273 msr = rdmsr(MSR_EBL_CR_POWERON); 2274 mult = (msr >> 22) & 0xf; 2275 mult = mult_code[mult]; 2276 if (!p3_early) 2277 mult += ((msr >> 27) & 0x1) * 40; 2278 2279 cpuspeed = (bus_clock * mult) / 1000; 2280 } 2281 2282 int 2283 pentium_cpuspeed(int *freq) 2284 { 2285 *freq = cpuspeed; 2286 return (0); 2287 } 2288 #endif /* !SMALL_KERNEL */ 2289 2290 /* 2291 * Send an interrupt to process. 2292 * 2293 * Stack is set up to allow sigcode stored 2294 * in u. to call routine, followed by kcall 2295 * to sigreturn routine below. After sigreturn 2296 * resets the signal mask, the stack, and the 2297 * frame pointer, it returns to the user 2298 * specified pc, psl. 2299 */ 2300 void 2301 sendsig(sig_t catcher, int sig, int mask, u_long code, int type, 2302 union sigval val) 2303 { 2304 struct proc *p = curproc; 2305 struct trapframe *tf = p->p_md.md_regs; 2306 struct sigframe *fp, frame; 2307 struct sigacts *psp = p->p_p->ps_sigacts; 2308 register_t sp; 2309 2310 /* 2311 * Build the argument list for the signal handler. 2312 */ 2313 bzero(&frame, sizeof(frame)); 2314 frame.sf_signum = sig; 2315 2316 /* 2317 * Allocate space for the signal handler context. 2318 */ 2319 if ((p->p_sigstk.ss_flags & SS_DISABLE) == 0 && 2320 !sigonstack(tf->tf_esp) && (psp->ps_sigonstack & sigmask(sig))) 2321 sp = (long)p->p_sigstk.ss_sp + p->p_sigstk.ss_size; 2322 else 2323 sp = tf->tf_esp; 2324 2325 frame.sf_sc.sc_fpstate = NULL; 2326 if (p->p_md.md_flags & MDP_USEDFPU) { 2327 npxsave_proc(p, 1); 2328 sp -= sizeof(union savefpu); 2329 sp &= ~0xf; /* for XMM regs */ 2330 frame.sf_sc.sc_fpstate = (void *)sp; 2331 if (copyout(&p->p_addr->u_pcb.pcb_savefpu, 2332 (void *)sp, sizeof(union savefpu))) 2333 sigexit(p, SIGILL); 2334 2335 /* Signal handlers get a completely clean FP state */ 2336 p->p_md.md_flags &= ~MDP_USEDFPU; 2337 } 2338 2339 fp = (struct sigframe *)sp - 1; 2340 frame.sf_scp = &fp->sf_sc; 2341 frame.sf_sip = NULL; 2342 frame.sf_handler = catcher; 2343 2344 /* 2345 * Build the signal context to be used by sigreturn. 2346 */ 2347 frame.sf_sc.sc_err = tf->tf_err; 2348 frame.sf_sc.sc_trapno = tf->tf_trapno; 2349 frame.sf_sc.sc_mask = mask; 2350 #ifdef VM86 2351 if (tf->tf_eflags & PSL_VM) { 2352 frame.sf_sc.sc_gs = tf->tf_vm86_gs; 2353 frame.sf_sc.sc_fs = tf->tf_vm86_fs; 2354 frame.sf_sc.sc_es = tf->tf_vm86_es; 2355 frame.sf_sc.sc_ds = tf->tf_vm86_ds; 2356 frame.sf_sc.sc_eflags = get_vflags(p); 2357 } else 2358 #endif 2359 { 2360 frame.sf_sc.sc_fs = tf->tf_fs; 2361 frame.sf_sc.sc_gs = tf->tf_gs; 2362 frame.sf_sc.sc_es = tf->tf_es; 2363 frame.sf_sc.sc_ds = tf->tf_ds; 2364 frame.sf_sc.sc_eflags = tf->tf_eflags; 2365 } 2366 frame.sf_sc.sc_edi = tf->tf_edi; 2367 frame.sf_sc.sc_esi = tf->tf_esi; 2368 frame.sf_sc.sc_ebp = tf->tf_ebp; 2369 frame.sf_sc.sc_ebx = tf->tf_ebx; 2370 frame.sf_sc.sc_edx = tf->tf_edx; 2371 frame.sf_sc.sc_ecx = tf->tf_ecx; 2372 frame.sf_sc.sc_eax = tf->tf_eax; 2373 frame.sf_sc.sc_eip = tf->tf_eip; 2374 frame.sf_sc.sc_cs = tf->tf_cs; 2375 frame.sf_sc.sc_esp = tf->tf_esp; 2376 frame.sf_sc.sc_ss = tf->tf_ss; 2377 2378 if (psp->ps_siginfo & sigmask(sig)) { 2379 frame.sf_sip = &fp->sf_si; 2380 initsiginfo(&frame.sf_si, sig, code, type, val); 2381 #ifdef VM86 2382 if (sig == SIGURG) /* VM86 userland trap */ 2383 frame.sf_si.si_trapno = code; 2384 #endif 2385 } 2386 2387 /* XXX don't copyout siginfo if not needed? */ 2388 if (copyout(&frame, fp, sizeof(frame)) != 0) { 2389 /* 2390 * Process has trashed its stack; give it an illegal 2391 * instruction to halt it in its tracks. 2392 */ 2393 sigexit(p, SIGILL); 2394 /* NOTREACHED */ 2395 } 2396 2397 /* 2398 * Build context to run handler in. 2399 */ 2400 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2401 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2402 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2403 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2404 tf->tf_eip = p->p_sigcode; 2405 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2406 tf->tf_eflags &= ~(PSL_T|PSL_D|PSL_VM|PSL_AC); 2407 tf->tf_esp = (int)fp; 2408 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2409 } 2410 2411 /* 2412 * System call to cleanup state after a signal 2413 * has been taken. Reset signal mask and 2414 * stack state from context left by sendsig (above). 2415 * Return to previous pc and psl as specified by 2416 * context left by sendsig. Check carefully to 2417 * make sure that the user has not modified the 2418 * psl to gain improper privileges or to cause 2419 * a machine fault. 2420 */ 2421 int 2422 sys_sigreturn(struct proc *p, void *v, register_t *retval) 2423 { 2424 struct sys_sigreturn_args /* { 2425 syscallarg(struct sigcontext *) sigcntxp; 2426 } */ *uap = v; 2427 struct sigcontext *scp, context; 2428 struct trapframe *tf = p->p_md.md_regs; 2429 int error; 2430 2431 /* 2432 * The trampoline code hands us the context. 2433 * It is unsafe to keep track of it ourselves, in the event that a 2434 * program jumps out of a signal handler. 2435 */ 2436 scp = SCARG(uap, sigcntxp); 2437 if (copyin((caddr_t)scp, &context, sizeof(*scp)) != 0) 2438 return (EFAULT); 2439 2440 /* 2441 * Restore signal context. 2442 */ 2443 #ifdef VM86 2444 if (context.sc_eflags & PSL_VM) { 2445 tf->tf_vm86_gs = context.sc_gs; 2446 tf->tf_vm86_fs = context.sc_fs; 2447 tf->tf_vm86_es = context.sc_es; 2448 tf->tf_vm86_ds = context.sc_ds; 2449 set_vflags(p, context.sc_eflags); 2450 } else 2451 #endif 2452 { 2453 /* 2454 * Check for security violations. If we're returning to 2455 * protected mode, the CPU will validate the segment registers 2456 * automatically and generate a trap on violations. We handle 2457 * the trap, rather than doing all of the checking here. 2458 */ 2459 if (((context.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 || 2460 !USERMODE(context.sc_cs, context.sc_eflags)) 2461 return (EINVAL); 2462 2463 tf->tf_fs = context.sc_fs; 2464 tf->tf_gs = context.sc_gs; 2465 tf->tf_es = context.sc_es; 2466 tf->tf_ds = context.sc_ds; 2467 tf->tf_eflags = context.sc_eflags; 2468 } 2469 tf->tf_edi = context.sc_edi; 2470 tf->tf_esi = context.sc_esi; 2471 tf->tf_ebp = context.sc_ebp; 2472 tf->tf_ebx = context.sc_ebx; 2473 tf->tf_edx = context.sc_edx; 2474 tf->tf_ecx = context.sc_ecx; 2475 tf->tf_eax = context.sc_eax; 2476 tf->tf_eip = context.sc_eip; 2477 tf->tf_cs = context.sc_cs; 2478 tf->tf_esp = context.sc_esp; 2479 tf->tf_ss = context.sc_ss; 2480 2481 if (p->p_md.md_flags & MDP_USEDFPU) 2482 npxsave_proc(p, 0); 2483 2484 if (context.sc_fpstate) { 2485 union savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu; 2486 2487 if ((error = copyin(context.sc_fpstate, sfp, sizeof(*sfp)))) 2488 return (error); 2489 if (i386_use_fxsave) 2490 sfp->sv_xmm.sv_env.en_mxcsr &= fpu_mxcsr_mask; 2491 p->p_md.md_flags |= MDP_USEDFPU; 2492 } 2493 2494 p->p_sigmask = context.sc_mask & ~sigcantmask; 2495 2496 return (EJUSTRETURN); 2497 } 2498 2499 #ifdef MULTIPROCESSOR 2500 /* force a CPU into the kernel, whether or not it's idle */ 2501 void 2502 cpu_kick(struct cpu_info *ci) 2503 { 2504 /* only need to kick other CPUs */ 2505 if (ci != curcpu()) { 2506 if (ci->ci_mwait != NULL) { 2507 /* 2508 * If not idling, then send an IPI, else 2509 * just clear the "keep idling" bit. 2510 */ 2511 if ((ci->ci_mwait[0] & MWAIT_IN_IDLE) == 0) 2512 i386_send_ipi(ci, I386_IPI_NOP); 2513 else 2514 atomic_clearbits_int(&ci->ci_mwait[0], 2515 MWAIT_KEEP_IDLING); 2516 } else { 2517 /* no mwait, so need an IPI */ 2518 i386_send_ipi(ci, I386_IPI_NOP); 2519 } 2520 } 2521 } 2522 #endif 2523 2524 /* 2525 * Notify the current process (p) that it has a signal pending, 2526 * process as soon as possible. 2527 */ 2528 void 2529 signotify(struct proc *p) 2530 { 2531 aston(p); 2532 cpu_kick(p->p_cpu); 2533 } 2534 2535 #ifdef MULTIPROCESSOR 2536 void 2537 cpu_unidle(struct cpu_info *ci) 2538 { 2539 if (ci->ci_mwait != NULL) { 2540 /* 2541 * Just clear the "keep idling" bit; if it wasn't 2542 * idling then we didn't need to do anything anyway. 2543 */ 2544 atomic_clearbits_int(&ci->ci_mwait[0], MWAIT_KEEP_IDLING); 2545 return; 2546 } 2547 2548 if (ci != curcpu()) 2549 i386_send_ipi(ci, I386_IPI_NOP); 2550 } 2551 #endif 2552 2553 int waittime = -1; 2554 struct pcb dumppcb; 2555 2556 void 2557 boot(int howto) 2558 { 2559 struct device *mainbus; 2560 2561 if (howto & RB_POWERDOWN) 2562 lid_suspend = 0; 2563 2564 if (cold) { 2565 /* 2566 * If the system is cold, just halt, unless the user 2567 * explicitly asked for reboot. 2568 */ 2569 if ((howto & RB_USERREQ) == 0) 2570 howto |= RB_HALT; 2571 goto haltsys; 2572 } 2573 2574 boothowto = howto; 2575 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 2576 extern struct proc proc0; 2577 2578 /* make sure there's a process to charge for I/O in sync() */ 2579 if (curproc == NULL) 2580 curproc = &proc0; 2581 2582 waittime = 0; 2583 vfs_shutdown(); 2584 /* 2585 * If we've been adjusting the clock, the todr 2586 * will be out of synch; adjust it now. 2587 */ 2588 if ((howto & RB_TIMEBAD) == 0) { 2589 resettodr(); 2590 } else { 2591 printf("WARNING: not updating battery clock\n"); 2592 } 2593 } 2594 if_downall(); 2595 2596 delay(4*1000000); /* XXX */ 2597 2598 uvm_shutdown(); 2599 splhigh(); /* Disable interrupts. */ 2600 2601 /* Do a dump if requested. */ 2602 if (howto & RB_DUMP) 2603 dumpsys(); 2604 2605 haltsys: 2606 doshutdownhooks(); 2607 mainbus = device_mainbus(); 2608 if (mainbus != NULL) 2609 config_suspend(mainbus, DVACT_POWERDOWN); 2610 2611 #ifdef MULTIPROCESSOR 2612 i386_broadcast_ipi(I386_IPI_HALT); 2613 #endif 2614 2615 if (howto & RB_HALT) { 2616 #if NACPI > 0 && !defined(SMALL_KERNEL) 2617 extern int acpi_enabled; 2618 2619 if (acpi_enabled) { 2620 delay(500000); 2621 if (howto & RB_POWERDOWN) 2622 acpi_powerdown(); 2623 } 2624 #endif 2625 2626 #if NAPM > 0 2627 if (howto & RB_POWERDOWN) { 2628 int rv; 2629 2630 printf("\nAttempting to power down...\n"); 2631 /* 2632 * Turn off, if we can. But try to turn disk off and 2633 * wait a bit first--some disk drives are slow to 2634 * clean up and users have reported disk corruption. 2635 * 2636 * If apm_set_powstate() fails the first time, don't 2637 * try to turn the system off. 2638 */ 2639 delay(500000); 2640 /* 2641 * It's been reported that the following bit of code 2642 * is required on most systems <mickey@openbsd.org> 2643 * but cause powerdown problem on other systems 2644 * <smcho@tsp.korea.ac.kr>. Use sysctl to set 2645 * apmhalt to a non-zero value to skip the offending 2646 * code. 2647 */ 2648 if (!cpu_apmhalt) { 2649 apm_set_powstate(APM_DEV_DISK(0xff), 2650 APM_SYS_OFF); 2651 delay(500000); 2652 } 2653 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2654 if (rv == 0 || rv == ENXIO) { 2655 delay(500000); 2656 (void) apm_set_powstate(APM_DEV_ALLDEVS, 2657 APM_SYS_OFF); 2658 } 2659 } 2660 #endif 2661 printf("\n"); 2662 printf("The operating system has halted.\n"); 2663 printf("Please press any key to reboot.\n\n"); 2664 cnpollc(1); /* for proper keyboard command handling */ 2665 cngetc(); 2666 cnpollc(0); 2667 } 2668 2669 printf("rebooting...\n"); 2670 cpu_reset(); 2671 for(;;) ; 2672 /*NOTREACHED*/ 2673 } 2674 2675 /* 2676 * This is called by configure to set dumplo and dumpsize. 2677 * Dumps always skip the first block of disk space 2678 * in case there might be a disk label stored there. 2679 * If there is extra space, put dump at the end to 2680 * reduce the chance that swapping trashes it. 2681 */ 2682 void 2683 dumpconf(void) 2684 { 2685 int nblks; /* size of dump area */ 2686 int i; 2687 2688 if (dumpdev == NODEV || 2689 (nblks = (bdevsw[major(dumpdev)].d_psize)(dumpdev)) == 0) 2690 return; 2691 if (nblks <= ctod(1)) 2692 return; 2693 2694 /* Always skip the first block, in case there is a label there. */ 2695 if (dumplo < ctod(1)) 2696 dumplo = ctod(1); 2697 2698 for (i = 0; i < ndumpmem; i++) 2699 dumpsize = max(dumpsize, dumpmem[i].end); 2700 2701 /* Put dump at end of partition, and make it fit. */ 2702 if (dumpsize > dtoc(nblks - dumplo - 1)) 2703 dumpsize = dtoc(nblks - dumplo - 1); 2704 if (dumplo < nblks - ctod(dumpsize) - 1) 2705 dumplo = nblks - ctod(dumpsize) - 1; 2706 } 2707 2708 /* 2709 * cpu_dump: dump machine-dependent kernel core dump headers. 2710 */ 2711 int 2712 cpu_dump() 2713 { 2714 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2715 long buf[dbtob(1) / sizeof (long)]; 2716 kcore_seg_t *segp; 2717 2718 dump = bdevsw[major(dumpdev)].d_dump; 2719 2720 segp = (kcore_seg_t *)buf; 2721 2722 /* 2723 * Generate a segment header. 2724 */ 2725 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 2726 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); 2727 2728 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1))); 2729 } 2730 2731 /* 2732 * Doadump comes here after turning off memory management and 2733 * getting on the dump stack, either when called above, or by 2734 * the auto-restart code. 2735 */ 2736 static vaddr_t dumpspace; 2737 2738 vaddr_t 2739 reserve_dumppages(vaddr_t p) 2740 { 2741 2742 dumpspace = p; 2743 return (p + PAGE_SIZE); 2744 } 2745 2746 void 2747 dumpsys() 2748 { 2749 u_int i, j, npg; 2750 int maddr; 2751 daddr_t blkno; 2752 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2753 int error; 2754 char *str; 2755 extern int msgbufmapped; 2756 2757 /* Save registers. */ 2758 savectx(&dumppcb); 2759 2760 msgbufmapped = 0; /* don't record dump msgs in msgbuf */ 2761 if (dumpdev == NODEV) 2762 return; 2763 2764 /* 2765 * For dumps during autoconfiguration, 2766 * if dump device has already configured... 2767 */ 2768 if (dumpsize == 0) 2769 dumpconf(); 2770 if (dumplo < 0) 2771 return; 2772 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo); 2773 2774 #ifdef UVM_SWAP_ENCRYPT 2775 uvm_swap_finicrypt_all(); 2776 #endif 2777 2778 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); 2779 printf("dump "); 2780 if (error == -1) { 2781 printf("area unavailable\n"); 2782 return; 2783 } 2784 2785 #if 0 /* XXX this doesn't work. grr. */ 2786 /* toss any characters present prior to dump */ 2787 while (sget() != NULL); /*syscons and pccons differ */ 2788 #endif 2789 2790 /* scan through the dumpmem list */ 2791 dump = bdevsw[major(dumpdev)].d_dump; 2792 error = cpu_dump(); 2793 for (i = 0; !error && i < ndumpmem; i++) { 2794 2795 npg = dumpmem[i].end - dumpmem[i].start; 2796 maddr = ptoa(dumpmem[i].start); 2797 blkno = dumplo + btodb(maddr) + 1; 2798 #if 0 2799 printf("(%d %lld %d) ", maddr, (long long)blkno, npg); 2800 #endif 2801 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) { 2802 2803 /* Print out how many MBs we have more to go. */ 2804 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG) 2805 printf("%ld ", 2806 (ptoa(dumpsize) - maddr) / (1024 * 1024)); 2807 #if 0 2808 printf("(%x %lld) ", maddr, (long long)blkno); 2809 #endif 2810 pmap_enter(pmap_kernel(), dumpspace, maddr, 2811 VM_PROT_READ, PMAP_WIRED); 2812 if ((error = (*dump)(dumpdev, blkno, 2813 (caddr_t)dumpspace, NBPG))) 2814 break; 2815 2816 #if 0 /* XXX this doesn't work. grr. */ 2817 /* operator aborting dump? */ 2818 if (sget() != NULL) { 2819 error = EINTR; 2820 break; 2821 } 2822 #endif 2823 } 2824 } 2825 2826 switch (error) { 2827 2828 case 0: str = "succeeded\n\n"; break; 2829 case ENXIO: str = "device bad\n\n"; break; 2830 case EFAULT: str = "device not ready\n\n"; break; 2831 case EINVAL: str = "area improper\n\n"; break; 2832 case EIO: str = "i/o error\n\n"; break; 2833 case EINTR: str = "aborted from console\n\n"; break; 2834 default: str = "error %d\n\n"; break; 2835 } 2836 printf(str, error); 2837 2838 delay(5000000); /* 5 seconds */ 2839 } 2840 2841 /* 2842 * Clear registers on exec 2843 */ 2844 void 2845 setregs(struct proc *p, struct exec_package *pack, u_long stack, 2846 register_t *retval) 2847 { 2848 struct pcb *pcb = &p->p_addr->u_pcb; 2849 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map); 2850 struct trapframe *tf = p->p_md.md_regs; 2851 2852 #if NNPX > 0 2853 /* If we were using the FPU, forget about it. */ 2854 if (pcb->pcb_fpcpu != NULL) 2855 npxsave_proc(p, 0); 2856 p->p_md.md_flags &= ~MDP_USEDFPU; 2857 #endif 2858 2859 #ifdef USER_LDT 2860 pmap_ldt_cleanup(p); 2861 #endif 2862 2863 /* 2864 * Reset the code segment limit to I386_MAX_EXE_ADDR in the pmap; 2865 * this gets copied into the GDT for GUCODE_SEL by pmap_activate(). 2866 * Similarly, reset the base of each of the two thread data 2867 * segments to zero in the pcb; they'll get copied into the 2868 * GDT for GUFS_SEL and GUGS_SEL. 2869 */ 2870 setsegment(&pmap->pm_codeseg, 0, atop(I386_MAX_EXE_ADDR) - 1, 2871 SDT_MEMERA, SEL_UPL, 1, 1); 2872 setsegment(&pcb->pcb_threadsegs[TSEG_FS], 0, 2873 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2874 setsegment(&pcb->pcb_threadsegs[TSEG_GS], 0, 2875 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2876 2877 /* 2878 * And update the GDT since we return to the user process 2879 * by leaving the syscall (we don't do another pmap_activate()). 2880 */ 2881 curcpu()->ci_gdt[GUCODE_SEL].sd = pmap->pm_codeseg; 2882 curcpu()->ci_gdt[GUFS_SEL].sd = pcb->pcb_threadsegs[TSEG_FS]; 2883 curcpu()->ci_gdt[GUGS_SEL].sd = pcb->pcb_threadsegs[TSEG_GS]; 2884 2885 /* 2886 * And reset the hiexec marker in the pmap. 2887 */ 2888 pmap->pm_hiexec = 0; 2889 2890 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2891 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2892 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2893 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2894 tf->tf_edi = 0; 2895 tf->tf_esi = 0; 2896 tf->tf_ebp = 0; 2897 tf->tf_ebx = (int)PS_STRINGS; 2898 tf->tf_edx = 0; 2899 tf->tf_ecx = 0; 2900 tf->tf_eax = 0; 2901 tf->tf_eip = pack->ep_entry; 2902 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2903 tf->tf_eflags = PSL_USERSET; 2904 tf->tf_esp = stack; 2905 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2906 2907 retval[1] = 0; 2908 } 2909 2910 /* 2911 * Initialize segments and descriptor tables 2912 */ 2913 2914 union descriptor ldt[NLDT]; 2915 struct gate_descriptor idt_region[NIDT]; 2916 struct gate_descriptor *idt = idt_region; 2917 2918 extern struct user *proc0paddr; 2919 2920 void 2921 setgate(struct gate_descriptor *gd, void *func, int args, int type, int dpl, 2922 int seg) 2923 { 2924 2925 gd->gd_looffset = (int)func; 2926 gd->gd_selector = GSEL(seg, SEL_KPL); 2927 gd->gd_stkcpy = args; 2928 gd->gd_xx = 0; 2929 gd->gd_type = type; 2930 gd->gd_dpl = dpl; 2931 gd->gd_p = 1; 2932 gd->gd_hioffset = (int)func >> 16; 2933 } 2934 2935 void 2936 unsetgate(struct gate_descriptor *gd) 2937 { 2938 gd->gd_p = 0; 2939 gd->gd_hioffset = 0; 2940 gd->gd_looffset = 0; 2941 gd->gd_selector = 0; 2942 gd->gd_xx = 0; 2943 gd->gd_stkcpy = 0; 2944 gd->gd_type = 0; 2945 gd->gd_dpl = 0; 2946 } 2947 2948 void 2949 setregion(struct region_descriptor *rd, void *base, size_t limit) 2950 { 2951 2952 rd->rd_limit = (int)limit; 2953 rd->rd_base = (int)base; 2954 } 2955 2956 void 2957 setsegment(struct segment_descriptor *sd, void *base, size_t limit, int type, 2958 int dpl, int def32, int gran) 2959 { 2960 2961 sd->sd_lolimit = (int)limit; 2962 sd->sd_lobase = (int)base; 2963 sd->sd_type = type; 2964 sd->sd_dpl = dpl; 2965 sd->sd_p = 1; 2966 sd->sd_hilimit = (int)limit >> 16; 2967 sd->sd_xx = 0; 2968 sd->sd_def32 = def32; 2969 sd->sd_gran = gran; 2970 sd->sd_hibase = (int)base >> 24; 2971 } 2972 2973 #define IDTVEC(name) __CONCAT(X, name) 2974 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 2975 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm), 2976 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page), 2977 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall), IDTVEC(mchk), 2978 IDTVEC(simd); 2979 2980 extern int IDTVEC(f00f_redirect); 2981 2982 int cpu_f00f_bug = 0; 2983 2984 void 2985 fix_f00f(void) 2986 { 2987 struct region_descriptor region; 2988 vaddr_t va; 2989 void *p; 2990 pt_entry_t *pte; 2991 2992 /* Allocate two new pages */ 2993 va = uvm_km_zalloc(kernel_map, NBPG*2); 2994 p = (void *)(va + NBPG - 7*sizeof(*idt)); 2995 2996 /* Copy over old IDT */ 2997 bcopy(idt, p, sizeof(idt_region)); 2998 idt = p; 2999 3000 /* Fix up paging redirect */ 3001 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386TGT, SEL_KPL, 3002 GCODE_SEL); 3003 3004 /* Map first page RO */ 3005 pte = PTE_BASE + atop(va); 3006 *pte &= ~PG_RW; 3007 3008 /* Reload idtr */ 3009 setregion(®ion, idt, sizeof(idt_region) - 1); 3010 lidt(®ion); 3011 3012 /* Tell the rest of the world */ 3013 cpu_f00f_bug = 1; 3014 } 3015 3016 #ifdef MULTIPROCESSOR 3017 void 3018 cpu_init_idt() 3019 { 3020 struct region_descriptor region; 3021 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3022 lidt(®ion); 3023 } 3024 3025 void 3026 cpu_default_ldt(struct cpu_info *ci) 3027 { 3028 ci->ci_ldt = ldt; 3029 ci->ci_ldt_len = sizeof(ldt); 3030 } 3031 3032 void 3033 cpu_alloc_ldt(struct cpu_info *ci) 3034 { 3035 union descriptor *cpu_ldt; 3036 size_t len = sizeof(ldt); 3037 3038 cpu_ldt = (union descriptor *)uvm_km_alloc(kernel_map, len); 3039 bcopy(ldt, cpu_ldt, len); 3040 ci->ci_ldt = cpu_ldt; 3041 ci->ci_ldt_len = len; 3042 } 3043 3044 void 3045 cpu_init_ldt(struct cpu_info *ci) 3046 { 3047 setsegment(&ci->ci_gdt[GLDT_SEL].sd, ci->ci_ldt, ci->ci_ldt_len - 1, 3048 SDT_SYSLDT, SEL_KPL, 0, 0); 3049 } 3050 #endif /* MULTIPROCESSOR */ 3051 3052 void 3053 init386(paddr_t first_avail) 3054 { 3055 int i, kb; 3056 struct region_descriptor region; 3057 bios_memmap_t *im; 3058 3059 proc0.p_addr = proc0paddr; 3060 cpu_info_primary.ci_self = &cpu_info_primary; 3061 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb; 3062 3063 /* 3064 * Initialize the I/O port and I/O mem extent maps. 3065 * Note: we don't have to check the return value since 3066 * creation of a fixed extent map will never fail (since 3067 * descriptor storage has already been allocated). 3068 * 3069 * N.B. The iomem extent manages _all_ physical addresses 3070 * on the machine. When the amount of RAM is found, the two 3071 * extents of RAM are allocated from the map (0 -> ISA hole 3072 * and end of ISA hole -> end of RAM). 3073 */ 3074 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF, 3075 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage), 3076 EX_NOCOALESCE|EX_NOWAIT); 3077 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF, 3078 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage), 3079 EX_NOCOALESCE|EX_NOWAIT); 3080 3081 /* make bootstrap gdt gates and memory segments */ 3082 setsegment(&gdt[GCODE_SEL].sd, 0, 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1); 3083 setsegment(&gdt[GICODE_SEL].sd, 0, 0xfffff, SDT_MEMERA, SEL_KPL, 1, 1); 3084 setsegment(&gdt[GDATA_SEL].sd, 0, 0xfffff, SDT_MEMRWA, SEL_KPL, 1, 1); 3085 setsegment(&gdt[GLDT_SEL].sd, ldt, sizeof(ldt) - 1, SDT_SYSLDT, 3086 SEL_KPL, 0, 0); 3087 setsegment(&gdt[GUCODE_SEL].sd, 0, atop(I386_MAX_EXE_ADDR) - 1, 3088 SDT_MEMERA, SEL_UPL, 1, 1); 3089 setsegment(&gdt[GUDATA_SEL].sd, 0, atop(VM_MAXUSER_ADDRESS) - 1, 3090 SDT_MEMRWA, SEL_UPL, 1, 1); 3091 setsegment(&gdt[GCPU_SEL].sd, &cpu_info_primary, 3092 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 0, 0); 3093 setsegment(&gdt[GUFS_SEL].sd, 0, atop(VM_MAXUSER_ADDRESS) - 1, 3094 SDT_MEMRWA, SEL_UPL, 1, 1); 3095 setsegment(&gdt[GUGS_SEL].sd, 0, atop(VM_MAXUSER_ADDRESS) - 1, 3096 SDT_MEMRWA, SEL_UPL, 1, 1); 3097 3098 /* exceptions */ 3099 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3100 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3101 setgate(&idt[ 2], &IDTVEC(nmi), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3102 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386TGT, SEL_UPL, GCODE_SEL); 3103 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386TGT, SEL_UPL, GCODE_SEL); 3104 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3105 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3106 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3107 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3108 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3109 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3110 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3111 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3112 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3113 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3114 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3115 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3116 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3117 setgate(&idt[ 18], &IDTVEC(mchk), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3118 setgate(&idt[ 19], &IDTVEC(simd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3119 for (i = 20; i < NRSVIDT; i++) 3120 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386TGT, SEL_KPL, GCODE_SEL); 3121 for (i = NRSVIDT; i < NIDT; i++) 3122 unsetgate(&idt[i]); 3123 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386TGT, SEL_UPL, GCODE_SEL); 3124 3125 setregion(®ion, gdt, NGDT * sizeof(union descriptor) - 1); 3126 lgdt(®ion); 3127 setregion(®ion, idt, sizeof(idt_region) - 1); 3128 lidt(®ion); 3129 3130 #if NISA > 0 3131 isa_defaultirq(); 3132 #endif 3133 3134 /* 3135 * Attach the glass console early in case we need to display a panic. 3136 */ 3137 cninit(); 3138 3139 /* 3140 * Saving SSE registers won't work if the save area isn't 3141 * 16-byte aligned. 3142 */ 3143 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf) 3144 panic("init386: pcb_savefpu not 16-byte aligned"); 3145 3146 /* call pmap initialization to make new kernel address space */ 3147 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE); 3148 3149 /* 3150 * Boot arguments are in a single page specified by /boot. 3151 * 3152 * We require the "new" vector form, as well as memory ranges 3153 * to be given in bytes rather than KB. 3154 */ 3155 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) == 3156 (BAPIV_VECTOR | BAPIV_BMEMMAP)) { 3157 if (bootargc > NBPG) 3158 panic("too many boot args"); 3159 3160 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc, 3161 EX_NOWAIT)) 3162 panic("cannot reserve /boot args memory"); 3163 3164 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv, 3165 VM_PROT_READ|VM_PROT_WRITE, 3166 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 3167 3168 bios_getopt(); 3169 3170 } else 3171 panic("/boot too old: upgrade!"); 3172 3173 #ifdef DIAGNOSTIC 3174 if (bios_memmap == NULL) 3175 panic("no BIOS memory map supplied"); 3176 #endif 3177 3178 #if defined(MULTIPROCESSOR) 3179 /* install the lowmem ptp after boot args for 1:1 mappings */ 3180 pmap_prealloc_lowmem_ptp(round_page((paddr_t)(bootargv + bootargc))); 3181 #endif 3182 3183 /* 3184 * account all the memory passed in the map from /boot 3185 * calculate avail_end and count the physmem. 3186 */ 3187 avail_end = 0; 3188 physmem = 0; 3189 #ifdef DEBUG 3190 printf("memmap:"); 3191 #endif 3192 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++) 3193 if (im->type == BIOS_MAP_FREE) { 3194 paddr_t a, e; 3195 #ifdef DEBUG 3196 printf(" %llx-%llx", im->addr, im->addr + im->size); 3197 #endif 3198 3199 if (im->addr >= 0x100000000ULL) { 3200 #ifdef DEBUG 3201 printf("-H"); 3202 #endif 3203 continue; 3204 } 3205 3206 a = round_page(im->addr); 3207 if (im->addr + im->size <= 0xfffff000ULL) 3208 e = trunc_page(im->addr + im->size); 3209 else { 3210 #ifdef DEBUG 3211 printf("-T"); 3212 #endif 3213 e = 0xfffff000; 3214 } 3215 3216 /* skip first 16 pages due to SMI corruption */ 3217 if (a < 16 * NBPG) 3218 a = 16 * NBPG; 3219 3220 #ifdef MULTIPROCESSOR 3221 /* skip MP trampoline code page */ 3222 if (a < MP_TRAMPOLINE + NBPG) 3223 a = MP_TRAMPOLINE + NBPG; 3224 #endif /* MULTIPROCESSOR */ 3225 3226 #if NACPI > 0 && !defined(SMALL_KERNEL) 3227 /* skip ACPI resume trampoline code page */ 3228 if (a < ACPI_TRAMPOLINE + NBPG) 3229 a = ACPI_TRAMPOLINE + NBPG; 3230 #endif /* ACPI */ 3231 3232 #ifdef HIBERNATE 3233 /* skip hibernate reserved pages */ 3234 if (a < HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE) 3235 a = HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE; 3236 #endif /* HIBERNATE */ 3237 3238 /* skip shorter than page regions */ 3239 if (a >= e || (e - a) < NBPG) { 3240 #ifdef DEBUG 3241 printf("-S"); 3242 #endif 3243 continue; 3244 } 3245 3246 /* 3247 * XXX Some buggy ACPI BIOSes use memory that 3248 * they declare as free. Typically the 3249 * affected memory areas are small blocks 3250 * between areas reserved for ACPI and other 3251 * BIOS goo. So skip areas smaller than 1 MB 3252 * above the 16 MB boundary (to avoid 3253 * affecting legacy stuff). 3254 */ 3255 if (a > 16*1024*1024 && (e - a) < 1*1024*1024) { 3256 #ifdef DEBUG 3257 printf("-X"); 3258 #endif 3259 continue; 3260 } 3261 3262 /* skip legacy IO region */ 3263 if ((a > IOM_BEGIN && a < IOM_END) || 3264 (e > IOM_BEGIN && e < IOM_END)) { 3265 #ifdef DEBUG 3266 printf("-I"); 3267 #endif 3268 continue; 3269 } 3270 3271 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT)) 3272 /* XXX What should we do? */ 3273 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)" 3274 " FROM IOMEM EXTENT MAP!\n", a, e); 3275 3276 physmem += atop(e - a); 3277 dumpmem[i].start = atop(a); 3278 dumpmem[i].end = atop(e); 3279 i++; 3280 avail_end = max(avail_end, e); 3281 } 3282 3283 ndumpmem = i; 3284 avail_end -= round_page(MSGBUFSIZE); 3285 3286 #ifdef DEBUG 3287 printf(": %lx\n", avail_end); 3288 #endif 3289 if (physmem < atop(4 * 1024 * 1024)) { 3290 printf("\awarning: too little memory available;" 3291 "running in degraded mode\npress a key to confirm\n\n"); 3292 cnpollc(1); 3293 cngetc(); 3294 cnpollc(0); 3295 } 3296 3297 #ifdef DEBUG 3298 printf("physload: "); 3299 #endif 3300 kb = atop(KERNTEXTOFF - KERNBASE); 3301 if (kb > atop(IOM_END)) { 3302 paddr_t lim = atop(IOM_END); 3303 #ifdef DEBUG 3304 printf(" %x-%x (<16M)", lim, kb); 3305 #endif 3306 uvm_page_physload(lim, kb, lim, kb, 0); 3307 } 3308 3309 for (i = 0; i < ndumpmem; i++) { 3310 paddr_t a, e; 3311 3312 a = dumpmem[i].start; 3313 e = dumpmem[i].end; 3314 if (a < atop(first_avail) && e > atop(first_avail)) 3315 a = atop(first_avail); 3316 if (e > atop(avail_end)) 3317 e = atop(avail_end); 3318 3319 if (a < e) { 3320 #ifdef DEBUG 3321 printf(" %x-%x", a, e); 3322 #endif 3323 uvm_page_physload(a, e, a, e, 0); 3324 } 3325 } 3326 #ifdef DEBUG 3327 printf("\n"); 3328 #endif 3329 3330 #if defined(MULTIPROCESSOR) || \ 3331 (NACPI > 0 && !defined(SMALL_KERNEL)) 3332 /* install the lowmem ptp after boot args for 1:1 mappings */ 3333 pmap_prealloc_lowmem_ptp(PTP0_PA); 3334 #endif 3335 3336 #ifdef MULTIPROCESSOR 3337 pmap_kenter_pa((vaddr_t)MP_TRAMPOLINE, /* virtual */ 3338 (paddr_t)MP_TRAMPOLINE, /* physical */ 3339 VM_PROT_ALL); /* protection */ 3340 #endif 3341 3342 #if NACPI > 0 && !defined(SMALL_KERNEL) 3343 pmap_kenter_pa((vaddr_t)ACPI_TRAMPOLINE,/* virtual */ 3344 (paddr_t)ACPI_TRAMPOLINE, /* physical */ 3345 VM_PROT_ALL); /* protection */ 3346 #endif 3347 3348 tlbflush(); 3349 #if 0 3350 #if NISADMA > 0 3351 /* 3352 * Some motherboards/BIOSes remap the 384K of RAM that would 3353 * normally be covered by the ISA hole to the end of memory 3354 * so that it can be used. However, on a 16M system, this 3355 * would cause bounce buffers to be allocated and used. 3356 * This is not desirable behaviour, as more than 384K of 3357 * bounce buffers might be allocated. As a work-around, 3358 * we round memory down to the nearest 1M boundary if 3359 * we're using any isadma devices and the remapped memory 3360 * is what puts us over 16M. 3361 */ 3362 if (extmem > (15*1024) && extmem < (16*1024)) { 3363 printf("Warning: ignoring %dk of remapped memory\n", 3364 extmem - (15*1024)); 3365 extmem = (15*1024); 3366 } 3367 #endif 3368 #endif 3369 3370 #ifdef DDB 3371 db_machine_init(); 3372 ddb_init(); 3373 if (boothowto & RB_KDB) 3374 Debugger(); 3375 #endif 3376 #ifdef KGDB 3377 kgdb_port_init(); 3378 if (boothowto & RB_KDB) { 3379 kgdb_debug_init = 1; 3380 kgdb_connect(1); 3381 } 3382 #endif /* KGDB */ 3383 3384 softintr_init(); 3385 } 3386 3387 /* 3388 * consinit: 3389 * initialize the system console. 3390 */ 3391 void 3392 consinit() 3393 { 3394 /* Already done in init386(). */ 3395 } 3396 3397 #ifdef KGDB 3398 void 3399 kgdb_port_init() 3400 { 3401 3402 #if NCOM > 0 3403 if (!strcmp(kgdb_devname, "com")) { 3404 bus_space_tag_t tag = I386_BUS_SPACE_IO; 3405 com_kgdb_attach(tag, comkgdbaddr, comkgdbrate, COM_FREQ, 3406 comkgdbmode); 3407 } 3408 #endif 3409 } 3410 #endif /* KGDB */ 3411 3412 void 3413 cpu_reset() 3414 { 3415 struct region_descriptor region; 3416 3417 disable_intr(); 3418 3419 if (cpuresetfn) 3420 (*cpuresetfn)(); 3421 3422 /* 3423 * The keyboard controller has 4 random output pins, one of which is 3424 * connected to the RESET pin on the CPU in many PCs. We tell the 3425 * keyboard controller to pulse this line a couple of times. 3426 */ 3427 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3428 delay(100000); 3429 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3430 delay(100000); 3431 3432 /* 3433 * Try to cause a triple fault and watchdog reset by setting the 3434 * IDT to point to nothing. 3435 */ 3436 bzero((caddr_t)idt, sizeof(idt_region)); 3437 setregion(®ion, idt, sizeof(idt_region) - 1); 3438 lidt(®ion); 3439 __asm __volatile("divl %0,%1" : : "q" (0), "a" (0)); 3440 3441 #if 1 3442 /* 3443 * Try to cause a triple fault and watchdog reset by unmapping the 3444 * entire address space. 3445 */ 3446 bzero((caddr_t)PTD, NBPG); 3447 tlbflush(); 3448 #endif 3449 3450 for (;;); 3451 } 3452 3453 void 3454 cpu_initclocks(void) 3455 { 3456 (*initclock_func)(); /* lapic or i8254 */ 3457 } 3458 3459 void 3460 need_resched(struct cpu_info *ci) 3461 { 3462 ci->ci_want_resched = 1; 3463 3464 /* There's a risk we'll be called before the idle threads start */ 3465 if (ci->ci_curproc) { 3466 aston(ci->ci_curproc); 3467 cpu_kick(ci); 3468 } 3469 } 3470 3471 /* Allocate an IDT vector slot within the given range. 3472 * XXX needs locking to avoid MP allocation races. 3473 */ 3474 3475 int 3476 idt_vec_alloc(int low, int high) 3477 { 3478 int vec; 3479 3480 for (vec = low; vec <= high; vec++) 3481 if (idt[vec].gd_p == 0) 3482 return (vec); 3483 return (0); 3484 } 3485 3486 void 3487 idt_vec_set(int vec, void (*function)(void)) 3488 { 3489 setgate(&idt[vec], function, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL); 3490 } 3491 3492 void 3493 idt_vec_free(int vec) 3494 { 3495 unsetgate(&idt[vec]); 3496 } 3497 3498 /* 3499 * machine dependent system variables. 3500 */ 3501 int 3502 cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 3503 size_t newlen, struct proc *p) 3504 { 3505 dev_t dev; 3506 3507 switch (name[0]) { 3508 case CPU_CONSDEV: 3509 if (namelen != 1) 3510 return (ENOTDIR); /* overloaded */ 3511 3512 if (cn_tab != NULL) 3513 dev = cn_tab->cn_dev; 3514 else 3515 dev = NODEV; 3516 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3517 #if NBIOS > 0 3518 case CPU_BIOS: 3519 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp, 3520 newp, newlen, p); 3521 #endif 3522 case CPU_BLK2CHR: 3523 if (namelen != 2) 3524 return (ENOTDIR); /* overloaded */ 3525 dev = blktochr((dev_t)name[1]); 3526 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3527 case CPU_CHR2BLK: 3528 if (namelen != 2) 3529 return (ENOTDIR); /* overloaded */ 3530 dev = chrtoblk((dev_t)name[1]); 3531 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3532 case CPU_ALLOWAPERTURE: 3533 #ifdef APERTURE 3534 if (securelevel > 0) 3535 return (sysctl_int_lower(oldp, oldlenp, newp, newlen, 3536 &allowaperture)); 3537 else 3538 return (sysctl_int(oldp, oldlenp, newp, newlen, 3539 &allowaperture)); 3540 #else 3541 return (sysctl_rdint(oldp, oldlenp, newp, 0)); 3542 #endif 3543 case CPU_CPUVENDOR: 3544 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor)); 3545 case CPU_CPUID: 3546 return (sysctl_rdint(oldp, oldlenp, newp, cpu_id)); 3547 case CPU_CPUFEATURE: 3548 return (sysctl_rdint(oldp, oldlenp, newp, curcpu()->ci_feature_flags)); 3549 #if NAPM > 0 3550 case CPU_APMWARN: 3551 return (sysctl_int(oldp, oldlenp, newp, newlen, &cpu_apmwarn)); 3552 case CPU_APMHALT: 3553 return (sysctl_int(oldp, oldlenp, newp, newlen, &cpu_apmhalt)); 3554 #endif 3555 case CPU_KBDRESET: 3556 if (securelevel > 0) 3557 return (sysctl_rdint(oldp, oldlenp, newp, 3558 kbd_reset)); 3559 else 3560 return (sysctl_int(oldp, oldlenp, newp, newlen, 3561 &kbd_reset)); 3562 #ifdef USER_LDT 3563 case CPU_USERLDT: 3564 return (sysctl_int(oldp, oldlenp, newp, newlen, 3565 &user_ldt_enable)); 3566 #endif 3567 case CPU_OSFXSR: 3568 return (sysctl_rdint(oldp, oldlenp, newp, i386_use_fxsave)); 3569 case CPU_SSE: 3570 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse)); 3571 case CPU_SSE2: 3572 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_sse2)); 3573 case CPU_XCRYPT: 3574 return (sysctl_rdint(oldp, oldlenp, newp, i386_has_xcrypt)); 3575 case CPU_LIDSUSPEND: 3576 return (sysctl_int(oldp, oldlenp, newp, newlen, &lid_suspend)); 3577 default: 3578 return (EOPNOTSUPP); 3579 } 3580 /* NOTREACHED */ 3581 } 3582 3583 int 3584 bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, 3585 bus_space_handle_t *bshp) 3586 { 3587 int error; 3588 struct extent *ex; 3589 3590 /* 3591 * Pick the appropriate extent map. 3592 */ 3593 switch (t) { 3594 case I386_BUS_SPACE_IO: 3595 ex = ioport_ex; 3596 if (flags & BUS_SPACE_MAP_LINEAR) 3597 return (EINVAL); 3598 break; 3599 3600 case I386_BUS_SPACE_MEM: 3601 ex = iomem_ex; 3602 break; 3603 3604 default: 3605 panic("bus_space_map: bad bus space tag"); 3606 } 3607 3608 /* 3609 * Before we go any further, let's make sure that this 3610 * region is available. 3611 */ 3612 error = extent_alloc_region(ex, bpa, size, 3613 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0)); 3614 if (error) 3615 return (error); 3616 3617 /* 3618 * For I/O space, that's all she wrote. 3619 */ 3620 if (t == I386_BUS_SPACE_IO) { 3621 *bshp = bpa; 3622 return (0); 3623 } 3624 3625 if (IOM_BEGIN <= bpa && bpa <= IOM_END) { 3626 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa); 3627 return (0); 3628 } 3629 3630 /* 3631 * For memory space, map the bus physical address to 3632 * a kernel virtual address. 3633 */ 3634 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3635 if (error) { 3636 if (extent_free(ex, bpa, size, EX_NOWAIT | 3637 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3638 printf("bus_space_map: pa 0x%lx, size 0x%lx\n", 3639 bpa, size); 3640 printf("bus_space_map: can't free region\n"); 3641 } 3642 } 3643 3644 return (error); 3645 } 3646 3647 int 3648 _bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, 3649 int flags, bus_space_handle_t *bshp) 3650 { 3651 /* 3652 * For I/O space, that's all she wrote. 3653 */ 3654 if (t == I386_BUS_SPACE_IO) { 3655 *bshp = bpa; 3656 return (0); 3657 } 3658 3659 /* 3660 * For memory space, map the bus physical address to 3661 * a kernel virtual address. 3662 */ 3663 return (bus_mem_add_mapping(bpa, size, flags, bshp)); 3664 } 3665 3666 int 3667 bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, 3668 bus_size_t size, bus_size_t alignment, bus_size_t boundary, 3669 int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) 3670 { 3671 struct extent *ex; 3672 u_long bpa; 3673 int error; 3674 3675 /* 3676 * Pick the appropriate extent map. 3677 */ 3678 switch (t) { 3679 case I386_BUS_SPACE_IO: 3680 ex = ioport_ex; 3681 break; 3682 3683 case I386_BUS_SPACE_MEM: 3684 ex = iomem_ex; 3685 break; 3686 3687 default: 3688 panic("bus_space_alloc: bad bus space tag"); 3689 } 3690 3691 /* 3692 * Sanity check the allocation against the extent's boundaries. 3693 */ 3694 if (rstart < ex->ex_start || rend > ex->ex_end) 3695 panic("bus_space_alloc: bad region start/end"); 3696 3697 /* 3698 * Do the requested allocation. 3699 */ 3700 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0, 3701 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0), 3702 &bpa); 3703 3704 if (error) 3705 return (error); 3706 3707 /* 3708 * For I/O space, that's all she wrote. 3709 */ 3710 if (t == I386_BUS_SPACE_IO) { 3711 *bshp = *bpap = bpa; 3712 return (0); 3713 } 3714 3715 /* 3716 * For memory space, map the bus physical address to 3717 * a kernel virtual address. 3718 */ 3719 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3720 if (error) { 3721 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT | 3722 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3723 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n", 3724 bpa, size); 3725 printf("bus_space_alloc: can't free region\n"); 3726 } 3727 } 3728 3729 *bpap = bpa; 3730 3731 return (error); 3732 } 3733 3734 int 3735 bus_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int flags, 3736 bus_space_handle_t *bshp) 3737 { 3738 paddr_t pa, endpa; 3739 vaddr_t va; 3740 bus_size_t map_size; 3741 int pmap_flags = PMAP_NOCACHE; 3742 3743 pa = trunc_page(bpa); 3744 endpa = round_page(bpa + size); 3745 3746 #ifdef DIAGNOSTIC 3747 if (endpa <= pa && endpa != 0) 3748 panic("bus_mem_add_mapping: overflow"); 3749 #endif 3750 3751 map_size = endpa - pa; 3752 3753 va = uvm_km_valloc(kernel_map, map_size); 3754 if (va == 0) 3755 return (ENOMEM); 3756 3757 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 3758 3759 if (flags & BUS_SPACE_MAP_CACHEABLE) 3760 pmap_flags = 0; 3761 else if (flags & BUS_SPACE_MAP_PREFETCHABLE) 3762 pmap_flags = PMAP_WC; 3763 3764 for (; map_size > 0; 3765 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE) 3766 pmap_kenter_pa(va, pa | pmap_flags, 3767 VM_PROT_READ | VM_PROT_WRITE); 3768 pmap_update(pmap_kernel()); 3769 3770 return 0; 3771 } 3772 3773 void 3774 bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3775 { 3776 struct extent *ex; 3777 u_long va, endva; 3778 bus_addr_t bpa; 3779 3780 /* 3781 * Find the correct extent and bus physical address. 3782 */ 3783 if (t == I386_BUS_SPACE_IO) { 3784 ex = ioport_ex; 3785 bpa = bsh; 3786 } else if (t == I386_BUS_SPACE_MEM) { 3787 ex = iomem_ex; 3788 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3789 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3790 goto ok; 3791 3792 va = trunc_page(bsh); 3793 endva = round_page(bsh + size); 3794 3795 #ifdef DIAGNOSTIC 3796 if (endva <= va) 3797 panic("bus_space_unmap: overflow"); 3798 #endif 3799 3800 (void) pmap_extract(pmap_kernel(), va, &bpa); 3801 bpa += (bsh & PGOFSET); 3802 3803 pmap_kremove(va, endva - va); 3804 pmap_update(pmap_kernel()); 3805 3806 /* 3807 * Free the kernel virtual mapping. 3808 */ 3809 uvm_km_free(kernel_map, va, endva - va); 3810 } else 3811 panic("bus_space_unmap: bad bus space tag"); 3812 3813 ok: 3814 if (extent_free(ex, bpa, size, 3815 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3816 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n", 3817 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size); 3818 printf("bus_space_unmap: can't free region\n"); 3819 } 3820 } 3821 3822 void 3823 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size, 3824 bus_addr_t *adrp) 3825 { 3826 u_long va, endva; 3827 bus_addr_t bpa; 3828 3829 /* 3830 * Find the correct bus physical address. 3831 */ 3832 if (t == I386_BUS_SPACE_IO) { 3833 bpa = bsh; 3834 } else if (t == I386_BUS_SPACE_MEM) { 3835 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3836 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3837 goto ok; 3838 3839 va = trunc_page(bsh); 3840 endva = round_page(bsh + size); 3841 3842 #ifdef DIAGNOSTIC 3843 if (endva <= va) 3844 panic("_bus_space_unmap: overflow"); 3845 #endif 3846 3847 (void) pmap_extract(pmap_kernel(), va, &bpa); 3848 bpa += (bsh & PGOFSET); 3849 3850 pmap_kremove(va, endva - va); 3851 pmap_update(pmap_kernel()); 3852 3853 /* 3854 * Free the kernel virtual mapping. 3855 */ 3856 uvm_km_free(kernel_map, va, endva - va); 3857 } else 3858 panic("bus_space_unmap: bad bus space tag"); 3859 3860 ok: 3861 if (adrp != NULL) 3862 *adrp = bpa; 3863 } 3864 3865 void 3866 bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3867 { 3868 3869 /* bus_space_unmap() does all that we need to do. */ 3870 bus_space_unmap(t, bsh, size); 3871 } 3872 3873 int 3874 bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 3875 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 3876 { 3877 *nbshp = bsh + offset; 3878 return (0); 3879 } 3880 3881 paddr_t 3882 bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags) 3883 { 3884 /* Can't mmap I/O space. */ 3885 if (t == I386_BUS_SPACE_IO) 3886 return (-1); 3887 3888 return (addr + off); 3889 } 3890 3891 #ifdef DIAGNOSTIC 3892 void 3893 splassert_check(int wantipl, const char *func) 3894 { 3895 if (lapic_tpr < wantipl) 3896 splassert_fail(wantipl, lapic_tpr, func); 3897 if (wantipl == IPL_NONE && curcpu()->ci_idepth != 0) 3898 splassert_fail(-1, curcpu()->ci_idepth, func); 3899 } 3900 #endif 3901 3902 #ifdef MULTIPROCESSOR 3903 void 3904 i386_softintlock(void) 3905 { 3906 __mp_lock(&kernel_lock); 3907 } 3908 3909 void 3910 i386_softintunlock(void) 3911 { 3912 __mp_unlock(&kernel_lock); 3913 } 3914 #endif 3915 3916 /* 3917 * True if the system has any non-level interrupts which are shared 3918 * on the same pin. 3919 */ 3920 int intr_shared_edge; 3921 3922 /* 3923 * Software interrupt registration 3924 * 3925 * We hand-code this to ensure that it's atomic. 3926 */ 3927 void 3928 softintr(int sir) 3929 { 3930 struct cpu_info *ci = curcpu(); 3931 3932 __asm __volatile("orl %1, %0" : 3933 "=m" (ci->ci_ipending) : "ir" (1 << sir)); 3934 } 3935 3936 /* 3937 * Raise current interrupt priority level, and return the old one. 3938 */ 3939 int 3940 splraise(int ncpl) 3941 { 3942 int ocpl; 3943 3944 _SPLRAISE(ocpl, ncpl); 3945 return (ocpl); 3946 } 3947 3948 /* 3949 * Restore an old interrupt priority level. If any thereby unmasked 3950 * interrupts are pending, call Xspllower() to process them. 3951 */ 3952 void 3953 splx(int ncpl) 3954 { 3955 _SPLX(ncpl); 3956 } 3957 3958 /* 3959 * Same as splx(), but we return the old value of spl, for the 3960 * benefit of some splsoftclock() callers. 3961 */ 3962 int 3963 spllower(int ncpl) 3964 { 3965 int ocpl = lapic_tpr; 3966 3967 splx(ncpl); 3968 return (ocpl); 3969 } 3970 3971 int 3972 intr_handler(struct intrframe *frame, struct intrhand *ih) 3973 { 3974 int rc; 3975 #ifdef MULTIPROCESSOR 3976 int need_lock; 3977 3978 if (ih->ih_flags & IPL_MPSAFE) 3979 need_lock = 0; 3980 else 3981 need_lock = frame->if_ppl < IPL_SCHED; 3982 3983 if (need_lock) 3984 __mp_lock(&kernel_lock); 3985 #endif 3986 rc = (*ih->ih_fun)(ih->ih_arg ? ih->ih_arg : frame); 3987 #ifdef MULTIPROCESSOR 3988 if (need_lock) 3989 __mp_unlock(&kernel_lock); 3990 #endif 3991 return rc; 3992 } 3993 3994