1 /* $OpenBSD: machdep.c,v 1.646 2021/10/06 15:46:03 claudio Exp $ */ 2 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 36 * Copyright (c) 1992 Terrence R. Lambert. 37 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to Berkeley by 41 * William Jolitz. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/signalvar.h> 73 #include <sys/kernel.h> 74 #include <sys/proc.h> 75 #include <sys/user.h> 76 #include <sys/exec.h> 77 #include <sys/buf.h> 78 #include <sys/reboot.h> 79 #include <sys/conf.h> 80 #include <sys/timeout.h> 81 #include <sys/malloc.h> 82 #include <sys/mbuf.h> 83 #include <sys/msgbuf.h> 84 #include <sys/mount.h> 85 #include <sys/vnode.h> 86 #include <sys/device.h> 87 #include <sys/extent.h> 88 #include <sys/sysctl.h> 89 #include <sys/syscallargs.h> 90 #include <sys/core.h> 91 #include <sys/kcore.h> 92 #include <sys/sensors.h> 93 94 #include <dev/cons.h> 95 #include <stand/boot/bootarg.h> 96 97 #include <net/if.h> 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <machine/cpu.h> 103 #include <machine/cpu_full.h> 104 #include <machine/cpufunc.h> 105 #include <machine/cpuvar.h> 106 #include <machine/gdt.h> 107 #include <machine/kcore.h> 108 #include <machine/pio.h> 109 #include <machine/psl.h> 110 #include <machine/reg.h> 111 #include <machine/specialreg.h> 112 #include <machine/biosvar.h> 113 #include <machine/pte.h> 114 #ifdef MULTIPROCESSOR 115 #include <machine/mpbiosvar.h> 116 #endif /* MULTIPROCESSOR */ 117 118 #include <dev/isa/isareg.h> 119 #include <dev/isa/isavar.h> 120 #include <dev/ic/i8042reg.h> 121 #include <dev/ic/mc146818reg.h> 122 #include <i386/isa/isa_machdep.h> 123 #include <i386/isa/nvram.h> 124 125 #include "acpi.h" 126 #if NACPI > 0 127 #include <dev/acpi/acpivar.h> 128 #endif 129 130 #include "apm.h" 131 #if NAPM > 0 132 #include <machine/apmvar.h> 133 #endif 134 135 #ifdef DDB 136 #include <machine/db_machdep.h> 137 #include <ddb/db_access.h> 138 #include <ddb/db_sym.h> 139 #include <ddb/db_extern.h> 140 #endif 141 142 #include "isa.h" 143 #include "isadma.h" 144 #include "npx.h" 145 #if NNPX > 0 146 extern struct proc *npxproc; 147 #endif 148 149 #include "bios.h" 150 #include "com.h" 151 152 #if NCOM > 0 153 #include <sys/termios.h> 154 #include <dev/ic/comreg.h> 155 #include <dev/ic/comvar.h> 156 #endif /* NCOM > 0 */ 157 158 #ifdef HIBERNATE 159 #include <machine/hibernate_var.h> 160 #endif /* HIBERNATE */ 161 162 #include "ukbd.h" 163 #include "pckbc.h" 164 #if NPCKBC > 0 && NUKBD > 0 165 #include <dev/ic/pckbcvar.h> 166 #endif 167 168 /* #define MACHDEP_DEBUG */ 169 170 #ifdef MACHDEP_DEBUG 171 #define DPRINTF(x...) do { printf(x); } while (0) 172 #else 173 #define DPRINTF(x...) 174 #endif /* MACHDEP_DEBUG */ 175 176 void replacesmap(void); 177 int intr_handler(struct intrframe *, struct intrhand *); 178 179 /* the following is used externally (sysctl_hw) */ 180 char machine[] = MACHINE; 181 182 /* 183 * switchto vectors 184 */ 185 void (*cpu_idle_leave_fcn)(void) = NULL; 186 void (*cpu_idle_cycle_fcn)(void) = NULL; 187 void (*cpu_idle_enter_fcn)(void) = NULL; 188 189 190 struct uvm_constraint_range isa_constraint = { 0x0, 0x00ffffffUL }; 191 struct uvm_constraint_range dma_constraint = { 0x0, 0xffffffffUL }; 192 struct uvm_constraint_range *uvm_md_constraints[] = { 193 &isa_constraint, 194 &dma_constraint, 195 NULL 196 }; 197 198 extern int boothowto; 199 int physmem; 200 201 struct dumpmem dumpmem[VM_PHYSSEG_MAX]; 202 u_int ndumpmem; 203 204 /* 205 * These variables are needed by /sbin/savecore 206 */ 207 u_long dumpmag = 0x8fca0101; /* magic number */ 208 int dumpsize = 0; /* pages */ 209 long dumplo = 0; /* blocks */ 210 211 int cpu_class; 212 int i386_fpu_present; 213 int i386_fpu_exception; 214 int i386_fpu_fdivbug; 215 216 int i386_use_fxsave; 217 int i386_has_sse; 218 int i386_has_sse2; 219 int i386_has_xcrypt; 220 221 bootarg_t *bootargp; 222 paddr_t avail_end; 223 224 struct vm_map *exec_map = NULL; 225 struct vm_map *phys_map = NULL; 226 227 #if !defined(SMALL_KERNEL) 228 int p4_model; 229 int p3_early; 230 void (*update_cpuspeed)(void) = NULL; 231 void via_update_sensor(void *args); 232 #endif 233 int kbd_reset; 234 int lid_action = 1; 235 int pwr_action = 1; 236 int forceukbd; 237 238 /* 239 * safepri is a safe priority for sleep to set for a spin-wait 240 * during autoconfiguration or after a panic. 241 */ 242 int safepri = 0; 243 244 #if !defined(SMALL_KERNEL) 245 int bus_clock; 246 #endif 247 void (*setperf_setup)(struct cpu_info *); 248 int setperf_prio = 0; /* for concurrent handlers */ 249 250 void (*cpusensors_setup)(struct cpu_info *); 251 252 void (*delay_func)(int) = i8254_delay; 253 void (*initclock_func)(void) = i8254_initclocks; 254 255 /* 256 * Extent maps to manage I/O and ISA memory hole space. Allocate 257 * storage for 16 regions in each, initially. Later, ioport_malloc_safe 258 * will indicate that it's safe to use malloc() to dynamically allocate 259 * region descriptors. 260 * 261 * N.B. At least two regions are _always_ allocated from the iomem 262 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM). 263 * 264 * The extent maps are not static! Machine-dependent ISA and EISA 265 * routines need access to them for bus address space allocation. 266 */ 267 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 268 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 269 struct extent *ioport_ex; 270 struct extent *iomem_ex; 271 static int ioport_malloc_safe; 272 273 void dumpsys(void); 274 int cpu_dump(void); 275 void init386(paddr_t); 276 void consinit(void); 277 void (*cpuresetfn)(void); 278 279 int bus_mem_add_mapping(bus_addr_t, bus_size_t, 280 int, bus_space_handle_t *); 281 282 #ifdef APERTURE 283 int allowaperture = 0; 284 #endif 285 286 int has_rdrand; 287 int has_rdseed; 288 289 #include "pvbus.h" 290 #if NPVBUS > 0 291 #include <dev/pv/pvvar.h> 292 #endif 293 294 void winchip_cpu_setup(struct cpu_info *); 295 void amd_family5_setperf_setup(struct cpu_info *); 296 void amd_family5_setup(struct cpu_info *); 297 void amd_family6_setperf_setup(struct cpu_info *); 298 void amd_family6_setup(struct cpu_info *); 299 void cyrix3_setperf_setup(struct cpu_info *); 300 void cyrix3_cpu_setup(struct cpu_info *); 301 void cyrix6x86_cpu_setup(struct cpu_info *); 302 void natsem6x86_cpu_setup(struct cpu_info *); 303 void intel586_cpu_setup(struct cpu_info *); 304 void intel686_cpusensors_setup(struct cpu_info *); 305 void intel686_setperf_setup(struct cpu_info *); 306 void intel686_common_cpu_setup(struct cpu_info *); 307 void intel686_cpu_setup(struct cpu_info *); 308 void intel686_p4_cpu_setup(struct cpu_info *); 309 void intelcore_update_sensor(void *); 310 void tm86_cpu_setup(struct cpu_info *); 311 char * intel686_cpu_name(int); 312 char * cyrix3_cpu_name(int, int); 313 char * tm86_cpu_name(int); 314 void cyrix3_get_bus_clock(struct cpu_info *); 315 void p4_get_bus_clock(struct cpu_info *); 316 void p3_get_bus_clock(struct cpu_info *); 317 void p4_update_cpuspeed(void); 318 void p3_update_cpuspeed(void); 319 int pentium_cpuspeed(int *); 320 void enter_shared_special_pages(void); 321 322 static __inline u_char 323 cyrix_read_reg(u_char reg) 324 { 325 outb(0x22, reg); 326 return inb(0x23); 327 } 328 329 static __inline void 330 cyrix_write_reg(u_char reg, u_char data) 331 { 332 outb(0x22, reg); 333 outb(0x23, data); 334 } 335 336 /* 337 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx. 338 * requires caller to provide u_int32_t regs[4] array. 339 */ 340 void 341 cpuid(u_int32_t ax, u_int32_t *regs) 342 { 343 __asm volatile( 344 "cpuid\n\t" 345 "movl %%eax, 0(%2)\n\t" 346 "movl %%ebx, 4(%2)\n\t" 347 "movl %%ecx, 8(%2)\n\t" 348 "movl %%edx, 12(%2)\n\t" 349 :"=a" (ax) 350 :"0" (ax), "S" (regs) 351 :"bx", "cx", "dx"); 352 } 353 354 /* 355 * Machine-dependent startup code 356 */ 357 void 358 cpu_startup(void) 359 { 360 unsigned i; 361 vaddr_t minaddr, maxaddr, va; 362 paddr_t pa; 363 364 /* 365 * Initialize error message buffer (at end of core). 366 * (space reserved in pmap_bootstrap) 367 */ 368 pa = avail_end; 369 va = (vaddr_t)msgbufp; 370 for (i = 0; i < atop(MSGBUFSIZE); i++) { 371 pmap_kenter_pa(va, pa, PROT_READ | PROT_WRITE); 372 va += PAGE_SIZE; 373 pa += PAGE_SIZE; 374 } 375 pmap_update(pmap_kernel()); 376 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); 377 378 printf("%s", version); 379 startclocks(); 380 rtcinit(); 381 382 printf("real mem = %llu (%lluMB)\n", 383 (unsigned long long)ptoa((psize_t)physmem), 384 (unsigned long long)ptoa((psize_t)physmem)/1024U/1024U); 385 386 /* 387 * Allocate a submap for exec arguments. This map effectively 388 * limits the number of processes exec'ing at any time. 389 */ 390 minaddr = vm_map_min(kernel_map); 391 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 392 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 393 394 /* 395 * Allocate a submap for physio 396 */ 397 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 398 VM_PHYS_SIZE, 0, FALSE, NULL); 399 400 printf("avail mem = %llu (%lluMB)\n", 401 (unsigned long long)ptoa((psize_t)uvmexp.free), 402 (unsigned long long)ptoa((psize_t)uvmexp.free)/1024U/1024U); 403 404 /* 405 * Set up buffers, so they can be used to read disk labels. 406 */ 407 bufinit(); 408 409 /* 410 * Configure the system. 411 */ 412 if (boothowto & RB_CONFIG) { 413 #ifdef BOOT_CONFIG 414 user_config(); 415 #else 416 printf("kernel does not support -c; continuing..\n"); 417 #endif 418 } 419 ioport_malloc_safe = 1; 420 421 #ifndef SMALL_KERNEL 422 cpu_ucode_setup(); 423 #endif 424 425 /* enter the IDT and trampoline code in the u-k maps */ 426 enter_shared_special_pages(); 427 428 /* initialize CPU0's TSS and GDT and put them in the u-k maps */ 429 cpu_enter_pages(&cpu_info_full_primary); 430 } 431 432 void 433 enter_shared_special_pages(void) 434 { 435 extern char __kutext_start[], __kutext_end[], __kernel_kutext_phys[]; 436 extern char __kudata_start[], __kudata_end[], __kernel_kudata_phys[]; 437 vaddr_t va; 438 paddr_t pa; 439 440 /* idt */ 441 pmap_extract(pmap_kernel(), (vaddr_t)idt, &pa); 442 pmap_enter_special((vaddr_t)idt, pa, PROT_READ, 0); 443 444 /* .kutext section */ 445 va = (vaddr_t)__kutext_start; 446 pa = (paddr_t)__kernel_kutext_phys; 447 while (va < (vaddr_t)__kutext_end) { 448 pmap_enter_special(va, pa, PROT_READ | PROT_EXEC, 0); 449 DPRINTF("%s: entered kutext page va 0x%08lx pa 0x%08lx\n", 450 __func__, (unsigned long)va, (unsigned long)pa); 451 va += PAGE_SIZE; 452 pa += PAGE_SIZE; 453 } 454 455 /* .kudata section */ 456 va = (vaddr_t)__kudata_start; 457 pa = (paddr_t)__kernel_kudata_phys; 458 while (va < (vaddr_t)__kudata_end) { 459 pmap_enter_special(va, pa, PROT_READ | PROT_WRITE, 0); 460 DPRINTF("%s: entered kudata page va 0x%08lx pa 0x%08lx\n", 461 __func__, (unsigned long)va, (unsigned long)pa); 462 va += PAGE_SIZE; 463 pa += PAGE_SIZE; 464 } 465 } 466 467 /* 468 * Set up proc0's TSS 469 */ 470 void 471 i386_proc0_tss_init(void) 472 { 473 struct pcb *pcb; 474 475 curpcb = pcb = &proc0.p_addr->u_pcb; 476 pcb->pcb_cr0 = rcr0(); 477 pcb->pcb_kstack = (int)proc0.p_addr + USPACE - 16; 478 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_kstack - 1; 479 } 480 481 #ifdef MULTIPROCESSOR 482 void 483 i386_init_pcb_tss(struct cpu_info *ci) 484 { 485 struct pcb *pcb = ci->ci_idle_pcb; 486 487 pcb->pcb_cr0 = rcr0(); 488 } 489 #endif /* MULTIPROCESSOR */ 490 491 /* 492 * Info for CTL_HW 493 */ 494 char cpu_model[120]; 495 496 /* 497 * Note: these are just the ones that may not have a cpuid instruction. 498 * We deal with the rest in a different way. 499 */ 500 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = { 501 { CPUVENDOR_INTEL, "Intel", "386SX", CPUCLASS_386, 502 NULL}, /* CPU_386SX */ 503 { CPUVENDOR_INTEL, "Intel", "386DX", CPUCLASS_386, 504 NULL}, /* CPU_386 */ 505 { CPUVENDOR_INTEL, "Intel", "486SX", CPUCLASS_486, 506 NULL}, /* CPU_486SX */ 507 { CPUVENDOR_INTEL, "Intel", "486DX", CPUCLASS_486, 508 NULL}, /* CPU_486 */ 509 { CPUVENDOR_CYRIX, "Cyrix", "486DLC", CPUCLASS_486, 510 NULL}, /* CPU_486DLC */ 511 { CPUVENDOR_CYRIX, "Cyrix", "6x86", CPUCLASS_486, 512 cyrix6x86_cpu_setup}, /* CPU_6x86 */ 513 { CPUVENDOR_NEXGEN,"NexGen","586", CPUCLASS_386, 514 NULL}, /* CPU_NX586 */ 515 }; 516 517 const char *classnames[] = { 518 "386", 519 "486", 520 "586", 521 "686" 522 }; 523 524 const char *modifiers[] = { 525 "", 526 "OverDrive ", 527 "Dual ", 528 "" 529 }; 530 531 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 532 { 533 "GenuineIntel", 534 CPUVENDOR_INTEL, 535 "Intel", 536 /* Family 4 */ 537 { { 538 CPUCLASS_486, 539 { 540 "486DX", "486DX", "486SX", "486DX2", "486SL", 541 "486SX2", 0, "486DX2 W/B", 542 "486DX4", 0, 0, 0, 0, 0, 0, 0, 543 "486" /* Default */ 544 }, 545 NULL 546 }, 547 /* Family 5 */ 548 { 549 CPUCLASS_586, 550 { 551 "Pentium (A-step)", "Pentium (P5)", 552 "Pentium (P54C)", "Pentium (P24T)", 553 "Pentium/MMX", "Pentium", 0, 554 "Pentium (P54C)", "Pentium/MMX", 555 0, 0, 0, 0, 0, 0, 0, 556 "Pentium" /* Default */ 557 }, 558 intel586_cpu_setup 559 }, 560 /* Family 6 */ 561 { 562 CPUCLASS_686, 563 { 564 "Pentium Pro", "Pentium Pro", 0, 565 "Pentium II", "Pentium Pro", 566 "Pentium II/Celeron", 567 "Celeron", 568 "Pentium III", 569 "Pentium III", 570 "Pentium M", 571 "Pentium III Xeon", 572 "Pentium III", 0, 573 "Pentium M", 574 "Core Duo/Solo", 0, 575 "Pentium Pro, II or III" /* Default */ 576 }, 577 intel686_cpu_setup 578 }, 579 /* Family 7 */ 580 { 581 CPUCLASS_686, 582 } , 583 /* Family 8 */ 584 { 585 CPUCLASS_686, 586 } , 587 /* Family 9 */ 588 { 589 CPUCLASS_686, 590 } , 591 /* Family A */ 592 { 593 CPUCLASS_686, 594 } , 595 /* Family B */ 596 { 597 CPUCLASS_686, 598 } , 599 /* Family C */ 600 { 601 CPUCLASS_686, 602 } , 603 /* Family D */ 604 { 605 CPUCLASS_686, 606 } , 607 /* Family E */ 608 { 609 CPUCLASS_686, 610 } , 611 /* Family F */ 612 { 613 CPUCLASS_686, 614 { 615 "Pentium 4", 0, 0, 0, 616 0, 0, 0, 0, 617 0, 0, 0, 0, 618 0, 0, 0, 0, 619 "Pentium 4" /* Default */ 620 }, 621 intel686_p4_cpu_setup 622 } } 623 }, 624 { 625 "AuthenticAMD", 626 CPUVENDOR_AMD, 627 "AMD", 628 /* Family 4 */ 629 { { 630 CPUCLASS_486, 631 { 632 0, 0, 0, "Am486DX2 W/T", 633 0, 0, 0, "Am486DX2 W/B", 634 "Am486DX4 W/T or Am5x86 W/T 150", 635 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 636 0, 0, "Am5x86 W/T 133/160", 637 "Am5x86 W/B 133/160", 638 "Am486 or Am5x86" /* Default */ 639 }, 640 NULL 641 }, 642 /* Family 5 */ 643 { 644 CPUCLASS_586, 645 { 646 "K5", "K5", "K5", "K5", 0, 0, "K6", 647 "K6", "K6-2", "K6-III", 0, 0, 0, 648 "K6-2+/III+", 0, 0, 649 "K5 or K6" /* Default */ 650 }, 651 amd_family5_setup 652 }, 653 /* Family 6 */ 654 { 655 CPUCLASS_686, 656 { 657 0, "Athlon Model 1", "Athlon Model 2", 658 "Duron Model 3", 659 "Athlon Model 4", 660 0, "Athlon XP Model 6", 661 "Duron Model 7", 662 "Athlon XP Model 8", 663 0, "Athlon XP Model 10", 664 0, 0, 0, 0, 0, 665 "K7" /* Default */ 666 }, 667 amd_family6_setup 668 }, 669 /* Family 7 */ 670 { 671 CPUCLASS_686, 672 } , 673 /* Family 8 */ 674 { 675 CPUCLASS_686, 676 } , 677 /* Family 9 */ 678 { 679 CPUCLASS_686, 680 } , 681 /* Family A */ 682 { 683 CPUCLASS_686, 684 } , 685 /* Family B */ 686 { 687 CPUCLASS_686, 688 } , 689 /* Family C */ 690 { 691 CPUCLASS_686, 692 } , 693 /* Family D */ 694 { 695 CPUCLASS_686, 696 } , 697 /* Family E */ 698 { 699 CPUCLASS_686, 700 } , 701 /* Family F */ 702 { 703 CPUCLASS_686, 704 { 705 0, 0, 0, 0, "Athlon64", 706 "Opteron or Athlon64FX", 0, 0, 707 0, 0, 0, 0, 0, 0, 0, 0, 708 "AMD64" /* DEFAULT */ 709 }, 710 amd_family6_setup 711 } } 712 }, 713 { 714 "CyrixInstead", 715 CPUVENDOR_CYRIX, 716 "Cyrix", 717 /* Family 4 */ 718 { { 719 CPUCLASS_486, 720 { 721 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0, 722 0, 0, 0, 0, 723 "486 class" /* Default */ 724 }, 725 NULL 726 }, 727 /* Family 5 */ 728 { 729 CPUCLASS_586, 730 { 731 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0, 732 0, 0, 0, 0, 0, 0, 733 "586 class" /* Default */ 734 }, 735 cyrix6x86_cpu_setup 736 }, 737 /* Family 6 */ 738 { 739 CPUCLASS_686, 740 { 741 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 742 0, 0, 0, 0, 743 "686 class" /* Default */ 744 }, 745 NULL 746 } } 747 }, 748 { 749 "CentaurHauls", 750 CPUVENDOR_IDT, 751 "IDT", 752 /* Family 4, not available from IDT */ 753 { { 754 CPUCLASS_486, 755 { 756 0, 0, 0, 0, 0, 0, 0, 0, 757 0, 0, 0, 0, 0, 0, 0, 0, 758 "486 class" /* Default */ 759 }, 760 NULL 761 }, 762 /* Family 5 */ 763 { 764 CPUCLASS_586, 765 { 766 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 767 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 768 "WinChip" /* Default */ 769 }, 770 winchip_cpu_setup 771 }, 772 /* Family 6 */ 773 { 774 CPUCLASS_686, 775 { 776 0, 0, 0, 0, 0, 0, 777 "C3 Samuel", 778 "C3 Samuel 2/Ezra", 779 "C3 Ezra-T", 780 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0, 781 "C3" /* Default */ 782 }, 783 cyrix3_cpu_setup 784 } } 785 }, 786 { 787 "RiseRiseRise", 788 CPUVENDOR_RISE, 789 "Rise", 790 /* Family 4, not available from Rise */ 791 { { 792 CPUCLASS_486, 793 { 794 0, 0, 0, 0, 0, 0, 0, 0, 795 0, 0, 0, 0, 0, 0, 0, 0, 796 "486 class" /* Default */ 797 }, 798 NULL 799 }, 800 /* Family 5 */ 801 { 802 CPUCLASS_586, 803 { 804 "mP6", 0, "mP6", 0, 0, 0, 0, 0, 805 0, 0, 0, 0, 0, 0, 0, 0, 806 "mP6" /* Default */ 807 }, 808 NULL 809 }, 810 /* Family 6, not yet available from Rise */ 811 { 812 CPUCLASS_686, 813 { 814 0, 0, 0, 0, 0, 0, 0, 0, 815 0, 0, 0, 0, 0, 0, 0, 0, 816 "686 class" /* Default */ 817 }, 818 NULL 819 } } 820 }, 821 { 822 "GenuineTMx86", 823 CPUVENDOR_TRANSMETA, 824 "Transmeta", 825 /* Family 4, not available from Transmeta */ 826 { { 827 CPUCLASS_486, 828 { 829 0, 0, 0, 0, 0, 0, 0, 0, 830 0, 0, 0, 0, 0, 0, 0, 0, 831 "486 class" /* Default */ 832 }, 833 NULL 834 }, 835 /* Family 5 */ 836 { 837 CPUCLASS_586, 838 { 839 0, 0, 0, 0, "TMS5x00", 0, 0, 840 0, 0, 0, 0, 0, 0, 0, 0, 0, 841 "TMS5x00" /* Default */ 842 }, 843 tm86_cpu_setup 844 }, 845 /* Family 6, not yet available from Transmeta */ 846 { 847 CPUCLASS_686, 848 { 849 0, 0, 0, 0, 0, 0, 0, 0, 850 0, 0, 0, 0, 0, 0, 0, 0, 851 "686 class" /* Default */ 852 }, 853 NULL 854 }, 855 /* Family 7 */ 856 { 857 CPUCLASS_686, 858 } , 859 /* Family 8 */ 860 { 861 CPUCLASS_686, 862 } , 863 /* Family 9 */ 864 { 865 CPUCLASS_686, 866 } , 867 /* Family A */ 868 { 869 CPUCLASS_686, 870 } , 871 /* Family B */ 872 { 873 CPUCLASS_686, 874 } , 875 /* Family C */ 876 { 877 CPUCLASS_686, 878 } , 879 /* Family D */ 880 { 881 CPUCLASS_686, 882 } , 883 /* Family E */ 884 { 885 CPUCLASS_686, 886 } , 887 /* Family F */ 888 { 889 /* Extended processor family - Transmeta Efficeon */ 890 CPUCLASS_686, 891 { 892 0, 0, "TM8000", "TM8000", 893 0, 0, 0, 0, 894 0, 0, 0, 0, 895 0, 0, 0, 0, 896 "TM8000" /* Default */ 897 }, 898 tm86_cpu_setup 899 } } 900 }, 901 { 902 "Geode by NSC", 903 CPUVENDOR_NS, 904 "National Semiconductor", 905 /* Family 4, not available from National Semiconductor */ 906 { { 907 CPUCLASS_486, 908 { 909 0, 0, 0, 0, 0, 0, 0, 0, 910 0, 0, 0, 0, 0, 0, 0, 0, 911 "486 class" /* Default */ 912 }, 913 NULL 914 }, 915 /* Family 5 */ 916 { 917 CPUCLASS_586, 918 { 919 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0, 920 0, 0, 0, 0, 0, 0, 921 "586 class" /* Default */ 922 }, 923 natsem6x86_cpu_setup 924 } } 925 }, 926 { 927 "SiS SiS SiS ", 928 CPUVENDOR_SIS, 929 "SiS", 930 /* Family 4, not available from SiS */ 931 { { 932 CPUCLASS_486, 933 { 934 0, 0, 0, 0, 0, 0, 0, 0, 935 0, 0, 0, 0, 0, 0, 0, 0, 936 "486 class" /* Default */ 937 }, 938 NULL 939 }, 940 /* Family 5 */ 941 { 942 CPUCLASS_586, 943 { 944 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0, 945 0, 0, 0, 0, 0, 0, 946 "586 class" /* Default */ 947 }, 948 NULL 949 } } 950 } 951 }; 952 953 const struct cpu_cpuid_feature i386_cpuid_features[] = { 954 { CPUID_FPU, "FPU" }, 955 { CPUID_VME, "V86" }, 956 { CPUID_DE, "DE" }, 957 { CPUID_PSE, "PSE" }, 958 { CPUID_TSC, "TSC" }, 959 { CPUID_MSR, "MSR" }, 960 { CPUID_PAE, "PAE" }, 961 { CPUID_MCE, "MCE" }, 962 { CPUID_CX8, "CX8" }, 963 { CPUID_APIC, "APIC" }, 964 { CPUID_SYS1, "SYS" }, 965 { CPUID_SEP, "SEP" }, 966 { CPUID_MTRR, "MTRR" }, 967 { CPUID_PGE, "PGE" }, 968 { CPUID_MCA, "MCA" }, 969 { CPUID_CMOV, "CMOV" }, 970 { CPUID_PAT, "PAT" }, 971 { CPUID_PSE36, "PSE36" }, 972 { CPUID_PSN, "PSN" }, 973 { CPUID_CFLUSH, "CFLUSH" }, 974 { CPUID_DS, "DS" }, 975 { CPUID_ACPI, "ACPI" }, 976 { CPUID_MMX, "MMX" }, 977 { CPUID_FXSR, "FXSR" }, 978 { CPUID_SSE, "SSE" }, 979 { CPUID_SSE2, "SSE2" }, 980 { CPUID_SS, "SS" }, 981 { CPUID_HTT, "HTT" }, 982 { CPUID_TM, "TM" }, 983 { CPUID_PBE, "PBE" } 984 }; 985 986 const struct cpu_cpuid_feature i386_ecpuid_features[] = { 987 { CPUID_MPC, "MPC" }, 988 { CPUID_NXE, "NXE" }, 989 { CPUID_MMXX, "MMXX" }, 990 { CPUID_FFXSR, "FFXSR" }, 991 { CPUID_PAGE1GB, "PAGE1GB" }, 992 { CPUID_RDTSCP, "RDTSCP" }, 993 { CPUID_LONG, "LONG" }, 994 { CPUID_3DNOW2, "3DNOW2" }, 995 { CPUID_3DNOW, "3DNOW" } 996 }; 997 998 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = { 999 { CPUIDECX_SSE3, "SSE3" }, 1000 { CPUIDECX_PCLMUL, "PCLMUL" }, 1001 { CPUIDECX_DTES64, "DTES64" }, 1002 { CPUIDECX_MWAIT, "MWAIT" }, 1003 { CPUIDECX_DSCPL, "DS-CPL" }, 1004 { CPUIDECX_VMX, "VMX" }, 1005 { CPUIDECX_SMX, "SMX" }, 1006 { CPUIDECX_EST, "EST" }, 1007 { CPUIDECX_TM2, "TM2" }, 1008 { CPUIDECX_SSSE3, "SSSE3" }, 1009 { CPUIDECX_CNXTID, "CNXT-ID" }, 1010 { CPUIDECX_SDBG, "SDBG" }, 1011 { CPUIDECX_FMA3, "FMA3" }, 1012 { CPUIDECX_CX16, "CX16" }, 1013 { CPUIDECX_XTPR, "xTPR" }, 1014 { CPUIDECX_PDCM, "PDCM" }, 1015 { CPUIDECX_PCID, "PCID" }, 1016 { CPUIDECX_DCA, "DCA" }, 1017 { CPUIDECX_SSE41, "SSE4.1" }, 1018 { CPUIDECX_SSE42, "SSE4.2" }, 1019 { CPUIDECX_X2APIC, "x2APIC" }, 1020 { CPUIDECX_MOVBE, "MOVBE" }, 1021 { CPUIDECX_POPCNT, "POPCNT" }, 1022 { CPUIDECX_DEADLINE, "DEADLINE" }, 1023 { CPUIDECX_AES, "AES" }, 1024 { CPUIDECX_XSAVE, "XSAVE" }, 1025 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 1026 { CPUIDECX_AVX, "AVX" }, 1027 { CPUIDECX_F16C, "F16C" }, 1028 { CPUIDECX_RDRAND, "RDRAND" }, 1029 { CPUIDECX_HV, "HV" }, 1030 }; 1031 1032 const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = { 1033 { CPUIDECX_LAHF, "LAHF" }, 1034 { CPUIDECX_CMPLEG, "CMPLEG" }, 1035 { CPUIDECX_SVM, "SVM" }, 1036 { CPUIDECX_EAPICSP, "EAPICSP" }, 1037 { CPUIDECX_AMCR8, "AMCR8" }, 1038 { CPUIDECX_ABM, "ABM" }, 1039 { CPUIDECX_SSE4A, "SSE4A" }, 1040 { CPUIDECX_MASSE, "MASSE" }, 1041 { CPUIDECX_3DNOWP, "3DNOWP" }, 1042 { CPUIDECX_OSVW, "OSVW" }, 1043 { CPUIDECX_IBS, "IBS" }, 1044 { CPUIDECX_XOP, "XOP" }, 1045 { CPUIDECX_SKINIT, "SKINIT" }, 1046 { CPUIDECX_WDT, "WDT" }, 1047 { CPUIDECX_LWP, "LWP" }, 1048 { CPUIDECX_FMA4, "FMA4" }, 1049 { CPUIDECX_TCE, "TCE" }, 1050 { CPUIDECX_NODEID, "NODEID" }, 1051 { CPUIDECX_TBM, "TBM" }, 1052 { CPUIDECX_TOPEXT, "TOPEXT" }, 1053 { CPUIDECX_CPCTR, "CPCTR" }, 1054 { CPUIDECX_DBKP, "DBKP" }, 1055 { CPUIDECX_PERFTSC, "PERFTSC" }, 1056 { CPUIDECX_PCTRL3, "PCTRL3" }, 1057 { CPUIDECX_MWAITX, "MWAITX" }, 1058 }; 1059 1060 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { 1061 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 1062 { SEFF0EBX_TSC_ADJUST, "TSC_ADJUST" }, 1063 { SEFF0EBX_SGX, "SGX" }, 1064 { SEFF0EBX_BMI1, "BMI1" }, 1065 { SEFF0EBX_HLE, "HLE" }, 1066 { SEFF0EBX_AVX2, "AVX2" }, 1067 { SEFF0EBX_SMEP, "SMEP" }, 1068 { SEFF0EBX_BMI2, "BMI2" }, 1069 { SEFF0EBX_ERMS, "ERMS" }, 1070 { SEFF0EBX_INVPCID, "INVPCID" }, 1071 { SEFF0EBX_RTM, "RTM" }, 1072 { SEFF0EBX_PQM, "PQM" }, 1073 { SEFF0EBX_MPX, "MPX" }, 1074 { SEFF0EBX_AVX512F, "AVX512F" }, 1075 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 1076 { SEFF0EBX_RDSEED, "RDSEED" }, 1077 { SEFF0EBX_ADX, "ADX" }, 1078 { SEFF0EBX_SMAP, "SMAP" }, 1079 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 1080 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 1081 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 1082 { SEFF0EBX_CLWB, "CLWB" }, 1083 { SEFF0EBX_PT, "PT" }, 1084 { SEFF0EBX_AVX512PF, "AVX512PF" }, 1085 { SEFF0EBX_AVX512ER, "AVX512ER" }, 1086 { SEFF0EBX_AVX512CD, "AVX512CD" }, 1087 { SEFF0EBX_SHA, "SHA" }, 1088 { SEFF0EBX_AVX512BW, "AVX512BW" }, 1089 { SEFF0EBX_AVX512VL, "AVX512VL" }, 1090 }; 1091 1092 const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = { 1093 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 1094 { SEFF0ECX_UMIP, "UMIP" }, 1095 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 1096 { SEFF0ECX_PKU, "PKU" }, 1097 }; 1098 1099 const struct cpu_cpuid_feature cpu_seff0_edxfeatures[] = { 1100 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 1101 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 1102 { SEFF0EDX_SRBDS_CTRL, "SRBDS_CTRL" }, 1103 { SEFF0EDX_MD_CLEAR, "MD_CLEAR" }, 1104 { SEFF0EDX_TSXFA, "TSXFA" }, 1105 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 1106 { SEFF0EDX_STIBP, "STIBP" }, 1107 { SEFF0EDX_L1DF, "L1DF" }, 1108 /* SEFF0EDX_ARCH_CAP (not printed) */ 1109 { SEFF0EDX_SSBD, "SSBD" }, 1110 }; 1111 1112 const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = { 1113 { TPM_SENSOR, "SENSOR" }, 1114 { TPM_ARAT, "ARAT" }, 1115 }; 1116 1117 const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = { 1118 { CPUIDEAX_VERID, "PERF" }, 1119 }; 1120 1121 const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = { 1122 { CPUIDEDX_ITSC, "ITSC" }, 1123 }; 1124 1125 const struct cpu_cpuid_feature cpu_xsave_extfeatures[] = { 1126 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 1127 { XSAVE_XSAVEC, "XSAVEC" }, 1128 { XSAVE_XGETBV1, "XGETBV1" }, 1129 { XSAVE_XSAVES, "XSAVES" }, 1130 }; 1131 1132 void 1133 winchip_cpu_setup(struct cpu_info *ci) 1134 { 1135 1136 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1137 case 4: /* WinChip C6 */ 1138 ci->ci_feature_flags &= ~CPUID_TSC; 1139 /* Disable RDTSC instruction from user-level. */ 1140 lcr4(rcr4() | CR4_TSD); 1141 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1142 break; 1143 } 1144 } 1145 1146 #if !defined(SMALL_KERNEL) 1147 void 1148 cyrix3_setperf_setup(struct cpu_info *ci) 1149 { 1150 if (cpu_ecxfeature & CPUIDECX_EST) { 1151 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1152 est_init(ci, CPUVENDOR_VIA); 1153 else 1154 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1155 ci->ci_dev->dv_xname); 1156 } 1157 } 1158 #endif 1159 1160 void 1161 cyrix3_cpu_setup(struct cpu_info *ci) 1162 { 1163 int model = (ci->ci_signature >> 4) & 15; 1164 int step = ci->ci_signature & 15; 1165 1166 u_int64_t msreg; 1167 u_int32_t regs[4]; 1168 unsigned int val; 1169 #if !defined(SMALL_KERNEL) 1170 extern void (*pagezero)(void *, size_t); 1171 extern void i686_pagezero(void *, size_t); 1172 1173 pagezero = i686_pagezero; 1174 1175 setperf_setup = cyrix3_setperf_setup; 1176 #endif 1177 1178 switch (model) { 1179 /* Possible earlier models */ 1180 case 0: case 1: case 2: 1181 case 3: case 4: case 5: 1182 break; 1183 1184 case 6: /* C3 Samuel 1 */ 1185 case 7: /* C3 Samuel 2 or C3 Ezra */ 1186 case 8: /* C3 Ezra-T */ 1187 cpuid(0x80000001, regs); 1188 val = regs[3]; 1189 if (val & (1U << 31)) { 1190 cpu_feature |= CPUID_3DNOW; 1191 } else { 1192 cpu_feature &= ~CPUID_3DNOW; 1193 } 1194 break; 1195 1196 case 9: 1197 if (step < 3) 1198 break; 1199 /* 1200 * C3 Nehemiah & later: fall through. 1201 */ 1202 1203 case 10: /* C7-M Type A */ 1204 case 13: /* C7-M Type D */ 1205 case 15: /* Nano */ 1206 #if !defined(SMALL_KERNEL) 1207 if (CPU_IS_PRIMARY(ci) && 1208 (model == 10 || model == 13 || model == 15)) { 1209 /* Setup the sensors structures */ 1210 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1211 sizeof(ci->ci_sensordev.xname)); 1212 ci->ci_sensor.type = SENSOR_TEMP; 1213 sensor_task_register(ci, via_update_sensor, 5); 1214 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1215 sensordev_install(&ci->ci_sensordev); 1216 } 1217 #endif 1218 1219 default: 1220 /* 1221 * C3 Nehemiah/Esther & later models: 1222 * First we check for extended feature flags, and then 1223 * (if present) retrieve the ones at 0xC0000001. In this 1224 * bit 2 tells us if the RNG is present. Bit 3 tells us 1225 * if the RNG has been enabled. In order to use the RNG 1226 * we need 3 things: We need an RNG, we need the FXSR bit 1227 * enabled in cr4 (SSE/SSE2 stuff), and we need to have 1228 * Bit 6 of MSR 0x110B set to 1 (the default), which will 1229 * show up as bit 3 set here. 1230 */ 1231 cpuid(0xC0000000, regs); /* Check for RNG */ 1232 val = regs[0]; 1233 if (val >= 0xC0000001) { 1234 cpuid(0xC0000001, regs); 1235 val = regs[3]; 1236 } else 1237 val = 0; 1238 1239 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 1240 printf("%s:", ci->ci_dev->dv_xname); 1241 1242 /* Enable RNG if present and disabled */ 1243 if (val & C3_CPUID_HAS_RNG) { 1244 extern int viac3_rnd_present; 1245 1246 if (!(val & C3_CPUID_DO_RNG)) { 1247 msreg = rdmsr(0x110B); 1248 msreg |= 0x40; 1249 wrmsr(0x110B, msreg); 1250 } 1251 viac3_rnd_present = 1; 1252 printf(" RNG"); 1253 } 1254 1255 /* Enable AES engine if present and disabled */ 1256 if (val & C3_CPUID_HAS_ACE) { 1257 #ifdef CRYPTO 1258 if (!(val & C3_CPUID_DO_ACE)) { 1259 msreg = rdmsr(0x1107); 1260 msreg |= (0x01 << 28); 1261 wrmsr(0x1107, msreg); 1262 } 1263 i386_has_xcrypt |= C3_HAS_AES; 1264 #endif /* CRYPTO */ 1265 printf(" AES"); 1266 } 1267 1268 /* Enable ACE2 engine if present and disabled */ 1269 if (val & C3_CPUID_HAS_ACE2) { 1270 #ifdef CRYPTO 1271 if (!(val & C3_CPUID_DO_ACE2)) { 1272 msreg = rdmsr(0x1107); 1273 msreg |= (0x01 << 28); 1274 wrmsr(0x1107, msreg); 1275 } 1276 i386_has_xcrypt |= C3_HAS_AESCTR; 1277 #endif /* CRYPTO */ 1278 printf(" AES-CTR"); 1279 } 1280 1281 /* Enable SHA engine if present and disabled */ 1282 if (val & C3_CPUID_HAS_PHE) { 1283 #ifdef CRYPTO 1284 if (!(val & C3_CPUID_DO_PHE)) { 1285 msreg = rdmsr(0x1107); 1286 msreg |= (0x01 << 28/**/); 1287 wrmsr(0x1107, msreg); 1288 } 1289 i386_has_xcrypt |= C3_HAS_SHA; 1290 #endif /* CRYPTO */ 1291 printf(" SHA1 SHA256"); 1292 } 1293 1294 /* Enable MM engine if present and disabled */ 1295 if (val & C3_CPUID_HAS_PMM) { 1296 #ifdef CRYPTO 1297 if (!(val & C3_CPUID_DO_PMM)) { 1298 msreg = rdmsr(0x1107); 1299 msreg |= (0x01 << 28/**/); 1300 wrmsr(0x1107, msreg); 1301 } 1302 i386_has_xcrypt |= C3_HAS_MM; 1303 #endif /* CRYPTO */ 1304 printf(" RSA"); 1305 } 1306 1307 printf("\n"); 1308 break; 1309 } 1310 } 1311 1312 #if !defined(SMALL_KERNEL) 1313 void 1314 via_update_sensor(void *args) 1315 { 1316 struct cpu_info *ci = (struct cpu_info *) args; 1317 u_int64_t msr; 1318 1319 switch (ci->ci_model) { 1320 case 0xa: 1321 case 0xd: 1322 msr = rdmsr(MSR_C7M_TMTEMPERATURE); 1323 break; 1324 case 0xf: 1325 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 1326 break; 1327 } 1328 ci->ci_sensor.value = (msr & 0xffffff); 1329 /* micro degrees */ 1330 ci->ci_sensor.value *= 1000000; 1331 ci->ci_sensor.value += 273150000; 1332 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1333 } 1334 #endif 1335 1336 void 1337 cyrix6x86_cpu_setup(struct cpu_info *ci) 1338 { 1339 extern int clock_broken_latch; 1340 1341 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1342 case -1: /* M1 w/o cpuid */ 1343 case 2: /* M1 */ 1344 /* set up various cyrix registers */ 1345 /* Enable suspend on halt */ 1346 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 1347 /* enable access to ccr4/ccr5 */ 1348 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10); 1349 /* cyrix's workaround for the "coma bug" */ 1350 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 1351 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 1352 cyrix_read_reg(0x33); cyrix_write_reg(0x33, 0); 1353 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 1354 /* disable access to ccr4/ccr5 */ 1355 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10); 1356 1357 printf("%s: xchg bug workaround performed\n", 1358 ci->ci_dev->dv_xname); 1359 break; /* fallthrough? */ 1360 case 4: /* GXm */ 1361 /* Unset the TSC bit until calibrate_delay() gets fixed. */ 1362 clock_broken_latch = 1; 1363 curcpu()->ci_feature_flags &= ~CPUID_TSC; 1364 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1365 break; 1366 } 1367 } 1368 1369 void 1370 natsem6x86_cpu_setup(struct cpu_info *ci) 1371 { 1372 extern int clock_broken_latch; 1373 int model = (ci->ci_signature >> 4) & 15; 1374 1375 clock_broken_latch = 1; 1376 switch (model) { 1377 case 4: 1378 cpu_feature &= ~CPUID_TSC; 1379 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1380 break; 1381 } 1382 } 1383 1384 void 1385 intel586_cpu_setup(struct cpu_info *ci) 1386 { 1387 if (!cpu_f00f_bug) { 1388 fix_f00f(); 1389 printf("%s: F00F bug workaround installed\n", 1390 ci->ci_dev->dv_xname); 1391 } 1392 } 1393 1394 #if !defined(SMALL_KERNEL) 1395 void 1396 amd_family5_setperf_setup(struct cpu_info *ci) 1397 { 1398 k6_powernow_init(); 1399 } 1400 #endif 1401 1402 void 1403 amd_family5_setup(struct cpu_info *ci) 1404 { 1405 int model = (ci->ci_signature >> 4) & 15; 1406 1407 switch (model) { 1408 case 0: /* AMD-K5 Model 0 */ 1409 /* 1410 * According to the AMD Processor Recognition App Note, 1411 * the AMD-K5 Model 0 uses the wrong bit to indicate 1412 * support for global PTEs, instead using bit 9 (APIC) 1413 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1414 */ 1415 if (cpu_feature & CPUID_APIC) 1416 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE; 1417 /* 1418 * XXX But pmap_pg_g is already initialized -- need to kick 1419 * XXX the pmap somehow. How does the MP branch do this? 1420 */ 1421 break; 1422 case 12: 1423 case 13: 1424 #if !defined(SMALL_KERNEL) 1425 setperf_setup = amd_family5_setperf_setup; 1426 #endif 1427 break; 1428 } 1429 } 1430 1431 #if !defined(SMALL_KERNEL) 1432 void 1433 amd_family6_setperf_setup(struct cpu_info *ci) 1434 { 1435 int family = (ci->ci_signature >> 8) & 15; 1436 1437 switch (family) { 1438 case 6: 1439 k7_powernow_init(); 1440 break; 1441 case 15: 1442 k8_powernow_init(); 1443 break; 1444 } 1445 if (ci->ci_family >= 0x10) 1446 k1x_init(ci); 1447 } 1448 #endif 1449 1450 void 1451 amd_family6_setup(struct cpu_info *ci) 1452 { 1453 #if !defined(SMALL_KERNEL) 1454 int family = (ci->ci_signature >> 8) & 15; 1455 extern void (*pagezero)(void *, size_t); 1456 extern void sse2_pagezero(void *, size_t); 1457 extern void i686_pagezero(void *, size_t); 1458 1459 if (cpu_feature & CPUID_SSE2) 1460 pagezero = sse2_pagezero; 1461 else 1462 pagezero = i686_pagezero; 1463 1464 setperf_setup = amd_family6_setperf_setup; 1465 1466 if (family == 0xf) { 1467 amd64_errata(ci); 1468 } 1469 #endif 1470 } 1471 1472 #if !defined(SMALL_KERNEL) 1473 /* 1474 * Temperature read on the CPU is relative to the maximum 1475 * temperature supported by the CPU, Tj(Max). 1476 * Refer to: 1477 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 1478 * Section 35 and 1479 * http://www.intel.com/content/dam/www/public/us/en/documents/ 1480 * white-papers/cpu-monitoring-dts-peci-paper.pdf 1481 * 1482 * The temperature on Intel CPUs can be between 70 and 105 degC, since 1483 * Westmere we can read the TJmax from the die. For older CPUs we have 1484 * to guess or use undocumented MSRs. Then we subtract the temperature 1485 * portion of thermal status from max to get current temperature. 1486 */ 1487 void 1488 intelcore_update_sensor(void *args) 1489 { 1490 struct cpu_info *ci = (struct cpu_info *) args; 1491 u_int64_t msr; 1492 int max = 100; 1493 1494 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 1495 if (ci->ci_model == 0x0e && 1496 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 1497 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 1498 max = 85; 1499 1500 /* 1501 * Newer CPUs can tell you what their max temperature is. 1502 * See: '64-ia-32-architectures-software-developer- 1503 * vol-3c-part-3-manual.pdf' 1504 */ 1505 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 1506 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 1507 ci->ci_model != 0x35 && ci->ci_model != 0x36) 1508 max = MSR_TEMPERATURE_TARGET_TJMAX( 1509 rdmsr(MSR_TEMPERATURE_TARGET)); 1510 1511 msr = rdmsr(MSR_THERM_STATUS); 1512 if (msr & MSR_THERM_STATUS_VALID_BIT) { 1513 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 1514 /* micro degrees */ 1515 ci->ci_sensor.value *= 1000000; 1516 /* kelvin */ 1517 ci->ci_sensor.value += 273150000; 1518 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1519 } else { 1520 ci->ci_sensor.value = 0; 1521 ci->ci_sensor.flags |= SENSOR_FINVALID; 1522 } 1523 } 1524 1525 void 1526 intel686_cpusensors_setup(struct cpu_info *ci) 1527 { 1528 if (!CPU_IS_PRIMARY(ci) || (ci->ci_feature_tpmflags & TPM_SENSOR) == 0) 1529 return; 1530 1531 /* Setup the sensors structures */ 1532 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1533 sizeof(ci->ci_sensordev.xname)); 1534 ci->ci_sensor.type = SENSOR_TEMP; 1535 sensor_task_register(ci, intelcore_update_sensor, 5); 1536 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1537 sensordev_install(&ci->ci_sensordev); 1538 } 1539 #endif 1540 1541 #if !defined(SMALL_KERNEL) 1542 void 1543 intel686_setperf_setup(struct cpu_info *ci) 1544 { 1545 int family = (ci->ci_signature >> 8) & 15; 1546 int step = ci->ci_signature & 15; 1547 1548 if (cpu_ecxfeature & CPUIDECX_EST) { 1549 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1550 est_init(ci, CPUVENDOR_INTEL); 1551 else 1552 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1553 ci->ci_dev->dv_xname); 1554 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) == 1555 (CPUID_ACPI | CPUID_TM)) 1556 p4tcc_init(family, step); 1557 } 1558 #endif 1559 1560 void 1561 intel686_common_cpu_setup(struct cpu_info *ci) 1562 { 1563 1564 #if !defined(SMALL_KERNEL) 1565 setperf_setup = intel686_setperf_setup; 1566 cpusensors_setup = intel686_cpusensors_setup; 1567 { 1568 extern void (*pagezero)(void *, size_t); 1569 extern void sse2_pagezero(void *, size_t); 1570 extern void i686_pagezero(void *, size_t); 1571 1572 if (cpu_feature & CPUID_SSE2) 1573 pagezero = sse2_pagezero; 1574 else 1575 pagezero = i686_pagezero; 1576 } 1577 #endif 1578 /* 1579 * Make sure SYSENTER is disabled. 1580 */ 1581 if (cpu_feature & CPUID_SEP) 1582 wrmsr(MSR_SYSENTER_CS, 0); 1583 } 1584 1585 void 1586 intel686_cpu_setup(struct cpu_info *ci) 1587 { 1588 int model = (ci->ci_signature >> 4) & 15; 1589 int step = ci->ci_signature & 15; 1590 u_quad_t msr119; 1591 1592 intel686_common_cpu_setup(ci); 1593 1594 /* 1595 * Original PPro returns SYSCALL in CPUID but is non-functional. 1596 * From Intel Application Note #485. 1597 */ 1598 if ((model == 1) && (step < 3)) 1599 ci->ci_feature_flags &= ~CPUID_SEP; 1600 1601 /* 1602 * Disable the Pentium3 serial number. 1603 */ 1604 if ((model == 7) && (ci->ci_feature_flags & CPUID_PSN)) { 1605 msr119 = rdmsr(MSR_BBL_CR_CTL); 1606 msr119 |= 0x0000000000200000LL; 1607 wrmsr(MSR_BBL_CR_CTL, msr119); 1608 1609 printf("%s: disabling processor serial number\n", 1610 ci->ci_dev->dv_xname); 1611 ci->ci_feature_flags &= ~CPUID_PSN; 1612 ci->ci_level = 2; 1613 } 1614 1615 #if !defined(SMALL_KERNEL) 1616 p3_early = (model == 8 && step == 1) ? 1 : 0; 1617 update_cpuspeed = p3_update_cpuspeed; 1618 #endif 1619 } 1620 1621 void 1622 intel686_p4_cpu_setup(struct cpu_info *ci) 1623 { 1624 intel686_common_cpu_setup(ci); 1625 1626 #if !defined(SMALL_KERNEL) 1627 p4_model = (ci->ci_signature >> 4) & 15; 1628 update_cpuspeed = p4_update_cpuspeed; 1629 #endif 1630 } 1631 1632 void 1633 tm86_cpu_setup(struct cpu_info *ci) 1634 { 1635 #if !defined(SMALL_KERNEL) 1636 longrun_init(); 1637 #endif 1638 } 1639 1640 char * 1641 intel686_cpu_name(int model) 1642 { 1643 char *ret = NULL; 1644 1645 switch (model) { 1646 case 5: 1647 switch (cpu_cache_edx & 0xFF) { 1648 case 0x40: 1649 case 0x41: 1650 ret = "Celeron"; 1651 break; 1652 /* 0x42 should not exist in this model. */ 1653 case 0x43: 1654 ret = "Pentium II"; 1655 break; 1656 case 0x44: 1657 case 0x45: 1658 ret = "Pentium II Xeon"; 1659 break; 1660 } 1661 break; 1662 case 7: 1663 switch (cpu_cache_edx & 0xFF) { 1664 /* 0x40 - 0x42 should not exist in this model. */ 1665 case 0x43: 1666 ret = "Pentium III"; 1667 break; 1668 case 0x44: 1669 case 0x45: 1670 ret = "Pentium III Xeon"; 1671 break; 1672 } 1673 break; 1674 } 1675 1676 return (ret); 1677 } 1678 1679 char * 1680 cyrix3_cpu_name(int model, int step) 1681 { 1682 char *name = NULL; 1683 1684 switch (model) { 1685 case 7: 1686 if (step < 8) 1687 name = "C3 Samuel 2"; 1688 else 1689 name = "C3 Ezra"; 1690 break; 1691 } 1692 return name; 1693 } 1694 1695 /* 1696 * Print identification for the given CPU. 1697 * XXX XXX 1698 * This is not as clean as one might like, because it references 1699 * 1700 * the "cpuid_level" and "cpu_vendor" globals. 1701 * cpuid_level isn't so bad, since both CPU's will hopefully 1702 * be of the same level. 1703 * 1704 * The Intel multiprocessor spec doesn't give us the cpu_vendor 1705 * information; however, the chance of multi-vendor SMP actually 1706 * ever *working* is sufficiently low that it's probably safe to assume 1707 * all processors are of the same vendor. 1708 */ 1709 void 1710 identifycpu(struct cpu_info *ci) 1711 { 1712 const char *name, *modifier, *vendorname, *token; 1713 int class = CPUCLASS_386, vendor, i, max; 1714 int family, model, step, modif, cachesize; 1715 const struct cpu_cpuid_nameclass *cpup = NULL; 1716 char *brandstr_from, *brandstr_to; 1717 char *cpu_device = ci->ci_dev->dv_xname; 1718 int skipspace; 1719 extern uint32_t cpu_meltdown; 1720 1721 if (cpuid_level == -1) { 1722 #ifdef DIAGNOSTIC 1723 if (cpu < 0 || cpu >= 1724 (sizeof i386_nocpuid_cpus/sizeof(struct cpu_nocpuid_nameclass))) 1725 panic("unknown cpu type %d", cpu); 1726 #endif 1727 name = i386_nocpuid_cpus[cpu].cpu_name; 1728 vendor = i386_nocpuid_cpus[cpu].cpu_vendor; 1729 vendorname = i386_nocpuid_cpus[cpu].cpu_vendorname; 1730 model = -1; 1731 step = -1; 1732 class = i386_nocpuid_cpus[cpu].cpu_class; 1733 ci->cpu_setup = i386_nocpuid_cpus[cpu].cpu_setup; 1734 modifier = ""; 1735 token = ""; 1736 } else { 1737 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1738 modif = (ci->ci_signature >> 12) & 3; 1739 family = (ci->ci_signature >> 8) & 15; 1740 ci->ci_family = family; 1741 model = (ci->ci_signature >> 4) & 15; 1742 ci->ci_model = model; 1743 step = ci->ci_signature & 15; 1744 #ifdef CPUDEBUG 1745 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n", 1746 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx, 1747 cpu_cache_ecx, cpu_cache_edx); 1748 #endif 1749 if (family < CPU_MINFAMILY) 1750 panic("identifycpu: strange family value"); 1751 1752 for (i = 0; i < max; i++) { 1753 if (!strncmp(cpu_vendor, 1754 i386_cpuid_cpus[i].cpu_id, 12)) { 1755 cpup = &i386_cpuid_cpus[i]; 1756 break; 1757 } 1758 } 1759 1760 if (cpup == NULL) { 1761 vendor = CPUVENDOR_UNKNOWN; 1762 if (cpu_vendor[0] != '\0') 1763 vendorname = &cpu_vendor[0]; 1764 else 1765 vendorname = "Unknown"; 1766 if (family > CPU_MAXFAMILY) 1767 family = CPU_MAXFAMILY; 1768 class = family - 3; 1769 if (class > CPUCLASS_686) 1770 class = CPUCLASS_686; 1771 modifier = ""; 1772 name = ""; 1773 token = ""; 1774 ci->cpu_setup = NULL; 1775 } else { 1776 token = cpup->cpu_id; 1777 vendor = cpup->cpu_vendor; 1778 vendorname = cpup->cpu_vendorname; 1779 /* 1780 * Special hack for the VIA C3 series. 1781 * 1782 * VIA bought Centaur Technology from IDT in Aug 1999 1783 * and marketed the processors as VIA Cyrix III/C3. 1784 */ 1785 if (vendor == CPUVENDOR_IDT && family >= 6) { 1786 vendor = CPUVENDOR_VIA; 1787 vendorname = "VIA"; 1788 } 1789 modifier = modifiers[modif]; 1790 if (family > CPU_MAXFAMILY) { 1791 family = CPU_MAXFAMILY; 1792 model = CPU_DEFMODEL; 1793 } else if (model > CPU_MAXMODEL) 1794 model = CPU_DEFMODEL; 1795 i = family - CPU_MINFAMILY; 1796 1797 /* store extended family/model values for later use */ 1798 if ((vendor == CPUVENDOR_INTEL && 1799 (family == 0x6 || family == 0xf)) || 1800 (vendor == CPUVENDOR_AMD && family == 0xf)) { 1801 ci->ci_family += (ci->ci_signature >> 20) & 1802 0xff; 1803 ci->ci_model += ((ci->ci_signature >> 16) & 1804 0x0f) << 4; 1805 } 1806 1807 /* Special hack for the PentiumII/III series. */ 1808 if (vendor == CPUVENDOR_INTEL && family == 6 && 1809 (model == 5 || model == 7)) { 1810 name = intel686_cpu_name(model); 1811 /* Special hack for the VIA C3 series. */ 1812 } else if (vendor == CPUVENDOR_VIA && family == 6 && 1813 model == 7) { 1814 name = cyrix3_cpu_name(model, step); 1815 /* Special hack for the TMS5x00 series. */ 1816 } else if (vendor == CPUVENDOR_TRANSMETA && 1817 family == 5 && model == 4) { 1818 name = tm86_cpu_name(model); 1819 } else 1820 name = cpup->cpu_family[i].cpu_models[model]; 1821 if (name == NULL) { 1822 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL]; 1823 if (name == NULL) 1824 name = ""; 1825 } 1826 class = cpup->cpu_family[i].cpu_class; 1827 ci->cpu_setup = cpup->cpu_family[i].cpu_setup; 1828 } 1829 } 1830 1831 /* Find the amount of on-chip L2 cache. */ 1832 cachesize = -1; 1833 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) { 1834 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 }; 1835 1836 if ((cpu_cache_edx & 0xFF) >= 0x40 && 1837 (cpu_cache_edx & 0xFF) <= 0x45) 1838 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40]; 1839 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) { 1840 u_int regs[4]; 1841 cpuid(0x80000000, regs); 1842 1843 if (regs[0] >= 0x80000005) 1844 cpuid(0x80000005, ci->ci_amdcacheinfo); 1845 1846 if (regs[0] >= 0x80000006) { 1847 cpuid(0x80000006, ci->ci_extcacheinfo); 1848 cachesize = (ci->ci_extcacheinfo[2] >> 16); 1849 } 1850 } 1851 1852 if (ci->ci_feature_flags & CPUID_CFLUSH) { 1853 u_int regs[4]; 1854 1855 /* to get the cacheline size you must do cpuid 1856 * with eax 0x01 1857 */ 1858 1859 cpuid(0x01, regs); 1860 ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; 1861 } 1862 1863 if (vendor == CPUVENDOR_INTEL) { 1864 u_int regs[4]; 1865 /* 1866 * PIII, Core Solo and Core Duo CPUs have known 1867 * errata stating: 1868 * "Page with PAT set to WC while associated MTRR is UC 1869 * may consolidate to UC". 1870 * Because of this it is best we just fallback to mtrrs 1871 * in this case. 1872 */ 1873 if (ci->ci_family == 6 && ci->ci_model < 15) 1874 ci->ci_feature_flags &= ~CPUID_PAT; 1875 1876 if (cpuid_level >= 0x1) { 1877 cpuid(0x80000000, regs); 1878 if (regs[0] >= 0x80000006) 1879 cpuid(0x80000006, ci->ci_extcacheinfo); 1880 } 1881 } 1882 1883 /* Remove leading, trailing and duplicated spaces from cpu_brandstr */ 1884 brandstr_from = brandstr_to = cpu_brandstr; 1885 skipspace = 1; 1886 while (*brandstr_from != '\0') { 1887 if (!skipspace || *brandstr_from != ' ') { 1888 skipspace = 0; 1889 *(brandstr_to++) = *brandstr_from; 1890 } 1891 if (*brandstr_from == ' ') 1892 skipspace = 1; 1893 brandstr_from++; 1894 } 1895 if (skipspace && brandstr_to > cpu_brandstr) 1896 brandstr_to--; 1897 *brandstr_to = '\0'; 1898 1899 if (cpu_brandstr[0] == '\0') { 1900 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */, 1901 "%s %s%s", vendorname, modifier, name); 1902 } 1903 1904 if (cachesize > -1) { 1905 snprintf(cpu_model, sizeof(cpu_model), 1906 "%s (%s%s%s%s-class, %dKB L2 cache)", 1907 cpu_brandstr, 1908 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1909 ((*token) ? "\" " : ""), classnames[class], cachesize); 1910 } else { 1911 snprintf(cpu_model, sizeof(cpu_model), 1912 "%s (%s%s%s%s-class)", 1913 cpu_brandstr, 1914 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1915 ((*token) ? "\" " : ""), classnames[class]); 1916 } 1917 1918 printf("%s: %s", cpu_device, cpu_model); 1919 1920 if (ci->ci_feature_flags && (ci->ci_feature_flags & CPUID_TSC)) { 1921 /* Has TSC, check if it's constant */ 1922 switch (vendor) { 1923 case CPUVENDOR_INTEL: 1924 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 1925 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 1926 ci->ci_flags |= CPUF_CONST_TSC; 1927 } 1928 break; 1929 case CPUVENDOR_VIA: 1930 if (ci->ci_model >= 0x0f) { 1931 ci->ci_flags |= CPUF_CONST_TSC; 1932 } 1933 break; 1934 } 1935 calibrate_cyclecounter(); 1936 if (cpuspeed > 994) { 1937 int ghz, fr; 1938 1939 ghz = (cpuspeed + 9) / 1000; 1940 fr = ((cpuspeed + 9) / 10 ) % 100; 1941 if (fr) 1942 printf(" %d.%02d GHz", ghz, fr); 1943 else 1944 printf(" %d GHz", ghz); 1945 } else { 1946 printf(" %d MHz", cpuspeed); 1947 } 1948 } 1949 1950 if (cpuid_level != -1) 1951 printf(", %02x-%02x-%02x", ci->ci_family, ci->ci_model, 1952 step); 1953 1954 printf("\n"); 1955 1956 if (ci->ci_feature_flags) { 1957 int numbits = 0; 1958 1959 printf("%s: ", cpu_device); 1960 max = sizeof(i386_cpuid_features) / 1961 sizeof(i386_cpuid_features[0]); 1962 for (i = 0; i < max; i++) { 1963 if (ci->ci_feature_flags & 1964 i386_cpuid_features[i].feature_bit) { 1965 printf("%s%s", (numbits == 0 ? "" : ","), 1966 i386_cpuid_features[i].feature_name); 1967 numbits++; 1968 } 1969 } 1970 max = sizeof(i386_cpuid_ecxfeatures) 1971 / sizeof(i386_cpuid_ecxfeatures[0]); 1972 for (i = 0; i < max; i++) { 1973 if (cpu_ecxfeature & 1974 i386_cpuid_ecxfeatures[i].feature_bit) { 1975 printf("%s%s", (numbits == 0 ? "" : ","), 1976 i386_cpuid_ecxfeatures[i].feature_name); 1977 numbits++; 1978 } 1979 } 1980 for (i = 0; i < nitems(i386_ecpuid_features); i++) { 1981 if (ecpu_feature & 1982 i386_ecpuid_features[i].feature_bit) { 1983 printf("%s%s", (numbits == 0 ? "" : ","), 1984 i386_ecpuid_features[i].feature_name); 1985 numbits++; 1986 } 1987 } 1988 for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) { 1989 if (ecpu_ecxfeature & 1990 i386_ecpuid_ecxfeatures[i].feature_bit) { 1991 printf("%s%s", (numbits == 0 ? "" : ","), 1992 i386_ecpuid_ecxfeatures[i].feature_name); 1993 numbits++; 1994 } 1995 } 1996 for (i = 0; i < nitems(i386_cpuid_eaxperf); i++) { 1997 if (cpu_perf_eax & 1998 i386_cpuid_eaxperf[i].feature_bit) { 1999 printf("%s%s", (numbits == 0 ? "" : ","), 2000 i386_cpuid_eaxperf[i].feature_name); 2001 numbits++; 2002 } 2003 } 2004 for (i = 0; i < nitems(i386_cpuid_edxapmi); i++) { 2005 if (cpu_apmi_edx & 2006 i386_cpuid_edxapmi[i].feature_bit) { 2007 printf("%s%s", (numbits == 0 ? "" : ","), 2008 i386_cpuid_edxapmi[i].feature_name); 2009 numbits++; 2010 } 2011 } 2012 2013 if (cpuid_level >= 0x07) { 2014 u_int dummy; 2015 2016 /* "Structured Extended Feature Flags" */ 2017 CPUID_LEAF(0x7, 0, dummy, 2018 ci->ci_feature_sefflags_ebx, 2019 ci->ci_feature_sefflags_ecx, 2020 ci->ci_feature_sefflags_edx); 2021 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 2022 if (ci->ci_feature_sefflags_ebx & 2023 cpu_seff0_ebxfeatures[i].feature_bit) 2024 printf("%s%s", 2025 (numbits == 0 ? "" : ","), 2026 cpu_seff0_ebxfeatures[i].feature_name); 2027 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 2028 if (ci->ci_feature_sefflags_ecx & 2029 cpu_seff0_ecxfeatures[i].feature_bit) 2030 printf("%s%s", 2031 (numbits == 0 ? "" : ","), 2032 cpu_seff0_ecxfeatures[i].feature_name); 2033 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 2034 if (ci->ci_feature_sefflags_edx & 2035 cpu_seff0_edxfeatures[i].feature_bit) 2036 printf("%s%s", 2037 (numbits == 0 ? "" : ","), 2038 cpu_seff0_edxfeatures[i].feature_name); 2039 } 2040 2041 if (!strcmp(cpu_vendor, "GenuineIntel") && 2042 cpuid_level >= 0x06 ) { 2043 u_int dummy; 2044 2045 CPUID(0x06, ci->ci_feature_tpmflags, dummy, 2046 dummy, dummy); 2047 max = nitems(cpu_tpm_eaxfeatures); 2048 for (i = 0; i < max; i++) 2049 if (ci->ci_feature_tpmflags & 2050 cpu_tpm_eaxfeatures[i].feature_bit) 2051 printf(",%s", cpu_tpm_eaxfeatures[i].feature_name); 2052 } 2053 2054 /* xsave subfeatures */ 2055 if (cpuid_level >= 0xd) { 2056 uint32_t dummy, val; 2057 2058 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 2059 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 2060 if (val & cpu_xsave_extfeatures[i].feature_bit) 2061 printf(",%s", 2062 cpu_xsave_extfeatures[i].feature_name); 2063 } 2064 2065 if (cpu_meltdown) 2066 printf(",MELTDOWN"); 2067 2068 printf("\n"); 2069 } 2070 2071 /* 2072 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques 2073 * for Managing Speculation on AMD Processors" 2074 * 2075 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch 2076 * serializing instruction. 2077 * 2078 * This MSR is available on all AMD families >= 10h, except 11h 2079 * where LFENCE is always serializing. 2080 */ 2081 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 2082 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) { 2083 uint64_t msr; 2084 2085 msr = rdmsr(MSR_DE_CFG); 2086 if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { 2087 msr |= DE_CFG_SERIALIZE_LFENCE; 2088 wrmsr(MSR_DE_CFG, msr); 2089 } 2090 } 2091 } 2092 2093 /* 2094 * Attempt to disable Silicon Debug and lock the configuration 2095 * if it's enabled and unlocked. 2096 */ 2097 if (!strcmp(cpu_vendor, "GenuineIntel") && 2098 (cpu_ecxfeature & CPUIDECX_SDBG)) { 2099 uint64_t msr; 2100 2101 msr = rdmsr(IA32_DEBUG_INTERFACE); 2102 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 2103 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 2104 msr &= IA32_DEBUG_INTERFACE_MASK; 2105 msr |= IA32_DEBUG_INTERFACE_LOCK; 2106 wrmsr(IA32_DEBUG_INTERFACE, msr); 2107 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 2108 printf("%s: cannot disable silicon debug\n", 2109 cpu_device); 2110 } 2111 2112 if (CPU_IS_PRIMARY(ci)) { 2113 if (cpu_ecxfeature & CPUIDECX_RDRAND) 2114 has_rdrand = 1; 2115 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 2116 has_rdseed = 1; 2117 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 2118 replacesmap(); 2119 } 2120 2121 #ifndef SMALL_KERNEL 2122 if (cpuspeed != 0 && cpu_cpuspeed == NULL) 2123 cpu_cpuspeed = pentium_cpuspeed; 2124 #endif 2125 2126 cpu_class = class; 2127 2128 if (cpu_class == CPUCLASS_386) { 2129 printf("WARNING: 386 (possibly unknown?) cpu class, assuming 486\n"); 2130 cpu_class = CPUCLASS_486; 2131 } 2132 2133 ci->cpu_class = class; 2134 2135 if (cpu == CPU_486DLC) 2136 printf("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n"); 2137 2138 /* 2139 * Enable ring 0 write protection (486 or above, but 386 2140 * no longer supported). 2141 */ 2142 lcr0(rcr0() | CR0_WP); 2143 2144 /* 2145 * If we have FXSAVE/FXRESTOR, use them. 2146 */ 2147 if (cpu_feature & CPUID_FXSR) { 2148 i386_use_fxsave = 1; 2149 lcr4(rcr4() | CR4_OSFXSR); 2150 2151 /* 2152 * If we have SSE/SSE2, enable XMM exceptions, and 2153 * notify userland. 2154 */ 2155 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) { 2156 if (cpu_feature & CPUID_SSE) 2157 i386_has_sse = 1; 2158 if (cpu_feature & CPUID_SSE2) 2159 i386_has_sse2 = 1; 2160 lcr4(rcr4() | CR4_OSXMMEXCPT); 2161 } 2162 } else 2163 i386_use_fxsave = 0; 2164 2165 } 2166 2167 char * 2168 tm86_cpu_name(int model) 2169 { 2170 u_int32_t regs[4]; 2171 char *name = NULL; 2172 2173 cpuid(0x80860001, regs); 2174 2175 switch (model) { 2176 case 4: 2177 if (((regs[1] >> 16) & 0xff) >= 0x3) 2178 name = "TMS5800"; 2179 else 2180 name = "TMS5600"; 2181 } 2182 2183 return name; 2184 } 2185 2186 #ifndef SMALL_KERNEL 2187 void 2188 cyrix3_get_bus_clock(struct cpu_info *ci) 2189 { 2190 u_int64_t msr; 2191 int bus; 2192 2193 msr = rdmsr(MSR_EBL_CR_POWERON); 2194 bus = (msr >> 18) & 0x3; 2195 switch (bus) { 2196 case 0: 2197 bus_clock = BUS100; 2198 break; 2199 case 1: 2200 bus_clock = BUS133; 2201 break; 2202 case 2: 2203 bus_clock = BUS200; 2204 break; 2205 case 3: 2206 bus_clock = BUS166; 2207 break; 2208 } 2209 } 2210 2211 void 2212 p4_get_bus_clock(struct cpu_info *ci) 2213 { 2214 u_int64_t msr; 2215 int model, bus; 2216 2217 model = (ci->ci_signature >> 4) & 15; 2218 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2219 if (model < 2) { 2220 bus = (msr >> 21) & 0x7; 2221 switch (bus) { 2222 case 0: 2223 bus_clock = BUS100; 2224 break; 2225 case 1: 2226 bus_clock = BUS133; 2227 break; 2228 default: 2229 printf("%s: unknown Pentium 4 (model %d) " 2230 "EBC_FREQUENCY_ID value %d\n", 2231 ci->ci_dev->dv_xname, model, bus); 2232 break; 2233 } 2234 } else { 2235 bus = (msr >> 16) & 0x7; 2236 switch (bus) { 2237 case 0: 2238 bus_clock = (model == 2) ? BUS100 : BUS266; 2239 break; 2240 case 1: 2241 bus_clock = BUS133; 2242 break; 2243 case 2: 2244 bus_clock = BUS200; 2245 break; 2246 case 3: 2247 bus_clock = BUS166; 2248 break; 2249 default: 2250 printf("%s: unknown Pentium 4 (model %d) " 2251 "EBC_FREQUENCY_ID value %d\n", 2252 ci->ci_dev->dv_xname, model, bus); 2253 break; 2254 } 2255 } 2256 } 2257 2258 void 2259 p3_get_bus_clock(struct cpu_info *ci) 2260 { 2261 u_int64_t msr; 2262 int bus; 2263 2264 switch (ci->ci_model) { 2265 case 0x9: /* Pentium M (130 nm, Banias) */ 2266 bus_clock = BUS100; 2267 break; 2268 case 0xd: /* Pentium M (90 nm, Dothan) */ 2269 msr = rdmsr(MSR_FSB_FREQ); 2270 bus = (msr >> 0) & 0x7; 2271 switch (bus) { 2272 case 0: 2273 bus_clock = BUS100; 2274 break; 2275 case 1: 2276 bus_clock = BUS133; 2277 break; 2278 default: 2279 printf("%s: unknown Pentium M FSB_FREQ value %d", 2280 ci->ci_dev->dv_xname, bus); 2281 goto print_msr; 2282 } 2283 break; 2284 case 0x15: /* EP80579 no FSB */ 2285 break; 2286 case 0xe: /* Core Duo/Solo */ 2287 case 0xf: /* Core Xeon */ 2288 case 0x16: /* 65nm Celeron */ 2289 case 0x17: /* Core 2 Extreme/45nm Xeon */ 2290 case 0x1d: /* Xeon MP 7400 */ 2291 msr = rdmsr(MSR_FSB_FREQ); 2292 bus = (msr >> 0) & 0x7; 2293 switch (bus) { 2294 case 5: 2295 bus_clock = BUS100; 2296 break; 2297 case 1: 2298 bus_clock = BUS133; 2299 break; 2300 case 3: 2301 bus_clock = BUS166; 2302 break; 2303 case 2: 2304 bus_clock = BUS200; 2305 break; 2306 case 0: 2307 bus_clock = BUS266; 2308 break; 2309 case 4: 2310 bus_clock = BUS333; 2311 break; 2312 default: 2313 printf("%s: unknown Core FSB_FREQ value %d", 2314 ci->ci_dev->dv_xname, bus); 2315 goto print_msr; 2316 } 2317 break; 2318 case 0x1c: /* Atom */ 2319 case 0x26: /* Atom Z6xx */ 2320 case 0x36: /* Atom [DN]2xxx */ 2321 msr = rdmsr(MSR_FSB_FREQ); 2322 bus = (msr >> 0) & 0x7; 2323 switch (bus) { 2324 case 5: 2325 bus_clock = BUS100; 2326 break; 2327 case 1: 2328 bus_clock = BUS133; 2329 break; 2330 case 3: 2331 bus_clock = BUS166; 2332 break; 2333 case 2: 2334 bus_clock = BUS200; 2335 break; 2336 default: 2337 printf("%s: unknown Atom FSB_FREQ value %d", 2338 ci->ci_dev->dv_xname, bus); 2339 goto print_msr; 2340 } 2341 break; 2342 case 0x1: /* Pentium Pro, model 1 */ 2343 case 0x3: /* Pentium II, model 3 */ 2344 case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */ 2345 case 0x6: /* Celeron, model 6 */ 2346 case 0x7: /* Pentium III, III Xeon, model 7 */ 2347 case 0x8: /* Pentium III, III Xeon, Celeron, model 8 */ 2348 case 0xa: /* Pentium III Xeon, model A */ 2349 case 0xb: /* Pentium III, model B */ 2350 msr = rdmsr(MSR_EBL_CR_POWERON); 2351 bus = (msr >> 18) & 0x3; 2352 switch (bus) { 2353 case 0: 2354 bus_clock = BUS66; 2355 break; 2356 case 1: 2357 bus_clock = BUS133; 2358 break; 2359 case 2: 2360 bus_clock = BUS100; 2361 break; 2362 default: 2363 printf("%s: unknown i686 EBL_CR_POWERON value %d", 2364 ci->ci_dev->dv_xname, bus); 2365 goto print_msr; 2366 } 2367 break; 2368 default: 2369 /* no FSB on modern Intel processors */ 2370 break; 2371 } 2372 return; 2373 print_msr: 2374 /* 2375 * Show the EBL_CR_POWERON MSR, so we'll at least have 2376 * some extra information, such as clock ratio, etc. 2377 */ 2378 printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON)); 2379 } 2380 2381 void 2382 p4_update_cpuspeed(void) 2383 { 2384 struct cpu_info *ci; 2385 u_int64_t msr; 2386 int mult; 2387 2388 ci = curcpu(); 2389 p4_get_bus_clock(ci); 2390 2391 if (bus_clock == 0) { 2392 printf("p4_update_cpuspeed: unknown bus clock\n"); 2393 return; 2394 } 2395 2396 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2397 mult = ((msr >> 24) & 0xff); 2398 2399 cpuspeed = (bus_clock * mult) / 100; 2400 } 2401 2402 void 2403 p3_update_cpuspeed(void) 2404 { 2405 struct cpu_info *ci; 2406 u_int64_t msr; 2407 int mult; 2408 const u_int8_t mult_code[] = { 2409 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 }; 2410 2411 ci = curcpu(); 2412 p3_get_bus_clock(ci); 2413 2414 if (bus_clock == 0) { 2415 printf("p3_update_cpuspeed: unknown bus clock\n"); 2416 return; 2417 } 2418 2419 msr = rdmsr(MSR_EBL_CR_POWERON); 2420 mult = (msr >> 22) & 0xf; 2421 mult = mult_code[mult]; 2422 if (!p3_early) 2423 mult += ((msr >> 27) & 0x1) * 40; 2424 2425 cpuspeed = (bus_clock * mult) / 1000; 2426 } 2427 2428 int 2429 pentium_cpuspeed(int *freq) 2430 { 2431 *freq = cpuspeed; 2432 return (0); 2433 } 2434 #endif /* !SMALL_KERNEL */ 2435 2436 /* 2437 * Send an interrupt to process. 2438 * 2439 * Stack is set up to allow sigcode stored 2440 * in u. to call routine, followed by kcall 2441 * to sigreturn routine below. After sigreturn 2442 * resets the signal mask, the stack, and the 2443 * frame pointer, it returns to the user 2444 * specified pc, psl. 2445 */ 2446 int 2447 sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip, 2448 int info, int onstack) 2449 { 2450 struct proc *p = curproc; 2451 struct trapframe *tf = p->p_md.md_regs; 2452 struct sigframe *fp, frame; 2453 register_t sp; 2454 2455 /* 2456 * Build the argument list for the signal handler. 2457 */ 2458 bzero(&frame, sizeof(frame)); 2459 frame.sf_signum = sig; 2460 2461 /* 2462 * Allocate space for the signal handler context. 2463 */ 2464 if ((p->p_sigstk.ss_flags & SS_DISABLE) == 0 && 2465 !sigonstack(tf->tf_esp) && onstack) 2466 sp = trunc_page((vaddr_t)p->p_sigstk.ss_sp + p->p_sigstk.ss_size); 2467 else 2468 sp = tf->tf_esp; 2469 2470 frame.sf_sc.sc_fpstate = NULL; 2471 if (p->p_md.md_flags & MDP_USEDFPU) { 2472 npxsave_proc(p, 1); 2473 sp -= sizeof(union savefpu); 2474 sp &= ~0xf; /* for XMM regs */ 2475 frame.sf_sc.sc_fpstate = (void *)sp; 2476 if (copyout(&p->p_addr->u_pcb.pcb_savefpu, 2477 (void *)sp, sizeof(union savefpu))) 2478 return 1; 2479 2480 /* Signal handlers get a completely clean FP state */ 2481 p->p_md.md_flags &= ~MDP_USEDFPU; 2482 } 2483 2484 fp = (struct sigframe *)sp - 1; 2485 frame.sf_scp = &fp->sf_sc; 2486 frame.sf_sip = NULL; 2487 frame.sf_handler = catcher; 2488 2489 /* 2490 * Build the signal context to be used by sigreturn. 2491 */ 2492 frame.sf_sc.sc_err = tf->tf_err; 2493 frame.sf_sc.sc_trapno = tf->tf_trapno; 2494 frame.sf_sc.sc_mask = mask; 2495 frame.sf_sc.sc_fs = tf->tf_fs; 2496 frame.sf_sc.sc_gs = tf->tf_gs; 2497 frame.sf_sc.sc_es = tf->tf_es; 2498 frame.sf_sc.sc_ds = tf->tf_ds; 2499 frame.sf_sc.sc_eflags = tf->tf_eflags; 2500 frame.sf_sc.sc_edi = tf->tf_edi; 2501 frame.sf_sc.sc_esi = tf->tf_esi; 2502 frame.sf_sc.sc_ebp = tf->tf_ebp; 2503 frame.sf_sc.sc_ebx = tf->tf_ebx; 2504 frame.sf_sc.sc_edx = tf->tf_edx; 2505 frame.sf_sc.sc_ecx = tf->tf_ecx; 2506 frame.sf_sc.sc_eax = tf->tf_eax; 2507 frame.sf_sc.sc_eip = tf->tf_eip; 2508 frame.sf_sc.sc_cs = tf->tf_cs; 2509 frame.sf_sc.sc_esp = tf->tf_esp; 2510 frame.sf_sc.sc_ss = tf->tf_ss; 2511 2512 if (info) { 2513 frame.sf_sip = &fp->sf_si; 2514 frame.sf_si = *ksip; 2515 } 2516 2517 /* XXX don't copyout siginfo if not needed? */ 2518 frame.sf_sc.sc_cookie = (long)&fp->sf_sc ^ p->p_p->ps_sigcookie; 2519 if (copyout(&frame, fp, sizeof(frame)) != 0) 2520 return 1; 2521 2522 /* 2523 * Build context to run handler in. 2524 */ 2525 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2526 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2527 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2528 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2529 tf->tf_eip = p->p_p->ps_sigcode; 2530 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2531 tf->tf_eflags &= ~(PSL_T|PSL_D|PSL_VM|PSL_AC); 2532 tf->tf_esp = (int)fp; 2533 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2534 2535 return 0; 2536 } 2537 2538 /* 2539 * System call to cleanup state after a signal 2540 * has been taken. Reset signal mask and 2541 * stack state from context left by sendsig (above). 2542 * Return to previous pc and psl as specified by 2543 * context left by sendsig. Check carefully to 2544 * make sure that the user has not modified the 2545 * psl to gain improper privileges or to cause 2546 * a machine fault. 2547 */ 2548 int 2549 sys_sigreturn(struct proc *p, void *v, register_t *retval) 2550 { 2551 struct sys_sigreturn_args /* { 2552 syscallarg(struct sigcontext *) sigcntxp; 2553 } */ *uap = v; 2554 struct sigcontext ksc, *scp = SCARG(uap, sigcntxp); 2555 struct trapframe *tf = p->p_md.md_regs; 2556 int error; 2557 2558 if (PROC_PC(p) != p->p_p->ps_sigcoderet) { 2559 sigexit(p, SIGILL); 2560 return (EPERM); 2561 } 2562 2563 if ((error = copyin((caddr_t)scp, &ksc, sizeof(*scp)))) 2564 return (error); 2565 2566 if (ksc.sc_cookie != ((long)scp ^ p->p_p->ps_sigcookie)) { 2567 sigexit(p, SIGILL); 2568 return (EFAULT); 2569 } 2570 2571 /* Prevent reuse of the sigcontext cookie */ 2572 ksc.sc_cookie = 0; 2573 (void)copyout(&ksc.sc_cookie, (caddr_t)scp + 2574 offsetof(struct sigcontext, sc_cookie), sizeof (ksc.sc_cookie)); 2575 2576 /* 2577 * Restore signal ksc. 2578 */ 2579 /* 2580 * Check for security violations. If we're returning to 2581 * protected mode, the CPU will validate the segment registers 2582 * automatically and generate a trap on violations. We handle 2583 * the trap, rather than doing all of the checking here. 2584 */ 2585 if (((ksc.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 || 2586 !USERMODE(ksc.sc_cs, ksc.sc_eflags)) 2587 return (EINVAL); 2588 2589 tf->tf_fs = ksc.sc_fs; 2590 tf->tf_gs = ksc.sc_gs; 2591 tf->tf_es = ksc.sc_es; 2592 tf->tf_ds = ksc.sc_ds; 2593 tf->tf_eflags = ksc.sc_eflags; 2594 tf->tf_edi = ksc.sc_edi; 2595 tf->tf_esi = ksc.sc_esi; 2596 tf->tf_ebp = ksc.sc_ebp; 2597 tf->tf_ebx = ksc.sc_ebx; 2598 tf->tf_edx = ksc.sc_edx; 2599 tf->tf_ecx = ksc.sc_ecx; 2600 tf->tf_eax = ksc.sc_eax; 2601 tf->tf_eip = ksc.sc_eip; 2602 tf->tf_cs = ksc.sc_cs; 2603 tf->tf_esp = ksc.sc_esp; 2604 tf->tf_ss = ksc.sc_ss; 2605 2606 if (p->p_md.md_flags & MDP_USEDFPU) 2607 npxsave_proc(p, 0); 2608 2609 if (ksc.sc_fpstate) { 2610 union savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu; 2611 2612 if ((error = copyin(ksc.sc_fpstate, sfp, sizeof(*sfp)))) 2613 return (error); 2614 if (i386_use_fxsave) 2615 sfp->sv_xmm.sv_env.en_mxcsr &= fpu_mxcsr_mask; 2616 p->p_md.md_flags |= MDP_USEDFPU; 2617 } 2618 2619 p->p_sigmask = ksc.sc_mask & ~sigcantmask; 2620 2621 return (EJUSTRETURN); 2622 } 2623 2624 #ifdef MULTIPROCESSOR 2625 /* force a CPU into the kernel, whether or not it's idle */ 2626 void 2627 cpu_kick(struct cpu_info *ci) 2628 { 2629 /* only need to kick other CPUs */ 2630 if (ci != curcpu()) { 2631 if (cpu_mwait_size > 0) { 2632 /* 2633 * If not idling, then send an IPI, else 2634 * just clear the "keep idling" bit. 2635 */ 2636 if ((ci->ci_mwait & MWAIT_IN_IDLE) == 0) 2637 i386_send_ipi(ci, I386_IPI_NOP); 2638 else 2639 atomic_clearbits_int(&ci->ci_mwait, 2640 MWAIT_KEEP_IDLING); 2641 } else { 2642 /* no mwait, so need an IPI */ 2643 i386_send_ipi(ci, I386_IPI_NOP); 2644 } 2645 } 2646 } 2647 #endif 2648 2649 /* 2650 * Notify the current process (p) that it has a signal pending, 2651 * process as soon as possible. 2652 */ 2653 void 2654 signotify(struct proc *p) 2655 { 2656 aston(p); 2657 cpu_kick(p->p_cpu); 2658 } 2659 2660 #ifdef MULTIPROCESSOR 2661 void 2662 cpu_unidle(struct cpu_info *ci) 2663 { 2664 if (cpu_mwait_size > 0 && (ci->ci_mwait & MWAIT_ONLY)) { 2665 /* 2666 * Just clear the "keep idling" bit; if it wasn't 2667 * idling then we didn't need to do anything anyway. 2668 */ 2669 atomic_clearbits_int(&ci->ci_mwait, MWAIT_KEEP_IDLING); 2670 return; 2671 } 2672 2673 if (ci != curcpu()) 2674 i386_send_ipi(ci, I386_IPI_NOP); 2675 } 2676 #endif 2677 2678 int waittime = -1; 2679 struct pcb dumppcb; 2680 2681 __dead void 2682 boot(int howto) 2683 { 2684 if ((howto & RB_POWERDOWN) != 0) 2685 lid_action = 0; 2686 2687 if ((howto & RB_RESET) != 0) 2688 goto doreset; 2689 2690 if (cold) { 2691 if ((howto & RB_USERREQ) == 0) 2692 howto |= RB_HALT; 2693 goto haltsys; 2694 } 2695 2696 boothowto = howto; 2697 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 2698 waittime = 0; 2699 vfs_shutdown(curproc); 2700 2701 if ((howto & RB_TIMEBAD) == 0) { 2702 resettodr(); 2703 } else { 2704 printf("WARNING: not updating battery clock\n"); 2705 } 2706 } 2707 if_downall(); 2708 2709 uvm_shutdown(); 2710 splhigh(); 2711 cold = 1; 2712 2713 if ((howto & RB_DUMP) != 0) 2714 dumpsys(); 2715 2716 haltsys: 2717 config_suspend_all(DVACT_POWERDOWN); 2718 2719 #ifdef MULTIPROCESSOR 2720 i386_broadcast_ipi(I386_IPI_HALT); 2721 #endif 2722 2723 if ((howto & RB_HALT) != 0) { 2724 #if NACPI > 0 && !defined(SMALL_KERNEL) 2725 extern int acpi_enabled; 2726 2727 if (acpi_enabled) { 2728 delay(500000); 2729 if ((howto & RB_POWERDOWN) != 0) 2730 acpi_powerdown(); 2731 } 2732 #endif 2733 2734 #if NAPM > 0 2735 if ((howto & RB_POWERDOWN) != 0) { 2736 int rv; 2737 2738 printf("\nAttempting to power down...\n"); 2739 /* 2740 * Turn off, if we can. But try to turn disk off and 2741 * wait a bit first--some disk drives are slow to 2742 * clean up and users have reported disk corruption. 2743 * 2744 * If apm_set_powstate() fails the first time, don't 2745 * try to turn the system off. 2746 */ 2747 delay(500000); 2748 apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2749 delay(500000); 2750 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2751 if (rv == 0 || rv == ENXIO) { 2752 delay(500000); 2753 (void) apm_set_powstate(APM_DEV_ALLDEVS, 2754 APM_SYS_OFF); 2755 } 2756 } 2757 #endif 2758 printf("\n"); 2759 printf("The operating system has halted.\n"); 2760 printf("Please press any key to reboot.\n\n"); 2761 cnpollc(1); /* for proper keyboard command handling */ 2762 cngetc(); 2763 cnpollc(0); 2764 } 2765 2766 doreset: 2767 printf("rebooting...\n"); 2768 cpu_reset(); 2769 for (;;) 2770 continue; 2771 /* NOTREACHED */ 2772 } 2773 2774 /* 2775 * This is called by configure to set dumplo and dumpsize. 2776 * Dumps always skip the first block of disk space 2777 * in case there might be a disk label stored there. 2778 * If there is extra space, put dump at the end to 2779 * reduce the chance that swapping trashes it. 2780 */ 2781 void 2782 dumpconf(void) 2783 { 2784 int nblks; /* size of dump area */ 2785 int i; 2786 2787 if (dumpdev == NODEV || 2788 (nblks = (bdevsw[major(dumpdev)].d_psize)(dumpdev)) == 0) 2789 return; 2790 if (nblks <= ctod(1)) 2791 return; 2792 2793 /* Always skip the first block, in case there is a label there. */ 2794 if (dumplo < ctod(1)) 2795 dumplo = ctod(1); 2796 2797 for (i = 0; i < ndumpmem; i++) 2798 dumpsize = max(dumpsize, dumpmem[i].end); 2799 2800 /* Put dump at end of partition, and make it fit. */ 2801 if (dumpsize > dtoc(nblks - dumplo - 1)) 2802 dumpsize = dtoc(nblks - dumplo - 1); 2803 if (dumplo < nblks - ctod(dumpsize) - 1) 2804 dumplo = nblks - ctod(dumpsize) - 1; 2805 } 2806 2807 /* 2808 * cpu_dump: dump machine-dependent kernel core dump headers. 2809 */ 2810 int 2811 cpu_dump(void) 2812 { 2813 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2814 long buf[dbtob(1) / sizeof (long)]; 2815 kcore_seg_t *segp; 2816 2817 dump = bdevsw[major(dumpdev)].d_dump; 2818 2819 segp = (kcore_seg_t *)buf; 2820 2821 /* 2822 * Generate a segment header. 2823 */ 2824 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 2825 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); 2826 2827 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1))); 2828 } 2829 2830 /* 2831 * Doadump comes here after turning off memory management and 2832 * getting on the dump stack, either when called above, or by 2833 * the auto-restart code. 2834 */ 2835 static vaddr_t dumpspace; 2836 2837 vaddr_t 2838 reserve_dumppages(vaddr_t p) 2839 { 2840 2841 dumpspace = p; 2842 return (p + PAGE_SIZE); 2843 } 2844 2845 void 2846 dumpsys(void) 2847 { 2848 u_int i, j, npg; 2849 int maddr; 2850 daddr_t blkno; 2851 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2852 int error; 2853 char *str; 2854 extern int msgbufmapped; 2855 2856 /* Save registers. */ 2857 savectx(&dumppcb); 2858 2859 msgbufmapped = 0; /* don't record dump msgs in msgbuf */ 2860 if (dumpdev == NODEV) 2861 return; 2862 2863 /* 2864 * For dumps during autoconfiguration, 2865 * if dump device has already configured... 2866 */ 2867 if (dumpsize == 0) 2868 dumpconf(); 2869 if (dumplo < 0) 2870 return; 2871 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo); 2872 2873 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); 2874 printf("dump "); 2875 if (error == -1) { 2876 printf("area unavailable\n"); 2877 return; 2878 } 2879 2880 #if 0 /* XXX this doesn't work. grr. */ 2881 /* toss any characters present prior to dump */ 2882 while (sget() != NULL); /*syscons and pccons differ */ 2883 #endif 2884 2885 /* scan through the dumpmem list */ 2886 dump = bdevsw[major(dumpdev)].d_dump; 2887 error = cpu_dump(); 2888 for (i = 0; !error && i < ndumpmem; i++) { 2889 2890 npg = dumpmem[i].end - dumpmem[i].start; 2891 maddr = ptoa(dumpmem[i].start); 2892 blkno = dumplo + btodb(maddr) + 1; 2893 #if 0 2894 printf("(%d %lld %d) ", maddr, (long long)blkno, npg); 2895 #endif 2896 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) { 2897 2898 /* Print out how many MBs we have more to go. */ 2899 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG) 2900 printf("%ld ", 2901 (ptoa(dumpsize) - maddr) / (1024 * 1024)); 2902 #if 0 2903 printf("(%x %lld) ", maddr, (long long)blkno); 2904 #endif 2905 pmap_enter(pmap_kernel(), dumpspace, maddr, 2906 PROT_READ, PMAP_WIRED); 2907 if ((error = (*dump)(dumpdev, blkno, 2908 (caddr_t)dumpspace, NBPG))) 2909 break; 2910 2911 #if 0 /* XXX this doesn't work. grr. */ 2912 /* operator aborting dump? */ 2913 if (sget() != NULL) { 2914 error = EINTR; 2915 break; 2916 } 2917 #endif 2918 } 2919 } 2920 2921 switch (error) { 2922 2923 case 0: str = "succeeded\n\n"; break; 2924 case ENXIO: str = "device bad\n\n"; break; 2925 case EFAULT: str = "device not ready\n\n"; break; 2926 case EINVAL: str = "area improper\n\n"; break; 2927 case EIO: str = "i/o error\n\n"; break; 2928 case EINTR: str = "aborted from console\n\n"; break; 2929 default: str = "error %d\n\n"; break; 2930 } 2931 printf(str, error); 2932 2933 delay(5000000); /* 5 seconds */ 2934 } 2935 2936 /* 2937 * Clear registers on exec 2938 */ 2939 void 2940 setregs(struct proc *p, struct exec_package *pack, u_long stack, 2941 register_t *retval) 2942 { 2943 struct pcb *pcb = &p->p_addr->u_pcb; 2944 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map); 2945 struct trapframe *tf = p->p_md.md_regs; 2946 2947 #if NNPX > 0 2948 /* If we were using the FPU, forget about it. */ 2949 if (pcb->pcb_fpcpu != NULL) 2950 npxsave_proc(p, 0); 2951 p->p_md.md_flags &= ~MDP_USEDFPU; 2952 #endif 2953 2954 initcodesegment(&pmap->pm_codeseg); 2955 setsegment(&pcb->pcb_threadsegs[TSEG_FS], 0, 2956 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2957 setsegment(&pcb->pcb_threadsegs[TSEG_GS], 0, 2958 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2959 2960 /* 2961 * And update the GDT since we return to the user process 2962 * by leaving the syscall (we don't do another pmap_activate()). 2963 */ 2964 curcpu()->ci_gdt[GUCODE_SEL].sd = pmap->pm_codeseg; 2965 curcpu()->ci_gdt[GUFS_SEL].sd = pcb->pcb_threadsegs[TSEG_FS]; 2966 curcpu()->ci_gdt[GUGS_SEL].sd = pcb->pcb_threadsegs[TSEG_GS]; 2967 2968 /* 2969 * And reset the hiexec marker in the pmap. 2970 */ 2971 pmap->pm_hiexec = 0; 2972 2973 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2974 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2975 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2976 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2977 tf->tf_edi = 0; 2978 tf->tf_esi = 0; 2979 tf->tf_ebp = 0; 2980 tf->tf_ebx = (int)p->p_p->ps_strings; 2981 tf->tf_edx = 0; 2982 tf->tf_ecx = 0; 2983 tf->tf_eax = 0; 2984 tf->tf_eip = pack->ep_entry; 2985 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2986 tf->tf_eflags = PSL_USERSET; 2987 tf->tf_esp = stack; 2988 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2989 2990 retval[1] = 0; 2991 } 2992 2993 /* 2994 * Initialize segments and descriptor tables 2995 */ 2996 2997 /* IDT is now a full page, so we can map it in u-k */ 2998 union { 2999 struct gate_descriptor idt[NIDT]; 3000 char align[PAGE_SIZE]; 3001 } _idt_region __aligned(PAGE_SIZE); 3002 #define idt_region _idt_region.idt 3003 struct gate_descriptor *idt = idt_region; 3004 3005 extern struct user *proc0paddr; 3006 3007 void 3008 setgate(struct gate_descriptor *gd, void *func, int args, int type, int dpl, 3009 int seg) 3010 { 3011 3012 gd->gd_looffset = (int)func; 3013 gd->gd_selector = GSEL(seg, SEL_KPL); 3014 gd->gd_stkcpy = args; 3015 gd->gd_xx = 0; 3016 gd->gd_type = type; 3017 gd->gd_dpl = dpl; 3018 gd->gd_p = 1; 3019 gd->gd_hioffset = (int)func >> 16; 3020 } 3021 3022 void 3023 unsetgate(struct gate_descriptor *gd) 3024 { 3025 gd->gd_p = 0; 3026 gd->gd_hioffset = 0; 3027 gd->gd_looffset = 0; 3028 gd->gd_selector = 0; 3029 gd->gd_xx = 0; 3030 gd->gd_stkcpy = 0; 3031 gd->gd_type = 0; 3032 gd->gd_dpl = 0; 3033 } 3034 3035 void 3036 setregion(struct region_descriptor *rd, void *base, size_t limit) 3037 { 3038 rd->rd_limit = (int)limit; 3039 rd->rd_base = (int)base; 3040 } 3041 3042 void 3043 initcodesegment(struct segment_descriptor *cs) 3044 { 3045 if (cpu_pae) { 3046 /* 3047 * When code execution is managed using NX feature 3048 * in pmapae.c, GUCODE_SEL should cover userland. 3049 */ 3050 setsegment(cs, 0, atop(VM_MAXUSER_ADDRESS - 1), 3051 SDT_MEMERA, SEL_UPL, 1, 1); 3052 } else { 3053 /* 3054 * For pmap.c's non-PAE/NX line-in-the-sand execution, reset 3055 * the code segment limit to I386_MAX_EXE_ADDR in the pmap; 3056 * this gets copied into the GDT for GUCODE_SEL by 3057 * pmap_activate(). Similarly, reset the base of each of 3058 * the two thread data segments to zero in the pcb; they'll 3059 * get copied into the GDT for GUFS_SEL and GUGS_SEL. 3060 */ 3061 setsegment(cs, 0, atop(I386_MAX_EXE_ADDR - 1), 3062 SDT_MEMERA, SEL_UPL, 1, 1); 3063 } 3064 } 3065 3066 void 3067 setsegment(struct segment_descriptor *sd, void *base, size_t limit, int type, 3068 int dpl, int def32, int gran) 3069 { 3070 3071 sd->sd_lolimit = (int)limit; 3072 sd->sd_lobase = (int)base; 3073 sd->sd_type = type; 3074 sd->sd_dpl = dpl; 3075 sd->sd_p = 1; 3076 sd->sd_hilimit = (int)limit >> 16; 3077 sd->sd_xx = 0; 3078 sd->sd_def32 = def32; 3079 sd->sd_gran = gran; 3080 sd->sd_hibase = (int)base >> 24; 3081 } 3082 3083 #define IDTVEC(name) __CONCAT(X, name) 3084 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 3085 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm), 3086 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page), 3087 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall), IDTVEC(mchk), 3088 IDTVEC(simd); 3089 3090 extern int IDTVEC(f00f_redirect); 3091 3092 int cpu_f00f_bug = 0; 3093 3094 void 3095 fix_f00f(void) 3096 { 3097 struct region_descriptor region; 3098 vaddr_t va; 3099 paddr_t pa; 3100 void *p; 3101 3102 /* Allocate two new pages */ 3103 va = (vaddr_t)km_alloc(NBPG*2, &kv_any, &kp_zero, &kd_waitok); 3104 p = (void *)(va + NBPG - 7*sizeof(*idt)); 3105 3106 /* Copy over old IDT */ 3107 bcopy(idt, p, sizeof(idt_region)); 3108 idt = p; 3109 3110 /* Fix up paging redirect */ 3111 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386IGT, SEL_KPL, 3112 GCODE_SEL); 3113 3114 /* Map first page RO */ 3115 pmap_pte_setbits(va, 0, PG_RW); 3116 3117 /* add k-u read-only mappings XXX old IDT stays in place */ 3118 /* XXX hshoexer: are f00f affected CPUs affected by meltdown? */ 3119 pmap_extract(pmap_kernel(), va, &pa); 3120 pmap_enter_special(va, pa, PROT_READ, 0); 3121 pmap_extract(pmap_kernel(), va + PAGE_SIZE, &pa); 3122 pmap_enter_special(va + PAGE_SIZE, pa, PROT_READ, 0); 3123 3124 /* Reload idtr */ 3125 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3126 lidt(®ion); 3127 3128 /* Tell the rest of the world */ 3129 cpu_f00f_bug = 1; 3130 } 3131 3132 #ifdef MULTIPROCESSOR 3133 void 3134 cpu_init_idt(void) 3135 { 3136 struct region_descriptor region; 3137 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3138 lidt(®ion); 3139 } 3140 #endif /* MULTIPROCESSOR */ 3141 3142 void 3143 init386(paddr_t first_avail) 3144 { 3145 int i, kb; 3146 struct region_descriptor region; 3147 bios_memmap_t *im; 3148 3149 proc0.p_addr = proc0paddr; 3150 cpu_info_primary.ci_self = &cpu_info_primary; 3151 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb; 3152 cpu_info_primary.ci_tss = &cpu_info_full_primary.cif_tss; 3153 cpu_info_primary.ci_nmi_tss = &cpu_info_full_primary.cif_nmi_tss; 3154 cpu_info_primary.ci_gdt = (void *)&cpu_info_full_primary.cif_gdt; 3155 3156 /* make bootstrap gdt gates and memory segments */ 3157 setsegment(&cpu_info_primary.ci_gdt[GCODE_SEL].sd, 0, 0xfffff, 3158 SDT_MEMERA, SEL_KPL, 1, 1); 3159 setsegment(&cpu_info_primary.ci_gdt[GICODE_SEL].sd, 0, 0xfffff, 3160 SDT_MEMERA, SEL_KPL, 1, 1); 3161 setsegment(&cpu_info_primary.ci_gdt[GDATA_SEL].sd, 0, 0xfffff, 3162 SDT_MEMRWA, SEL_KPL, 1, 1); 3163 setsegment(&cpu_info_primary.ci_gdt[GUCODE_SEL].sd, 0, 3164 atop(I386_MAX_EXE_ADDR) - 1, SDT_MEMERA, SEL_UPL, 1, 1); 3165 setsegment(&cpu_info_primary.ci_gdt[GUDATA_SEL].sd, 0, 3166 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3167 setsegment(&cpu_info_primary.ci_gdt[GCPU_SEL].sd, &cpu_info_primary, 3168 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 0, 0); 3169 setsegment(&cpu_info_primary.ci_gdt[GUFS_SEL].sd, 0, 3170 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3171 setsegment(&cpu_info_primary.ci_gdt[GUGS_SEL].sd, 0, 3172 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3173 setsegment(&cpu_info_primary.ci_gdt[GTSS_SEL].sd, 3174 cpu_info_primary.ci_tss, sizeof(struct i386tss)-1, 3175 SDT_SYS386TSS, SEL_KPL, 0, 0); 3176 setsegment(&cpu_info_primary.ci_gdt[GNMITSS_SEL].sd, 3177 cpu_info_primary.ci_nmi_tss, sizeof(struct i386tss)-1, 3178 SDT_SYS386TSS, SEL_KPL, 0, 0); 3179 3180 /* exceptions */ 3181 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3182 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3183 setgate(&idt[ 2], NULL, 0, SDT_SYSTASKGT, SEL_KPL, GNMITSS_SEL); 3184 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3185 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3186 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3187 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3188 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3189 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3190 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3191 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3192 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3193 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3194 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3195 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3196 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3197 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3198 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3199 setgate(&idt[ 18], &IDTVEC(mchk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3200 setgate(&idt[ 19], &IDTVEC(simd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3201 for (i = 20; i < NRSVIDT; i++) 3202 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3203 for (i = NRSVIDT; i < NIDT; i++) 3204 unsetgate(&idt[i]); 3205 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3206 3207 setregion(®ion, cpu_info_primary.ci_gdt, GDT_SIZE - 1); 3208 lgdt(®ion); 3209 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3210 lidt(®ion); 3211 3212 /* 3213 * Initialize the I/O port and I/O mem extent maps. 3214 * Note: we don't have to check the return value since 3215 * creation of a fixed extent map will never fail (since 3216 * descriptor storage has already been allocated). 3217 * 3218 * N.B. The iomem extent manages _all_ physical addresses 3219 * on the machine. When the amount of RAM is found, the two 3220 * extents of RAM are allocated from the map (0 -> ISA hole 3221 * and end of ISA hole -> end of RAM). 3222 */ 3223 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF, 3224 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage), 3225 EX_NOCOALESCE|EX_NOWAIT); 3226 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF, 3227 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage), 3228 EX_NOCOALESCE|EX_NOWAIT); 3229 3230 #if NISA > 0 3231 isa_defaultirq(); 3232 #endif 3233 3234 /* 3235 * Attach the glass console early in case we need to display a panic. 3236 */ 3237 cninit(); 3238 3239 /* 3240 * Saving SSE registers won't work if the save area isn't 3241 * 16-byte aligned. 3242 */ 3243 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf) 3244 panic("init386: pcb_savefpu not 16-byte aligned"); 3245 3246 /* call pmap initialization to make new kernel address space */ 3247 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE); 3248 3249 /* 3250 * Boot arguments are in a single page specified by /boot. 3251 * 3252 * We require the "new" vector form, as well as memory ranges 3253 * to be given in bytes rather than KB. 3254 */ 3255 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) == 3256 (BAPIV_VECTOR | BAPIV_BMEMMAP)) { 3257 if (bootargc > NBPG) 3258 panic("too many boot args"); 3259 3260 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc, 3261 EX_NOWAIT)) 3262 panic("cannot reserve /boot args memory"); 3263 3264 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv, 3265 PROT_READ | PROT_WRITE, 3266 PROT_READ | PROT_WRITE | PMAP_WIRED); 3267 3268 bios_getopt(); 3269 3270 } else 3271 panic("/boot too old: upgrade!"); 3272 3273 #ifdef DIAGNOSTIC 3274 if (bios_memmap == NULL) 3275 panic("no BIOS memory map supplied"); 3276 #endif 3277 3278 /* 3279 * account all the memory passed in the map from /boot 3280 * calculate avail_end and count the physmem. 3281 */ 3282 avail_end = 0; 3283 physmem = 0; 3284 #ifdef DEBUG 3285 printf("memmap:"); 3286 #endif 3287 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++) 3288 if (im->type == BIOS_MAP_FREE) { 3289 paddr_t a, e; 3290 #ifdef DEBUG 3291 printf(" %llx-%llx", im->addr, im->addr + im->size); 3292 #endif 3293 3294 if (im->addr >= 0x100000000ULL) { 3295 #ifdef DEBUG 3296 printf("-H"); 3297 #endif 3298 continue; 3299 } 3300 3301 a = round_page(im->addr); 3302 if (im->addr + im->size <= 0xfffff000ULL) 3303 e = trunc_page(im->addr + im->size); 3304 else { 3305 #ifdef DEBUG 3306 printf("-T"); 3307 #endif 3308 e = 0xfffff000; 3309 } 3310 3311 /* skip first 16 pages due to SMI corruption */ 3312 if (a < 16 * NBPG) 3313 a = 16 * NBPG; 3314 3315 #ifdef MULTIPROCESSOR 3316 /* skip MP trampoline code page */ 3317 if (a < MP_TRAMPOLINE + NBPG) 3318 a = MP_TRAMPOLINE + NBPG; 3319 3320 /* skip MP trampoline data page */ 3321 if (a < MP_TRAMP_DATA + NBPG) 3322 a = MP_TRAMP_DATA + NBPG; 3323 #endif /* MULTIPROCESSOR */ 3324 3325 #if NACPI > 0 && !defined(SMALL_KERNEL) 3326 /* skip ACPI resume trampoline code page */ 3327 if (a < ACPI_TRAMPOLINE + NBPG) 3328 a = ACPI_TRAMPOLINE + NBPG; 3329 3330 /* skip ACPI resume trampoline data page */ 3331 if (a < ACPI_TRAMP_DATA + NBPG) 3332 a = ACPI_TRAMP_DATA + NBPG; 3333 #endif /* ACPI */ 3334 3335 #ifdef HIBERNATE 3336 /* skip hibernate reserved pages */ 3337 if (a < HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE) 3338 a = HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE; 3339 #endif /* HIBERNATE */ 3340 3341 /* skip shorter than page regions */ 3342 if (a >= e || (e - a) < NBPG) { 3343 #ifdef DEBUG 3344 printf("-S"); 3345 #endif 3346 continue; 3347 } 3348 3349 /* 3350 * XXX Some buggy ACPI BIOSes use memory that 3351 * they declare as free. Typically the 3352 * affected memory areas are small blocks 3353 * between areas reserved for ACPI and other 3354 * BIOS goo. So skip areas smaller than 1 MB 3355 * above the 16 MB boundary (to avoid 3356 * affecting legacy stuff). 3357 */ 3358 if (a > 16*1024*1024 && (e - a) < 1*1024*1024) { 3359 #ifdef DEBUG 3360 printf("-X"); 3361 #endif 3362 continue; 3363 } 3364 3365 /* skip legacy IO region */ 3366 if ((a > IOM_BEGIN && a < IOM_END) || 3367 (e > IOM_BEGIN && e < IOM_END)) { 3368 #ifdef DEBUG 3369 printf("-I"); 3370 #endif 3371 continue; 3372 } 3373 3374 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT)) 3375 /* XXX What should we do? */ 3376 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)" 3377 " FROM IOMEM EXTENT MAP!\n", a, e); 3378 3379 physmem += atop(e - a); 3380 dumpmem[i].start = atop(a); 3381 dumpmem[i].end = atop(e); 3382 i++; 3383 avail_end = max(avail_end, e); 3384 } 3385 3386 ndumpmem = i; 3387 avail_end -= round_page(MSGBUFSIZE); 3388 3389 #ifdef DEBUG 3390 printf(": %lx\n", avail_end); 3391 #endif 3392 if (physmem < atop(4 * 1024 * 1024)) { 3393 printf("\awarning: too little memory available;" 3394 "running in degraded mode\npress a key to confirm\n\n"); 3395 cnpollc(1); 3396 cngetc(); 3397 cnpollc(0); 3398 } 3399 3400 #ifdef DEBUG 3401 printf("physload: "); 3402 #endif 3403 kb = atop(KERNTEXTOFF - KERNBASE); 3404 if (kb > atop(IOM_END)) { 3405 paddr_t lim = atop(IOM_END); 3406 #ifdef DEBUG 3407 printf(" %lx-%x (<16M)", lim, kb); 3408 #endif 3409 uvm_page_physload(lim, kb, lim, kb, 0); 3410 } 3411 3412 for (i = 0; i < ndumpmem; i++) { 3413 paddr_t a, e; 3414 3415 a = dumpmem[i].start; 3416 e = dumpmem[i].end; 3417 if (a < atop(first_avail) && e > atop(first_avail)) 3418 a = atop(first_avail); 3419 if (e > atop(avail_end)) 3420 e = atop(avail_end); 3421 3422 if (a < e) { 3423 #ifdef DEBUG 3424 printf(" %lx-%lx", a, e); 3425 #endif 3426 uvm_page_physload(a, e, a, e, 0); 3427 } 3428 } 3429 #ifdef DEBUG 3430 printf("\n"); 3431 #endif 3432 3433 tlbflush(); 3434 #if 0 3435 #if NISADMA > 0 3436 /* 3437 * Some motherboards/BIOSes remap the 384K of RAM that would 3438 * normally be covered by the ISA hole to the end of memory 3439 * so that it can be used. However, on a 16M system, this 3440 * would cause bounce buffers to be allocated and used. 3441 * This is not desirable behaviour, as more than 384K of 3442 * bounce buffers might be allocated. As a work-around, 3443 * we round memory down to the nearest 1M boundary if 3444 * we're using any isadma devices and the remapped memory 3445 * is what puts us over 16M. 3446 */ 3447 if (extmem > (15*1024) && extmem < (16*1024)) { 3448 printf("Warning: ignoring %dk of remapped memory\n", 3449 extmem - (15*1024)); 3450 extmem = (15*1024); 3451 } 3452 #endif 3453 #endif 3454 3455 #ifdef DDB 3456 db_machine_init(); 3457 ddb_init(); 3458 if (boothowto & RB_KDB) 3459 db_enter(); 3460 #endif 3461 3462 softintr_init(); 3463 } 3464 3465 /* 3466 * consinit: 3467 * initialize the system console. 3468 */ 3469 void 3470 consinit(void) 3471 { 3472 /* Already done in init386(). */ 3473 } 3474 3475 void 3476 cpu_reset(void) 3477 { 3478 struct region_descriptor region; 3479 3480 intr_disable(); 3481 3482 if (cpuresetfn) 3483 (*cpuresetfn)(); 3484 3485 /* 3486 * The keyboard controller has 4 random output pins, one of which is 3487 * connected to the RESET pin on the CPU in many PCs. We tell the 3488 * keyboard controller to pulse this line a couple of times. 3489 */ 3490 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3491 delay(100000); 3492 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3493 delay(100000); 3494 3495 /* 3496 * Try to cause a triple fault and watchdog reset by setting the 3497 * IDT to point to nothing. 3498 */ 3499 bzero((caddr_t)idt, sizeof(idt_region)); 3500 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3501 lidt(®ion); 3502 __asm volatile("divl %0,%1" : : "q" (0), "a" (0)); 3503 3504 /* 3505 * Try to cause a triple fault and watchdog reset by unmapping the 3506 * entire address space. 3507 */ 3508 bzero((caddr_t)PTD, NBPG); 3509 tlbflush(); 3510 3511 for (;;) 3512 continue; 3513 /* NOTREACHED */ 3514 } 3515 3516 void 3517 cpu_initclocks(void) 3518 { 3519 (*initclock_func)(); /* lapic or i8254 */ 3520 } 3521 3522 void 3523 need_resched(struct cpu_info *ci) 3524 { 3525 ci->ci_want_resched = 1; 3526 3527 /* There's a risk we'll be called before the idle threads start */ 3528 if (ci->ci_curproc) { 3529 aston(ci->ci_curproc); 3530 cpu_kick(ci); 3531 } 3532 } 3533 3534 /* Allocate an IDT vector slot within the given range. 3535 * XXX needs locking to avoid MP allocation races. 3536 */ 3537 3538 int 3539 idt_vec_alloc(int low, int high) 3540 { 3541 int vec; 3542 3543 for (vec = low; vec <= high; vec++) 3544 if (idt[vec].gd_p == 0) 3545 return (vec); 3546 return (0); 3547 } 3548 3549 void 3550 idt_vec_set(int vec, void (*function)(void)) 3551 { 3552 setgate(&idt[vec], function, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL); 3553 } 3554 3555 void 3556 idt_vec_free(int vec) 3557 { 3558 unsetgate(&idt[vec]); 3559 } 3560 3561 const struct sysctl_bounded_args cpuctl_vars[] = { 3562 { CPU_LIDACTION, &lid_action, 0, 2 }, 3563 { CPU_CPUID, &cpu_id, SYSCTL_INT_READONLY }, 3564 { CPU_OSFXSR, &i386_use_fxsave, SYSCTL_INT_READONLY }, 3565 { CPU_SSE, &i386_has_sse, SYSCTL_INT_READONLY }, 3566 { CPU_SSE2, &i386_has_sse2, SYSCTL_INT_READONLY }, 3567 { CPU_XCRYPT, &i386_has_xcrypt, SYSCTL_INT_READONLY }, 3568 }; 3569 3570 /* 3571 * machine dependent system variables. 3572 */ 3573 int 3574 cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 3575 size_t newlen, struct proc *p) 3576 { 3577 dev_t dev; 3578 3579 switch (name[0]) { 3580 case CPU_CONSDEV: 3581 if (namelen != 1) 3582 return (ENOTDIR); /* overloaded */ 3583 3584 if (cn_tab != NULL) 3585 dev = cn_tab->cn_dev; 3586 else 3587 dev = NODEV; 3588 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3589 #if NBIOS > 0 3590 case CPU_BIOS: 3591 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp, 3592 newp, newlen, p); 3593 #endif 3594 case CPU_BLK2CHR: 3595 if (namelen != 2) 3596 return (ENOTDIR); /* overloaded */ 3597 dev = blktochr((dev_t)name[1]); 3598 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3599 case CPU_CHR2BLK: 3600 if (namelen != 2) 3601 return (ENOTDIR); /* overloaded */ 3602 dev = chrtoblk((dev_t)name[1]); 3603 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3604 case CPU_ALLOWAPERTURE: 3605 #ifdef APERTURE 3606 if (securelevel > 0) 3607 return (sysctl_int_lower(oldp, oldlenp, newp, newlen, 3608 &allowaperture)); 3609 else 3610 return (sysctl_int(oldp, oldlenp, newp, newlen, 3611 &allowaperture)); 3612 #else 3613 return (sysctl_rdint(oldp, oldlenp, newp, 0)); 3614 #endif 3615 case CPU_CPUVENDOR: 3616 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor)); 3617 case CPU_CPUFEATURE: 3618 return (sysctl_rdint(oldp, oldlenp, newp, curcpu()->ci_feature_flags)); 3619 case CPU_KBDRESET: 3620 if (securelevel > 0) 3621 return (sysctl_rdint(oldp, oldlenp, newp, 3622 kbd_reset)); 3623 else 3624 return (sysctl_int(oldp, oldlenp, newp, newlen, 3625 &kbd_reset)); 3626 #if NPCKBC > 0 && NUKBD > 0 3627 case CPU_FORCEUKBD: 3628 { 3629 int error; 3630 3631 if (forceukbd) 3632 return (sysctl_rdint(oldp, oldlenp, newp, forceukbd)); 3633 3634 error = sysctl_int(oldp, oldlenp, newp, newlen, &forceukbd); 3635 if (forceukbd) 3636 pckbc_release_console(); 3637 return (error); 3638 } 3639 #endif 3640 default: 3641 return (sysctl_bounded_arr(cpuctl_vars, nitems(cpuctl_vars), 3642 name, namelen, oldp, oldlenp, newp, newlen)); 3643 } 3644 /* NOTREACHED */ 3645 } 3646 3647 int 3648 bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, 3649 bus_space_handle_t *bshp) 3650 { 3651 int error; 3652 struct extent *ex; 3653 3654 /* 3655 * Pick the appropriate extent map. 3656 */ 3657 if (t == I386_BUS_SPACE_IO) { 3658 ex = ioport_ex; 3659 if (flags & BUS_SPACE_MAP_LINEAR) 3660 return (EINVAL); 3661 } else if (t == I386_BUS_SPACE_MEM) { 3662 ex = iomem_ex; 3663 } else { 3664 panic("bus_space_map: bad bus space tag"); 3665 } 3666 3667 /* 3668 * Before we go any further, let's make sure that this 3669 * region is available. 3670 */ 3671 error = extent_alloc_region(ex, bpa, size, 3672 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0)); 3673 if (error) 3674 return (error); 3675 3676 /* 3677 * For I/O space, that's all she wrote. 3678 */ 3679 if (t == I386_BUS_SPACE_IO) { 3680 *bshp = bpa; 3681 return (0); 3682 } 3683 3684 if (IOM_BEGIN <= bpa && bpa <= IOM_END) { 3685 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa); 3686 return (0); 3687 } 3688 3689 /* 3690 * For memory space, map the bus physical address to 3691 * a kernel virtual address. 3692 */ 3693 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3694 if (error) { 3695 if (extent_free(ex, bpa, size, EX_NOWAIT | 3696 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3697 printf("bus_space_map: pa 0x%lx, size 0x%lx\n", 3698 bpa, size); 3699 printf("bus_space_map: can't free region\n"); 3700 } 3701 } 3702 3703 return (error); 3704 } 3705 3706 int 3707 _bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, 3708 int flags, bus_space_handle_t *bshp) 3709 { 3710 /* 3711 * For I/O space, that's all she wrote. 3712 */ 3713 if (t == I386_BUS_SPACE_IO) { 3714 *bshp = bpa; 3715 return (0); 3716 } 3717 3718 /* 3719 * For memory space, map the bus physical address to 3720 * a kernel virtual address. 3721 */ 3722 return (bus_mem_add_mapping(bpa, size, flags, bshp)); 3723 } 3724 3725 int 3726 bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, 3727 bus_size_t size, bus_size_t alignment, bus_size_t boundary, 3728 int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) 3729 { 3730 struct extent *ex; 3731 u_long bpa; 3732 int error; 3733 3734 /* 3735 * Pick the appropriate extent map. 3736 */ 3737 if (t == I386_BUS_SPACE_IO) { 3738 ex = ioport_ex; 3739 } else if (t == I386_BUS_SPACE_MEM) { 3740 ex = iomem_ex; 3741 } else { 3742 panic("bus_space_alloc: bad bus space tag"); 3743 } 3744 3745 /* 3746 * Sanity check the allocation against the extent's boundaries. 3747 */ 3748 if (rstart < ex->ex_start || rend > ex->ex_end) 3749 panic("bus_space_alloc: bad region start/end"); 3750 3751 /* 3752 * Do the requested allocation. 3753 */ 3754 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0, 3755 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0), 3756 &bpa); 3757 3758 if (error) 3759 return (error); 3760 3761 /* 3762 * For I/O space, that's all she wrote. 3763 */ 3764 if (t == I386_BUS_SPACE_IO) { 3765 *bshp = *bpap = bpa; 3766 return (0); 3767 } 3768 3769 /* 3770 * For memory space, map the bus physical address to 3771 * a kernel virtual address. 3772 */ 3773 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3774 if (error) { 3775 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT | 3776 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3777 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n", 3778 bpa, size); 3779 printf("bus_space_alloc: can't free region\n"); 3780 } 3781 } 3782 3783 *bpap = bpa; 3784 3785 return (error); 3786 } 3787 3788 int 3789 bus_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int flags, 3790 bus_space_handle_t *bshp) 3791 { 3792 paddr_t pa, endpa; 3793 vaddr_t va; 3794 bus_size_t map_size; 3795 int pmap_flags = PMAP_NOCACHE; 3796 3797 pa = trunc_page(bpa); 3798 endpa = round_page(bpa + size); 3799 3800 #ifdef DIAGNOSTIC 3801 if (endpa <= pa && endpa != 0) 3802 panic("bus_mem_add_mapping: overflow"); 3803 #endif 3804 3805 map_size = endpa - pa; 3806 3807 va = (vaddr_t)km_alloc(map_size, &kv_any, &kp_none, &kd_nowait); 3808 if (va == 0) 3809 return (ENOMEM); 3810 3811 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 3812 3813 if (flags & BUS_SPACE_MAP_CACHEABLE) 3814 pmap_flags = 0; 3815 else if (flags & BUS_SPACE_MAP_PREFETCHABLE) 3816 pmap_flags = PMAP_WC; 3817 3818 for (; map_size > 0; 3819 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE) 3820 pmap_kenter_pa(va, pa | pmap_flags, 3821 PROT_READ | PROT_WRITE); 3822 pmap_update(pmap_kernel()); 3823 3824 return 0; 3825 } 3826 3827 void 3828 bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3829 { 3830 struct extent *ex; 3831 u_long va, endva; 3832 bus_addr_t bpa; 3833 3834 /* 3835 * Find the correct extent and bus physical address. 3836 */ 3837 if (t == I386_BUS_SPACE_IO) { 3838 ex = ioport_ex; 3839 bpa = bsh; 3840 } else if (t == I386_BUS_SPACE_MEM) { 3841 ex = iomem_ex; 3842 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3843 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3844 goto ok; 3845 3846 va = trunc_page(bsh); 3847 endva = round_page(bsh + size); 3848 3849 #ifdef DIAGNOSTIC 3850 if (endva <= va) 3851 panic("bus_space_unmap: overflow"); 3852 #endif 3853 3854 (void) pmap_extract(pmap_kernel(), va, &bpa); 3855 bpa += (bsh & PGOFSET); 3856 3857 pmap_kremove(va, endva - va); 3858 pmap_update(pmap_kernel()); 3859 3860 /* 3861 * Free the kernel virtual mapping. 3862 */ 3863 km_free((void *)va, endva - va, &kv_any, &kp_none); 3864 } else 3865 panic("bus_space_unmap: bad bus space tag"); 3866 3867 ok: 3868 if (extent_free(ex, bpa, size, 3869 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3870 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n", 3871 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size); 3872 printf("bus_space_unmap: can't free region\n"); 3873 } 3874 } 3875 3876 void 3877 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size, 3878 bus_addr_t *adrp) 3879 { 3880 u_long va, endva; 3881 bus_addr_t bpa; 3882 3883 /* 3884 * Find the correct bus physical address. 3885 */ 3886 if (t == I386_BUS_SPACE_IO) { 3887 bpa = bsh; 3888 } else if (t == I386_BUS_SPACE_MEM) { 3889 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3890 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3891 goto ok; 3892 3893 va = trunc_page(bsh); 3894 endva = round_page(bsh + size); 3895 3896 #ifdef DIAGNOSTIC 3897 if (endva <= va) 3898 panic("_bus_space_unmap: overflow"); 3899 #endif 3900 3901 (void) pmap_extract(pmap_kernel(), va, &bpa); 3902 bpa += (bsh & PGOFSET); 3903 3904 pmap_kremove(va, endva - va); 3905 pmap_update(pmap_kernel()); 3906 3907 /* 3908 * Free the kernel virtual mapping. 3909 */ 3910 km_free((void *)va, endva - va, &kv_any, &kp_none); 3911 } else 3912 panic("bus_space_unmap: bad bus space tag"); 3913 3914 ok: 3915 if (adrp != NULL) 3916 *adrp = bpa; 3917 } 3918 3919 void 3920 bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3921 { 3922 3923 /* bus_space_unmap() does all that we need to do. */ 3924 bus_space_unmap(t, bsh, size); 3925 } 3926 3927 int 3928 bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 3929 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 3930 { 3931 *nbshp = bsh + offset; 3932 return (0); 3933 } 3934 3935 paddr_t 3936 bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags) 3937 { 3938 /* Can't mmap I/O space. */ 3939 if (t == I386_BUS_SPACE_IO) 3940 return (-1); 3941 3942 return (addr + off); 3943 } 3944 3945 #ifdef DIAGNOSTIC 3946 void 3947 splassert_check(int wantipl, const char *func) 3948 { 3949 if (lapic_tpr < wantipl) 3950 splassert_fail(wantipl, lapic_tpr, func); 3951 if (wantipl == IPL_NONE && curcpu()->ci_idepth != 0) 3952 splassert_fail(-1, curcpu()->ci_idepth, func); 3953 } 3954 #endif 3955 3956 int 3957 copyin32(const uint32_t *uaddr, uint32_t *kaddr) 3958 { 3959 if ((vaddr_t)uaddr & 0x3) 3960 return EFAULT; 3961 3962 /* copyin(9) is atomic */ 3963 return copyin(uaddr, kaddr, sizeof(uint32_t)); 3964 } 3965 3966 /* 3967 * True if the system has any non-level interrupts which are shared 3968 * on the same pin. 3969 */ 3970 int intr_shared_edge; 3971 3972 /* 3973 * Software interrupt registration 3974 * 3975 * We hand-code this to ensure that it's atomic. 3976 */ 3977 void 3978 softintr(int sir) 3979 { 3980 struct cpu_info *ci = curcpu(); 3981 3982 __asm volatile("orl %1, %0" : 3983 "=m" (ci->ci_ipending) : "ir" (1 << sir)); 3984 } 3985 3986 /* 3987 * Raise current interrupt priority level, and return the old one. 3988 */ 3989 int 3990 splraise(int ncpl) 3991 { 3992 int ocpl; 3993 3994 KASSERT(ncpl >= IPL_NONE); 3995 3996 _SPLRAISE(ocpl, ncpl); 3997 return (ocpl); 3998 } 3999 4000 /* 4001 * Restore an old interrupt priority level. If any thereby unmasked 4002 * interrupts are pending, call Xspllower() to process them. 4003 */ 4004 void 4005 splx(int ncpl) 4006 { 4007 _SPLX(ncpl); 4008 } 4009 4010 /* 4011 * Same as splx(), but we return the old value of spl, for the 4012 * benefit of some splsoftclock() callers. 4013 */ 4014 int 4015 spllower(int ncpl) 4016 { 4017 int ocpl = lapic_tpr; 4018 4019 splx(ncpl); 4020 return (ocpl); 4021 } 4022 4023 int 4024 intr_handler(struct intrframe *frame, struct intrhand *ih) 4025 { 4026 int rc; 4027 #ifdef MULTIPROCESSOR 4028 int need_lock; 4029 4030 if (ih->ih_flags & IPL_MPSAFE) 4031 need_lock = 0; 4032 else 4033 need_lock = 1; 4034 4035 if (need_lock) 4036 __mp_lock(&kernel_lock); 4037 #endif 4038 rc = (*ih->ih_fun)(ih->ih_arg ? ih->ih_arg : frame); 4039 #ifdef MULTIPROCESSOR 4040 if (need_lock) 4041 __mp_unlock(&kernel_lock); 4042 #endif 4043 return rc; 4044 } 4045 4046 void 4047 intr_barrier(void *ih) 4048 { 4049 sched_barrier(NULL); 4050 } 4051 4052 unsigned int 4053 cpu_rnd_messybits(void) 4054 { 4055 struct timespec ts; 4056 4057 nanotime(&ts); 4058 return (ts.tv_nsec ^ (ts.tv_sec << 20)); 4059 } 4060