1 /* $OpenBSD: machdep.c,v 1.662 2023/01/11 02:49:34 cheloha Exp $ */ 2 /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 1993, 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 36 * Copyright (c) 1992 Terrence R. Lambert. 37 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 38 * All rights reserved. 39 * 40 * This code is derived from software contributed to Berkeley by 41 * William Jolitz. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 68 */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/signalvar.h> 73 #include <sys/kernel.h> 74 #include <sys/proc.h> 75 #include <sys/user.h> 76 #include <sys/exec.h> 77 #include <sys/buf.h> 78 #include <sys/reboot.h> 79 #include <sys/conf.h> 80 #include <sys/timeout.h> 81 #include <sys/malloc.h> 82 #include <sys/mbuf.h> 83 #include <sys/msgbuf.h> 84 #include <sys/mount.h> 85 #include <sys/vnode.h> 86 #include <sys/device.h> 87 #include <sys/extent.h> 88 #include <sys/sysctl.h> 89 #include <sys/syscallargs.h> 90 #include <sys/core.h> 91 #include <sys/kcore.h> 92 #include <sys/sensors.h> 93 94 #include <dev/cons.h> 95 #include <stand/boot/bootarg.h> 96 97 #include <net/if.h> 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <machine/cpu.h> 103 #include <machine/cpu_full.h> 104 #include <machine/cpufunc.h> 105 #include <machine/cpuvar.h> 106 #include <machine/gdt.h> 107 #include <machine/kcore.h> 108 #include <machine/pio.h> 109 #include <machine/psl.h> 110 #include <machine/reg.h> 111 #include <machine/specialreg.h> 112 #include <machine/biosvar.h> 113 #include <machine/pte.h> 114 #ifdef MULTIPROCESSOR 115 #include <machine/mpbiosvar.h> 116 #endif /* MULTIPROCESSOR */ 117 118 #include <dev/isa/isareg.h> 119 #include <dev/isa/isavar.h> 120 #include <dev/ic/i8042reg.h> 121 #include <dev/ic/mc146818reg.h> 122 #include <i386/isa/isa_machdep.h> 123 #include <i386/isa/nvram.h> 124 125 #include "acpi.h" 126 #if NACPI > 0 127 #include <dev/acpi/acpivar.h> 128 #endif 129 130 #include "apm.h" 131 #if NAPM > 0 132 #include <machine/apmvar.h> 133 #endif 134 135 #ifdef DDB 136 #include <machine/db_machdep.h> 137 #include <ddb/db_access.h> 138 #include <ddb/db_sym.h> 139 #include <ddb/db_extern.h> 140 #endif 141 142 #include "isa.h" 143 #include "isadma.h" 144 #include "npx.h" 145 #if NNPX > 0 146 extern struct proc *npxproc; 147 #endif 148 149 #include "bios.h" 150 #include "com.h" 151 152 #if NCOM > 0 153 #include <sys/termios.h> 154 #include <dev/ic/comreg.h> 155 #include <dev/ic/comvar.h> 156 #endif /* NCOM > 0 */ 157 158 #ifdef HIBERNATE 159 #include <machine/hibernate_var.h> 160 #endif /* HIBERNATE */ 161 162 #include "ukbd.h" 163 #include "pckbc.h" 164 #if NPCKBC > 0 && NUKBD > 0 165 #include <dev/ic/pckbcvar.h> 166 #endif 167 168 /* #define MACHDEP_DEBUG */ 169 170 #ifdef MACHDEP_DEBUG 171 #define DPRINTF(x...) do { printf(x); } while (0) 172 #else 173 #define DPRINTF(x...) 174 #endif /* MACHDEP_DEBUG */ 175 176 void replacesmap(void); 177 int intr_handler(struct intrframe *, struct intrhand *); 178 179 /* the following is used externally (sysctl_hw) */ 180 char machine[] = MACHINE; 181 182 /* 183 * switchto vectors 184 */ 185 void (*cpu_idle_leave_fcn)(void) = NULL; 186 void (*cpu_idle_cycle_fcn)(void) = NULL; 187 void (*cpu_idle_enter_fcn)(void) = NULL; 188 189 190 struct uvm_constraint_range isa_constraint = { 0x0, 0x00ffffffUL }; 191 struct uvm_constraint_range dma_constraint = { 0x0, 0xffffffffUL }; 192 struct uvm_constraint_range *uvm_md_constraints[] = { 193 &isa_constraint, 194 &dma_constraint, 195 NULL 196 }; 197 198 extern int boothowto; 199 int physmem; 200 201 struct dumpmem dumpmem[VM_PHYSSEG_MAX]; 202 u_int ndumpmem; 203 204 /* 205 * These variables are needed by /sbin/savecore 206 */ 207 u_long dumpmag = 0x8fca0101; /* magic number */ 208 int dumpsize = 0; /* pages */ 209 long dumplo = 0; /* blocks */ 210 211 int cpu_class; 212 int i386_fpu_present; 213 int i386_fpu_exception; 214 int i386_fpu_fdivbug; 215 216 int i386_use_fxsave; 217 int i386_has_sse; 218 int i386_has_sse2; 219 int i386_has_xcrypt; 220 221 bootarg_t *bootargp; 222 paddr_t avail_end; 223 224 struct vm_map *exec_map = NULL; 225 struct vm_map *phys_map = NULL; 226 227 #if !defined(SMALL_KERNEL) 228 int p4_model; 229 int p3_early; 230 void (*update_cpuspeed)(void) = NULL; 231 void via_update_sensor(void *args); 232 #endif 233 int kbd_reset; 234 int lid_action = 1; 235 int pwr_action = 1; 236 int forceukbd; 237 238 /* 239 * safepri is a safe priority for sleep to set for a spin-wait 240 * during autoconfiguration or after a panic. 241 */ 242 int safepri = 0; 243 244 #if !defined(SMALL_KERNEL) 245 int bus_clock; 246 #endif 247 void (*setperf_setup)(struct cpu_info *); 248 int setperf_prio = 0; /* for concurrent handlers */ 249 250 void (*cpusensors_setup)(struct cpu_info *); 251 252 void (*delay_func)(int) = i8254_delay; 253 void (*initclock_func)(void) = i8254_initclocks; 254 255 /* 256 * Extent maps to manage I/O and ISA memory hole space. Allocate 257 * storage for 16 regions in each, initially. Later, ioport_malloc_safe 258 * will indicate that it's safe to use malloc() to dynamically allocate 259 * region descriptors. 260 * 261 * N.B. At least two regions are _always_ allocated from the iomem 262 * extent map; (0 -> ISA hole) and (end of ISA hole -> end of RAM). 263 * 264 * The extent maps are not static! Machine-dependent ISA and EISA 265 * routines need access to them for bus address space allocation. 266 */ 267 static long ioport_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 268 static long iomem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 269 struct extent *ioport_ex; 270 struct extent *iomem_ex; 271 static int ioport_malloc_safe; 272 273 void dumpsys(void); 274 int cpu_dump(void); 275 void init386(paddr_t); 276 void consinit(void); 277 void (*cpuresetfn)(void); 278 279 int bus_mem_add_mapping(bus_addr_t, bus_size_t, 280 int, bus_space_handle_t *); 281 282 #ifdef APERTURE 283 int allowaperture = 0; 284 #endif 285 286 int has_rdrand; 287 int has_rdseed; 288 289 #include "pvbus.h" 290 #if NPVBUS > 0 291 #include <dev/pv/pvvar.h> 292 #endif 293 294 void winchip_cpu_setup(struct cpu_info *); 295 void amd_family5_setperf_setup(struct cpu_info *); 296 void amd_family5_setup(struct cpu_info *); 297 void amd_family6_setperf_setup(struct cpu_info *); 298 void amd_family6_setup(struct cpu_info *); 299 void cyrix3_setperf_setup(struct cpu_info *); 300 void cyrix3_cpu_setup(struct cpu_info *); 301 void cyrix6x86_cpu_setup(struct cpu_info *); 302 void natsem6x86_cpu_setup(struct cpu_info *); 303 void intel586_cpu_setup(struct cpu_info *); 304 void intel686_cpusensors_setup(struct cpu_info *); 305 void intel686_setperf_setup(struct cpu_info *); 306 void intel686_common_cpu_setup(struct cpu_info *); 307 void intel686_cpu_setup(struct cpu_info *); 308 void intel686_p4_cpu_setup(struct cpu_info *); 309 void intelcore_update_sensor(void *); 310 void tm86_cpu_setup(struct cpu_info *); 311 char * intel686_cpu_name(int); 312 char * cyrix3_cpu_name(int, int); 313 char * tm86_cpu_name(int); 314 void cyrix3_get_bus_clock(struct cpu_info *); 315 void p4_get_bus_clock(struct cpu_info *); 316 void p3_get_bus_clock(struct cpu_info *); 317 void p4_update_cpuspeed(void); 318 void p3_update_cpuspeed(void); 319 int pentium_cpuspeed(int *); 320 void enter_shared_special_pages(void); 321 322 static __inline u_char 323 cyrix_read_reg(u_char reg) 324 { 325 outb(0x22, reg); 326 return inb(0x23); 327 } 328 329 static __inline void 330 cyrix_write_reg(u_char reg, u_char data) 331 { 332 outb(0x22, reg); 333 outb(0x23, data); 334 } 335 336 /* 337 * cpuid instruction. request in eax, result in eax, ebx, ecx, edx. 338 * requires caller to provide u_int32_t regs[4] array. 339 */ 340 void 341 cpuid(u_int32_t ax, u_int32_t *regs) 342 { 343 __asm volatile( 344 "cpuid\n\t" 345 "movl %%eax, 0(%2)\n\t" 346 "movl %%ebx, 4(%2)\n\t" 347 "movl %%ecx, 8(%2)\n\t" 348 "movl %%edx, 12(%2)\n\t" 349 :"=a" (ax) 350 :"0" (ax), "S" (regs) 351 :"bx", "cx", "dx"); 352 } 353 354 /* 355 * Machine-dependent startup code 356 */ 357 void 358 cpu_startup(void) 359 { 360 unsigned i; 361 vaddr_t minaddr, maxaddr, va; 362 paddr_t pa; 363 364 /* 365 * Initialize error message buffer (at end of core). 366 * (space reserved in pmap_bootstrap) 367 */ 368 pa = avail_end; 369 va = (vaddr_t)msgbufp; 370 for (i = 0; i < atop(MSGBUFSIZE); i++) { 371 pmap_kenter_pa(va, pa, PROT_READ | PROT_WRITE); 372 va += PAGE_SIZE; 373 pa += PAGE_SIZE; 374 } 375 pmap_update(pmap_kernel()); 376 initmsgbuf((caddr_t)msgbufp, round_page(MSGBUFSIZE)); 377 378 printf("%s", version); 379 startclocks(); 380 rtcinit(); 381 382 printf("real mem = %llu (%lluMB)\n", 383 (unsigned long long)ptoa((psize_t)physmem), 384 (unsigned long long)ptoa((psize_t)physmem)/1024U/1024U); 385 386 /* 387 * Allocate a submap for exec arguments. This map effectively 388 * limits the number of processes exec'ing at any time. 389 */ 390 minaddr = vm_map_min(kernel_map); 391 exec_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 392 16*NCARGS, VM_MAP_PAGEABLE, FALSE, NULL); 393 394 /* 395 * Allocate a submap for physio 396 */ 397 phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr, 398 VM_PHYS_SIZE, 0, FALSE, NULL); 399 400 printf("avail mem = %llu (%lluMB)\n", 401 (unsigned long long)ptoa((psize_t)uvmexp.free), 402 (unsigned long long)ptoa((psize_t)uvmexp.free)/1024U/1024U); 403 404 /* 405 * Set up buffers, so they can be used to read disk labels. 406 */ 407 bufinit(); 408 409 /* 410 * Configure the system. 411 */ 412 if (boothowto & RB_CONFIG) { 413 #ifdef BOOT_CONFIG 414 user_config(); 415 #else 416 printf("kernel does not support -c; continuing..\n"); 417 #endif 418 } 419 ioport_malloc_safe = 1; 420 421 #ifndef SMALL_KERNEL 422 cpu_ucode_setup(); 423 #endif 424 425 /* enter the IDT and trampoline code in the u-k maps */ 426 enter_shared_special_pages(); 427 428 /* initialize CPU0's TSS and GDT and put them in the u-k maps */ 429 cpu_enter_pages(&cpu_info_full_primary); 430 } 431 432 void 433 enter_shared_special_pages(void) 434 { 435 extern char __kutext_start[], __kutext_end[], __kernel_kutext_phys[]; 436 extern char __kudata_start[], __kudata_end[], __kernel_kudata_phys[]; 437 vaddr_t va; 438 paddr_t pa; 439 440 /* idt */ 441 pmap_extract(pmap_kernel(), (vaddr_t)idt, &pa); 442 pmap_enter_special((vaddr_t)idt, pa, PROT_READ, 0); 443 444 /* .kutext section */ 445 va = (vaddr_t)__kutext_start; 446 pa = (paddr_t)__kernel_kutext_phys; 447 while (va < (vaddr_t)__kutext_end) { 448 pmap_enter_special(va, pa, PROT_READ | PROT_EXEC, 0); 449 DPRINTF("%s: entered kutext page va 0x%08lx pa 0x%08lx\n", 450 __func__, (unsigned long)va, (unsigned long)pa); 451 va += PAGE_SIZE; 452 pa += PAGE_SIZE; 453 } 454 455 /* .kudata section */ 456 va = (vaddr_t)__kudata_start; 457 pa = (paddr_t)__kernel_kudata_phys; 458 while (va < (vaddr_t)__kudata_end) { 459 pmap_enter_special(va, pa, PROT_READ | PROT_WRITE, 0); 460 DPRINTF("%s: entered kudata page va 0x%08lx pa 0x%08lx\n", 461 __func__, (unsigned long)va, (unsigned long)pa); 462 va += PAGE_SIZE; 463 pa += PAGE_SIZE; 464 } 465 } 466 467 /* 468 * Set up proc0's TSS 469 */ 470 void 471 i386_proc0_tss_init(void) 472 { 473 struct pcb *pcb; 474 475 curpcb = pcb = &proc0.p_addr->u_pcb; 476 pcb->pcb_cr0 = rcr0(); 477 pcb->pcb_kstack = (int)proc0.p_addr + USPACE - 16; 478 proc0.p_md.md_regs = (struct trapframe *)pcb->pcb_kstack - 1; 479 } 480 481 #ifdef MULTIPROCESSOR 482 void 483 i386_init_pcb_tss(struct cpu_info *ci) 484 { 485 struct pcb *pcb = ci->ci_idle_pcb; 486 487 pcb->pcb_cr0 = rcr0(); 488 } 489 #endif /* MULTIPROCESSOR */ 490 491 /* 492 * Info for CTL_HW 493 */ 494 char cpu_model[120]; 495 496 const char *classnames[] = { 497 "", 498 "486", 499 "586", 500 "686" 501 }; 502 503 const char *modifiers[] = { 504 "", 505 "OverDrive ", 506 "Dual ", 507 "" 508 }; 509 510 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = { 511 { 512 "GenuineIntel", 513 CPUVENDOR_INTEL, 514 "Intel", 515 /* Family 4 */ 516 { { 517 CPUCLASS_486, 518 { 519 "486DX", "486DX", "486SX", "486DX2", "486SL", 520 "486SX2", 0, "486DX2 W/B", 521 "486DX4", 0, 0, 0, 0, 0, 0, 0, 522 "486" /* Default */ 523 }, 524 NULL 525 }, 526 /* Family 5 */ 527 { 528 CPUCLASS_586, 529 { 530 "Pentium (A-step)", "Pentium (P5)", 531 "Pentium (P54C)", "Pentium (P24T)", 532 "Pentium/MMX", "Pentium", 0, 533 "Pentium (P54C)", "Pentium/MMX", 534 0, 0, 0, 0, 0, 0, 0, 535 "Pentium" /* Default */ 536 }, 537 intel586_cpu_setup 538 }, 539 /* Family 6 */ 540 { 541 CPUCLASS_686, 542 { 543 "Pentium Pro", "Pentium Pro", 0, 544 "Pentium II", "Pentium Pro", 545 "Pentium II/Celeron", 546 "Celeron", 547 "Pentium III", 548 "Pentium III", 549 "Pentium M", 550 "Pentium III Xeon", 551 "Pentium III", 0, 552 "Pentium M", 553 "Core Duo/Solo", 0, 554 "Pentium Pro, II or III" /* Default */ 555 }, 556 intel686_cpu_setup 557 }, 558 /* Family 7 */ 559 { 560 CPUCLASS_686, 561 } , 562 /* Family 8 */ 563 { 564 CPUCLASS_686, 565 } , 566 /* Family 9 */ 567 { 568 CPUCLASS_686, 569 } , 570 /* Family A */ 571 { 572 CPUCLASS_686, 573 } , 574 /* Family B */ 575 { 576 CPUCLASS_686, 577 } , 578 /* Family C */ 579 { 580 CPUCLASS_686, 581 } , 582 /* Family D */ 583 { 584 CPUCLASS_686, 585 } , 586 /* Family E */ 587 { 588 CPUCLASS_686, 589 } , 590 /* Family F */ 591 { 592 CPUCLASS_686, 593 { 594 "Pentium 4", 0, 0, 0, 595 0, 0, 0, 0, 596 0, 0, 0, 0, 597 0, 0, 0, 0, 598 "Pentium 4" /* Default */ 599 }, 600 intel686_p4_cpu_setup 601 } } 602 }, 603 { 604 "AuthenticAMD", 605 CPUVENDOR_AMD, 606 "AMD", 607 /* Family 4 */ 608 { { 609 CPUCLASS_486, 610 { 611 0, 0, 0, "Am486DX2 W/T", 612 0, 0, 0, "Am486DX2 W/B", 613 "Am486DX4 W/T or Am5x86 W/T 150", 614 "Am486DX4 W/B or Am5x86 W/B 150", 0, 0, 615 0, 0, "Am5x86 W/T 133/160", 616 "Am5x86 W/B 133/160", 617 "Am486 or Am5x86" /* Default */ 618 }, 619 NULL 620 }, 621 /* Family 5 */ 622 { 623 CPUCLASS_586, 624 { 625 "K5", "K5", "K5", "K5", 0, 0, "K6", 626 "K6", "K6-2", "K6-III", 0, 0, 0, 627 "K6-2+/III+", 0, 0, 628 "K5 or K6" /* Default */ 629 }, 630 amd_family5_setup 631 }, 632 /* Family 6 */ 633 { 634 CPUCLASS_686, 635 { 636 0, "Athlon Model 1", "Athlon Model 2", 637 "Duron Model 3", 638 "Athlon Model 4", 639 0, "Athlon XP Model 6", 640 "Duron Model 7", 641 "Athlon XP Model 8", 642 0, "Athlon XP Model 10", 643 0, 0, 0, 0, 0, 644 "K7" /* Default */ 645 }, 646 amd_family6_setup 647 }, 648 /* Family 7 */ 649 { 650 CPUCLASS_686, 651 } , 652 /* Family 8 */ 653 { 654 CPUCLASS_686, 655 } , 656 /* Family 9 */ 657 { 658 CPUCLASS_686, 659 } , 660 /* Family A */ 661 { 662 CPUCLASS_686, 663 } , 664 /* Family B */ 665 { 666 CPUCLASS_686, 667 } , 668 /* Family C */ 669 { 670 CPUCLASS_686, 671 } , 672 /* Family D */ 673 { 674 CPUCLASS_686, 675 } , 676 /* Family E */ 677 { 678 CPUCLASS_686, 679 } , 680 /* Family F */ 681 { 682 CPUCLASS_686, 683 { 684 0, 0, 0, 0, "Athlon64", 685 "Opteron or Athlon64FX", 0, 0, 686 0, 0, 0, 0, 0, 0, 0, 0, 687 "AMD64" /* DEFAULT */ 688 }, 689 amd_family6_setup 690 } } 691 }, 692 { 693 "CyrixInstead", 694 CPUVENDOR_CYRIX, 695 "Cyrix", 696 /* Family 4 */ 697 { { 698 CPUCLASS_486, 699 { 700 0, 0, 0, "MediaGX", 0, 0, 0, 0, "5x86", 0, 0, 701 0, 0, 0, 0, 702 "486 class" /* Default */ 703 }, 704 NULL 705 }, 706 /* Family 5 */ 707 { 708 CPUCLASS_586, 709 { 710 0, 0, "6x86", 0, "GXm", 0, 0, 0, 0, 0, 711 0, 0, 0, 0, 0, 0, 712 "586 class" /* Default */ 713 }, 714 cyrix6x86_cpu_setup 715 }, 716 /* Family 6 */ 717 { 718 CPUCLASS_686, 719 { 720 "6x86MX", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 721 0, 0, 0, 0, 722 "686 class" /* Default */ 723 }, 724 NULL 725 } } 726 }, 727 { 728 "CentaurHauls", 729 CPUVENDOR_IDT, 730 "IDT", 731 /* Family 4, not available from IDT */ 732 { { 733 CPUCLASS_486, 734 { 735 0, 0, 0, 0, 0, 0, 0, 0, 736 0, 0, 0, 0, 0, 0, 0, 0, 737 "486 class" /* Default */ 738 }, 739 NULL 740 }, 741 /* Family 5 */ 742 { 743 CPUCLASS_586, 744 { 745 0, 0, 0, 0, "WinChip C6", 0, 0, 0, 746 "WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0, 747 "WinChip" /* Default */ 748 }, 749 winchip_cpu_setup 750 }, 751 /* Family 6 */ 752 { 753 CPUCLASS_686, 754 { 755 0, 0, 0, 0, 0, 0, 756 "C3 Samuel", 757 "C3 Samuel 2/Ezra", 758 "C3 Ezra-T", 759 "C3 Nehemiah", "C3 Esther", 0, 0, 0, 0, 0, 760 "C3" /* Default */ 761 }, 762 cyrix3_cpu_setup 763 } } 764 }, 765 { 766 "GenuineTMx86", 767 CPUVENDOR_TRANSMETA, 768 "Transmeta", 769 /* Family 4, not available from Transmeta */ 770 { { 771 CPUCLASS_486, 772 { 773 0, 0, 0, 0, 0, 0, 0, 0, 774 0, 0, 0, 0, 0, 0, 0, 0, 775 "486 class" /* Default */ 776 }, 777 NULL 778 }, 779 /* Family 5 */ 780 { 781 CPUCLASS_586, 782 { 783 0, 0, 0, 0, "TMS5x00", 0, 0, 784 0, 0, 0, 0, 0, 0, 0, 0, 0, 785 "TMS5x00" /* Default */ 786 }, 787 tm86_cpu_setup 788 }, 789 /* Family 6, not yet available from Transmeta */ 790 { 791 CPUCLASS_686, 792 { 793 0, 0, 0, 0, 0, 0, 0, 0, 794 0, 0, 0, 0, 0, 0, 0, 0, 795 "686 class" /* Default */ 796 }, 797 NULL 798 }, 799 /* Family 7 */ 800 { 801 CPUCLASS_686, 802 } , 803 /* Family 8 */ 804 { 805 CPUCLASS_686, 806 } , 807 /* Family 9 */ 808 { 809 CPUCLASS_686, 810 } , 811 /* Family A */ 812 { 813 CPUCLASS_686, 814 } , 815 /* Family B */ 816 { 817 CPUCLASS_686, 818 } , 819 /* Family C */ 820 { 821 CPUCLASS_686, 822 } , 823 /* Family D */ 824 { 825 CPUCLASS_686, 826 } , 827 /* Family E */ 828 { 829 CPUCLASS_686, 830 } , 831 /* Family F */ 832 { 833 /* Extended processor family - Transmeta Efficeon */ 834 CPUCLASS_686, 835 { 836 0, 0, "TM8000", "TM8000", 837 0, 0, 0, 0, 838 0, 0, 0, 0, 839 0, 0, 0, 0, 840 "TM8000" /* Default */ 841 }, 842 tm86_cpu_setup 843 } } 844 }, 845 { 846 "Geode by NSC", 847 CPUVENDOR_NS, 848 "National Semiconductor", 849 /* Family 4, not available from National Semiconductor */ 850 { { 851 CPUCLASS_486, 852 { 853 0, 0, 0, 0, 0, 0, 0, 0, 854 0, 0, 0, 0, 0, 0, 0, 0, 855 "486 class" /* Default */ 856 }, 857 NULL 858 }, 859 /* Family 5 */ 860 { 861 CPUCLASS_586, 862 { 863 0, 0, 0, 0, "Geode GX1", 0, 0, 0, 0, 0, 864 0, 0, 0, 0, 0, 0, 865 "586 class" /* Default */ 866 }, 867 natsem6x86_cpu_setup 868 } } 869 }, 870 { 871 "SiS SiS SiS ", 872 CPUVENDOR_SIS, 873 "SiS", 874 /* Family 4, not available from SiS */ 875 { { 876 CPUCLASS_486, 877 { 878 0, 0, 0, 0, 0, 0, 0, 0, 879 0, 0, 0, 0, 0, 0, 0, 0, 880 "486 class" /* Default */ 881 }, 882 NULL 883 }, 884 /* Family 5 */ 885 { 886 CPUCLASS_586, 887 { 888 "SiS55x", 0, 0, 0, 0, 0, 0, 0, 0, 0, 889 0, 0, 0, 0, 0, 0, 890 "586 class" /* Default */ 891 }, 892 NULL 893 } } 894 } 895 }; 896 897 const struct cpu_cpuid_feature i386_cpuid_features[] = { 898 { CPUID_FPU, "FPU" }, 899 { CPUID_VME, "V86" }, 900 { CPUID_DE, "DE" }, 901 { CPUID_PSE, "PSE" }, 902 { CPUID_TSC, "TSC" }, 903 { CPUID_MSR, "MSR" }, 904 { CPUID_PAE, "PAE" }, 905 { CPUID_MCE, "MCE" }, 906 { CPUID_CX8, "CX8" }, 907 { CPUID_APIC, "APIC" }, 908 { CPUID_SYS1, "SYS" }, 909 { CPUID_SEP, "SEP" }, 910 { CPUID_MTRR, "MTRR" }, 911 { CPUID_PGE, "PGE" }, 912 { CPUID_MCA, "MCA" }, 913 { CPUID_CMOV, "CMOV" }, 914 { CPUID_PAT, "PAT" }, 915 { CPUID_PSE36, "PSE36" }, 916 { CPUID_PSN, "PSN" }, 917 { CPUID_CFLUSH, "CFLUSH" }, 918 { CPUID_DS, "DS" }, 919 { CPUID_ACPI, "ACPI" }, 920 { CPUID_MMX, "MMX" }, 921 { CPUID_FXSR, "FXSR" }, 922 { CPUID_SSE, "SSE" }, 923 { CPUID_SSE2, "SSE2" }, 924 { CPUID_SS, "SS" }, 925 { CPUID_HTT, "HTT" }, 926 { CPUID_TM, "TM" }, 927 { CPUID_PBE, "PBE" } 928 }; 929 930 const struct cpu_cpuid_feature i386_ecpuid_features[] = { 931 { CPUID_MPC, "MPC" }, 932 { CPUID_NXE, "NXE" }, 933 { CPUID_MMXX, "MMXX" }, 934 { CPUID_FFXSR, "FFXSR" }, 935 { CPUID_PAGE1GB, "PAGE1GB" }, 936 { CPUID_RDTSCP, "RDTSCP" }, 937 { CPUID_LONG, "LONG" }, 938 { CPUID_3DNOW2, "3DNOW2" }, 939 { CPUID_3DNOW, "3DNOW" } 940 }; 941 942 const struct cpu_cpuid_feature i386_cpuid_ecxfeatures[] = { 943 { CPUIDECX_SSE3, "SSE3" }, 944 { CPUIDECX_PCLMUL, "PCLMUL" }, 945 { CPUIDECX_DTES64, "DTES64" }, 946 { CPUIDECX_MWAIT, "MWAIT" }, 947 { CPUIDECX_DSCPL, "DS-CPL" }, 948 { CPUIDECX_VMX, "VMX" }, 949 { CPUIDECX_SMX, "SMX" }, 950 { CPUIDECX_EST, "EST" }, 951 { CPUIDECX_TM2, "TM2" }, 952 { CPUIDECX_SSSE3, "SSSE3" }, 953 { CPUIDECX_CNXTID, "CNXT-ID" }, 954 { CPUIDECX_SDBG, "SDBG" }, 955 { CPUIDECX_FMA3, "FMA3" }, 956 { CPUIDECX_CX16, "CX16" }, 957 { CPUIDECX_XTPR, "xTPR" }, 958 { CPUIDECX_PDCM, "PDCM" }, 959 { CPUIDECX_PCID, "PCID" }, 960 { CPUIDECX_DCA, "DCA" }, 961 { CPUIDECX_SSE41, "SSE4.1" }, 962 { CPUIDECX_SSE42, "SSE4.2" }, 963 { CPUIDECX_X2APIC, "x2APIC" }, 964 { CPUIDECX_MOVBE, "MOVBE" }, 965 { CPUIDECX_POPCNT, "POPCNT" }, 966 { CPUIDECX_DEADLINE, "DEADLINE" }, 967 { CPUIDECX_AES, "AES" }, 968 { CPUIDECX_XSAVE, "XSAVE" }, 969 { CPUIDECX_OSXSAVE, "OSXSAVE" }, 970 { CPUIDECX_AVX, "AVX" }, 971 { CPUIDECX_F16C, "F16C" }, 972 { CPUIDECX_RDRAND, "RDRAND" }, 973 { CPUIDECX_HV, "HV" }, 974 }; 975 976 const struct cpu_cpuid_feature i386_ecpuid_ecxfeatures[] = { 977 { CPUIDECX_LAHF, "LAHF" }, 978 { CPUIDECX_CMPLEG, "CMPLEG" }, 979 { CPUIDECX_SVM, "SVM" }, 980 { CPUIDECX_EAPICSP, "EAPICSP" }, 981 { CPUIDECX_AMCR8, "AMCR8" }, 982 { CPUIDECX_ABM, "ABM" }, 983 { CPUIDECX_SSE4A, "SSE4A" }, 984 { CPUIDECX_MASSE, "MASSE" }, 985 { CPUIDECX_3DNOWP, "3DNOWP" }, 986 { CPUIDECX_OSVW, "OSVW" }, 987 { CPUIDECX_IBS, "IBS" }, 988 { CPUIDECX_XOP, "XOP" }, 989 { CPUIDECX_SKINIT, "SKINIT" }, 990 { CPUIDECX_WDT, "WDT" }, 991 { CPUIDECX_LWP, "LWP" }, 992 { CPUIDECX_FMA4, "FMA4" }, 993 { CPUIDECX_TCE, "TCE" }, 994 { CPUIDECX_NODEID, "NODEID" }, 995 { CPUIDECX_TBM, "TBM" }, 996 { CPUIDECX_TOPEXT, "TOPEXT" }, 997 { CPUIDECX_CPCTR, "CPCTR" }, 998 { CPUIDECX_DBKP, "DBKP" }, 999 { CPUIDECX_PERFTSC, "PERFTSC" }, 1000 { CPUIDECX_PCTRL3, "PCTRL3" }, 1001 { CPUIDECX_MWAITX, "MWAITX" }, 1002 }; 1003 1004 const struct cpu_cpuid_feature cpu_seff0_ebxfeatures[] = { 1005 { SEFF0EBX_FSGSBASE, "FSGSBASE" }, 1006 { SEFF0EBX_TSC_ADJUST, "TSC_ADJUST" }, 1007 { SEFF0EBX_SGX, "SGX" }, 1008 { SEFF0EBX_BMI1, "BMI1" }, 1009 { SEFF0EBX_HLE, "HLE" }, 1010 { SEFF0EBX_AVX2, "AVX2" }, 1011 { SEFF0EBX_SMEP, "SMEP" }, 1012 { SEFF0EBX_BMI2, "BMI2" }, 1013 { SEFF0EBX_ERMS, "ERMS" }, 1014 { SEFF0EBX_INVPCID, "INVPCID" }, 1015 { SEFF0EBX_RTM, "RTM" }, 1016 { SEFF0EBX_PQM, "PQM" }, 1017 { SEFF0EBX_MPX, "MPX" }, 1018 { SEFF0EBX_AVX512F, "AVX512F" }, 1019 { SEFF0EBX_AVX512DQ, "AVX512DQ" }, 1020 { SEFF0EBX_RDSEED, "RDSEED" }, 1021 { SEFF0EBX_ADX, "ADX" }, 1022 { SEFF0EBX_SMAP, "SMAP" }, 1023 { SEFF0EBX_AVX512IFMA, "AVX512IFMA" }, 1024 { SEFF0EBX_PCOMMIT, "PCOMMIT" }, 1025 { SEFF0EBX_CLFLUSHOPT, "CLFLUSHOPT" }, 1026 { SEFF0EBX_CLWB, "CLWB" }, 1027 { SEFF0EBX_PT, "PT" }, 1028 { SEFF0EBX_AVX512PF, "AVX512PF" }, 1029 { SEFF0EBX_AVX512ER, "AVX512ER" }, 1030 { SEFF0EBX_AVX512CD, "AVX512CD" }, 1031 { SEFF0EBX_SHA, "SHA" }, 1032 { SEFF0EBX_AVX512BW, "AVX512BW" }, 1033 { SEFF0EBX_AVX512VL, "AVX512VL" }, 1034 }; 1035 1036 const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = { 1037 { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, 1038 { SEFF0ECX_UMIP, "UMIP" }, 1039 { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, 1040 { SEFF0ECX_PKU, "PKU" }, 1041 { SEFF0ECX_WAITPKG, "WAITPKG" }, 1042 }; 1043 1044 const struct cpu_cpuid_feature cpu_seff0_edxfeatures[] = { 1045 { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, 1046 { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, 1047 { SEFF0EDX_SRBDS_CTRL, "SRBDS_CTRL" }, 1048 { SEFF0EDX_MD_CLEAR, "MD_CLEAR" }, 1049 { SEFF0EDX_TSXFA, "TSXFA" }, 1050 { SEFF0EDX_IBRS, "IBRS,IBPB" }, 1051 { SEFF0EDX_STIBP, "STIBP" }, 1052 { SEFF0EDX_L1DF, "L1DF" }, 1053 /* SEFF0EDX_ARCH_CAP (not printed) */ 1054 { SEFF0EDX_SSBD, "SSBD" }, 1055 }; 1056 1057 const struct cpu_cpuid_feature cpu_tpm_eaxfeatures[] = { 1058 { TPM_SENSOR, "SENSOR" }, 1059 { TPM_ARAT, "ARAT" }, 1060 }; 1061 1062 const struct cpu_cpuid_feature i386_cpuid_eaxperf[] = { 1063 { CPUIDEAX_VERID, "PERF" }, 1064 }; 1065 1066 const struct cpu_cpuid_feature i386_cpuid_edxapmi[] = { 1067 { CPUIDEDX_ITSC, "ITSC" }, 1068 }; 1069 1070 const struct cpu_cpuid_feature cpu_xsave_extfeatures[] = { 1071 { XSAVE_XSAVEOPT, "XSAVEOPT" }, 1072 { XSAVE_XSAVEC, "XSAVEC" }, 1073 { XSAVE_XGETBV1, "XGETBV1" }, 1074 { XSAVE_XSAVES, "XSAVES" }, 1075 }; 1076 1077 void 1078 winchip_cpu_setup(struct cpu_info *ci) 1079 { 1080 1081 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1082 case 4: /* WinChip C6 */ 1083 ci->ci_feature_flags &= ~CPUID_TSC; 1084 /* Disable RDTSC instruction from user-level. */ 1085 lcr4(rcr4() | CR4_TSD); 1086 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1087 break; 1088 } 1089 } 1090 1091 #if !defined(SMALL_KERNEL) 1092 void 1093 cyrix3_setperf_setup(struct cpu_info *ci) 1094 { 1095 if (cpu_ecxfeature & CPUIDECX_EST) { 1096 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1097 est_init(ci, CPUVENDOR_VIA); 1098 else 1099 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1100 ci->ci_dev->dv_xname); 1101 } 1102 } 1103 #endif 1104 1105 void 1106 cyrix3_cpu_setup(struct cpu_info *ci) 1107 { 1108 int model = (ci->ci_signature >> 4) & 15; 1109 int step = ci->ci_signature & 15; 1110 1111 u_int64_t msreg; 1112 u_int32_t regs[4]; 1113 unsigned int val; 1114 #if !defined(SMALL_KERNEL) 1115 extern void (*pagezero)(void *, size_t); 1116 extern void i686_pagezero(void *, size_t); 1117 1118 pagezero = i686_pagezero; 1119 1120 setperf_setup = cyrix3_setperf_setup; 1121 #endif 1122 1123 switch (model) { 1124 /* Possible earlier models */ 1125 case 0: case 1: case 2: 1126 case 3: case 4: case 5: 1127 break; 1128 1129 case 6: /* C3 Samuel 1 */ 1130 case 7: /* C3 Samuel 2 or C3 Ezra */ 1131 case 8: /* C3 Ezra-T */ 1132 cpuid(0x80000001, regs); 1133 val = regs[3]; 1134 if (val & (1U << 31)) { 1135 cpu_feature |= CPUID_3DNOW; 1136 } else { 1137 cpu_feature &= ~CPUID_3DNOW; 1138 } 1139 break; 1140 1141 case 9: 1142 if (step < 3) 1143 break; 1144 /* 1145 * C3 Nehemiah & later: fall through. 1146 */ 1147 1148 case 10: /* C7-M Type A */ 1149 case 13: /* C7-M Type D */ 1150 case 15: /* Nano */ 1151 #if !defined(SMALL_KERNEL) 1152 if (CPU_IS_PRIMARY(ci) && 1153 (model == 10 || model == 13 || model == 15)) { 1154 /* Setup the sensors structures */ 1155 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1156 sizeof(ci->ci_sensordev.xname)); 1157 ci->ci_sensor.type = SENSOR_TEMP; 1158 sensor_task_register(ci, via_update_sensor, 5); 1159 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1160 sensordev_install(&ci->ci_sensordev); 1161 } 1162 #endif 1163 1164 default: 1165 /* 1166 * C3 Nehemiah/Esther & later models: 1167 * First we check for extended feature flags, and then 1168 * (if present) retrieve the ones at 0xC0000001. In this 1169 * bit 2 tells us if the RNG is present. Bit 3 tells us 1170 * if the RNG has been enabled. In order to use the RNG 1171 * we need 3 things: We need an RNG, we need the FXSR bit 1172 * enabled in cr4 (SSE/SSE2 stuff), and we need to have 1173 * Bit 6 of MSR 0x110B set to 1 (the default), which will 1174 * show up as bit 3 set here. 1175 */ 1176 cpuid(0xC0000000, regs); /* Check for RNG */ 1177 val = regs[0]; 1178 if (val >= 0xC0000001) { 1179 cpuid(0xC0000001, regs); 1180 val = regs[3]; 1181 } else 1182 val = 0; 1183 1184 if (val & (C3_CPUID_HAS_RNG | C3_CPUID_HAS_ACE)) 1185 printf("%s:", ci->ci_dev->dv_xname); 1186 1187 /* Enable RNG if present and disabled */ 1188 if (val & C3_CPUID_HAS_RNG) { 1189 extern int viac3_rnd_present; 1190 1191 if (!(val & C3_CPUID_DO_RNG)) { 1192 msreg = rdmsr(0x110B); 1193 msreg |= 0x40; 1194 wrmsr(0x110B, msreg); 1195 } 1196 viac3_rnd_present = 1; 1197 printf(" RNG"); 1198 } 1199 1200 /* Enable AES engine if present and disabled */ 1201 if (val & C3_CPUID_HAS_ACE) { 1202 #ifdef CRYPTO 1203 if (!(val & C3_CPUID_DO_ACE)) { 1204 msreg = rdmsr(0x1107); 1205 msreg |= (0x01 << 28); 1206 wrmsr(0x1107, msreg); 1207 } 1208 i386_has_xcrypt |= C3_HAS_AES; 1209 #endif /* CRYPTO */ 1210 printf(" AES"); 1211 } 1212 1213 /* Enable ACE2 engine if present and disabled */ 1214 if (val & C3_CPUID_HAS_ACE2) { 1215 #ifdef CRYPTO 1216 if (!(val & C3_CPUID_DO_ACE2)) { 1217 msreg = rdmsr(0x1107); 1218 msreg |= (0x01 << 28); 1219 wrmsr(0x1107, msreg); 1220 } 1221 i386_has_xcrypt |= C3_HAS_AESCTR; 1222 #endif /* CRYPTO */ 1223 printf(" AES-CTR"); 1224 } 1225 1226 /* Enable SHA engine if present and disabled */ 1227 if (val & C3_CPUID_HAS_PHE) { 1228 #ifdef CRYPTO 1229 if (!(val & C3_CPUID_DO_PHE)) { 1230 msreg = rdmsr(0x1107); 1231 msreg |= (0x01 << 28/**/); 1232 wrmsr(0x1107, msreg); 1233 } 1234 i386_has_xcrypt |= C3_HAS_SHA; 1235 #endif /* CRYPTO */ 1236 printf(" SHA1 SHA256"); 1237 } 1238 1239 /* Enable MM engine if present and disabled */ 1240 if (val & C3_CPUID_HAS_PMM) { 1241 #ifdef CRYPTO 1242 if (!(val & C3_CPUID_DO_PMM)) { 1243 msreg = rdmsr(0x1107); 1244 msreg |= (0x01 << 28/**/); 1245 wrmsr(0x1107, msreg); 1246 } 1247 i386_has_xcrypt |= C3_HAS_MM; 1248 #endif /* CRYPTO */ 1249 printf(" RSA"); 1250 } 1251 1252 printf("\n"); 1253 break; 1254 } 1255 } 1256 1257 #if !defined(SMALL_KERNEL) 1258 void 1259 via_update_sensor(void *args) 1260 { 1261 struct cpu_info *ci = (struct cpu_info *) args; 1262 u_int64_t msr; 1263 1264 switch (ci->ci_model) { 1265 case 0xa: 1266 case 0xd: 1267 msr = rdmsr(MSR_C7M_TMTEMPERATURE); 1268 break; 1269 case 0xf: 1270 msr = rdmsr(MSR_CENT_TMTEMPERATURE); 1271 break; 1272 } 1273 ci->ci_sensor.value = (msr & 0xffffff); 1274 /* micro degrees */ 1275 ci->ci_sensor.value *= 1000000; 1276 ci->ci_sensor.value += 273150000; 1277 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1278 } 1279 #endif 1280 1281 void 1282 cyrix6x86_cpu_setup(struct cpu_info *ci) 1283 { 1284 extern int clock_broken_latch; 1285 1286 switch ((ci->ci_signature >> 4) & 15) { /* model */ 1287 case -1: /* M1 w/o cpuid */ 1288 case 2: /* M1 */ 1289 /* set up various cyrix registers */ 1290 /* Enable suspend on halt */ 1291 cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08); 1292 /* enable access to ccr4/ccr5 */ 1293 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) | 0x10); 1294 /* cyrix's workaround for the "coma bug" */ 1295 cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8); 1296 cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f); 1297 cyrix_read_reg(0x33); cyrix_write_reg(0x33, 0); 1298 cyrix_write_reg(0x3c, cyrix_read_reg(0x3c) | 0x87); 1299 /* disable access to ccr4/ccr5 */ 1300 cyrix_write_reg(0xC3, cyrix_read_reg(0xC3) & ~0x10); 1301 1302 printf("%s: xchg bug workaround performed\n", 1303 ci->ci_dev->dv_xname); 1304 break; /* fallthrough? */ 1305 case 4: /* GXm */ 1306 /* Unset the TSC bit until calibrate_delay() gets fixed. */ 1307 clock_broken_latch = 1; 1308 curcpu()->ci_feature_flags &= ~CPUID_TSC; 1309 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1310 break; 1311 } 1312 } 1313 1314 void 1315 natsem6x86_cpu_setup(struct cpu_info *ci) 1316 { 1317 extern int clock_broken_latch; 1318 int model = (ci->ci_signature >> 4) & 15; 1319 1320 clock_broken_latch = 1; 1321 switch (model) { 1322 case 4: 1323 cpu_feature &= ~CPUID_TSC; 1324 printf("%s: TSC disabled\n", ci->ci_dev->dv_xname); 1325 break; 1326 } 1327 } 1328 1329 void 1330 intel586_cpu_setup(struct cpu_info *ci) 1331 { 1332 if (!cpu_f00f_bug) { 1333 fix_f00f(); 1334 printf("%s: F00F bug workaround installed\n", 1335 ci->ci_dev->dv_xname); 1336 } 1337 } 1338 1339 #if !defined(SMALL_KERNEL) 1340 void 1341 amd_family5_setperf_setup(struct cpu_info *ci) 1342 { 1343 k6_powernow_init(); 1344 } 1345 #endif 1346 1347 void 1348 amd_family5_setup(struct cpu_info *ci) 1349 { 1350 int model = (ci->ci_signature >> 4) & 15; 1351 1352 switch (model) { 1353 case 0: /* AMD-K5 Model 0 */ 1354 /* 1355 * According to the AMD Processor Recognition App Note, 1356 * the AMD-K5 Model 0 uses the wrong bit to indicate 1357 * support for global PTEs, instead using bit 9 (APIC) 1358 * rather than bit 13 (i.e. "0x200" vs. 0x2000". Oops!). 1359 */ 1360 if (cpu_feature & CPUID_APIC) 1361 cpu_feature = (cpu_feature & ~CPUID_APIC) | CPUID_PGE; 1362 /* 1363 * XXX But pmap_pg_g is already initialized -- need to kick 1364 * XXX the pmap somehow. How does the MP branch do this? 1365 */ 1366 break; 1367 case 12: 1368 case 13: 1369 #if !defined(SMALL_KERNEL) 1370 setperf_setup = amd_family5_setperf_setup; 1371 #endif 1372 break; 1373 } 1374 } 1375 1376 #if !defined(SMALL_KERNEL) 1377 void 1378 amd_family6_setperf_setup(struct cpu_info *ci) 1379 { 1380 int family = (ci->ci_signature >> 8) & 15; 1381 1382 switch (family) { 1383 case 6: 1384 k7_powernow_init(); 1385 break; 1386 case 15: 1387 k8_powernow_init(); 1388 break; 1389 } 1390 if (ci->ci_family >= 0x10) 1391 k1x_init(ci); 1392 } 1393 #endif 1394 1395 void 1396 amd_family6_setup(struct cpu_info *ci) 1397 { 1398 #if !defined(SMALL_KERNEL) 1399 int family = (ci->ci_signature >> 8) & 15; 1400 extern void (*pagezero)(void *, size_t); 1401 extern void sse2_pagezero(void *, size_t); 1402 extern void i686_pagezero(void *, size_t); 1403 1404 if (cpu_feature & CPUID_SSE2) 1405 pagezero = sse2_pagezero; 1406 else 1407 pagezero = i686_pagezero; 1408 1409 setperf_setup = amd_family6_setperf_setup; 1410 1411 if (family == 0xf) { 1412 amd64_errata(ci); 1413 } 1414 #endif 1415 } 1416 1417 #if !defined(SMALL_KERNEL) 1418 /* 1419 * Temperature read on the CPU is relative to the maximum 1420 * temperature supported by the CPU, Tj(Max). 1421 * Refer to: 1422 * 64-ia-32-architectures-software-developer-vol-3c-part-3-manual.pdf 1423 * Section 35 and 1424 * http://www.intel.com/content/dam/www/public/us/en/documents/ 1425 * white-papers/cpu-monitoring-dts-peci-paper.pdf 1426 * 1427 * The temperature on Intel CPUs can be between 70 and 105 degC, since 1428 * Westmere we can read the TJmax from the die. For older CPUs we have 1429 * to guess or use undocumented MSRs. Then we subtract the temperature 1430 * portion of thermal status from max to get current temperature. 1431 */ 1432 void 1433 intelcore_update_sensor(void *args) 1434 { 1435 struct cpu_info *ci = (struct cpu_info *) args; 1436 u_int64_t msr; 1437 int max = 100; 1438 1439 /* Only some Core family chips have MSR_TEMPERATURE_TARGET. */ 1440 if (ci->ci_model == 0x0e && 1441 (rdmsr(MSR_TEMPERATURE_TARGET_UNDOCUMENTED) & 1442 MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED)) 1443 max = 85; 1444 1445 /* 1446 * Newer CPUs can tell you what their max temperature is. 1447 * See: '64-ia-32-architectures-software-developer- 1448 * vol-3c-part-3-manual.pdf' 1449 */ 1450 if (ci->ci_model > 0x17 && ci->ci_model != 0x1c && 1451 ci->ci_model != 0x26 && ci->ci_model != 0x27 && 1452 ci->ci_model != 0x35 && ci->ci_model != 0x36) 1453 max = MSR_TEMPERATURE_TARGET_TJMAX( 1454 rdmsr(MSR_TEMPERATURE_TARGET)); 1455 1456 msr = rdmsr(MSR_THERM_STATUS); 1457 if (msr & MSR_THERM_STATUS_VALID_BIT) { 1458 ci->ci_sensor.value = max - MSR_THERM_STATUS_TEMP(msr); 1459 /* micro degrees */ 1460 ci->ci_sensor.value *= 1000000; 1461 /* kelvin */ 1462 ci->ci_sensor.value += 273150000; 1463 ci->ci_sensor.flags &= ~SENSOR_FINVALID; 1464 } else { 1465 ci->ci_sensor.value = 0; 1466 ci->ci_sensor.flags |= SENSOR_FINVALID; 1467 } 1468 } 1469 1470 void 1471 intel686_cpusensors_setup(struct cpu_info *ci) 1472 { 1473 if (!CPU_IS_PRIMARY(ci) || (ci->ci_feature_tpmflags & TPM_SENSOR) == 0) 1474 return; 1475 1476 /* Setup the sensors structures */ 1477 strlcpy(ci->ci_sensordev.xname, ci->ci_dev->dv_xname, 1478 sizeof(ci->ci_sensordev.xname)); 1479 ci->ci_sensor.type = SENSOR_TEMP; 1480 sensor_task_register(ci, intelcore_update_sensor, 5); 1481 sensor_attach(&ci->ci_sensordev, &ci->ci_sensor); 1482 sensordev_install(&ci->ci_sensordev); 1483 } 1484 #endif 1485 1486 #if !defined(SMALL_KERNEL) 1487 void 1488 intel686_setperf_setup(struct cpu_info *ci) 1489 { 1490 int family = (ci->ci_signature >> 8) & 15; 1491 int step = ci->ci_signature & 15; 1492 1493 if (cpu_ecxfeature & CPUIDECX_EST) { 1494 if (rdmsr(MSR_MISC_ENABLE) & (1 << 16)) 1495 est_init(ci, CPUVENDOR_INTEL); 1496 else 1497 printf("%s: Enhanced SpeedStep disabled by BIOS\n", 1498 ci->ci_dev->dv_xname); 1499 } else if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) == 1500 (CPUID_ACPI | CPUID_TM)) 1501 p4tcc_init(family, step); 1502 } 1503 #endif 1504 1505 void 1506 intel686_common_cpu_setup(struct cpu_info *ci) 1507 { 1508 1509 #if !defined(SMALL_KERNEL) 1510 setperf_setup = intel686_setperf_setup; 1511 cpusensors_setup = intel686_cpusensors_setup; 1512 { 1513 extern void (*pagezero)(void *, size_t); 1514 extern void sse2_pagezero(void *, size_t); 1515 extern void i686_pagezero(void *, size_t); 1516 1517 if (cpu_feature & CPUID_SSE2) 1518 pagezero = sse2_pagezero; 1519 else 1520 pagezero = i686_pagezero; 1521 } 1522 #endif 1523 /* 1524 * Make sure SYSENTER is disabled. 1525 */ 1526 if (cpu_feature & CPUID_SEP) 1527 wrmsr(MSR_SYSENTER_CS, 0); 1528 } 1529 1530 void 1531 intel686_cpu_setup(struct cpu_info *ci) 1532 { 1533 int model = (ci->ci_signature >> 4) & 15; 1534 int step = ci->ci_signature & 15; 1535 u_quad_t msr119; 1536 1537 intel686_common_cpu_setup(ci); 1538 1539 /* 1540 * Original PPro returns SYSCALL in CPUID but is non-functional. 1541 * From Intel Application Note #485. 1542 */ 1543 if ((model == 1) && (step < 3)) 1544 ci->ci_feature_flags &= ~CPUID_SEP; 1545 1546 /* 1547 * Disable the Pentium3 serial number. 1548 */ 1549 if ((model == 7) && (ci->ci_feature_flags & CPUID_PSN)) { 1550 msr119 = rdmsr(MSR_BBL_CR_CTL); 1551 msr119 |= 0x0000000000200000LL; 1552 wrmsr(MSR_BBL_CR_CTL, msr119); 1553 1554 printf("%s: disabling processor serial number\n", 1555 ci->ci_dev->dv_xname); 1556 ci->ci_feature_flags &= ~CPUID_PSN; 1557 ci->ci_level = 2; 1558 } 1559 1560 #if !defined(SMALL_KERNEL) 1561 p3_early = (model == 8 && step == 1) ? 1 : 0; 1562 update_cpuspeed = p3_update_cpuspeed; 1563 #endif 1564 } 1565 1566 void 1567 intel686_p4_cpu_setup(struct cpu_info *ci) 1568 { 1569 intel686_common_cpu_setup(ci); 1570 1571 #if !defined(SMALL_KERNEL) 1572 p4_model = (ci->ci_signature >> 4) & 15; 1573 update_cpuspeed = p4_update_cpuspeed; 1574 #endif 1575 } 1576 1577 void 1578 tm86_cpu_setup(struct cpu_info *ci) 1579 { 1580 #if !defined(SMALL_KERNEL) 1581 longrun_init(); 1582 #endif 1583 } 1584 1585 char * 1586 intel686_cpu_name(int model) 1587 { 1588 char *ret = NULL; 1589 1590 switch (model) { 1591 case 5: 1592 switch (cpu_cache_edx & 0xFF) { 1593 case 0x40: 1594 case 0x41: 1595 ret = "Celeron"; 1596 break; 1597 /* 0x42 should not exist in this model. */ 1598 case 0x43: 1599 ret = "Pentium II"; 1600 break; 1601 case 0x44: 1602 case 0x45: 1603 ret = "Pentium II Xeon"; 1604 break; 1605 } 1606 break; 1607 case 7: 1608 switch (cpu_cache_edx & 0xFF) { 1609 /* 0x40 - 0x42 should not exist in this model. */ 1610 case 0x43: 1611 ret = "Pentium III"; 1612 break; 1613 case 0x44: 1614 case 0x45: 1615 ret = "Pentium III Xeon"; 1616 break; 1617 } 1618 break; 1619 } 1620 1621 return (ret); 1622 } 1623 1624 char * 1625 cyrix3_cpu_name(int model, int step) 1626 { 1627 char *name = NULL; 1628 1629 switch (model) { 1630 case 7: 1631 if (step < 8) 1632 name = "C3 Samuel 2"; 1633 else 1634 name = "C3 Ezra"; 1635 break; 1636 } 1637 return name; 1638 } 1639 1640 /* 1641 * Print identification for the given CPU. 1642 * XXX XXX 1643 * This is not as clean as one might like, because it references 1644 * 1645 * the "cpuid_level" and "cpu_vendor" globals. 1646 * cpuid_level isn't so bad, since both CPU's will hopefully 1647 * be of the same level. 1648 * 1649 * The Intel multiprocessor spec doesn't give us the cpu_vendor 1650 * information; however, the chance of multi-vendor SMP actually 1651 * ever *working* is sufficiently low that it's probably safe to assume 1652 * all processors are of the same vendor. 1653 */ 1654 void 1655 identifycpu(struct cpu_info *ci) 1656 { 1657 const char *name, *modifier, *vendorname, *token; 1658 int class = CPUCLASS_486, vendor, i, max; 1659 int family, model, step, modif, cachesize; 1660 const struct cpu_cpuid_nameclass *cpup = NULL; 1661 char *brandstr_from, *brandstr_to; 1662 char *cpu_device = ci->ci_dev->dv_xname; 1663 int skipspace; 1664 extern uint32_t cpu_meltdown; 1665 1666 if (cpuid_level == -1) { 1667 name = "486DX"; 1668 vendor = CPUVENDOR_INTEL; 1669 vendorname = "Intel"; 1670 model = -1; 1671 step = -1; 1672 class = CPUCLASS_486; 1673 ci->cpu_setup = NULL; 1674 modifier = ""; 1675 token = ""; 1676 } else { 1677 max = sizeof (i386_cpuid_cpus) / sizeof (i386_cpuid_cpus[0]); 1678 modif = (ci->ci_signature >> 12) & 3; 1679 family = (ci->ci_signature >> 8) & 15; 1680 ci->ci_family = family; 1681 model = (ci->ci_signature >> 4) & 15; 1682 ci->ci_model = model; 1683 step = ci->ci_signature & 15; 1684 #ifdef CPUDEBUG 1685 printf("%s: cpuid level %d cache eax %x ebx %x ecx %x edx %x\n", 1686 cpu_device, cpuid_level, cpu_cache_eax, cpu_cache_ebx, 1687 cpu_cache_ecx, cpu_cache_edx); 1688 #endif 1689 if (family < CPU_MINFAMILY) 1690 panic("identifycpu: strange family value"); 1691 1692 for (i = 0; i < max; i++) { 1693 if (!strncmp(cpu_vendor, 1694 i386_cpuid_cpus[i].cpu_id, 12)) { 1695 cpup = &i386_cpuid_cpus[i]; 1696 break; 1697 } 1698 } 1699 1700 if (cpup == NULL) { 1701 vendor = CPUVENDOR_UNKNOWN; 1702 if (cpu_vendor[0] != '\0') 1703 vendorname = &cpu_vendor[0]; 1704 else 1705 vendorname = "Unknown"; 1706 if (family > CPU_MAXFAMILY) 1707 family = CPU_MAXFAMILY; 1708 class = family - 3; 1709 if (class > CPUCLASS_686) 1710 class = CPUCLASS_686; 1711 modifier = ""; 1712 name = ""; 1713 token = ""; 1714 ci->cpu_setup = NULL; 1715 } else { 1716 token = cpup->cpu_id; 1717 vendor = cpup->cpu_vendor; 1718 vendorname = cpup->cpu_vendorname; 1719 /* 1720 * Special hack for the VIA C3 series. 1721 * 1722 * VIA bought Centaur Technology from IDT in Aug 1999 1723 * and marketed the processors as VIA Cyrix III/C3. 1724 */ 1725 if (vendor == CPUVENDOR_IDT && family >= 6) { 1726 vendor = CPUVENDOR_VIA; 1727 vendorname = "VIA"; 1728 } 1729 modifier = modifiers[modif]; 1730 if (family > CPU_MAXFAMILY) { 1731 family = CPU_MAXFAMILY; 1732 model = CPU_DEFMODEL; 1733 } else if (model > CPU_MAXMODEL) 1734 model = CPU_DEFMODEL; 1735 i = family - CPU_MINFAMILY; 1736 1737 /* store extended family/model values for later use */ 1738 if ((vendor == CPUVENDOR_INTEL && 1739 (family == 0x6 || family == 0xf)) || 1740 (vendor == CPUVENDOR_AMD && family == 0xf)) { 1741 ci->ci_family += (ci->ci_signature >> 20) & 1742 0xff; 1743 ci->ci_model += ((ci->ci_signature >> 16) & 1744 0x0f) << 4; 1745 } 1746 1747 /* Special hack for the PentiumII/III series. */ 1748 if (vendor == CPUVENDOR_INTEL && family == 6 && 1749 (model == 5 || model == 7)) { 1750 name = intel686_cpu_name(model); 1751 /* Special hack for the VIA C3 series. */ 1752 } else if (vendor == CPUVENDOR_VIA && family == 6 && 1753 model == 7) { 1754 name = cyrix3_cpu_name(model, step); 1755 /* Special hack for the TMS5x00 series. */ 1756 } else if (vendor == CPUVENDOR_TRANSMETA && 1757 family == 5 && model == 4) { 1758 name = tm86_cpu_name(model); 1759 } else 1760 name = cpup->cpu_family[i].cpu_models[model]; 1761 if (name == NULL) { 1762 name = cpup->cpu_family[i].cpu_models[CPU_DEFMODEL]; 1763 if (name == NULL) 1764 name = ""; 1765 } 1766 class = cpup->cpu_family[i].cpu_class; 1767 ci->cpu_setup = cpup->cpu_family[i].cpu_setup; 1768 } 1769 } 1770 1771 /* Find the amount of on-chip L2 cache. */ 1772 cachesize = -1; 1773 if (vendor == CPUVENDOR_INTEL && cpuid_level >= 2 && family < 0xf) { 1774 int intel_cachetable[] = { 0, 128, 256, 512, 1024, 2048 }; 1775 1776 if ((cpu_cache_edx & 0xFF) >= 0x40 && 1777 (cpu_cache_edx & 0xFF) <= 0x45) 1778 cachesize = intel_cachetable[(cpu_cache_edx & 0xFF) - 0x40]; 1779 } else if (vendor == CPUVENDOR_AMD && class == CPUCLASS_686) { 1780 u_int regs[4]; 1781 cpuid(0x80000000, regs); 1782 1783 if (regs[0] >= 0x80000006) { 1784 cpuid(0x80000006, regs); 1785 cachesize = (regs[2] >> 16); 1786 } 1787 } 1788 1789 if (ci->ci_feature_flags & CPUID_CFLUSH) { 1790 u_int regs[4]; 1791 1792 /* to get the cacheline size you must do cpuid 1793 * with eax 0x01 1794 */ 1795 1796 cpuid(0x01, regs); 1797 ci->ci_cflushsz = ((regs[1] >> 8) & 0xff) * 8; 1798 } 1799 1800 if (vendor == CPUVENDOR_INTEL) { 1801 /* 1802 * PIII, Core Solo and Core Duo CPUs have known 1803 * errata stating: 1804 * "Page with PAT set to WC while associated MTRR is UC 1805 * may consolidate to UC". 1806 * Because of this it is best we just fallback to mtrrs 1807 * in this case. 1808 */ 1809 if (ci->ci_family == 6 && ci->ci_model < 15) 1810 ci->ci_feature_flags &= ~CPUID_PAT; 1811 } 1812 1813 /* Remove leading, trailing and duplicated spaces from cpu_brandstr */ 1814 brandstr_from = brandstr_to = cpu_brandstr; 1815 skipspace = 1; 1816 while (*brandstr_from != '\0') { 1817 if (!skipspace || *brandstr_from != ' ') { 1818 skipspace = 0; 1819 *(brandstr_to++) = *brandstr_from; 1820 } 1821 if (*brandstr_from == ' ') 1822 skipspace = 1; 1823 brandstr_from++; 1824 } 1825 if (skipspace && brandstr_to > cpu_brandstr) 1826 brandstr_to--; 1827 *brandstr_to = '\0'; 1828 1829 if (cpu_brandstr[0] == '\0') { 1830 snprintf(cpu_brandstr, 48 /* sizeof(cpu_brandstr) */, 1831 "%s %s%s", vendorname, modifier, name); 1832 } 1833 1834 if (cachesize > -1) { 1835 snprintf(cpu_model, sizeof(cpu_model), 1836 "%s (%s%s%s%s-class, %dKB L2 cache)", 1837 cpu_brandstr, 1838 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1839 ((*token) ? "\" " : ""), classnames[class], cachesize); 1840 } else { 1841 snprintf(cpu_model, sizeof(cpu_model), 1842 "%s (%s%s%s%s-class)", 1843 cpu_brandstr, 1844 ((*token) ? "\"" : ""), ((*token) ? token : ""), 1845 ((*token) ? "\" " : ""), classnames[class]); 1846 } 1847 1848 printf("%s: %s", cpu_device, cpu_model); 1849 1850 if (ci->ci_feature_flags && (ci->ci_feature_flags & CPUID_TSC)) { 1851 /* Has TSC, check if it's constant */ 1852 switch (vendor) { 1853 case CPUVENDOR_INTEL: 1854 if ((ci->ci_family == 0x0f && ci->ci_model >= 0x03) || 1855 (ci->ci_family == 0x06 && ci->ci_model >= 0x0e)) { 1856 ci->ci_flags |= CPUF_CONST_TSC; 1857 } 1858 break; 1859 case CPUVENDOR_VIA: 1860 if (ci->ci_model >= 0x0f) { 1861 ci->ci_flags |= CPUF_CONST_TSC; 1862 } 1863 break; 1864 } 1865 calibrate_cyclecounter(); 1866 if (cpuspeed > 994) { 1867 int ghz, fr; 1868 1869 ghz = (cpuspeed + 9) / 1000; 1870 fr = ((cpuspeed + 9) / 10 ) % 100; 1871 if (fr) 1872 printf(" %d.%02d GHz", ghz, fr); 1873 else 1874 printf(" %d GHz", ghz); 1875 } else { 1876 printf(" %d MHz", cpuspeed); 1877 } 1878 } 1879 1880 if (cpuid_level != -1) 1881 printf(", %02x-%02x-%02x", ci->ci_family, ci->ci_model, 1882 step); 1883 1884 printf("\n"); 1885 1886 if (ci->ci_feature_flags) { 1887 int numbits = 0; 1888 1889 printf("%s: ", cpu_device); 1890 max = sizeof(i386_cpuid_features) / 1891 sizeof(i386_cpuid_features[0]); 1892 for (i = 0; i < max; i++) { 1893 if (ci->ci_feature_flags & 1894 i386_cpuid_features[i].feature_bit) { 1895 printf("%s%s", (numbits == 0 ? "" : ","), 1896 i386_cpuid_features[i].feature_name); 1897 numbits++; 1898 } 1899 } 1900 max = sizeof(i386_cpuid_ecxfeatures) 1901 / sizeof(i386_cpuid_ecxfeatures[0]); 1902 for (i = 0; i < max; i++) { 1903 if (cpu_ecxfeature & 1904 i386_cpuid_ecxfeatures[i].feature_bit) { 1905 printf("%s%s", (numbits == 0 ? "" : ","), 1906 i386_cpuid_ecxfeatures[i].feature_name); 1907 numbits++; 1908 } 1909 } 1910 for (i = 0; i < nitems(i386_ecpuid_features); i++) { 1911 if (ecpu_feature & 1912 i386_ecpuid_features[i].feature_bit) { 1913 printf("%s%s", (numbits == 0 ? "" : ","), 1914 i386_ecpuid_features[i].feature_name); 1915 numbits++; 1916 } 1917 } 1918 for (i = 0; i < nitems(i386_ecpuid_ecxfeatures); i++) { 1919 if (ecpu_ecxfeature & 1920 i386_ecpuid_ecxfeatures[i].feature_bit) { 1921 printf("%s%s", (numbits == 0 ? "" : ","), 1922 i386_ecpuid_ecxfeatures[i].feature_name); 1923 numbits++; 1924 } 1925 } 1926 for (i = 0; i < nitems(i386_cpuid_eaxperf); i++) { 1927 if (cpu_perf_eax & 1928 i386_cpuid_eaxperf[i].feature_bit) { 1929 printf("%s%s", (numbits == 0 ? "" : ","), 1930 i386_cpuid_eaxperf[i].feature_name); 1931 numbits++; 1932 } 1933 } 1934 for (i = 0; i < nitems(i386_cpuid_edxapmi); i++) { 1935 if (cpu_apmi_edx & 1936 i386_cpuid_edxapmi[i].feature_bit) { 1937 printf("%s%s", (numbits == 0 ? "" : ","), 1938 i386_cpuid_edxapmi[i].feature_name); 1939 numbits++; 1940 } 1941 } 1942 1943 if (cpuid_level >= 0x07) { 1944 u_int dummy; 1945 1946 /* "Structured Extended Feature Flags" */ 1947 CPUID_LEAF(0x7, 0, dummy, 1948 ci->ci_feature_sefflags_ebx, 1949 ci->ci_feature_sefflags_ecx, 1950 ci->ci_feature_sefflags_edx); 1951 for (i = 0; i < nitems(cpu_seff0_ebxfeatures); i++) 1952 if (ci->ci_feature_sefflags_ebx & 1953 cpu_seff0_ebxfeatures[i].feature_bit) 1954 printf("%s%s", 1955 (numbits == 0 ? "" : ","), 1956 cpu_seff0_ebxfeatures[i].feature_name); 1957 for (i = 0; i < nitems(cpu_seff0_ecxfeatures); i++) 1958 if (ci->ci_feature_sefflags_ecx & 1959 cpu_seff0_ecxfeatures[i].feature_bit) 1960 printf("%s%s", 1961 (numbits == 0 ? "" : ","), 1962 cpu_seff0_ecxfeatures[i].feature_name); 1963 for (i = 0; i < nitems(cpu_seff0_edxfeatures); i++) 1964 if (ci->ci_feature_sefflags_edx & 1965 cpu_seff0_edxfeatures[i].feature_bit) 1966 printf("%s%s", 1967 (numbits == 0 ? "" : ","), 1968 cpu_seff0_edxfeatures[i].feature_name); 1969 } 1970 1971 if (!strcmp(cpu_vendor, "GenuineIntel") && 1972 cpuid_level >= 0x06 ) { 1973 u_int dummy; 1974 1975 CPUID(0x06, ci->ci_feature_tpmflags, dummy, 1976 dummy, dummy); 1977 max = nitems(cpu_tpm_eaxfeatures); 1978 for (i = 0; i < max; i++) 1979 if (ci->ci_feature_tpmflags & 1980 cpu_tpm_eaxfeatures[i].feature_bit) 1981 printf(",%s", cpu_tpm_eaxfeatures[i].feature_name); 1982 } 1983 1984 /* xsave subfeatures */ 1985 if (cpuid_level >= 0xd) { 1986 uint32_t dummy, val; 1987 1988 CPUID_LEAF(0xd, 1, val, dummy, dummy, dummy); 1989 for (i = 0; i < nitems(cpu_xsave_extfeatures); i++) 1990 if (val & cpu_xsave_extfeatures[i].feature_bit) 1991 printf(",%s", 1992 cpu_xsave_extfeatures[i].feature_name); 1993 } 1994 1995 if (cpu_meltdown) 1996 printf(",MELTDOWN"); 1997 1998 printf("\n"); 1999 } 2000 2001 /* 2002 * "Mitigation G-2" per AMD's Whitepaper "Software Techniques 2003 * for Managing Speculation on AMD Processors" 2004 * 2005 * By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch 2006 * serializing instruction. 2007 * 2008 * This MSR is available on all AMD families >= 10h, except 11h 2009 * where LFENCE is always serializing. 2010 */ 2011 if (!strcmp(cpu_vendor, "AuthenticAMD")) { 2012 if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) { 2013 uint64_t msr; 2014 2015 msr = rdmsr(MSR_DE_CFG); 2016 if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) { 2017 msr |= DE_CFG_SERIALIZE_LFENCE; 2018 wrmsr(MSR_DE_CFG, msr); 2019 } 2020 } 2021 } 2022 2023 /* 2024 * Attempt to disable Silicon Debug and lock the configuration 2025 * if it's enabled and unlocked. 2026 */ 2027 if (!strcmp(cpu_vendor, "GenuineIntel") && 2028 (cpu_ecxfeature & CPUIDECX_SDBG)) { 2029 uint64_t msr; 2030 2031 msr = rdmsr(IA32_DEBUG_INTERFACE); 2032 if ((msr & IA32_DEBUG_INTERFACE_ENABLE) && 2033 (msr & IA32_DEBUG_INTERFACE_LOCK) == 0) { 2034 msr &= IA32_DEBUG_INTERFACE_MASK; 2035 msr |= IA32_DEBUG_INTERFACE_LOCK; 2036 wrmsr(IA32_DEBUG_INTERFACE, msr); 2037 } else if (msr & IA32_DEBUG_INTERFACE_ENABLE) 2038 printf("%s: cannot disable silicon debug\n", 2039 cpu_device); 2040 } 2041 2042 if (CPU_IS_PRIMARY(ci)) { 2043 if (cpu_ecxfeature & CPUIDECX_RDRAND) 2044 has_rdrand = 1; 2045 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_RDSEED) 2046 has_rdseed = 1; 2047 if (ci->ci_feature_sefflags_ebx & SEFF0EBX_SMAP) 2048 replacesmap(); 2049 } 2050 2051 #ifndef SMALL_KERNEL 2052 if (cpuspeed != 0 && cpu_cpuspeed == NULL) 2053 cpu_cpuspeed = pentium_cpuspeed; 2054 #endif 2055 2056 cpu_class = class; 2057 2058 ci->cpu_class = class; 2059 2060 /* 2061 * Enable ring 0 write protection. 2062 */ 2063 lcr0(rcr0() | CR0_WP); 2064 2065 /* 2066 * If we have FXSAVE/FXRESTOR, use them. 2067 */ 2068 if (cpu_feature & CPUID_FXSR) { 2069 i386_use_fxsave = 1; 2070 lcr4(rcr4() | CR4_OSFXSR); 2071 2072 /* 2073 * If we have SSE/SSE2, enable XMM exceptions, and 2074 * notify userland. 2075 */ 2076 if (cpu_feature & (CPUID_SSE|CPUID_SSE2)) { 2077 if (cpu_feature & CPUID_SSE) 2078 i386_has_sse = 1; 2079 if (cpu_feature & CPUID_SSE2) 2080 i386_has_sse2 = 1; 2081 lcr4(rcr4() | CR4_OSXMMEXCPT); 2082 } 2083 } else 2084 i386_use_fxsave = 0; 2085 2086 } 2087 2088 char * 2089 tm86_cpu_name(int model) 2090 { 2091 u_int32_t regs[4]; 2092 char *name = NULL; 2093 2094 cpuid(0x80860001, regs); 2095 2096 switch (model) { 2097 case 4: 2098 if (((regs[1] >> 16) & 0xff) >= 0x3) 2099 name = "TMS5800"; 2100 else 2101 name = "TMS5600"; 2102 } 2103 2104 return name; 2105 } 2106 2107 #ifndef SMALL_KERNEL 2108 void 2109 cyrix3_get_bus_clock(struct cpu_info *ci) 2110 { 2111 u_int64_t msr; 2112 int bus; 2113 2114 msr = rdmsr(MSR_EBL_CR_POWERON); 2115 bus = (msr >> 18) & 0x3; 2116 switch (bus) { 2117 case 0: 2118 bus_clock = BUS100; 2119 break; 2120 case 1: 2121 bus_clock = BUS133; 2122 break; 2123 case 2: 2124 bus_clock = BUS200; 2125 break; 2126 case 3: 2127 bus_clock = BUS166; 2128 break; 2129 } 2130 } 2131 2132 void 2133 p4_get_bus_clock(struct cpu_info *ci) 2134 { 2135 u_int64_t msr; 2136 int model, bus; 2137 2138 model = (ci->ci_signature >> 4) & 15; 2139 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2140 if (model < 2) { 2141 bus = (msr >> 21) & 0x7; 2142 switch (bus) { 2143 case 0: 2144 bus_clock = BUS100; 2145 break; 2146 case 1: 2147 bus_clock = BUS133; 2148 break; 2149 default: 2150 printf("%s: unknown Pentium 4 (model %d) " 2151 "EBC_FREQUENCY_ID value %d\n", 2152 ci->ci_dev->dv_xname, model, bus); 2153 break; 2154 } 2155 } else { 2156 bus = (msr >> 16) & 0x7; 2157 switch (bus) { 2158 case 0: 2159 bus_clock = (model == 2) ? BUS100 : BUS266; 2160 break; 2161 case 1: 2162 bus_clock = BUS133; 2163 break; 2164 case 2: 2165 bus_clock = BUS200; 2166 break; 2167 case 3: 2168 bus_clock = BUS166; 2169 break; 2170 default: 2171 printf("%s: unknown Pentium 4 (model %d) " 2172 "EBC_FREQUENCY_ID value %d\n", 2173 ci->ci_dev->dv_xname, model, bus); 2174 break; 2175 } 2176 } 2177 } 2178 2179 void 2180 p3_get_bus_clock(struct cpu_info *ci) 2181 { 2182 u_int64_t msr; 2183 int bus; 2184 2185 switch (ci->ci_model) { 2186 case 0x9: /* Pentium M (130 nm, Banias) */ 2187 bus_clock = BUS100; 2188 break; 2189 case 0xd: /* Pentium M (90 nm, Dothan) */ 2190 msr = rdmsr(MSR_FSB_FREQ); 2191 bus = (msr >> 0) & 0x7; 2192 switch (bus) { 2193 case 0: 2194 bus_clock = BUS100; 2195 break; 2196 case 1: 2197 bus_clock = BUS133; 2198 break; 2199 default: 2200 printf("%s: unknown Pentium M FSB_FREQ value %d", 2201 ci->ci_dev->dv_xname, bus); 2202 goto print_msr; 2203 } 2204 break; 2205 case 0x15: /* EP80579 no FSB */ 2206 break; 2207 case 0xe: /* Core Duo/Solo */ 2208 case 0xf: /* Core Xeon */ 2209 case 0x16: /* 65nm Celeron */ 2210 case 0x17: /* Core 2 Extreme/45nm Xeon */ 2211 case 0x1d: /* Xeon MP 7400 */ 2212 msr = rdmsr(MSR_FSB_FREQ); 2213 bus = (msr >> 0) & 0x7; 2214 switch (bus) { 2215 case 5: 2216 bus_clock = BUS100; 2217 break; 2218 case 1: 2219 bus_clock = BUS133; 2220 break; 2221 case 3: 2222 bus_clock = BUS166; 2223 break; 2224 case 2: 2225 bus_clock = BUS200; 2226 break; 2227 case 0: 2228 bus_clock = BUS266; 2229 break; 2230 case 4: 2231 bus_clock = BUS333; 2232 break; 2233 default: 2234 printf("%s: unknown Core FSB_FREQ value %d", 2235 ci->ci_dev->dv_xname, bus); 2236 goto print_msr; 2237 } 2238 break; 2239 case 0x1c: /* Atom */ 2240 case 0x26: /* Atom Z6xx */ 2241 case 0x36: /* Atom [DN]2xxx */ 2242 msr = rdmsr(MSR_FSB_FREQ); 2243 bus = (msr >> 0) & 0x7; 2244 switch (bus) { 2245 case 5: 2246 bus_clock = BUS100; 2247 break; 2248 case 1: 2249 bus_clock = BUS133; 2250 break; 2251 case 3: 2252 bus_clock = BUS166; 2253 break; 2254 case 2: 2255 bus_clock = BUS200; 2256 break; 2257 default: 2258 printf("%s: unknown Atom FSB_FREQ value %d", 2259 ci->ci_dev->dv_xname, bus); 2260 goto print_msr; 2261 } 2262 break; 2263 case 0x1: /* Pentium Pro, model 1 */ 2264 case 0x3: /* Pentium II, model 3 */ 2265 case 0x5: /* Pentium II, II Xeon, Celeron, model 5 */ 2266 case 0x6: /* Celeron, model 6 */ 2267 case 0x7: /* Pentium III, III Xeon, model 7 */ 2268 case 0x8: /* Pentium III, III Xeon, Celeron, model 8 */ 2269 case 0xa: /* Pentium III Xeon, model A */ 2270 case 0xb: /* Pentium III, model B */ 2271 msr = rdmsr(MSR_EBL_CR_POWERON); 2272 bus = (msr >> 18) & 0x3; 2273 switch (bus) { 2274 case 0: 2275 bus_clock = BUS66; 2276 break; 2277 case 1: 2278 bus_clock = BUS133; 2279 break; 2280 case 2: 2281 bus_clock = BUS100; 2282 break; 2283 default: 2284 printf("%s: unknown i686 EBL_CR_POWERON value %d", 2285 ci->ci_dev->dv_xname, bus); 2286 goto print_msr; 2287 } 2288 break; 2289 default: 2290 /* no FSB on modern Intel processors */ 2291 break; 2292 } 2293 return; 2294 print_msr: 2295 /* 2296 * Show the EBL_CR_POWERON MSR, so we'll at least have 2297 * some extra information, such as clock ratio, etc. 2298 */ 2299 printf(" (0x%llx)\n", rdmsr(MSR_EBL_CR_POWERON)); 2300 } 2301 2302 void 2303 p4_update_cpuspeed(void) 2304 { 2305 struct cpu_info *ci; 2306 u_int64_t msr; 2307 int mult; 2308 2309 ci = curcpu(); 2310 p4_get_bus_clock(ci); 2311 2312 if (bus_clock == 0) { 2313 printf("p4_update_cpuspeed: unknown bus clock\n"); 2314 return; 2315 } 2316 2317 msr = rdmsr(MSR_EBC_FREQUENCY_ID); 2318 mult = ((msr >> 24) & 0xff); 2319 2320 cpuspeed = (bus_clock * mult) / 100; 2321 } 2322 2323 void 2324 p3_update_cpuspeed(void) 2325 { 2326 struct cpu_info *ci; 2327 u_int64_t msr; 2328 int mult; 2329 const u_int8_t mult_code[] = { 2330 50, 30, 40, 0, 55, 35, 45, 0, 0, 70, 80, 60, 0, 75, 0, 65 }; 2331 2332 ci = curcpu(); 2333 p3_get_bus_clock(ci); 2334 2335 if (bus_clock == 0) { 2336 printf("p3_update_cpuspeed: unknown bus clock\n"); 2337 return; 2338 } 2339 2340 msr = rdmsr(MSR_EBL_CR_POWERON); 2341 mult = (msr >> 22) & 0xf; 2342 mult = mult_code[mult]; 2343 if (!p3_early) 2344 mult += ((msr >> 27) & 0x1) * 40; 2345 2346 cpuspeed = (bus_clock * mult) / 1000; 2347 } 2348 2349 int 2350 pentium_cpuspeed(int *freq) 2351 { 2352 *freq = cpuspeed; 2353 return (0); 2354 } 2355 #endif /* !SMALL_KERNEL */ 2356 2357 /* 2358 * Send an interrupt to process. 2359 * 2360 * Stack is set up to allow sigcode stored 2361 * in u. to call routine, followed by kcall 2362 * to sigreturn routine below. After sigreturn 2363 * resets the signal mask, the stack, and the 2364 * frame pointer, it returns to the user 2365 * specified pc, psl. 2366 */ 2367 int 2368 sendsig(sig_t catcher, int sig, sigset_t mask, const siginfo_t *ksip, 2369 int info, int onstack) 2370 { 2371 struct proc *p = curproc; 2372 struct trapframe *tf = p->p_md.md_regs; 2373 struct sigframe *fp, frame; 2374 register_t sp; 2375 2376 /* 2377 * Build the argument list for the signal handler. 2378 */ 2379 bzero(&frame, sizeof(frame)); 2380 frame.sf_signum = sig; 2381 2382 /* 2383 * Allocate space for the signal handler context. 2384 */ 2385 if ((p->p_sigstk.ss_flags & SS_DISABLE) == 0 && 2386 !sigonstack(tf->tf_esp) && onstack) 2387 sp = trunc_page((vaddr_t)p->p_sigstk.ss_sp + p->p_sigstk.ss_size); 2388 else 2389 sp = tf->tf_esp; 2390 2391 frame.sf_sc.sc_fpstate = NULL; 2392 if (p->p_md.md_flags & MDP_USEDFPU) { 2393 npxsave_proc(p, 1); 2394 sp -= sizeof(union savefpu); 2395 sp &= ~0xf; /* for XMM regs */ 2396 frame.sf_sc.sc_fpstate = (void *)sp; 2397 if (copyout(&p->p_addr->u_pcb.pcb_savefpu, 2398 (void *)sp, sizeof(union savefpu))) 2399 return 1; 2400 2401 /* Signal handlers get a completely clean FP state */ 2402 p->p_md.md_flags &= ~MDP_USEDFPU; 2403 } 2404 2405 fp = (struct sigframe *)sp - 1; 2406 frame.sf_scp = &fp->sf_sc; 2407 frame.sf_sip = NULL; 2408 frame.sf_handler = catcher; 2409 2410 /* 2411 * Build the signal context to be used by sigreturn. 2412 */ 2413 frame.sf_sc.sc_err = tf->tf_err; 2414 frame.sf_sc.sc_trapno = tf->tf_trapno; 2415 frame.sf_sc.sc_mask = mask; 2416 frame.sf_sc.sc_fs = tf->tf_fs; 2417 frame.sf_sc.sc_gs = tf->tf_gs; 2418 frame.sf_sc.sc_es = tf->tf_es; 2419 frame.sf_sc.sc_ds = tf->tf_ds; 2420 frame.sf_sc.sc_eflags = tf->tf_eflags; 2421 frame.sf_sc.sc_edi = tf->tf_edi; 2422 frame.sf_sc.sc_esi = tf->tf_esi; 2423 frame.sf_sc.sc_ebp = tf->tf_ebp; 2424 frame.sf_sc.sc_ebx = tf->tf_ebx; 2425 frame.sf_sc.sc_edx = tf->tf_edx; 2426 frame.sf_sc.sc_ecx = tf->tf_ecx; 2427 frame.sf_sc.sc_eax = tf->tf_eax; 2428 frame.sf_sc.sc_eip = tf->tf_eip; 2429 frame.sf_sc.sc_cs = tf->tf_cs; 2430 frame.sf_sc.sc_esp = tf->tf_esp; 2431 frame.sf_sc.sc_ss = tf->tf_ss; 2432 2433 if (info) { 2434 frame.sf_sip = &fp->sf_si; 2435 frame.sf_si = *ksip; 2436 } 2437 2438 /* XXX don't copyout siginfo if not needed? */ 2439 frame.sf_sc.sc_cookie = (long)&fp->sf_sc ^ p->p_p->ps_sigcookie; 2440 if (copyout(&frame, fp, sizeof(frame)) != 0) 2441 return 1; 2442 2443 /* 2444 * Build context to run handler in. 2445 */ 2446 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2447 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2448 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2449 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2450 tf->tf_eip = p->p_p->ps_sigcode; 2451 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2452 tf->tf_eflags &= ~(PSL_T|PSL_D|PSL_VM|PSL_AC); 2453 tf->tf_esp = (int)fp; 2454 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2455 2456 return 0; 2457 } 2458 2459 /* 2460 * System call to cleanup state after a signal 2461 * has been taken. Reset signal mask and 2462 * stack state from context left by sendsig (above). 2463 * Return to previous pc and psl as specified by 2464 * context left by sendsig. Check carefully to 2465 * make sure that the user has not modified the 2466 * psl to gain improper privileges or to cause 2467 * a machine fault. 2468 */ 2469 int 2470 sys_sigreturn(struct proc *p, void *v, register_t *retval) 2471 { 2472 struct sys_sigreturn_args /* { 2473 syscallarg(struct sigcontext *) sigcntxp; 2474 } */ *uap = v; 2475 struct sigcontext ksc, *scp = SCARG(uap, sigcntxp); 2476 struct trapframe *tf = p->p_md.md_regs; 2477 int error; 2478 2479 if (PROC_PC(p) != p->p_p->ps_sigcoderet) { 2480 sigexit(p, SIGILL); 2481 return (EPERM); 2482 } 2483 2484 if ((error = copyin((caddr_t)scp, &ksc, sizeof(*scp)))) 2485 return (error); 2486 2487 if (ksc.sc_cookie != ((long)scp ^ p->p_p->ps_sigcookie)) { 2488 sigexit(p, SIGILL); 2489 return (EFAULT); 2490 } 2491 2492 /* Prevent reuse of the sigcontext cookie */ 2493 ksc.sc_cookie = 0; 2494 (void)copyout(&ksc.sc_cookie, (caddr_t)scp + 2495 offsetof(struct sigcontext, sc_cookie), sizeof (ksc.sc_cookie)); 2496 2497 /* 2498 * Restore signal ksc. 2499 */ 2500 /* 2501 * Check for security violations. If we're returning to 2502 * protected mode, the CPU will validate the segment registers 2503 * automatically and generate a trap on violations. We handle 2504 * the trap, rather than doing all of the checking here. 2505 */ 2506 if (((ksc.sc_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 || 2507 !USERMODE(ksc.sc_cs, ksc.sc_eflags)) 2508 return (EINVAL); 2509 2510 tf->tf_fs = ksc.sc_fs; 2511 tf->tf_gs = ksc.sc_gs; 2512 tf->tf_es = ksc.sc_es; 2513 tf->tf_ds = ksc.sc_ds; 2514 tf->tf_eflags = ksc.sc_eflags; 2515 tf->tf_edi = ksc.sc_edi; 2516 tf->tf_esi = ksc.sc_esi; 2517 tf->tf_ebp = ksc.sc_ebp; 2518 tf->tf_ebx = ksc.sc_ebx; 2519 tf->tf_edx = ksc.sc_edx; 2520 tf->tf_ecx = ksc.sc_ecx; 2521 tf->tf_eax = ksc.sc_eax; 2522 tf->tf_eip = ksc.sc_eip; 2523 tf->tf_cs = ksc.sc_cs; 2524 tf->tf_esp = ksc.sc_esp; 2525 tf->tf_ss = ksc.sc_ss; 2526 2527 if (p->p_md.md_flags & MDP_USEDFPU) 2528 npxsave_proc(p, 0); 2529 2530 if (ksc.sc_fpstate) { 2531 union savefpu *sfp = &p->p_addr->u_pcb.pcb_savefpu; 2532 2533 if ((error = copyin(ksc.sc_fpstate, sfp, sizeof(*sfp)))) 2534 return (error); 2535 if (i386_use_fxsave) 2536 sfp->sv_xmm.sv_env.en_mxcsr &= fpu_mxcsr_mask; 2537 p->p_md.md_flags |= MDP_USEDFPU; 2538 } 2539 2540 p->p_sigmask = ksc.sc_mask & ~sigcantmask; 2541 2542 return (EJUSTRETURN); 2543 } 2544 2545 #ifdef MULTIPROCESSOR 2546 /* force a CPU into the kernel, whether or not it's idle */ 2547 void 2548 cpu_kick(struct cpu_info *ci) 2549 { 2550 /* only need to kick other CPUs */ 2551 if (ci != curcpu()) { 2552 if (cpu_mwait_size > 0) { 2553 /* 2554 * If not idling, then send an IPI, else 2555 * just clear the "keep idling" bit. 2556 */ 2557 if ((ci->ci_mwait & MWAIT_IN_IDLE) == 0) 2558 i386_send_ipi(ci, I386_IPI_NOP); 2559 else 2560 atomic_clearbits_int(&ci->ci_mwait, 2561 MWAIT_KEEP_IDLING); 2562 } else { 2563 /* no mwait, so need an IPI */ 2564 i386_send_ipi(ci, I386_IPI_NOP); 2565 } 2566 } 2567 } 2568 #endif 2569 2570 /* 2571 * Notify the current process (p) that it has a signal pending, 2572 * process as soon as possible. 2573 */ 2574 void 2575 signotify(struct proc *p) 2576 { 2577 aston(p); 2578 cpu_kick(p->p_cpu); 2579 } 2580 2581 #ifdef MULTIPROCESSOR 2582 void 2583 cpu_unidle(struct cpu_info *ci) 2584 { 2585 if (cpu_mwait_size > 0 && (ci->ci_mwait & MWAIT_ONLY)) { 2586 /* 2587 * Just clear the "keep idling" bit; if it wasn't 2588 * idling then we didn't need to do anything anyway. 2589 */ 2590 atomic_clearbits_int(&ci->ci_mwait, MWAIT_KEEP_IDLING); 2591 return; 2592 } 2593 2594 if (ci != curcpu()) 2595 i386_send_ipi(ci, I386_IPI_NOP); 2596 } 2597 #endif 2598 2599 int waittime = -1; 2600 struct pcb dumppcb; 2601 2602 __dead void 2603 boot(int howto) 2604 { 2605 if ((howto & RB_POWERDOWN) != 0) 2606 lid_action = 0; 2607 2608 if ((howto & RB_RESET) != 0) 2609 goto doreset; 2610 2611 if (cold) { 2612 if ((howto & RB_USERREQ) == 0) 2613 howto |= RB_HALT; 2614 goto haltsys; 2615 } 2616 2617 boothowto = howto; 2618 if ((howto & RB_NOSYNC) == 0 && waittime < 0) { 2619 waittime = 0; 2620 vfs_shutdown(curproc); 2621 2622 if ((howto & RB_TIMEBAD) == 0) { 2623 resettodr(); 2624 } else { 2625 printf("WARNING: not updating battery clock\n"); 2626 } 2627 } 2628 if_downall(); 2629 2630 uvm_shutdown(); 2631 splhigh(); 2632 cold = 1; 2633 2634 if ((howto & RB_DUMP) != 0) 2635 dumpsys(); 2636 2637 haltsys: 2638 config_suspend_all(DVACT_POWERDOWN); 2639 2640 #ifdef MULTIPROCESSOR 2641 i386_broadcast_ipi(I386_IPI_HALT); 2642 #endif 2643 2644 if ((howto & RB_HALT) != 0) { 2645 #if NACPI > 0 && !defined(SMALL_KERNEL) 2646 extern int acpi_enabled; 2647 2648 if (acpi_enabled) { 2649 delay(500000); 2650 if ((howto & RB_POWERDOWN) != 0) 2651 acpi_powerdown(); 2652 } 2653 #endif 2654 2655 #if NAPM > 0 2656 if ((howto & RB_POWERDOWN) != 0) { 2657 int rv; 2658 2659 printf("\nAttempting to power down...\n"); 2660 /* 2661 * Turn off, if we can. But try to turn disk off and 2662 * wait a bit first--some disk drives are slow to 2663 * clean up and users have reported disk corruption. 2664 * 2665 * If apm_set_powstate() fails the first time, don't 2666 * try to turn the system off. 2667 */ 2668 delay(500000); 2669 apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2670 delay(500000); 2671 rv = apm_set_powstate(APM_DEV_DISK(0xff), APM_SYS_OFF); 2672 if (rv == 0 || rv == ENXIO) { 2673 delay(500000); 2674 (void) apm_set_powstate(APM_DEV_ALLDEVS, 2675 APM_SYS_OFF); 2676 } 2677 } 2678 #endif 2679 printf("\n"); 2680 printf("The operating system has halted.\n"); 2681 printf("Please press any key to reboot.\n\n"); 2682 cnpollc(1); /* for proper keyboard command handling */ 2683 cngetc(); 2684 cnpollc(0); 2685 } 2686 2687 doreset: 2688 printf("rebooting...\n"); 2689 cpu_reset(); 2690 for (;;) 2691 continue; 2692 /* NOTREACHED */ 2693 } 2694 2695 /* 2696 * This is called by configure to set dumplo and dumpsize. 2697 * Dumps always skip the first block of disk space 2698 * in case there might be a disk label stored there. 2699 * If there is extra space, put dump at the end to 2700 * reduce the chance that swapping trashes it. 2701 */ 2702 void 2703 dumpconf(void) 2704 { 2705 int nblks; /* size of dump area */ 2706 int i; 2707 2708 if (dumpdev == NODEV || 2709 (nblks = (bdevsw[major(dumpdev)].d_psize)(dumpdev)) == 0) 2710 return; 2711 if (nblks <= ctod(1)) 2712 return; 2713 2714 /* Always skip the first block, in case there is a label there. */ 2715 if (dumplo < ctod(1)) 2716 dumplo = ctod(1); 2717 2718 for (i = 0; i < ndumpmem; i++) 2719 dumpsize = max(dumpsize, dumpmem[i].end); 2720 2721 /* Put dump at end of partition, and make it fit. */ 2722 if (dumpsize > dtoc(nblks - dumplo - 1)) 2723 dumpsize = dtoc(nblks - dumplo - 1); 2724 if (dumplo < nblks - ctod(dumpsize) - 1) 2725 dumplo = nblks - ctod(dumpsize) - 1; 2726 } 2727 2728 /* 2729 * cpu_dump: dump machine-dependent kernel core dump headers. 2730 */ 2731 int 2732 cpu_dump(void) 2733 { 2734 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2735 long buf[dbtob(1) / sizeof (long)]; 2736 kcore_seg_t *segp; 2737 2738 dump = bdevsw[major(dumpdev)].d_dump; 2739 2740 segp = (kcore_seg_t *)buf; 2741 2742 /* 2743 * Generate a segment header. 2744 */ 2745 CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); 2746 segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); 2747 2748 return (dump(dumpdev, dumplo, (caddr_t)buf, dbtob(1))); 2749 } 2750 2751 /* 2752 * Doadump comes here after turning off memory management and 2753 * getting on the dump stack, either when called above, or by 2754 * the auto-restart code. 2755 */ 2756 static vaddr_t dumpspace; 2757 2758 vaddr_t 2759 reserve_dumppages(vaddr_t p) 2760 { 2761 2762 dumpspace = p; 2763 return (p + PAGE_SIZE); 2764 } 2765 2766 void 2767 dumpsys(void) 2768 { 2769 u_int i, j, npg; 2770 int maddr; 2771 daddr_t blkno; 2772 int (*dump)(dev_t, daddr_t, caddr_t, size_t); 2773 int error; 2774 char *str; 2775 extern int msgbufmapped; 2776 2777 /* Save registers. */ 2778 savectx(&dumppcb); 2779 2780 msgbufmapped = 0; /* don't record dump msgs in msgbuf */ 2781 if (dumpdev == NODEV) 2782 return; 2783 2784 /* 2785 * For dumps during autoconfiguration, 2786 * if dump device has already configured... 2787 */ 2788 if (dumpsize == 0) 2789 dumpconf(); 2790 if (dumplo < 0) 2791 return; 2792 printf("\ndumping to dev %x, offset %ld\n", dumpdev, dumplo); 2793 2794 error = (*bdevsw[major(dumpdev)].d_psize)(dumpdev); 2795 printf("dump "); 2796 if (error == -1) { 2797 printf("area unavailable\n"); 2798 return; 2799 } 2800 2801 #if 0 /* XXX this doesn't work. grr. */ 2802 /* toss any characters present prior to dump */ 2803 while (sget() != NULL); /*syscons and pccons differ */ 2804 #endif 2805 2806 /* scan through the dumpmem list */ 2807 dump = bdevsw[major(dumpdev)].d_dump; 2808 error = cpu_dump(); 2809 for (i = 0; !error && i < ndumpmem; i++) { 2810 2811 npg = dumpmem[i].end - dumpmem[i].start; 2812 maddr = ptoa(dumpmem[i].start); 2813 blkno = dumplo + btodb(maddr) + 1; 2814 #if 0 2815 printf("(%d %lld %d) ", maddr, (long long)blkno, npg); 2816 #endif 2817 for (j = npg; j--; maddr += NBPG, blkno += btodb(NBPG)) { 2818 2819 /* Print out how many MBs we have more to go. */ 2820 if (dbtob(blkno - dumplo) % (1024 * 1024) < NBPG) 2821 printf("%ld ", 2822 (ptoa(dumpsize) - maddr) / (1024 * 1024)); 2823 #if 0 2824 printf("(%x %lld) ", maddr, (long long)blkno); 2825 #endif 2826 pmap_enter(pmap_kernel(), dumpspace, maddr, 2827 PROT_READ, PMAP_WIRED); 2828 if ((error = (*dump)(dumpdev, blkno, 2829 (caddr_t)dumpspace, NBPG))) 2830 break; 2831 2832 #if 0 /* XXX this doesn't work. grr. */ 2833 /* operator aborting dump? */ 2834 if (sget() != NULL) { 2835 error = EINTR; 2836 break; 2837 } 2838 #endif 2839 } 2840 } 2841 2842 switch (error) { 2843 2844 case 0: str = "succeeded\n\n"; break; 2845 case ENXIO: str = "device bad\n\n"; break; 2846 case EFAULT: str = "device not ready\n\n"; break; 2847 case EINVAL: str = "area improper\n\n"; break; 2848 case EIO: str = "i/o error\n\n"; break; 2849 case EINTR: str = "aborted from console\n\n"; break; 2850 default: str = "error %d\n\n"; break; 2851 } 2852 printf(str, error); 2853 2854 delay(5000000); /* 5 seconds */ 2855 } 2856 2857 /* 2858 * Clear registers on exec 2859 */ 2860 void 2861 setregs(struct proc *p, struct exec_package *pack, u_long stack, 2862 struct ps_strings *arginfo) 2863 { 2864 struct pcb *pcb = &p->p_addr->u_pcb; 2865 struct pmap *pmap = vm_map_pmap(&p->p_vmspace->vm_map); 2866 struct trapframe *tf = p->p_md.md_regs; 2867 2868 #if NNPX > 0 2869 /* If we were using the FPU, forget about it. */ 2870 if (pcb->pcb_fpcpu != NULL) 2871 npxsave_proc(p, 0); 2872 p->p_md.md_flags &= ~MDP_USEDFPU; 2873 #endif 2874 2875 initcodesegment(&pmap->pm_codeseg); 2876 setsegment(&pcb->pcb_threadsegs[TSEG_FS], 0, 2877 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2878 setsegment(&pcb->pcb_threadsegs[TSEG_GS], 0, 2879 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 2880 2881 /* 2882 * And update the GDT since we return to the user process 2883 * by leaving the syscall (we don't do another pmap_activate()). 2884 */ 2885 curcpu()->ci_gdt[GUCODE_SEL].sd = pmap->pm_codeseg; 2886 curcpu()->ci_gdt[GUFS_SEL].sd = pcb->pcb_threadsegs[TSEG_FS]; 2887 curcpu()->ci_gdt[GUGS_SEL].sd = pcb->pcb_threadsegs[TSEG_GS]; 2888 2889 /* 2890 * And reset the hiexec marker in the pmap. 2891 */ 2892 pmap->pm_hiexec = 0; 2893 2894 tf->tf_fs = GSEL(GUFS_SEL, SEL_UPL); 2895 tf->tf_gs = GSEL(GUGS_SEL, SEL_UPL); 2896 tf->tf_es = GSEL(GUDATA_SEL, SEL_UPL); 2897 tf->tf_ds = GSEL(GUDATA_SEL, SEL_UPL); 2898 tf->tf_edi = 0; 2899 tf->tf_esi = 0; 2900 tf->tf_ebp = 0; 2901 tf->tf_ebx = (int)p->p_p->ps_strings; 2902 tf->tf_edx = 0; 2903 tf->tf_ecx = 0; 2904 tf->tf_eax = 0; 2905 tf->tf_eip = pack->ep_entry; 2906 tf->tf_cs = GSEL(GUCODE_SEL, SEL_UPL); 2907 tf->tf_eflags = PSL_USERSET; 2908 tf->tf_esp = stack; 2909 tf->tf_ss = GSEL(GUDATA_SEL, SEL_UPL); 2910 } 2911 2912 /* 2913 * Initialize segments and descriptor tables 2914 */ 2915 2916 /* IDT is now a full page, so we can map it in u-k */ 2917 union { 2918 struct gate_descriptor idt[NIDT]; 2919 char align[PAGE_SIZE]; 2920 } _idt_region __aligned(PAGE_SIZE); 2921 #define idt_region _idt_region.idt 2922 struct gate_descriptor *idt = idt_region; 2923 2924 extern struct user *proc0paddr; 2925 2926 void 2927 setgate(struct gate_descriptor *gd, void *func, int args, int type, int dpl, 2928 int seg) 2929 { 2930 2931 gd->gd_looffset = (int)func; 2932 gd->gd_selector = GSEL(seg, SEL_KPL); 2933 gd->gd_stkcpy = args; 2934 gd->gd_xx = 0; 2935 gd->gd_type = type; 2936 gd->gd_dpl = dpl; 2937 gd->gd_p = 1; 2938 gd->gd_hioffset = (int)func >> 16; 2939 } 2940 2941 void 2942 unsetgate(struct gate_descriptor *gd) 2943 { 2944 gd->gd_p = 0; 2945 gd->gd_hioffset = 0; 2946 gd->gd_looffset = 0; 2947 gd->gd_selector = 0; 2948 gd->gd_xx = 0; 2949 gd->gd_stkcpy = 0; 2950 gd->gd_type = 0; 2951 gd->gd_dpl = 0; 2952 } 2953 2954 void 2955 setregion(struct region_descriptor *rd, void *base, size_t limit) 2956 { 2957 rd->rd_limit = (int)limit; 2958 rd->rd_base = (int)base; 2959 } 2960 2961 void 2962 initcodesegment(struct segment_descriptor *cs) 2963 { 2964 if (cpu_pae) { 2965 /* 2966 * When code execution is managed using NX feature 2967 * in pmapae.c, GUCODE_SEL should cover userland. 2968 */ 2969 setsegment(cs, 0, atop(VM_MAXUSER_ADDRESS - 1), 2970 SDT_MEMERA, SEL_UPL, 1, 1); 2971 } else { 2972 /* 2973 * For pmap.c's non-PAE/NX line-in-the-sand execution, reset 2974 * the code segment limit to I386_MAX_EXE_ADDR in the pmap; 2975 * this gets copied into the GDT for GUCODE_SEL by 2976 * pmap_activate(). Similarly, reset the base of each of 2977 * the two thread data segments to zero in the pcb; they'll 2978 * get copied into the GDT for GUFS_SEL and GUGS_SEL. 2979 */ 2980 setsegment(cs, 0, atop(I386_MAX_EXE_ADDR - 1), 2981 SDT_MEMERA, SEL_UPL, 1, 1); 2982 } 2983 } 2984 2985 void 2986 setsegment(struct segment_descriptor *sd, void *base, size_t limit, int type, 2987 int dpl, int def32, int gran) 2988 { 2989 2990 sd->sd_lolimit = (int)limit; 2991 sd->sd_lobase = (int)base; 2992 sd->sd_type = type; 2993 sd->sd_dpl = dpl; 2994 sd->sd_p = 1; 2995 sd->sd_hilimit = (int)limit >> 16; 2996 sd->sd_xx = 0; 2997 sd->sd_def32 = def32; 2998 sd->sd_gran = gran; 2999 sd->sd_hibase = (int)base >> 24; 3000 } 3001 3002 #define IDTVEC(name) __CONCAT(X, name) 3003 extern int IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 3004 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(dble), IDTVEC(fpusegm), 3005 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), IDTVEC(page), 3006 IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), IDTVEC(syscall), IDTVEC(mchk), 3007 IDTVEC(simd); 3008 3009 extern int IDTVEC(f00f_redirect); 3010 3011 int cpu_f00f_bug = 0; 3012 3013 void 3014 fix_f00f(void) 3015 { 3016 struct region_descriptor region; 3017 vaddr_t va; 3018 paddr_t pa; 3019 void *p; 3020 3021 /* Allocate two new pages */ 3022 va = (vaddr_t)km_alloc(NBPG*2, &kv_any, &kp_zero, &kd_waitok); 3023 p = (void *)(va + NBPG - 7*sizeof(*idt)); 3024 3025 /* Copy over old IDT */ 3026 bcopy(idt, p, sizeof(idt_region)); 3027 idt = p; 3028 3029 /* Fix up paging redirect */ 3030 setgate(&idt[ 14], &IDTVEC(f00f_redirect), 0, SDT_SYS386IGT, SEL_KPL, 3031 GCODE_SEL); 3032 3033 /* Map first page RO */ 3034 pmap_pte_setbits(va, 0, PG_RW); 3035 3036 /* add k-u read-only mappings XXX old IDT stays in place */ 3037 /* XXX hshoexer: are f00f affected CPUs affected by meltdown? */ 3038 pmap_extract(pmap_kernel(), va, &pa); 3039 pmap_enter_special(va, pa, PROT_READ, 0); 3040 pmap_extract(pmap_kernel(), va + PAGE_SIZE, &pa); 3041 pmap_enter_special(va + PAGE_SIZE, pa, PROT_READ, 0); 3042 3043 /* Reload idtr */ 3044 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3045 lidt(®ion); 3046 3047 /* Tell the rest of the world */ 3048 cpu_f00f_bug = 1; 3049 } 3050 3051 #ifdef MULTIPROCESSOR 3052 void 3053 cpu_init_idt(void) 3054 { 3055 struct region_descriptor region; 3056 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3057 lidt(®ion); 3058 } 3059 #endif /* MULTIPROCESSOR */ 3060 3061 void 3062 init386(paddr_t first_avail) 3063 { 3064 int i, kb; 3065 struct region_descriptor region; 3066 bios_memmap_t *im; 3067 3068 proc0.p_addr = proc0paddr; 3069 cpu_info_primary.ci_self = &cpu_info_primary; 3070 cpu_info_primary.ci_curpcb = &proc0.p_addr->u_pcb; 3071 cpu_info_primary.ci_tss = &cpu_info_full_primary.cif_tss; 3072 cpu_info_primary.ci_nmi_tss = &cpu_info_full_primary.cif_nmi_tss; 3073 cpu_info_primary.ci_gdt = (void *)&cpu_info_full_primary.cif_gdt; 3074 3075 /* make bootstrap gdt gates and memory segments */ 3076 setsegment(&cpu_info_primary.ci_gdt[GCODE_SEL].sd, 0, 0xfffff, 3077 SDT_MEMERA, SEL_KPL, 1, 1); 3078 setsegment(&cpu_info_primary.ci_gdt[GICODE_SEL].sd, 0, 0xfffff, 3079 SDT_MEMERA, SEL_KPL, 1, 1); 3080 setsegment(&cpu_info_primary.ci_gdt[GDATA_SEL].sd, 0, 0xfffff, 3081 SDT_MEMRWA, SEL_KPL, 1, 1); 3082 setsegment(&cpu_info_primary.ci_gdt[GUCODE_SEL].sd, 0, 3083 atop(I386_MAX_EXE_ADDR) - 1, SDT_MEMERA, SEL_UPL, 1, 1); 3084 setsegment(&cpu_info_primary.ci_gdt[GUDATA_SEL].sd, 0, 3085 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3086 setsegment(&cpu_info_primary.ci_gdt[GCPU_SEL].sd, &cpu_info_primary, 3087 sizeof(struct cpu_info)-1, SDT_MEMRWA, SEL_KPL, 0, 0); 3088 setsegment(&cpu_info_primary.ci_gdt[GUFS_SEL].sd, 0, 3089 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3090 setsegment(&cpu_info_primary.ci_gdt[GUGS_SEL].sd, 0, 3091 atop(VM_MAXUSER_ADDRESS) - 1, SDT_MEMRWA, SEL_UPL, 1, 1); 3092 setsegment(&cpu_info_primary.ci_gdt[GTSS_SEL].sd, 3093 cpu_info_primary.ci_tss, sizeof(struct i386tss)-1, 3094 SDT_SYS386TSS, SEL_KPL, 0, 0); 3095 setsegment(&cpu_info_primary.ci_gdt[GNMITSS_SEL].sd, 3096 cpu_info_primary.ci_nmi_tss, sizeof(struct i386tss)-1, 3097 SDT_SYS386TSS, SEL_KPL, 0, 0); 3098 3099 /* exceptions */ 3100 setgate(&idt[ 0], &IDTVEC(div), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3101 setgate(&idt[ 1], &IDTVEC(dbg), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3102 setgate(&idt[ 2], NULL, 0, SDT_SYSTASKGT, SEL_KPL, GNMITSS_SEL); 3103 setgate(&idt[ 3], &IDTVEC(bpt), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3104 setgate(&idt[ 4], &IDTVEC(ofl), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3105 setgate(&idt[ 5], &IDTVEC(bnd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3106 setgate(&idt[ 6], &IDTVEC(ill), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3107 setgate(&idt[ 7], &IDTVEC(dna), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3108 setgate(&idt[ 8], &IDTVEC(dble), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3109 setgate(&idt[ 9], &IDTVEC(fpusegm), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3110 setgate(&idt[ 10], &IDTVEC(tss), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3111 setgate(&idt[ 11], &IDTVEC(missing), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3112 setgate(&idt[ 12], &IDTVEC(stk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3113 setgate(&idt[ 13], &IDTVEC(prot), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3114 setgate(&idt[ 14], &IDTVEC(page), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3115 setgate(&idt[ 15], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3116 setgate(&idt[ 16], &IDTVEC(fpu), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3117 setgate(&idt[ 17], &IDTVEC(align), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3118 setgate(&idt[ 18], &IDTVEC(mchk), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3119 setgate(&idt[ 19], &IDTVEC(simd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3120 for (i = 20; i < NRSVIDT; i++) 3121 setgate(&idt[i], &IDTVEC(rsvd), 0, SDT_SYS386IGT, SEL_KPL, GCODE_SEL); 3122 for (i = NRSVIDT; i < NIDT; i++) 3123 unsetgate(&idt[i]); 3124 setgate(&idt[128], &IDTVEC(syscall), 0, SDT_SYS386IGT, SEL_UPL, GCODE_SEL); 3125 3126 setregion(®ion, cpu_info_primary.ci_gdt, GDT_SIZE - 1); 3127 lgdt(®ion); 3128 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3129 lidt(®ion); 3130 3131 /* 3132 * Initialize the I/O port and I/O mem extent maps. 3133 * Note: we don't have to check the return value since 3134 * creation of a fixed extent map will never fail (since 3135 * descriptor storage has already been allocated). 3136 * 3137 * N.B. The iomem extent manages _all_ physical addresses 3138 * on the machine. When the amount of RAM is found, the two 3139 * extents of RAM are allocated from the map (0 -> ISA hole 3140 * and end of ISA hole -> end of RAM). 3141 */ 3142 ioport_ex = extent_create("ioport", 0x0, 0xffff, M_DEVBUF, 3143 (caddr_t)ioport_ex_storage, sizeof(ioport_ex_storage), 3144 EX_NOCOALESCE|EX_NOWAIT); 3145 iomem_ex = extent_create("iomem", 0x0, 0xffffffff, M_DEVBUF, 3146 (caddr_t)iomem_ex_storage, sizeof(iomem_ex_storage), 3147 EX_NOCOALESCE|EX_NOWAIT); 3148 3149 #if NISA > 0 3150 isa_defaultirq(); 3151 #endif 3152 3153 /* 3154 * Attach the glass console early in case we need to display a panic. 3155 */ 3156 cninit(); 3157 3158 /* 3159 * Saving SSE registers won't work if the save area isn't 3160 * 16-byte aligned. 3161 */ 3162 if (offsetof(struct user, u_pcb.pcb_savefpu) & 0xf) 3163 panic("init386: pcb_savefpu not 16-byte aligned"); 3164 3165 /* call pmap initialization to make new kernel address space */ 3166 pmap_bootstrap((vaddr_t)atdevbase + IOM_SIZE); 3167 3168 /* 3169 * Boot arguments are in a single page specified by /boot. 3170 * 3171 * We require the "new" vector form, as well as memory ranges 3172 * to be given in bytes rather than KB. 3173 */ 3174 if ((bootapiver & (BAPIV_VECTOR | BAPIV_BMEMMAP)) == 3175 (BAPIV_VECTOR | BAPIV_BMEMMAP)) { 3176 if (bootargc > NBPG) 3177 panic("too many boot args"); 3178 3179 if (extent_alloc_region(iomem_ex, (paddr_t)bootargv, bootargc, 3180 EX_NOWAIT)) 3181 panic("cannot reserve /boot args memory"); 3182 3183 pmap_enter(pmap_kernel(), (vaddr_t)bootargp, (paddr_t)bootargv, 3184 PROT_READ | PROT_WRITE, 3185 PROT_READ | PROT_WRITE | PMAP_WIRED); 3186 3187 bios_getopt(); 3188 3189 } else 3190 panic("/boot too old: upgrade!"); 3191 3192 #ifdef DIAGNOSTIC 3193 if (bios_memmap == NULL) 3194 panic("no BIOS memory map supplied"); 3195 #endif 3196 3197 /* 3198 * account all the memory passed in the map from /boot 3199 * calculate avail_end and count the physmem. 3200 */ 3201 avail_end = 0; 3202 physmem = 0; 3203 #ifdef DEBUG 3204 printf("memmap:"); 3205 #endif 3206 for(i = 0, im = bios_memmap; im->type != BIOS_MAP_END; im++) 3207 if (im->type == BIOS_MAP_FREE) { 3208 paddr_t a, e; 3209 #ifdef DEBUG 3210 printf(" %llx-%llx", im->addr, im->addr + im->size); 3211 #endif 3212 3213 if (im->addr >= 0x100000000ULL) { 3214 #ifdef DEBUG 3215 printf("-H"); 3216 #endif 3217 continue; 3218 } 3219 3220 a = round_page(im->addr); 3221 if (im->addr + im->size <= 0xfffff000ULL) 3222 e = trunc_page(im->addr + im->size); 3223 else { 3224 #ifdef DEBUG 3225 printf("-T"); 3226 #endif 3227 e = 0xfffff000; 3228 } 3229 3230 /* skip first 16 pages due to SMI corruption */ 3231 if (a < 16 * NBPG) 3232 a = 16 * NBPG; 3233 3234 #ifdef MULTIPROCESSOR 3235 /* skip MP trampoline code page */ 3236 if (a < MP_TRAMPOLINE + NBPG) 3237 a = MP_TRAMPOLINE + NBPG; 3238 3239 /* skip MP trampoline data page */ 3240 if (a < MP_TRAMP_DATA + NBPG) 3241 a = MP_TRAMP_DATA + NBPG; 3242 #endif /* MULTIPROCESSOR */ 3243 3244 #if NACPI > 0 && !defined(SMALL_KERNEL) 3245 /* skip ACPI resume trampoline code page */ 3246 if (a < ACPI_TRAMPOLINE + NBPG) 3247 a = ACPI_TRAMPOLINE + NBPG; 3248 3249 /* skip ACPI resume trampoline data page */ 3250 if (a < ACPI_TRAMP_DATA + NBPG) 3251 a = ACPI_TRAMP_DATA + NBPG; 3252 #endif /* ACPI */ 3253 3254 #ifdef HIBERNATE 3255 /* skip hibernate reserved pages */ 3256 if (a < HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE) 3257 a = HIBERNATE_HIBALLOC_PAGE + PAGE_SIZE; 3258 #endif /* HIBERNATE */ 3259 3260 /* skip shorter than page regions */ 3261 if (a >= e || (e - a) < NBPG) { 3262 #ifdef DEBUG 3263 printf("-S"); 3264 #endif 3265 continue; 3266 } 3267 3268 /* 3269 * XXX Some buggy ACPI BIOSes use memory that 3270 * they declare as free. Current worst offender 3271 * is Supermicro 5019D-FTN4. Typically the 3272 * affected memory areas are small blocks 3273 * between areas reserved for ACPI and other 3274 * BIOS goo. So skip areas smaller than 32 MB 3275 * above the 16 MB boundary (to avoid 3276 * affecting legacy stuff). 3277 */ 3278 if (a > 16*1024*1024 && (e - a) < 32*1024*1024) { 3279 #ifdef DEBUG 3280 printf("-X"); 3281 #endif 3282 continue; 3283 } 3284 3285 /* skip legacy IO region */ 3286 if ((a > IOM_BEGIN && a < IOM_END) || 3287 (e > IOM_BEGIN && e < IOM_END)) { 3288 #ifdef DEBUG 3289 printf("-I"); 3290 #endif 3291 continue; 3292 } 3293 3294 if (extent_alloc_region(iomem_ex, a, e - a, EX_NOWAIT)) 3295 /* XXX What should we do? */ 3296 printf("\nWARNING: CAN'T ALLOCATE RAM (%lx-%lx)" 3297 " FROM IOMEM EXTENT MAP!\n", a, e); 3298 3299 physmem += atop(e - a); 3300 dumpmem[i].start = atop(a); 3301 dumpmem[i].end = atop(e); 3302 i++; 3303 avail_end = max(avail_end, e); 3304 } 3305 3306 ndumpmem = i; 3307 avail_end -= round_page(MSGBUFSIZE); 3308 3309 #ifdef DEBUG 3310 printf(": %lx\n", avail_end); 3311 #endif 3312 if (physmem < atop(4 * 1024 * 1024)) { 3313 printf("\awarning: too little memory available;" 3314 "running in degraded mode\npress a key to confirm\n\n"); 3315 cnpollc(1); 3316 cngetc(); 3317 cnpollc(0); 3318 } 3319 3320 #ifdef DEBUG 3321 printf("physload: "); 3322 #endif 3323 kb = atop(KERNTEXTOFF - KERNBASE); 3324 if (kb > atop(IOM_END)) { 3325 paddr_t lim = atop(IOM_END); 3326 #ifdef DEBUG 3327 printf(" %lx-%x (<16M)", lim, kb); 3328 #endif 3329 uvm_page_physload(lim, kb, lim, kb, 0); 3330 } 3331 3332 for (i = 0; i < ndumpmem; i++) { 3333 paddr_t a, e; 3334 3335 a = dumpmem[i].start; 3336 e = dumpmem[i].end; 3337 if (a < atop(first_avail) && e > atop(first_avail)) 3338 a = atop(first_avail); 3339 if (e > atop(avail_end)) 3340 e = atop(avail_end); 3341 3342 if (a < e) { 3343 #ifdef DEBUG 3344 printf(" %lx-%lx", a, e); 3345 #endif 3346 uvm_page_physload(a, e, a, e, 0); 3347 } 3348 } 3349 #ifdef DEBUG 3350 printf("\n"); 3351 #endif 3352 3353 tlbflush(); 3354 #if 0 3355 #if NISADMA > 0 3356 /* 3357 * Some motherboards/BIOSes remap the 384K of RAM that would 3358 * normally be covered by the ISA hole to the end of memory 3359 * so that it can be used. However, on a 16M system, this 3360 * would cause bounce buffers to be allocated and used. 3361 * This is not desirable behaviour, as more than 384K of 3362 * bounce buffers might be allocated. As a work-around, 3363 * we round memory down to the nearest 1M boundary if 3364 * we're using any isadma devices and the remapped memory 3365 * is what puts us over 16M. 3366 */ 3367 if (extmem > (15*1024) && extmem < (16*1024)) { 3368 printf("Warning: ignoring %dk of remapped memory\n", 3369 extmem - (15*1024)); 3370 extmem = (15*1024); 3371 } 3372 #endif 3373 #endif 3374 3375 #ifdef DDB 3376 db_machine_init(); 3377 ddb_init(); 3378 if (boothowto & RB_KDB) 3379 db_enter(); 3380 #endif 3381 3382 softintr_init(); 3383 } 3384 3385 /* 3386 * consinit: 3387 * initialize the system console. 3388 */ 3389 void 3390 consinit(void) 3391 { 3392 /* Already done in init386(). */ 3393 } 3394 3395 void 3396 cpu_reset(void) 3397 { 3398 struct region_descriptor region; 3399 3400 intr_disable(); 3401 3402 if (cpuresetfn) 3403 (*cpuresetfn)(); 3404 3405 /* 3406 * The keyboard controller has 4 random output pins, one of which is 3407 * connected to the RESET pin on the CPU in many PCs. We tell the 3408 * keyboard controller to pulse this line a couple of times. 3409 */ 3410 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3411 delay(100000); 3412 outb(IO_KBD + KBCMDP, KBC_PULSE0); 3413 delay(100000); 3414 3415 /* 3416 * Try to cause a triple fault and watchdog reset by setting the 3417 * IDT to point to nothing. 3418 */ 3419 bzero((caddr_t)idt, sizeof(idt_region)); 3420 setregion(®ion, idt, NIDT * sizeof(idt[0]) - 1); 3421 lidt(®ion); 3422 __asm volatile("divl %0,%1" : : "q" (0), "a" (0)); 3423 3424 /* 3425 * Try to cause a triple fault and watchdog reset by unmapping the 3426 * entire address space. 3427 */ 3428 bzero((caddr_t)PTD, NBPG); 3429 tlbflush(); 3430 3431 for (;;) 3432 continue; 3433 /* NOTREACHED */ 3434 } 3435 3436 void 3437 cpu_initclocks(void) 3438 { 3439 (*initclock_func)(); /* lapic or i8254 */ 3440 } 3441 3442 void 3443 need_resched(struct cpu_info *ci) 3444 { 3445 ci->ci_want_resched = 1; 3446 3447 /* There's a risk we'll be called before the idle threads start */ 3448 if (ci->ci_curproc) { 3449 aston(ci->ci_curproc); 3450 cpu_kick(ci); 3451 } 3452 } 3453 3454 /* Allocate an IDT vector slot within the given range. 3455 * XXX needs locking to avoid MP allocation races. 3456 */ 3457 3458 int 3459 idt_vec_alloc(int low, int high) 3460 { 3461 int vec; 3462 3463 for (vec = low; vec <= high; vec++) 3464 if (idt[vec].gd_p == 0) 3465 return (vec); 3466 return (0); 3467 } 3468 3469 void 3470 idt_vec_set(int vec, void (*function)(void)) 3471 { 3472 setgate(&idt[vec], function, 0, SDT_SYS386IGT, SEL_KPL, GICODE_SEL); 3473 } 3474 3475 void 3476 idt_vec_free(int vec) 3477 { 3478 unsetgate(&idt[vec]); 3479 } 3480 3481 const struct sysctl_bounded_args cpuctl_vars[] = { 3482 { CPU_LIDACTION, &lid_action, 0, 2 }, 3483 { CPU_CPUID, &cpu_id, SYSCTL_INT_READONLY }, 3484 { CPU_OSFXSR, &i386_use_fxsave, SYSCTL_INT_READONLY }, 3485 { CPU_SSE, &i386_has_sse, SYSCTL_INT_READONLY }, 3486 { CPU_SSE2, &i386_has_sse2, SYSCTL_INT_READONLY }, 3487 { CPU_XCRYPT, &i386_has_xcrypt, SYSCTL_INT_READONLY }, 3488 }; 3489 3490 /* 3491 * machine dependent system variables. 3492 */ 3493 int 3494 cpu_sysctl(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp, 3495 size_t newlen, struct proc *p) 3496 { 3497 dev_t dev; 3498 3499 switch (name[0]) { 3500 case CPU_CONSDEV: 3501 if (namelen != 1) 3502 return (ENOTDIR); /* overloaded */ 3503 3504 if (cn_tab != NULL) 3505 dev = cn_tab->cn_dev; 3506 else 3507 dev = NODEV; 3508 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3509 #if NBIOS > 0 3510 case CPU_BIOS: 3511 return bios_sysctl(name + 1, namelen - 1, oldp, oldlenp, 3512 newp, newlen, p); 3513 #endif 3514 case CPU_BLK2CHR: 3515 if (namelen != 2) 3516 return (ENOTDIR); /* overloaded */ 3517 dev = blktochr((dev_t)name[1]); 3518 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3519 case CPU_CHR2BLK: 3520 if (namelen != 2) 3521 return (ENOTDIR); /* overloaded */ 3522 dev = chrtoblk((dev_t)name[1]); 3523 return sysctl_rdstruct(oldp, oldlenp, newp, &dev, sizeof(dev)); 3524 case CPU_ALLOWAPERTURE: 3525 #ifdef APERTURE 3526 if (securelevel > 0) 3527 return (sysctl_int_lower(oldp, oldlenp, newp, newlen, 3528 &allowaperture)); 3529 else 3530 return (sysctl_int(oldp, oldlenp, newp, newlen, 3531 &allowaperture)); 3532 #else 3533 return (sysctl_rdint(oldp, oldlenp, newp, 0)); 3534 #endif 3535 case CPU_CPUVENDOR: 3536 return (sysctl_rdstring(oldp, oldlenp, newp, cpu_vendor)); 3537 case CPU_CPUFEATURE: 3538 return (sysctl_rdint(oldp, oldlenp, newp, curcpu()->ci_feature_flags)); 3539 case CPU_KBDRESET: 3540 return (sysctl_securelevel_int(oldp, oldlenp, newp, newlen, 3541 &kbd_reset)); 3542 #if NPCKBC > 0 && NUKBD > 0 3543 case CPU_FORCEUKBD: 3544 { 3545 int error; 3546 3547 if (forceukbd) 3548 return (sysctl_rdint(oldp, oldlenp, newp, forceukbd)); 3549 3550 error = sysctl_int(oldp, oldlenp, newp, newlen, &forceukbd); 3551 if (forceukbd) 3552 pckbc_release_console(); 3553 return (error); 3554 } 3555 #endif 3556 default: 3557 return (sysctl_bounded_arr(cpuctl_vars, nitems(cpuctl_vars), 3558 name, namelen, oldp, oldlenp, newp, newlen)); 3559 } 3560 /* NOTREACHED */ 3561 } 3562 3563 int 3564 bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, int flags, 3565 bus_space_handle_t *bshp) 3566 { 3567 int error; 3568 struct extent *ex; 3569 3570 /* 3571 * Pick the appropriate extent map. 3572 */ 3573 if (t == I386_BUS_SPACE_IO) { 3574 ex = ioport_ex; 3575 if (flags & BUS_SPACE_MAP_LINEAR) 3576 return (EINVAL); 3577 } else if (t == I386_BUS_SPACE_MEM) { 3578 ex = iomem_ex; 3579 } else { 3580 panic("bus_space_map: bad bus space tag"); 3581 } 3582 3583 /* 3584 * Before we go any further, let's make sure that this 3585 * region is available. 3586 */ 3587 error = extent_alloc_region(ex, bpa, size, 3588 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0)); 3589 if (error) 3590 return (error); 3591 3592 /* 3593 * For I/O space, that's all she wrote. 3594 */ 3595 if (t == I386_BUS_SPACE_IO) { 3596 *bshp = bpa; 3597 return (0); 3598 } 3599 3600 if (IOM_BEGIN <= bpa && bpa <= IOM_END) { 3601 *bshp = (bus_space_handle_t)ISA_HOLE_VADDR(bpa); 3602 return (0); 3603 } 3604 3605 /* 3606 * For memory space, map the bus physical address to 3607 * a kernel virtual address. 3608 */ 3609 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3610 if (error) { 3611 if (extent_free(ex, bpa, size, EX_NOWAIT | 3612 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3613 printf("bus_space_map: pa 0x%lx, size 0x%lx\n", 3614 bpa, size); 3615 printf("bus_space_map: can't free region\n"); 3616 } 3617 } 3618 3619 return (error); 3620 } 3621 3622 int 3623 _bus_space_map(bus_space_tag_t t, bus_addr_t bpa, bus_size_t size, 3624 int flags, bus_space_handle_t *bshp) 3625 { 3626 /* 3627 * For I/O space, that's all she wrote. 3628 */ 3629 if (t == I386_BUS_SPACE_IO) { 3630 *bshp = bpa; 3631 return (0); 3632 } 3633 3634 /* 3635 * For memory space, map the bus physical address to 3636 * a kernel virtual address. 3637 */ 3638 return (bus_mem_add_mapping(bpa, size, flags, bshp)); 3639 } 3640 3641 int 3642 bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, bus_addr_t rend, 3643 bus_size_t size, bus_size_t alignment, bus_size_t boundary, 3644 int flags, bus_addr_t *bpap, bus_space_handle_t *bshp) 3645 { 3646 struct extent *ex; 3647 u_long bpa; 3648 int error; 3649 3650 /* 3651 * Pick the appropriate extent map. 3652 */ 3653 if (t == I386_BUS_SPACE_IO) { 3654 ex = ioport_ex; 3655 } else if (t == I386_BUS_SPACE_MEM) { 3656 ex = iomem_ex; 3657 } else { 3658 panic("bus_space_alloc: bad bus space tag"); 3659 } 3660 3661 /* 3662 * Sanity check the allocation against the extent's boundaries. 3663 */ 3664 if (rstart < ex->ex_start || rend > ex->ex_end) 3665 panic("bus_space_alloc: bad region start/end"); 3666 3667 /* 3668 * Do the requested allocation. 3669 */ 3670 error = extent_alloc_subregion(ex, rstart, rend, size, alignment, 0, 3671 boundary, EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0), 3672 &bpa); 3673 3674 if (error) 3675 return (error); 3676 3677 /* 3678 * For I/O space, that's all she wrote. 3679 */ 3680 if (t == I386_BUS_SPACE_IO) { 3681 *bshp = *bpap = bpa; 3682 return (0); 3683 } 3684 3685 /* 3686 * For memory space, map the bus physical address to 3687 * a kernel virtual address. 3688 */ 3689 error = bus_mem_add_mapping(bpa, size, flags, bshp); 3690 if (error) { 3691 if (extent_free(iomem_ex, bpa, size, EX_NOWAIT | 3692 (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3693 printf("bus_space_alloc: pa 0x%lx, size 0x%lx\n", 3694 bpa, size); 3695 printf("bus_space_alloc: can't free region\n"); 3696 } 3697 } 3698 3699 *bpap = bpa; 3700 3701 return (error); 3702 } 3703 3704 int 3705 bus_mem_add_mapping(bus_addr_t bpa, bus_size_t size, int flags, 3706 bus_space_handle_t *bshp) 3707 { 3708 paddr_t pa, endpa; 3709 vaddr_t va; 3710 bus_size_t map_size; 3711 int pmap_flags = PMAP_NOCACHE; 3712 3713 pa = trunc_page(bpa); 3714 endpa = round_page(bpa + size); 3715 3716 #ifdef DIAGNOSTIC 3717 if (endpa <= pa && endpa != 0) 3718 panic("bus_mem_add_mapping: overflow"); 3719 #endif 3720 3721 map_size = endpa - pa; 3722 3723 va = (vaddr_t)km_alloc(map_size, &kv_any, &kp_none, &kd_nowait); 3724 if (va == 0) 3725 return (ENOMEM); 3726 3727 *bshp = (bus_space_handle_t)(va + (bpa & PGOFSET)); 3728 3729 if (flags & BUS_SPACE_MAP_CACHEABLE) 3730 pmap_flags = 0; 3731 else if (flags & BUS_SPACE_MAP_PREFETCHABLE) 3732 pmap_flags = PMAP_WC; 3733 3734 for (; map_size > 0; 3735 pa += PAGE_SIZE, va += PAGE_SIZE, map_size -= PAGE_SIZE) 3736 pmap_kenter_pa(va, pa | pmap_flags, 3737 PROT_READ | PROT_WRITE); 3738 pmap_update(pmap_kernel()); 3739 3740 return 0; 3741 } 3742 3743 void 3744 bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3745 { 3746 struct extent *ex; 3747 u_long va, endva; 3748 bus_addr_t bpa; 3749 3750 /* 3751 * Find the correct extent and bus physical address. 3752 */ 3753 if (t == I386_BUS_SPACE_IO) { 3754 ex = ioport_ex; 3755 bpa = bsh; 3756 } else if (t == I386_BUS_SPACE_MEM) { 3757 ex = iomem_ex; 3758 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3759 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3760 goto ok; 3761 3762 va = trunc_page(bsh); 3763 endva = round_page(bsh + size); 3764 3765 #ifdef DIAGNOSTIC 3766 if (endva <= va) 3767 panic("bus_space_unmap: overflow"); 3768 #endif 3769 3770 (void) pmap_extract(pmap_kernel(), va, &bpa); 3771 bpa += (bsh & PGOFSET); 3772 3773 pmap_kremove(va, endva - va); 3774 pmap_update(pmap_kernel()); 3775 3776 /* 3777 * Free the kernel virtual mapping. 3778 */ 3779 km_free((void *)va, endva - va, &kv_any, &kp_none); 3780 } else 3781 panic("bus_space_unmap: bad bus space tag"); 3782 3783 ok: 3784 if (extent_free(ex, bpa, size, 3785 EX_NOWAIT | (ioport_malloc_safe ? EX_MALLOCOK : 0))) { 3786 printf("bus_space_unmap: %s 0x%lx, size 0x%lx\n", 3787 (t == I386_BUS_SPACE_IO) ? "port" : "pa", bpa, size); 3788 printf("bus_space_unmap: can't free region\n"); 3789 } 3790 } 3791 3792 void 3793 _bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size, 3794 bus_addr_t *adrp) 3795 { 3796 u_long va, endva; 3797 bus_addr_t bpa; 3798 3799 /* 3800 * Find the correct bus physical address. 3801 */ 3802 if (t == I386_BUS_SPACE_IO) { 3803 bpa = bsh; 3804 } else if (t == I386_BUS_SPACE_MEM) { 3805 bpa = (bus_addr_t)ISA_PHYSADDR(bsh); 3806 if (IOM_BEGIN <= bpa && bpa <= IOM_END) 3807 goto ok; 3808 3809 va = trunc_page(bsh); 3810 endva = round_page(bsh + size); 3811 3812 #ifdef DIAGNOSTIC 3813 if (endva <= va) 3814 panic("_bus_space_unmap: overflow"); 3815 #endif 3816 3817 (void) pmap_extract(pmap_kernel(), va, &bpa); 3818 bpa += (bsh & PGOFSET); 3819 3820 pmap_kremove(va, endva - va); 3821 pmap_update(pmap_kernel()); 3822 3823 /* 3824 * Free the kernel virtual mapping. 3825 */ 3826 km_free((void *)va, endva - va, &kv_any, &kp_none); 3827 } else 3828 panic("bus_space_unmap: bad bus space tag"); 3829 3830 ok: 3831 if (adrp != NULL) 3832 *adrp = bpa; 3833 } 3834 3835 void 3836 bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t size) 3837 { 3838 3839 /* bus_space_unmap() does all that we need to do. */ 3840 bus_space_unmap(t, bsh, size); 3841 } 3842 3843 int 3844 bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh, 3845 bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp) 3846 { 3847 *nbshp = bsh + offset; 3848 return (0); 3849 } 3850 3851 paddr_t 3852 bus_space_mmap(bus_space_tag_t t, bus_addr_t addr, off_t off, int prot, int flags) 3853 { 3854 /* Can't mmap I/O space. */ 3855 if (t == I386_BUS_SPACE_IO) 3856 return (-1); 3857 3858 return (addr + off); 3859 } 3860 3861 #ifdef DIAGNOSTIC 3862 void 3863 splassert_check(int wantipl, const char *func) 3864 { 3865 if (lapic_tpr < wantipl) 3866 splassert_fail(wantipl, lapic_tpr, func); 3867 if (wantipl == IPL_NONE && curcpu()->ci_idepth != 0) 3868 splassert_fail(-1, curcpu()->ci_idepth, func); 3869 } 3870 #endif 3871 3872 int 3873 copyin32(const uint32_t *uaddr, uint32_t *kaddr) 3874 { 3875 if ((vaddr_t)uaddr & 0x3) 3876 return EFAULT; 3877 3878 /* copyin(9) is atomic */ 3879 return copyin(uaddr, kaddr, sizeof(uint32_t)); 3880 } 3881 3882 /* 3883 * True if the system has any non-level interrupts which are shared 3884 * on the same pin. 3885 */ 3886 int intr_shared_edge; 3887 3888 /* 3889 * Software interrupt registration 3890 * 3891 * We hand-code this to ensure that it's atomic. 3892 */ 3893 void 3894 softintr(int sir) 3895 { 3896 struct cpu_info *ci = curcpu(); 3897 3898 __asm volatile("orl %1, %0" : 3899 "=m" (ci->ci_ipending) : "ir" (1 << sir)); 3900 } 3901 3902 /* 3903 * Raise current interrupt priority level, and return the old one. 3904 */ 3905 int 3906 splraise(int ncpl) 3907 { 3908 int ocpl; 3909 3910 KASSERT(ncpl >= IPL_NONE); 3911 3912 _SPLRAISE(ocpl, ncpl); 3913 return (ocpl); 3914 } 3915 3916 /* 3917 * Restore an old interrupt priority level. If any thereby unmasked 3918 * interrupts are pending, call Xspllower() to process them. 3919 */ 3920 void 3921 splx(int ncpl) 3922 { 3923 _SPLX(ncpl); 3924 } 3925 3926 /* 3927 * Same as splx(), but we return the old value of spl, for the 3928 * benefit of some splsoftclock() callers. 3929 */ 3930 int 3931 spllower(int ncpl) 3932 { 3933 int ocpl = lapic_tpr; 3934 3935 splx(ncpl); 3936 return (ocpl); 3937 } 3938 3939 int 3940 intr_handler(struct intrframe *frame, struct intrhand *ih) 3941 { 3942 int rc; 3943 #ifdef MULTIPROCESSOR 3944 int need_lock; 3945 3946 if (ih->ih_flags & IPL_MPSAFE) 3947 need_lock = 0; 3948 else 3949 need_lock = 1; 3950 3951 if (need_lock) 3952 __mp_lock(&kernel_lock); 3953 #endif 3954 rc = (*ih->ih_fun)(ih->ih_arg ? ih->ih_arg : frame); 3955 #ifdef MULTIPROCESSOR 3956 if (need_lock) 3957 __mp_unlock(&kernel_lock); 3958 #endif 3959 return rc; 3960 } 3961 3962 void 3963 intr_barrier(void *ih) 3964 { 3965 sched_barrier(NULL); 3966 } 3967 3968 unsigned int 3969 cpu_rnd_messybits(void) 3970 { 3971 struct timespec ts; 3972 3973 nanotime(&ts); 3974 return (ts.tv_nsec ^ (ts.tv_sec << 20)); 3975 } 3976 3977 int i386_delay_quality; 3978 3979 void 3980 delay_init(void(*fn)(int), int fn_quality) 3981 { 3982 if (fn_quality > i386_delay_quality) { 3983 delay_func = fn; 3984 i386_delay_quality = fn_quality; 3985 } 3986 } 3987 3988 void 3989 delay_fini(void (*fn)(int)) 3990 { 3991 if (delay_func == fn) { 3992 delay_func = i8254_delay; 3993 i386_delay_quality = 0; 3994 } 3995 } 3996