1 /* $OpenBSD: cmmu.h,v 1.32 2013/11/16 18:45:20 miod Exp $ */ 2 /* 3 * Mach Operating System 4 * Copyright (c) 1993-1992 Carnegie Mellon University 5 * All Rights Reserved. 6 * 7 * Permission to use, copy, modify and distribute this software and its 8 * documentation is hereby granted, provided that both the copyright 9 * notice and this permission notice appear in all copies of the 10 * software, derivative works or modified versions, and any portions 11 * thereof, and that both notices appear in supporting documentation. 12 * 13 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 14 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 15 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 16 * 17 * Carnegie Mellon requests users of this software to return to 18 * 19 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 20 * School of Computer Science 21 * Carnegie Mellon University 22 * Pittsburgh PA 15213-3890 23 * 24 * any improvements or extensions that they make and grant Carnegie Mellon 25 * the rights to redistribute these changes. 26 */ 27 28 #ifndef _M88K_CMMU_H_ 29 #define _M88K_CMMU_H_ 30 31 /* 32 * Prototypes and stuff for cmmu.c. 33 */ 34 #if defined(_KERNEL) && !defined(_LOCORE) 35 36 #include <machine/mmu.h> 37 38 /* machine dependent cmmu function pointer structure */ 39 struct cmmu_p { 40 cpuid_t (*init)(void); 41 void (*batc_setup)(cpuid_t, apr_t); 42 void (*setup_board_config)(void); 43 void (*cpu_configuration_print)(int); 44 void (*shutdown)(void); 45 46 cpuid_t (*cpu_number)(void); 47 48 apr_t (*apr_cmode)(void); 49 apr_t (*pte_cmode)(void); 50 void (*set_sapr)(apr_t); 51 void (*set_uapr)(apr_t); 52 53 void (*tlb_inv_s)(cpuid_t, vaddr_t, pt_entry_t); 54 void (*tlb_inv_u)(cpuid_t, vaddr_t, pt_entry_t); 55 void (*tlb_inv_all)(cpuid_t); 56 57 void (*cache_wbinv)(cpuid_t, paddr_t, psize_t); 58 void (*dcache_wb)(cpuid_t, paddr_t, psize_t); 59 void (*icache_inv)(cpuid_t, paddr_t, psize_t); 60 void (*dma_cachectl)(paddr_t, psize_t, int); 61 62 #ifdef MULTIPROCESSOR 63 void (*dma_cachectl_local)(paddr_t, psize_t, int); 64 void (*initialize_cpu)(cpuid_t); 65 #endif 66 }; 67 68 extern const struct cmmu_p *cmmu; 69 70 #ifdef MULTIPROCESSOR 71 /* 72 * On 8820x-based systems, this lock protects the CMMU SAR and SCR registers; 73 * other registers may be accessed without locking it. 74 * On 88410-based systems, this lock protects accesses to the BusSwitch GCSR 75 * register, which masks or unmasks the 88410 control addresses. 76 */ 77 extern __cpu_simple_lock_t cmmu_cpu_lock; 78 #define CMMU_LOCK __cpu_simple_lock(&cmmu_cpu_lock) 79 #define CMMU_UNLOCK __cpu_simple_unlock(&cmmu_cpu_lock) 80 #else 81 #define CMMU_LOCK do { /* nothing */ } while (0) 82 #define CMMU_UNLOCK do { /* nothing */ } while (0) 83 #endif /* MULTIPROCESSOR */ 84 85 #define cmmu_init (cmmu->init) 86 #define cmmu_batc_setup (cmmu->batc_setup) 87 #define setup_board_config (cmmu->setup_board_config) 88 #define cpu_configuration_print(cpu) (cmmu->cpu_configuration_print)(cpu) 89 #define cmmu_shutdown (cmmu->shutdown) 90 #define cmmu_cpu_number (cmmu->cpu_number) 91 #define cmmu_apr_cmode (cmmu->apr_cmode) 92 #define cmmu_pte_cmode (cmmu->pte_cmode) 93 #define cmmu_set_sapr(apr) (cmmu->set_sapr)(apr) 94 #define cmmu_set_uapr(apr) (cmmu->set_uapr)(apr) 95 #define cmmu_tlbis(cpu, va, pte) (cmmu->tlb_inv_s)(cpu, va, pte) 96 #define cmmu_tlbiu(cpu, va, pte) (cmmu->tlb_inv_u)(cpu, va, pte) 97 #define cmmu_tlbia(cpu) (cmmu->tlb_inv_all)(cpu) 98 #define cmmu_cache_wbinv(cpu, pa, s) (cmmu->cache_wbinv)(cpu, pa, s) 99 #define cmmu_dcache_wb(cpu, pa, s) (cmmu->dcache_wb)(cpu, pa, s) 100 #define cmmu_icache_inv(cpu,pa,s) (cmmu->icache_inv)(cpu, pa, s) 101 #define dma_cachectl(pa, s, op) (cmmu->dma_cachectl)(pa, s, op) 102 #define dma_cachectl_local(pa, s, op) (cmmu->dma_cachectl_local)(pa, s, op) 103 #define cmmu_initialize_cpu(cpu) (cmmu->initialize_cpu)(cpu) 104 105 /* 106 * dma_cachectl{,_local}() modes 107 */ 108 #define DMA_CACHE_INV 0x00 109 #define DMA_CACHE_SYNC_INVAL 0x01 110 #define DMA_CACHE_SYNC 0x02 111 112 /* 113 * Current BATC values. 114 */ 115 116 extern batc_t global_dbatc[BATC_MAX], global_ibatc[BATC_MAX]; 117 118 #endif /* _KERNEL && !_LOCORE */ 119 120 #endif /* _M88K_CMMU_H_ */ 121