1 /* $OpenBSD: cmmu.h,v 1.21 2009/02/01 00:52:17 miod Exp $ */ 2 /* 3 * Mach Operating System 4 * Copyright (c) 1993-1992 Carnegie Mellon University 5 * All Rights Reserved. 6 * 7 * Permission to use, copy, modify and distribute this software and its 8 * documentation is hereby granted, provided that both the copyright 9 * notice and this permission notice appear in all copies of the 10 * software, derivative works or modified versions, and any portions 11 * thereof, and that both notices appear in supporting documentation. 12 * 13 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 14 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 15 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 16 * 17 * Carnegie Mellon requests users of this software to return to 18 * 19 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 20 * School of Computer Science 21 * Carnegie Mellon University 22 * Pittsburgh PA 15213-3890 23 * 24 * any improvements or extensions that they make and grant Carnegie Mellon 25 * the rights to redistribute these changes. 26 */ 27 28 #ifndef _M88K_CMMU_H_ 29 #define _M88K_CMMU_H_ 30 31 /* 32 * Prototypes and stuff for cmmu.c. 33 */ 34 #if defined(_KERNEL) && !defined(_LOCORE) 35 36 /* machine dependent cmmu function pointer structure */ 37 struct cmmu_p { 38 cpuid_t (*init)(void); 39 void (*setup_board_config)(void); 40 void (*cpu_configuration_print)(int); 41 void (*shutdown)(void); 42 cpuid_t (*cpu_number)(void); 43 void (*set_sapr)(apr_t); 44 void (*set_uapr)(apr_t); 45 void (*flush_tlb)(cpuid_t, u_int, vaddr_t, u_int); 46 void (*flush_cache)(cpuid_t, paddr_t, psize_t); 47 void (*flush_inst_cache)(cpuid_t, paddr_t, psize_t); 48 void (*dma_cachectl)(paddr_t, psize_t, int); 49 #ifdef MULTIPROCESSOR 50 void (*initialize_cpu)(cpuid_t); 51 #endif 52 }; 53 54 extern struct cmmu_p *cmmu; 55 56 #ifdef MULTIPROCESSOR 57 /* 58 * On 8820x-based systems, this lock protects the CMMU SAR and SCR registers; 59 * other registers may be accessed without locking it. 60 * On 88410-based systems, this lock protects accesses to the BusSwitch GCSR 61 * register, which masks or unmasks the 88410 control addresses. 62 */ 63 extern __cpu_simple_lock_t cmmu_cpu_lock; 64 #define CMMU_LOCK __cpu_simple_lock(&cmmu_cpu_lock) 65 #define CMMU_UNLOCK __cpu_simple_unlock(&cmmu_cpu_lock) 66 #else 67 #define CMMU_LOCK do { /* nothing */ } while (0) 68 #define CMMU_UNLOCK do { /* nothing */ } while (0) 69 #endif /* MULTIPROCESSOR */ 70 71 #define cmmu_init (cmmu->init) 72 #define setup_board_config (cmmu->setup_board_config) 73 #define cpu_configuration_print(a) (cmmu->cpu_configuration_print)(a) 74 #define cmmu_shutdown (cmmu->shutdown) 75 #define cmmu_cpu_number (cmmu->cpu_number) 76 #define cmmu_set_sapr(a) (cmmu->set_sapr)(a) 77 #define cmmu_set_uapr(a) (cmmu->set_uapr)(a) 78 #define cmmu_flush_tlb(a, b, c, d) (cmmu->flush_tlb)(a, b, c, d) 79 #define cmmu_flush_cache(a, b, c) (cmmu->flush_cache)(a, b, c) 80 #define cmmu_flush_inst_cache(a, b, c) (cmmu->flush_inst_cache)(a, b, c) 81 #define dma_cachectl(a, b, c) (cmmu->dma_cachectl)(a, b, c) 82 #define cmmu_initialize_cpu(a) (cmmu->initialize_cpu)(a) 83 84 /* 85 * dma_cachectl() modes 86 */ 87 #define DMA_CACHE_SYNC 0 88 #define DMA_CACHE_SYNC_INVAL 1 89 #define DMA_CACHE_INV 2 90 91 #endif /* _KERNEL && !_LOCORE */ 92 93 #endif /* _M88K_CMMU_H_ */ 94