1 /* $OpenBSD: cmmu.h,v 1.29 2013/02/19 21:02:06 miod Exp $ */ 2 /* 3 * Mach Operating System 4 * Copyright (c) 1993-1992 Carnegie Mellon University 5 * All Rights Reserved. 6 * 7 * Permission to use, copy, modify and distribute this software and its 8 * documentation is hereby granted, provided that both the copyright 9 * notice and this permission notice appear in all copies of the 10 * software, derivative works or modified versions, and any portions 11 * thereof, and that both notices appear in supporting documentation. 12 * 13 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 14 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 15 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 16 * 17 * Carnegie Mellon requests users of this software to return to 18 * 19 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 20 * School of Computer Science 21 * Carnegie Mellon University 22 * Pittsburgh PA 15213-3890 23 * 24 * any improvements or extensions that they make and grant Carnegie Mellon 25 * the rights to redistribute these changes. 26 */ 27 28 #ifndef _M88K_CMMU_H_ 29 #define _M88K_CMMU_H_ 30 31 /* 32 * Prototypes and stuff for cmmu.c. 33 */ 34 #if defined(_KERNEL) && !defined(_LOCORE) 35 36 /* machine dependent cmmu function pointer structure */ 37 struct cmmu_p { 38 cpuid_t (*init)(void); 39 void (*setup_board_config)(void); 40 void (*cpu_configuration_print)(int); 41 void (*shutdown)(void); 42 43 cpuid_t (*cpu_number)(void); 44 45 apr_t (*kapr_cmode)(void); 46 void (*set_sapr)(apr_t); 47 void (*set_uapr)(apr_t); 48 49 void (*tlb_inv_s)(cpuid_t, vaddr_t, pt_entry_t); 50 void (*tlb_inv_u)(cpuid_t, vaddr_t, pt_entry_t); 51 void (*tlb_inv_all)(cpuid_t); 52 53 void (*cache_wbinv)(cpuid_t, paddr_t, psize_t); 54 void (*dcache_wb)(cpuid_t, paddr_t, psize_t); 55 void (*icache_inv)(cpuid_t, paddr_t, psize_t); 56 void (*dma_cachectl)(paddr_t, psize_t, int); 57 58 #ifdef MULTIPROCESSOR 59 void (*dma_cachectl_local)(paddr_t, psize_t, int); 60 void (*initialize_cpu)(cpuid_t); 61 #endif 62 }; 63 64 extern const struct cmmu_p *cmmu; 65 66 #ifdef MULTIPROCESSOR 67 /* 68 * On 8820x-based systems, this lock protects the CMMU SAR and SCR registers; 69 * other registers may be accessed without locking it. 70 * On 88410-based systems, this lock protects accesses to the BusSwitch GCSR 71 * register, which masks or unmasks the 88410 control addresses. 72 */ 73 extern __cpu_simple_lock_t cmmu_cpu_lock; 74 #define CMMU_LOCK __cpu_simple_lock(&cmmu_cpu_lock) 75 #define CMMU_UNLOCK __cpu_simple_unlock(&cmmu_cpu_lock) 76 #else 77 #define CMMU_LOCK do { /* nothing */ } while (0) 78 #define CMMU_UNLOCK do { /* nothing */ } while (0) 79 #endif /* MULTIPROCESSOR */ 80 81 #define cmmu_init (cmmu->init) 82 #define setup_board_config (cmmu->setup_board_config) 83 #define cpu_configuration_print(cpu) (cmmu->cpu_configuration_print)(cpu) 84 #define cmmu_shutdown (cmmu->shutdown) 85 #define cmmu_cpu_number (cmmu->cpu_number) 86 #define cmmu_kapr_cmode (cmmu->kapr_cmode) 87 #define cmmu_set_sapr(apr) (cmmu->set_sapr)(apr) 88 #define cmmu_set_uapr(apr) (cmmu->set_uapr)(apr) 89 #define cmmu_tlbis(cpu, va, pte) (cmmu->tlb_inv_s)(cpu, va, pte) 90 #define cmmu_tlbiu(cpu, va, pte) (cmmu->tlb_inv_u)(cpu, va, pte) 91 #define cmmu_tlbia(cpu) (cmmu->tlb_inv_all)(cpu) 92 #define cmmu_cache_wbinv(cpu, pa, s) (cmmu->cache_wbinv)(cpu, pa, s) 93 #define cmmu_dcache_wb(cpu, pa, s) (cmmu->dcache_wb)(cpu, pa, s) 94 #define cmmu_icache_inv(cpu,pa,s) (cmmu->icache_inv)(cpu, pa, s) 95 #define dma_cachectl(pa, s, op) (cmmu->dma_cachectl)(pa, s, op) 96 #define dma_cachectl_local(pa, s, op) (cmmu->dma_cachectl_local)(pa, s, op) 97 #define cmmu_initialize_cpu(cpu) (cmmu->initialize_cpu)(cpu) 98 99 /* 100 * dma_cachectl{,_local}() modes 101 */ 102 #define DMA_CACHE_INV 0x00 103 #define DMA_CACHE_SYNC_INVAL 0x01 104 #define DMA_CACHE_SYNC 0x02 105 106 #endif /* _KERNEL && !_LOCORE */ 107 108 #endif /* _M88K_CMMU_H_ */ 109