1/* $OpenBSD: lcore_ddb.S,v 1.15 2022/01/25 07:08:43 visa Exp $ */ 2 3/* 4 * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/errno.h> 29#include <sys/syscall.h> 30 31#include <machine/param.h> 32#include <machine/asm.h> 33#include <machine/cpu.h> 34#include <mips64/mips_cpu.h> 35#include <machine/regnum.h> 36#include <machine/cpustate.h> 37#include <machine/trap.h> 38 39#include "assym.h" 40 41 .set mips3 42 .set noreorder # Noreorder is default style! 43 44LEAF(kdbpeekd, 0) 45 GET_CPU_INFO(t1, t0) 46 PTR_L t0, CI_CURPROCPADDR(t1) 47 li v0, KT_DDBERR 48 lw t1, PCB_ONFAULT(t0) 49 and v1, a0, 7 # unaligned ? 50 bne v1, zero, 1f 51 sw v0, PCB_ONFAULT(t0) 52 53 ld v0, (a0) 54 jr ra 55 sw t1, PCB_ONFAULT(t0) 56 571: 58 LDHI v0, 0(a0) 59 LDLO v0, 7(a0) 60 jr ra 61 sw t1, PCB_ONFAULT(t0) 62END(kdbpeekd) 63 64LEAF(kdbpeek, 0) 65 GET_CPU_INFO(t1, t0) 66 PTR_L t0, CI_CURPROCPADDR(t1) 67 li v0, KT_DDBERR 68 lw t1, PCB_ONFAULT(t0) 69 and v1, a0, 3 # unaligned ? 70 bne v1, zero, 1f 71 sw v0, PCB_ONFAULT(t0) 72 73 lwu v0, (a0) 74 jr ra 75 sw t1, PCB_ONFAULT(t0) 76 771: 78 LWHI v0, 0(a0) 79 LWLO v0, 3(a0) 80 jr ra 81 sw t1, PCB_ONFAULT(t0) 82END(kdbpeek) 83 84LEAF(kdbpeekw, 0) 85 GET_CPU_INFO(t1, t0) 86 PTR_L t0, CI_CURPROCPADDR(t1) 87 li v0, KT_DDBERR 88 lw t1, PCB_ONFAULT(t0) 89 and v1, a0, 1 # unaligned ? 90 bne v1, zero, 1f 91 sw v0, PCB_ONFAULT(t0) 92 93 lh v0, (a0) 94 jr ra 95 sw t1, PCB_ONFAULT(t0) 96 971: 98 li v0, -1 # error! 99 jr ra 100 sw t1, PCB_ONFAULT(t0) 101END(kdbpeekw) 102 103LEAF(kdbpeekb, 0) 104 GET_CPU_INFO(t1, t0) 105 PTR_L t0, CI_CURPROCPADDR(t1) 106 li v0, KT_DDBERR 107 lw t1, PCB_ONFAULT(t0) 108 sw v0, PCB_ONFAULT(t0) 109 lb v0, 0(a0) 110 jr ra 111 sw t1, PCB_ONFAULT(t0) 112END(kdbpeekb) 113 114 .globl kt_ddberr 115kt_ddberr: 116 jr ra 117 li v0, -1 118 119LEAF(kdbpoked, 0) 120 GET_CPU_INFO(t1, t0) 121 PTR_L t0, CI_CURPROCPADDR(t1) 122 li v0, KT_DDBERR 123 lw t1, PCB_ONFAULT(t0) 124 and v1, a0, 7 # unaligned ? 125 bne v1, zero, 1f 126 sw v0, PCB_ONFAULT(t0) 127 128 sd a1, (a0) 129 jr ra 130 sw t1, PCB_ONFAULT(t0) 131 1321: 133 SDHI a1, 0(a0) 134 SDLO a1, 7(a0) 135 jr ra 136 sw t1, PCB_ONFAULT(t0) 137END(kdbpoked) 138 139LEAF(kdbpoke, 0) 140 GET_CPU_INFO(t1, t0) 141 PTR_L t0, CI_CURPROCPADDR(t1) 142 li v0, KT_DDBERR 143 lw t1, PCB_ONFAULT(t0) 144 and v1, a0, 3 # unaligned ? 145 bne v1, zero, 1f 146 sw v0, PCB_ONFAULT(t0) 147 148 sw a1, (a0) 149 jr ra 150 sw t1, PCB_ONFAULT(t0) 151 1521: 153 SWHI a1, 0(a0) 154 SWLO a1, 3(a0) 155 jr ra 156 sw t1, PCB_ONFAULT(t0) 157END(kdbpoke) 158 159LEAF(kdbpokew, 0) 160 GET_CPU_INFO(t1, t0) 161 PTR_L t0, CI_CURPROCPADDR(t1) 162 li v0, KT_DDBERR 163 lw t1, PCB_ONFAULT(t0) 164 and v1, a0, 1 # unaligned ? 165 bne v1, zero, 1f 166 sw v0, PCB_ONFAULT(t0) 167 168 sh a1, (a0) 169 jr ra 170 sw t1, PCB_ONFAULT(t0) 171 1721: 173 jr ra 174 sw t1, PCB_ONFAULT(t0) 175END(kdbpokew) 176 177LEAF(kdbpokeb, 0) 178 GET_CPU_INFO(t1, t0) 179 PTR_L t0, CI_CURPROCPADDR(t1) 180 li v0, KT_DDBERR 181 lw t1, PCB_ONFAULT(t0) 182 sw v0, PCB_ONFAULT(t0) 183 sb a1, 0(a0) 184 jr ra 185 sw t1, PCB_ONFAULT(t0) 186END(kdbpokeb) 187 188LEAF(db_enter, 0) 189 break BREAK_SOVER_VAL 190 jr ra 191 NOP 192END(db_enter) 193 194LEAF(setjmp, 0) 195 MFC0 v0, COP_0_STATUS_REG 196 MFC0_HAZARD 197 REG_S s0, REGSZ * 0(a0) 198 REG_S s1, REGSZ * 1(a0) 199 REG_S s2, REGSZ * 2(a0) 200 REG_S s3, REGSZ * 3(a0) 201 REG_S s4, REGSZ * 4(a0) 202 REG_S s5, REGSZ * 5(a0) 203 REG_S s6, REGSZ * 6(a0) 204 REG_S s7, REGSZ * 7(a0) 205 REG_S s8, REGSZ * 8(a0) 206 REG_S sp, REGSZ * 9(a0) 207 REG_S ra, REGSZ * 10(a0) 208 REG_S v0, REGSZ * 11(a0) 209 jr ra 210 li v0, 0 # setjmp return 211END(setjmp) 212 213LEAF(longjmp, 0) 214 REG_L v0, REGSZ * 11(a0) 215 REG_L ra, REGSZ * 10(a0) 216 REG_L s0, REGSZ * 0(a0) 217 REG_L s1, REGSZ * 1(a0) 218 REG_L s2, REGSZ * 2(a0) 219 REG_L s3, REGSZ * 3(a0) 220 REG_L s4, REGSZ * 4(a0) 221 REG_L s5, REGSZ * 5(a0) 222 REG_L s6, REGSZ * 6(a0) 223 REG_L s7, REGSZ * 7(a0) 224 REG_L s8, REGSZ * 8(a0) 225 REG_L sp, REGSZ * 9(a0) 226 MTC0 v0, COP_0_STATUS_REG 227 MTC0_SR_IE_HAZARD 228 jr ra 229 li v0, 1 # longjmp return 230END(longjmp) 231