1/* $OpenBSD: lcore_ddb.S,v 1.14 2017/04/30 16:45:45 mpi Exp $ */ 2 3/* 4 * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/errno.h> 29#include <sys/syscall.h> 30 31#include <machine/param.h> 32#include <machine/asm.h> 33#include <machine/cpu.h> 34#include <mips64/mips_cpu.h> 35#include <machine/regnum.h> 36#include <machine/cpustate.h> 37#include <machine/trap.h> 38 39#include "assym.h" 40 41 .set mips3 42 .set noreorder # Noreorder is default style! 43 44LEAF(kdbpeekd, 0) 45 GET_CPU_INFO(t1, t0) 46 PTR_L t0, CI_CURPROCPADDR(t1) 47 li v0, KT_DDBERR 48 and v1, a0, 7 # unaligned ? 49 bne v1, zero, 1f 50 sw v0, PCB_ONFAULT(t0) 51 52 ld v0, (a0) 53 jr ra 54 sw zero, PCB_ONFAULT(t0) 55 561: 57 LDHI v0, 0(a0) 58 LDLO v0, 7(a0) 59 jr ra 60 sw zero, PCB_ONFAULT(t0) 61END(kdbpeekd) 62 63LEAF(kdbpeek, 0) 64 GET_CPU_INFO(t1, t0) 65 PTR_L t0, CI_CURPROCPADDR(t1) 66 li v0, KT_DDBERR 67 and v1, a0, 3 # unaligned ? 68 bne v1, zero, 1f 69 sw v0, PCB_ONFAULT(t0) 70 71 lwu v0, (a0) 72 jr ra 73 sw zero, PCB_ONFAULT(t0) 74 751: 76 LWHI v0, 0(a0) 77 LWLO v0, 3(a0) 78 jr ra 79 sw zero, PCB_ONFAULT(t0) 80END(kdbpeek) 81 82LEAF(kdbpeekw, 0) 83 GET_CPU_INFO(t1, t0) 84 PTR_L t0, CI_CURPROCPADDR(t1) 85 li v0, KT_DDBERR 86 and v1, a0, 1 # unaligned ? 87 bne v1, zero, 1f 88 sw v0, PCB_ONFAULT(t0) 89 90 lh v0, (a0) 91 jr ra 92 sw zero, PCB_ONFAULT(t0) 93 941: 95 li v0, -1 # error! 96 jr ra 97 sw zero, PCB_ONFAULT(t0) 98END(kdbpeekw) 99 100LEAF(kdbpeekb, 0) 101 GET_CPU_INFO(t1, t0) 102 PTR_L t0, CI_CURPROCPADDR(t1) 103 li v0, KT_DDBERR 104 sw v0, PCB_ONFAULT(t0) 105 lb v0, 0(a0) 106 jr ra 107 sw zero, PCB_ONFAULT(t0) 108END(kdbpeekb) 109 110 .globl kt_ddberr 111kt_ddberr: 112 jr ra 113 li v0, -1 114 115LEAF(kdbpoked, 0) 116 GET_CPU_INFO(t1, t0) 117 PTR_L t0, CI_CURPROCPADDR(t1) 118 li v0, KT_DDBERR 119 and v1, a0, 7 # unaligned ? 120 bne v1, zero, 1f 121 sw v0, PCB_ONFAULT(t0) 122 123 sd a1, (a0) 124 jr ra 125 sw zero, PCB_ONFAULT(t0) 126 1271: 128 SDHI a1, 0(a0) 129 SDLO a1, 7(a0) 130 jr ra 131 sw zero, PCB_ONFAULT(t0) 132END(kdbpoked) 133 134LEAF(kdbpoke, 0) 135 GET_CPU_INFO(t1, t0) 136 PTR_L t0, CI_CURPROCPADDR(t1) 137 li v0, KT_DDBERR 138 and v1, a0, 3 # unaligned ? 139 bne v1, zero, 1f 140 sw v0, PCB_ONFAULT(t0) 141 142 sw a1, (a0) 143 jr ra 144 sw zero, PCB_ONFAULT(t0) 145 1461: 147 SWHI a1, 0(a0) 148 SWLO a1, 3(a0) 149 jr ra 150 sw zero, PCB_ONFAULT(t0) 151END(kdbpoke) 152 153LEAF(kdbpokew, 0) 154 GET_CPU_INFO(t1, t0) 155 PTR_L t0, CI_CURPROCPADDR(t1) 156 li v0, KT_DDBERR 157 and v1, a0, 1 # unaligned ? 158 bne v1, zero, 1f 159 sw v0, PCB_ONFAULT(t0) 160 161 sh a1, (a0) 162 jr ra 163 sw zero, PCB_ONFAULT(t0) 164 1651: 166 jr ra 167 sw zero, PCB_ONFAULT(t0) 168END(kdbpokew) 169 170LEAF(kdbpokeb, 0) 171 GET_CPU_INFO(t1, t0) 172 PTR_L t0, CI_CURPROCPADDR(t1) 173 li v0, KT_DDBERR 174 sw v0, PCB_ONFAULT(t0) 175 sb a1, 0(a0) 176 jr ra 177 sw zero, PCB_ONFAULT(t0) 178END(kdbpokeb) 179 180LEAF(db_enter, 0) 181 break BREAK_SOVER_VAL 182 jr ra 183 NOP 184END(db_enter) 185 186LEAF(setjmp, 0) 187 MFC0 v0, COP_0_STATUS_REG 188 MFC0_HAZARD 189 REG_S s0, REGSZ * 0(a0) 190 REG_S s1, REGSZ * 1(a0) 191 REG_S s2, REGSZ * 2(a0) 192 REG_S s3, REGSZ * 3(a0) 193 REG_S s4, REGSZ * 4(a0) 194 REG_S s5, REGSZ * 5(a0) 195 REG_S s6, REGSZ * 6(a0) 196 REG_S s7, REGSZ * 7(a0) 197 REG_S s8, REGSZ * 8(a0) 198 REG_S sp, REGSZ * 9(a0) 199 REG_S ra, REGSZ * 10(a0) 200 REG_S v0, REGSZ * 11(a0) 201 jr ra 202 li v0, 0 # setjmp return 203END(setjmp) 204 205LEAF(longjmp, 0) 206 REG_L v0, REGSZ * 11(a0) 207 REG_L ra, REGSZ * 10(a0) 208 REG_L s0, REGSZ * 0(a0) 209 REG_L s1, REGSZ * 1(a0) 210 REG_L s2, REGSZ * 2(a0) 211 REG_L s3, REGSZ * 3(a0) 212 REG_L s4, REGSZ * 4(a0) 213 REG_L s5, REGSZ * 5(a0) 214 REG_L s6, REGSZ * 6(a0) 215 REG_L s7, REGSZ * 7(a0) 216 REG_L s8, REGSZ * 8(a0) 217 REG_L sp, REGSZ * 9(a0) 218 MTC0 v0, COP_0_STATUS_REG 219 MTC0_SR_IE_HAZARD 220 jr ra 221 li v0, 1 # longjmp return 222END(longjmp) 223