xref: /openbsd/sys/arch/powerpc/powerpc/softintr.c (revision 311b6aa8)
1 /*	$OpenBSD: softintr.c,v 1.10 2020/09/11 09:27:10 mpi Exp $	*/
2 /*	$NetBSD: softintr.c,v 1.2 2003/07/15 00:24:39 lukem Exp $	*/
3 
4 /*
5  * Copyright (c) 2001 Wasabi Systems, Inc.
6  * All rights reserved.
7  *
8  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *	This product includes software developed for the NetBSD Project by
21  *	Wasabi Systems, Inc.
22  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23  *    or promote products derived from this software without specific prior
24  *    written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36  * POSSIBILITY OF SUCH DAMAGE.
37  */
38 
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/mutex.h>
43 
44 #include <uvm/uvm_extern.h>
45 
46 #include <machine/atomic.h>
47 #include <machine/intr.h>
48 
49 struct soft_intrq soft_intrq[SI_NQUEUES];
50 
51 /*
52  * Initialize the software interrupt system.
53  */
54 void
softintr_init(void)55 softintr_init(void)
56 {
57 	struct soft_intrq *siq;
58 	int i;
59 
60 	for (i = 0; i < SI_NQUEUES; i++) {
61 		siq = &soft_intrq[i];
62 		TAILQ_INIT(&siq->siq_list);
63 		siq->siq_si = i;
64 		mtx_init(&siq->siq_mtx, IPL_HIGH);
65 	}
66 }
67 
68 /*
69  * Process pending software interrupts on the specified queue.
70  *
71  * NOTE: We must already be at the correct interrupt priority level.
72  */
73 void
softintr_dispatch(int si)74 softintr_dispatch(int si)
75 {
76 	struct soft_intrq *siq = &soft_intrq[si];
77 	struct soft_intrhand *sih;
78 
79 	for (;;) {
80 		mtx_enter(&siq->siq_mtx);
81 		sih = TAILQ_FIRST(&siq->siq_list);
82 		if (sih == NULL) {
83 			mtx_leave(&siq->siq_mtx);
84 			break;
85 		}
86 
87 		TAILQ_REMOVE(&siq->siq_list, sih, sih_list);
88 		sih->sih_pending = 0;
89 
90 		uvmexp.softs++;
91 
92 		mtx_leave(&siq->siq_mtx);
93 
94 		(*sih->sih_func)(sih->sih_arg);
95 	}
96 }
97 
98 /*
99  * Register a software interrupt handler.
100  */
101 void *
softintr_establish(int ipl,void (* func)(void *),void * arg)102 softintr_establish(int ipl, void (*func)(void *), void *arg)
103 {
104 	struct soft_intrhand *sih;
105 	int si;
106 
107 	switch (ipl) {
108 #if 0
109 	case IPL_SOFT:
110 		si = SI_SOFT;
111 		break;
112 #endif
113 	case IPL_SOFTCLOCK:
114 		si = SI_SOFTCLOCK;
115 		break;
116 	case IPL_SOFTNET:
117 		si = SI_SOFTNET;
118 		break;
119 	case IPL_TTY:			/* XXX until MI code is fixed */
120 	case IPL_SOFTTTY:
121 		si = SI_SOFTTTY;
122 		break;
123 	default:
124 		printf("softintr_establish: unknown soft IPL %d\n", ipl);
125 		return NULL;
126 	}
127 
128 	sih = malloc(sizeof(*sih), M_DEVBUF, M_NOWAIT);
129 	if (__predict_true(sih != NULL)) {
130 		sih->sih_func = func;
131 		sih->sih_arg = arg;
132 		sih->sih_siq = &soft_intrq[si];
133 		sih->sih_pending = 0;
134 	}
135 	return (sih);
136 }
137 
138 /*
139  * Unregister a software interrupt handler.
140  */
141 void
softintr_disestablish(void * arg)142 softintr_disestablish(void *arg)
143 {
144 	struct soft_intrhand *sih = arg;
145 	struct soft_intrq *siq = sih->sih_siq;
146 
147 	mtx_enter(&siq->siq_mtx);
148 	if (sih->sih_pending) {
149 		TAILQ_REMOVE(&siq->siq_list, sih, sih_list);
150 		sih->sih_pending = 0;
151 	}
152 	mtx_leave(&siq->siq_mtx);
153 
154 	free(sih, M_DEVBUF, sizeof *sih);
155 }
156 
157 /*
158  * Schedule a software interrupt.
159  */
160 void
softintr_schedule(void * arg)161 softintr_schedule(void *arg)
162 {
163 	struct soft_intrhand *sih = (struct soft_intrhand *)arg;
164 	struct soft_intrq *siq = sih->sih_siq;
165 	struct cpu_info *ci = curcpu();
166 
167 	mtx_enter(&siq->siq_mtx);
168 	if (sih->sih_pending == 0) {
169 		TAILQ_INSERT_TAIL(&siq->siq_list, sih, sih_list);
170 		sih->sih_pending = 1;
171 		atomic_setbits_int(&ci->ci_ipending, SI_TO_IRQBIT(siq->siq_si));
172 	}
173 	mtx_leave(&siq->siq_mtx);
174 }
175 
176 void
dosoftint(int pcpl)177 dosoftint(int pcpl)
178 {
179 	struct cpu_info *ci = curcpu();
180 	int sir, q, mask;
181 
182 	ppc_intr_enable(1);
183 	KERNEL_LOCK();
184 
185 	while ((sir = (ci->ci_ipending & ppc_smask[pcpl])) != 0) {
186 		atomic_clearbits_int(&ci->ci_ipending, sir);
187 
188 		for (q = SI_NQUEUES - 1; q >= 0; q--) {
189 			mask = SI_TO_IRQBIT(q);
190 			if (sir & mask)
191 				softintr_dispatch(q);
192 		}
193 	}
194 
195 	KERNEL_UNLOCK();
196 	(void)ppc_intr_disable();
197 }
198