1 /* $OpenBSD: amlpwm.c,v 1.3 2021/10/24 17:52:26 mpi Exp $ */
2 /*
3 * Copyright (c) 2019 Mark Kettenis <kettenis@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/device.h>
21
22 #include <machine/intr.h>
23 #include <machine/bus.h>
24 #include <machine/fdt.h>
25
26 #include <dev/ofw/openfirm.h>
27 #include <dev/ofw/ofw_clock.h>
28 #include <dev/ofw/ofw_misc.h>
29 #include <dev/ofw/ofw_pinctrl.h>
30 #include <dev/ofw/fdt.h>
31
32 #define PWM_PWM_A 0x00
33 #define PWM_PWM_B 0x01
34 #define PWM_PWM_HIGH(x) ((x) >> 16)
35 #define PWM_PWM_HIGH_SHIFT 16
36 #define PWM_PWM_LOW(x) ((x) & 0xffff)
37 #define PWM_PWM_LOW_SHIFT 0
38 #define PWM_MISC_REG_AB 0x02
39 #define PWM_B_CLK_EN (1 << 23)
40 #define PWM_B_CLK_DIV_MASK (0x7f << 16)
41 #define PWM_B_CLK_DIV_SHIFT 16
42 #define PWM_B_CLK_DIV(x) ((((x) >> 16) & 0x7f) + 1)
43 #define PWM_A_CLK_EN (1 << 15)
44 #define PWM_A_CLK_DIV_MASK (0x7f << 8)
45 #define PWM_A_CLK_DIV_SHIFT 8
46 #define PWM_A_CLK_DIV(x) ((((x) >> 8) & 0x7f) + 1)
47 #define PWM_B_EN (1 << 1)
48 #define PWM_A_EN (1 << 0)
49
50 #define HREAD4(sc, reg) \
51 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2))
52 #define HWRITE4(sc, reg, val) \
53 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg) << 2, (val))
54 #define HSET4(sc, reg, bits) \
55 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits))
56 #define HCLR4(sc, reg, bits) \
57 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits))
58
59 struct amlpwm_softc {
60 struct device sc_dev;
61 bus_space_tag_t sc_iot;
62 bus_space_handle_t sc_ioh;
63
64 uint32_t sc_clkin[2];
65
66 struct pwm_device sc_pd;
67 };
68
69 int amlpwm_match(struct device *, void *, void *);
70 void amlpwm_attach(struct device *, struct device *, void *);
71
72 const struct cfattach amlpwm_ca = {
73 sizeof (struct amlpwm_softc), amlpwm_match, amlpwm_attach
74 };
75
76 struct cfdriver amlpwm_cd = {
77 NULL, "amlpwm", DV_DULL
78 };
79
80 int amlpwm_get_state(void *, uint32_t *, struct pwm_state *);
81 int amlpwm_set_state(void *, uint32_t *, struct pwm_state *);
82
83 int
amlpwm_match(struct device * parent,void * match,void * aux)84 amlpwm_match(struct device *parent, void *match, void *aux)
85 {
86 struct fdt_attach_args *faa = aux;
87 int node = faa->fa_node;
88
89 return (OF_is_compatible(node, "amlogic,meson-g12a-ao-pwm-cd") ||
90 OF_is_compatible(node, "amlogic,meson-g12a-ee-pwm"));
91 }
92
93 void
amlpwm_attach(struct device * parent,struct device * self,void * aux)94 amlpwm_attach(struct device *parent, struct device *self, void *aux)
95 {
96 struct amlpwm_softc *sc = (struct amlpwm_softc *)self;
97 struct fdt_attach_args *faa = aux;
98
99 if (faa->fa_nreg < 1) {
100 printf(": no registers\n");
101 return;
102 }
103
104 sc->sc_iot = faa->fa_iot;
105 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
106 faa->fa_reg[0].size, 0, &sc->sc_ioh)) {
107 printf(": can't map registers\n");
108 return;
109 }
110
111 sc->sc_clkin[0] = clock_get_frequency(faa->fa_node, "clkin0");
112 sc->sc_clkin[1] = clock_get_frequency(faa->fa_node, "clkin1");
113
114 printf("\n");
115
116 pinctrl_byname(faa->fa_node, "default");
117
118 sc->sc_pd.pd_node = faa->fa_node;
119 sc->sc_pd.pd_cookie = sc;
120 sc->sc_pd.pd_get_state = amlpwm_get_state;
121 sc->sc_pd.pd_set_state = amlpwm_set_state;
122 pwm_register(&sc->sc_pd);
123 }
124
125 static inline uint32_t
cycles_to_ns(uint64_t clk_freq,uint32_t clk_div,uint32_t cycles)126 cycles_to_ns(uint64_t clk_freq, uint32_t clk_div, uint32_t cycles)
127 {
128 return cycles * clk_div * 1000000000ULL / clk_freq;
129 }
130
131 static inline uint32_t
ns_to_cycles(uint64_t clk_freq,uint32_t clk_div,uint32_t ns)132 ns_to_cycles(uint64_t clk_freq, uint32_t clk_div, uint32_t ns)
133 {
134 return ns * clk_freq / (clk_div * 1000000000ULL);
135 }
136
137 int
amlpwm_get_state(void * cookie,uint32_t * cells,struct pwm_state * ps)138 amlpwm_get_state(void *cookie, uint32_t *cells, struct pwm_state *ps)
139 {
140 struct amlpwm_softc *sc = cookie;
141 uint32_t idx = cells[0];
142 uint32_t pwm, misc;
143 uint32_t total, high;
144 uint32_t clk_div;
145 int enabled = 0;
146
147 if (idx > 1 || sc->sc_clkin[idx] == 0)
148 return EINVAL;
149
150 pwm = HREAD4(sc, idx == 0 ? PWM_PWM_A : PWM_PWM_B);
151 misc = HREAD4(sc, PWM_MISC_REG_AB);
152
153 if (idx == 0) {
154 if ((misc & PWM_A_CLK_EN) && (misc & PWM_A_EN))
155 enabled = 1;
156 clk_div = PWM_A_CLK_DIV(misc);
157 } else {
158 if ((misc & PWM_B_CLK_EN) && (misc & PWM_B_EN))
159 enabled = 1;
160 clk_div = PWM_B_CLK_DIV(misc);
161 }
162
163 total = PWM_PWM_LOW(pwm) + PWM_PWM_HIGH(pwm);
164 high = PWM_PWM_HIGH(pwm);
165
166 memset(ps, 0, sizeof(struct pwm_state));
167 ps->ps_period = cycles_to_ns(sc->sc_clkin[idx], clk_div, total);
168 ps->ps_pulse_width = cycles_to_ns(sc->sc_clkin[idx], clk_div, high);
169 ps->ps_enabled = enabled;
170
171 return 0;
172 }
173
174 int
amlpwm_set_state(void * cookie,uint32_t * cells,struct pwm_state * ps)175 amlpwm_set_state(void *cookie, uint32_t *cells, struct pwm_state *ps)
176 {
177 struct amlpwm_softc *sc = cookie;
178 uint32_t idx = cells[0];
179 uint32_t pwm, misc;
180 uint32_t total, high, low;
181 uint32_t clk_div = 1;
182
183 if (idx > 1 || sc->sc_clkin[idx] == 0)
184 return EINVAL;
185
186 /* Hardware doesn't support polarity inversion. */
187 if (ps->ps_flags & PWM_POLARITY_INVERTED)
188 return EINVAL;
189
190 if (!ps->ps_enabled) {
191 HCLR4(sc, PWM_MISC_REG_AB, (idx == 0) ? PWM_A_EN : PWM_B_EN);
192 return 0;
193 }
194
195 total = ns_to_cycles(sc->sc_clkin[idx], clk_div, ps->ps_period);
196 while ((total / clk_div) > 0xffff)
197 clk_div++;
198 if (clk_div > 128)
199 return EINVAL;
200
201 total = ns_to_cycles(sc->sc_clkin[idx], clk_div, ps->ps_period);
202 high = ns_to_cycles(sc->sc_clkin[idx], clk_div, ps->ps_pulse_width);
203 low = total - high;
204
205 pwm = (high << PWM_PWM_HIGH_SHIFT) | (low << PWM_PWM_LOW_SHIFT);
206 misc = HREAD4(sc, PWM_MISC_REG_AB);
207
208 if (idx == 0) {
209 misc &= ~PWM_A_CLK_DIV_MASK;
210 misc |= (clk_div - 1) << PWM_A_CLK_DIV_SHIFT;
211 misc |= PWM_A_CLK_EN;
212 } else {
213 misc &= ~PWM_B_CLK_DIV_MASK;
214 misc |= (clk_div - 1) << PWM_B_CLK_DIV_SHIFT;
215 misc |= PWM_B_CLK_EN;
216 }
217
218 HWRITE4(sc, PWM_MISC_REG_AB, misc);
219 HWRITE4(sc, (idx == 0) ? PWM_PWM_A : PWM_PWM_B, pwm);
220 HSET4(sc, PWM_MISC_REG_AB, (idx == 0) ? PWM_A_EN : PWM_B_EN);
221
222 return 0;
223 }
224