1 /* $OpenBSD: dwpcie.c,v 1.36 2021/10/24 17:52:26 mpi Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/param.h> 19 #include <sys/systm.h> 20 #include <sys/device.h> 21 #include <sys/extent.h> 22 #include <sys/malloc.h> 23 24 #include <machine/intr.h> 25 #include <machine/bus.h> 26 #include <machine/fdt.h> 27 28 #include <dev/pci/pcidevs.h> 29 #include <dev/pci/pcireg.h> 30 #include <dev/pci/pcivar.h> 31 #include <dev/pci/ppbreg.h> 32 33 #include <dev/ofw/openfirm.h> 34 #include <dev/ofw/ofw_clock.h> 35 #include <dev/ofw/ofw_gpio.h> 36 #include <dev/ofw/ofw_misc.h> 37 #include <dev/ofw/ofw_pinctrl.h> 38 #include <dev/ofw/ofw_power.h> 39 #include <dev/ofw/fdt.h> 40 41 /* Registers */ 42 #define PCIE_PORT_LINK_CTRL 0x710 43 #define PCIE_PORT_LINK_CTRL_LANES_MASK (0x3f << 16) 44 #define PCIE_PORT_LINK_CTRL_LANES_1 (0x1 << 16) 45 #define PCIE_PORT_LINK_CTRL_LANES_2 (0x3 << 16) 46 #define PCIE_PORT_LINK_CTRL_LANES_4 (0x7 << 16) 47 #define PCIE_PORT_LINK_CTRL_LANES_8 (0xf << 16) 48 #define PCIE_PHY_DEBUG_R1 0x72c 49 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) 50 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) 51 #define PCIE_LINK_WIDTH_SPEED_CTRL 0x80c 52 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_MASK (0x1f << 8) 53 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_1 (0x1 << 8) 54 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_2 (0x2 << 8) 55 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_4 (0x4 << 8) 56 #define PCIE_LINK_WIDTH_SPEED_CTRL_LANES_8 (0x8 << 8) 57 #define PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE (1 << 17) 58 59 #define MISC_CONTROL_1 0x8bc 60 #define MISC_CONTROL_1_DBI_RO_WR_EN (1 << 0) 61 #define IATU_VIEWPORT 0x900 62 #define IATU_VIEWPORT_INDEX0 0 63 #define IATU_VIEWPORT_INDEX1 1 64 #define IATU_VIEWPORT_INDEX2 2 65 #define IATU_VIEWPORT_INDEX3 3 66 #define IATU_OFFSET_VIEWPORT 0x904 67 #define IATU_OFFSET_UNROLL(x) (0x200 * (x)) 68 #define IATU_REGION_CTRL_1 0x000 69 #define IATU_REGION_CTRL_1_TYPE_MEM 0 70 #define IATU_REGION_CTRL_1_TYPE_IO 2 71 #define IATU_REGION_CTRL_1_TYPE_CFG0 4 72 #define IATU_REGION_CTRL_1_TYPE_CFG1 5 73 #define IATU_REGION_CTRL_2 0x004 74 #define IATU_REGION_CTRL_2_REGION_EN (1U << 31) 75 #define IATU_LWR_BASE_ADDR 0x08 76 #define IATU_UPPER_BASE_ADDR 0x0c 77 #define IATU_LIMIT_ADDR 0x10 78 #define IATU_LWR_TARGET_ADDR 0x14 79 #define IATU_UPPER_TARGET_ADDR 0x18 80 81 #define PCIE_GLOBAL_CTRL 0x8000 82 #define PCIE_GLOBAL_CTRL_APP_LTSSM_EN (1 << 2) 83 #define PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK (0xf << 4) 84 #define PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC (0x4 << 4) 85 #define PCIE_GLOBAL_STATUS 0x8008 86 #define PCIE_GLOBAL_STATUS_RDLH_LINK_UP (1 << 1) 87 #define PCIE_GLOBAL_STATUS_PHY_LINK_UP (1 << 9) 88 #define PCIE_PM_STATUS 0x8014 89 #define PCIE_GLOBAL_INT_CAUSE 0x801c 90 #define PCIE_GLOBAL_INT_MASK 0x8020 91 #define PCIE_GLOBAL_INT_MASK_INT_A (1 << 9) 92 #define PCIE_GLOBAL_INT_MASK_INT_B (1 << 10) 93 #define PCIE_GLOBAL_INT_MASK_INT_C (1 << 11) 94 #define PCIE_GLOBAL_INT_MASK_INT_D (1 << 12) 95 #define PCIE_ARCACHE_TRC 0x8050 96 #define PCIE_ARCACHE_TRC_DEFAULT 0x3511 97 #define PCIE_AWCACHE_TRC 0x8054 98 #define PCIE_AWCACHE_TRC_DEFAULT 0x5311 99 #define PCIE_ARUSER 0x805c 100 #define PCIE_AWUSER 0x8060 101 #define PCIE_AXUSER_DOMAIN_MASK (0x3 << 4) 102 #define PCIE_AXUSER_DOMAIN_INNER_SHARABLE (0x1 << 4) 103 #define PCIE_AXUSER_DOMAIN_OUTER_SHARABLE (0x2 << 4) 104 #define PCIE_STREAMID 0x8064 105 #define PCIE_STREAMID_FUNC_BITS(x) ((x) << 0) 106 #define PCIE_STREAMID_DEV_BITS(x) ((x) << 4) 107 #define PCIE_STREAMID_BUS_BITS(x) ((x) << 8) 108 #define PCIE_STREAMID_ROOTPORT(x) ((x) << 12) 109 #define PCIE_STREAMID_8040 \ 110 (PCIE_STREAMID_ROOTPORT(0x80) | PCIE_STREAMID_BUS_BITS(2) | \ 111 PCIE_STREAMID_DEV_BITS(2) | PCIE_STREAMID_FUNC_BITS(3)) 112 113 /* Amlogic G12A registers */ 114 #define PCIE_CFG0 0x0000 115 #define PCIE_CFG0_APP_LTSSM_EN (1 << 7) 116 #define PCIE_STATUS12 0x0030 117 #define PCIE_STATUS12_RDLH_LINK_UP (1 << 16) 118 #define PCIE_STATUS12_LTSSM_MASK (0x1f << 10) 119 #define PCIE_STATUS12_LTSSM_UP (0x11 << 10) 120 #define PCIE_STATUS12_SMLH_LINK_UP (1 << 6) 121 122 /* NXP i.MX8MQ registers */ 123 #define PCIE_RC_LCR 0x7c 124 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 125 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 126 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf 127 #define PCIE_RC_LCR_L1EL_MASK (0x7 << 15) 128 #define PCIE_RC_LCR_L1EL_64US (0x6 << 15) 129 130 #define IOMUXC_GPR12 0x30 131 #define IMX8MQ_GPR_PCIE2_DEVICE_TYPE_MASK (0xf << 8) 132 #define IMX8MQ_GPR_PCIE2_DEVICE_TYPE_RC (0x4 << 8) 133 #define IMX8MQ_GPR_PCIE1_DEVICE_TYPE_MASK (0xf << 12) 134 #define IMX8MQ_GPR_PCIE1_DEVICE_TYPE_RC (0x4 << 12) 135 #define IOMUXC_GPR14 0x38 136 #define IOMUXC_GPR16 0x40 137 #define IMX8MQ_GPR_PCIE_REF_USE_PAD (1 << 9) 138 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN (1 << 10) 139 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE (1 << 11) 140 #define IMX8MM_GPR_PCIE_SSC_EN (1 << 16) 141 #define IMX8MM_GPR_PCIE_POWER_OFF (1 << 17) 142 #define IMX8MM_GPR_PCIE_CMN_RST (1 << 18) 143 #define IMX8MM_GPR_PCIE_AUX_EN (1 << 19) 144 #define IMX8MM_GPR_PCIE_REF_CLK_MASK (0x3 << 24) 145 #define IMX8MM_GPR_PCIE_REF_CLK_PLL (0x3 << 24) 146 #define IMX8MM_GPR_PCIE_REF_CLK_EXT (0x2 << 24) 147 148 #define IMX8MM_PCIE_PHY_CMN_REG62 0x188 149 #define IMX8MM_PCIE_PHY_CMN_REG62_PLL_CLK_OUT 0x08 150 #define IMX8MM_PCIE_PHY_CMN_REG64 0x190 151 #define IMX8MM_PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM 0x8c 152 #define IMX8MM_PCIE_PHY_CMN_REG75 0x1d4 153 #define IMX8MM_PCIE_PHY_CMN_REG75_PLL_DONE 0x3 154 #define IMX8MM_PCIE_PHY_TRSV_REG5 0x414 155 #define IMX8MM_PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2d 156 #define IMX8MM_PCIE_PHY_TRSV_REG6 0x418 157 #define IMX8MM_PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xf 158 159 #define ANATOP_PLLOUT_CTL 0x74 160 #define ANATOP_PLLOUT_CTL_CKE (1 << 4) 161 #define ANATOP_PLLOUT_CTL_SEL_SYSPLL1 0xb 162 #define ANATOP_PLLOUT_CTL_SEL_MASK 0xf 163 #define ANATOP_PLLOUT_DIV 0x7c 164 #define ANATOP_PLLOUT_DIV_SYSPLL1 0x7 165 166 #define HREAD4(sc, reg) \ 167 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 168 #define HWRITE4(sc, reg, val) \ 169 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 170 #define HSET4(sc, reg, bits) \ 171 HWRITE4((sc), (reg), HREAD4((sc), (reg)) | (bits)) 172 #define HCLR4(sc, reg, bits) \ 173 HWRITE4((sc), (reg), HREAD4((sc), (reg)) & ~(bits)) 174 175 struct dwpcie_range { 176 uint32_t flags; 177 uint64_t pci_base; 178 uint64_t phys_base; 179 uint64_t size; 180 }; 181 182 struct dwpcie_softc { 183 struct device sc_dev; 184 bus_space_tag_t sc_iot; 185 bus_space_handle_t sc_ioh; 186 bus_dma_tag_t sc_dmat; 187 188 bus_addr_t sc_ctrl_base; 189 bus_size_t sc_ctrl_size; 190 191 bus_addr_t sc_conf_base; 192 bus_size_t sc_conf_size; 193 bus_space_handle_t sc_conf_ioh; 194 195 bus_addr_t sc_glue_base; 196 bus_size_t sc_glue_size; 197 bus_space_handle_t sc_glue_ioh; 198 199 bus_addr_t sc_io_base; 200 bus_addr_t sc_io_bus_addr; 201 bus_size_t sc_io_size; 202 bus_addr_t sc_mem_base; 203 bus_addr_t sc_mem_bus_addr; 204 bus_size_t sc_mem_size; 205 bus_addr_t sc_pmem_base; 206 bus_addr_t sc_pmem_bus_addr; 207 bus_size_t sc_pmem_size; 208 209 int sc_node; 210 int sc_acells; 211 int sc_scells; 212 int sc_pacells; 213 int sc_pscells; 214 struct dwpcie_range *sc_ranges; 215 int sc_nranges; 216 217 struct bus_space sc_bus_iot; 218 struct bus_space sc_bus_memt; 219 220 struct machine_pci_chipset sc_pc; 221 int sc_bus; 222 223 int sc_num_viewport; 224 bus_addr_t sc_atu_base; 225 int sc_atu_unroll; 226 227 void *sc_ih; 228 }; 229 230 struct dwpcie_intr_handle { 231 struct machine_intr_handle pih_ih; 232 bus_dma_tag_t pih_dmat; 233 bus_dmamap_t pih_map; 234 }; 235 236 int dwpcie_match(struct device *, void *, void *); 237 void dwpcie_attach(struct device *, struct device *, void *); 238 239 const struct cfattach dwpcie_ca = { 240 sizeof (struct dwpcie_softc), dwpcie_match, dwpcie_attach 241 }; 242 243 struct cfdriver dwpcie_cd = { 244 NULL, "dwpcie", DV_DULL 245 }; 246 247 int 248 dwpcie_match(struct device *parent, void *match, void *aux) 249 { 250 struct fdt_attach_args *faa = aux; 251 252 return (OF_is_compatible(faa->fa_node, "amlogic,g12a-pcie") || 253 OF_is_compatible(faa->fa_node, "marvell,armada8k-pcie") || 254 OF_is_compatible(faa->fa_node, "fsl,imx8mm-pcie") || 255 OF_is_compatible(faa->fa_node, "fsl,imx8mq-pcie") || 256 OF_is_compatible(faa->fa_node, "sifive,fu740-pcie")); 257 } 258 259 void dwpcie_attach_deferred(struct device *); 260 261 void dwpcie_atu_config(struct dwpcie_softc *, int, int, 262 uint64_t, uint64_t, uint64_t); 263 void dwpcie_link_config(struct dwpcie_softc *); 264 int dwpcie_link_up(struct dwpcie_softc *); 265 266 int dwpcie_armada8k_init(struct dwpcie_softc *); 267 int dwpcie_armada8k_link_up(struct dwpcie_softc *); 268 int dwpcie_armada8k_intr(void *); 269 270 int dwpcie_g12a_init(struct dwpcie_softc *); 271 int dwpcie_g12a_link_up(struct dwpcie_softc *); 272 273 int dwpcie_imx8mq_init(struct dwpcie_softc *); 274 int dwpcie_imx8mq_intr(void *); 275 276 int dwpcie_fu740_init(struct dwpcie_softc *); 277 278 void dwpcie_attach_hook(struct device *, struct device *, 279 struct pcibus_attach_args *); 280 int dwpcie_bus_maxdevs(void *, int); 281 pcitag_t dwpcie_make_tag(void *, int, int, int); 282 void dwpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 283 int dwpcie_conf_size(void *, pcitag_t); 284 pcireg_t dwpcie_conf_read(void *, pcitag_t, int); 285 void dwpcie_conf_write(void *, pcitag_t, int, pcireg_t); 286 int dwpcie_probe_device_hook(void *, struct pci_attach_args *); 287 288 int dwpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 289 const char *dwpcie_intr_string(void *, pci_intr_handle_t); 290 void *dwpcie_intr_establish(void *, pci_intr_handle_t, int, 291 struct cpu_info *, int (*)(void *), void *, char *); 292 void dwpcie_intr_disestablish(void *, void *); 293 294 int dwpcie_bs_iomap(bus_space_tag_t, bus_addr_t, bus_size_t, int, 295 bus_space_handle_t *); 296 int dwpcie_bs_memmap(bus_space_tag_t, bus_addr_t, bus_size_t, int, 297 bus_space_handle_t *); 298 299 struct interrupt_controller dwpcie_ic = { 300 .ic_barrier = intr_barrier 301 }; 302 303 void 304 dwpcie_attach(struct device *parent, struct device *self, void *aux) 305 { 306 struct dwpcie_softc *sc = (struct dwpcie_softc *)self; 307 struct fdt_attach_args *faa = aux; 308 uint32_t *ranges; 309 int i, j, nranges, rangeslen; 310 int config, glue; 311 312 if (faa->fa_nreg < 2) { 313 printf(": no registers\n"); 314 return; 315 } 316 317 sc->sc_ctrl_base = faa->fa_reg[0].addr; 318 sc->sc_ctrl_size = faa->fa_reg[0].size; 319 320 config = OF_getindex(faa->fa_node, "config", "reg-names"); 321 if (config < 0 || config >= faa->fa_nreg) { 322 printf(": no config registers\n"); 323 return; 324 } 325 326 sc->sc_conf_base = faa->fa_reg[config].addr; 327 sc->sc_conf_size = faa->fa_reg[config].size; 328 329 if (OF_is_compatible(faa->fa_node, "amlogic,g12a-pcie")) { 330 glue = OF_getindex(faa->fa_node, "cfg", "reg-names"); 331 if (glue < 0 || glue >= faa->fa_nreg) { 332 printf(": no glue registers\n"); 333 return; 334 } 335 336 sc->sc_glue_base = faa->fa_reg[glue].addr; 337 sc->sc_glue_size = faa->fa_reg[glue].size; 338 } 339 340 sc->sc_iot = faa->fa_iot; 341 sc->sc_dmat = faa->fa_dmat; 342 sc->sc_node = faa->fa_node; 343 344 sc->sc_acells = OF_getpropint(sc->sc_node, "#address-cells", 345 faa->fa_acells); 346 sc->sc_scells = OF_getpropint(sc->sc_node, "#size-cells", 347 faa->fa_scells); 348 sc->sc_pacells = faa->fa_acells; 349 sc->sc_pscells = faa->fa_scells; 350 351 rangeslen = OF_getproplen(sc->sc_node, "ranges"); 352 if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) || 353 (rangeslen / sizeof(uint32_t)) % (sc->sc_acells + 354 sc->sc_pacells + sc->sc_scells)) { 355 printf(": invalid ranges property\n"); 356 return; 357 } 358 359 ranges = malloc(rangeslen, M_TEMP, M_WAITOK); 360 OF_getpropintarray(sc->sc_node, "ranges", ranges, 361 rangeslen); 362 363 nranges = (rangeslen / sizeof(uint32_t)) / 364 (sc->sc_acells + sc->sc_pacells + sc->sc_scells); 365 sc->sc_ranges = mallocarray(nranges, 366 sizeof(struct dwpcie_range), M_TEMP, M_WAITOK); 367 sc->sc_nranges = nranges; 368 369 for (i = 0, j = 0; i < sc->sc_nranges; i++) { 370 sc->sc_ranges[i].flags = ranges[j++]; 371 sc->sc_ranges[i].pci_base = ranges[j++]; 372 if (sc->sc_acells - 1 == 2) { 373 sc->sc_ranges[i].pci_base <<= 32; 374 sc->sc_ranges[i].pci_base |= ranges[j++]; 375 } 376 sc->sc_ranges[i].phys_base = ranges[j++]; 377 if (sc->sc_pacells == 2) { 378 sc->sc_ranges[i].phys_base <<= 32; 379 sc->sc_ranges[i].phys_base |= ranges[j++]; 380 } 381 sc->sc_ranges[i].size = ranges[j++]; 382 if (sc->sc_scells == 2) { 383 sc->sc_ranges[i].size <<= 32; 384 sc->sc_ranges[i].size |= ranges[j++]; 385 } 386 } 387 388 free(ranges, M_TEMP, rangeslen); 389 390 if (bus_space_map(sc->sc_iot, sc->sc_ctrl_base, 391 sc->sc_ctrl_size, 0, &sc->sc_ioh)) { 392 free(sc->sc_ranges, M_TEMP, sc->sc_nranges * 393 sizeof(struct dwpcie_range)); 394 printf(": can't map ctrl registers\n"); 395 return; 396 } 397 398 if (bus_space_map(sc->sc_iot, sc->sc_conf_base, 399 sc->sc_conf_size, 0, &sc->sc_conf_ioh)) { 400 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ctrl_size); 401 free(sc->sc_ranges, M_TEMP, sc->sc_nranges * 402 sizeof(struct dwpcie_range)); 403 printf(": can't map config registers\n"); 404 return; 405 } 406 407 sc->sc_num_viewport = OF_getpropint(sc->sc_node, "num-viewport", 2); 408 409 printf("\n"); 410 411 pinctrl_byname(sc->sc_node, "default"); 412 clock_set_assigned(sc->sc_node); 413 414 config_defer(self, dwpcie_attach_deferred); 415 } 416 417 void 418 dwpcie_attach_deferred(struct device *self) 419 { 420 struct dwpcie_softc *sc = (struct dwpcie_softc *)self; 421 struct pcibus_attach_args pba; 422 bus_addr_t iobase, iolimit; 423 bus_addr_t membase, memlimit; 424 bus_addr_t pmembase, pmemlimit; 425 uint32_t bus_range[2]; 426 pcireg_t bir, blr, csr; 427 int i, error = 0; 428 429 if (OF_is_compatible(sc->sc_node, "marvell,armada8k-pcie")) 430 error = dwpcie_armada8k_init(sc); 431 if (OF_is_compatible(sc->sc_node, "amlogic,g12a-pcie")) 432 error = dwpcie_g12a_init(sc); 433 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie") || 434 OF_is_compatible(sc->sc_node, "fsl,imx8mq-pcie")) 435 error = dwpcie_imx8mq_init(sc); 436 if (OF_is_compatible(sc->sc_node, "sifive,fu740-pcie")) 437 error = dwpcie_fu740_init(sc); 438 if (error != 0) { 439 bus_space_unmap(sc->sc_iot, sc->sc_conf_ioh, sc->sc_conf_size); 440 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ctrl_size); 441 free(sc->sc_ranges, M_TEMP, sc->sc_nranges * 442 sizeof(struct dwpcie_range)); 443 printf("%s: can't initialize hardware\n", 444 sc->sc_dev.dv_xname); 445 return; 446 } 447 448 if (HREAD4(sc, IATU_VIEWPORT) == 0xffffffff) { 449 sc->sc_atu_base = 0x300000; 450 sc->sc_atu_unroll = 1; 451 } 452 453 /* Set up address translation for I/O space. */ 454 for (i = 0; i < sc->sc_nranges; i++) { 455 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000 && 456 sc->sc_ranges[i].size > 0) { 457 sc->sc_io_base = sc->sc_ranges[i].phys_base; 458 sc->sc_io_bus_addr = sc->sc_ranges[i].pci_base; 459 sc->sc_io_size = sc->sc_ranges[i].size; 460 } 461 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x02000000 && 462 sc->sc_ranges[i].size > 0) { 463 sc->sc_mem_base = sc->sc_ranges[i].phys_base; 464 sc->sc_mem_bus_addr = sc->sc_ranges[i].pci_base; 465 sc->sc_mem_size = sc->sc_ranges[i].size; 466 } 467 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x03000000 && 468 sc->sc_ranges[i].size > 0) { 469 sc->sc_pmem_base = sc->sc_ranges[i].phys_base; 470 sc->sc_pmem_bus_addr = sc->sc_ranges[i].pci_base; 471 sc->sc_pmem_size = sc->sc_ranges[i].size; 472 } 473 } 474 if (sc->sc_mem_size == 0) { 475 printf("%s: no memory mapped I/O window\n", 476 sc->sc_dev.dv_xname); 477 return; 478 } 479 480 /* 481 * Disable prefetchable memory mapped I/O window if we don't 482 * have enough viewports to enable it. 483 */ 484 if (sc->sc_num_viewport < 4) 485 sc->sc_pmem_size = 0; 486 487 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX0, 488 IATU_REGION_CTRL_1_TYPE_MEM, sc->sc_mem_base, 489 sc->sc_mem_bus_addr, sc->sc_mem_size); 490 if (sc->sc_num_viewport > 2 && sc->sc_io_size > 0) 491 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX2, 492 IATU_REGION_CTRL_1_TYPE_IO, sc->sc_io_base, 493 sc->sc_io_bus_addr, sc->sc_io_size); 494 if (sc->sc_num_viewport > 3 && sc->sc_pmem_size > 0) 495 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX3, 496 IATU_REGION_CTRL_1_TYPE_MEM, sc->sc_pmem_base, 497 sc->sc_pmem_bus_addr, sc->sc_pmem_size); 498 499 /* Enable modification of read-only bits. */ 500 HSET4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN); 501 502 /* A Root Port is a PCI-PCI Bridge. */ 503 HWRITE4(sc, PCI_CLASS_REG, 504 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 505 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 506 507 /* Clear BAR as U-Boot seems to leave garbage in it. */ 508 HWRITE4(sc, PCI_MAPREG_START, PCI_MAPREG_MEM_TYPE_64BIT); 509 HWRITE4(sc, PCI_MAPREG_START + 4, 0); 510 511 /* Enable 32-bit I/O addressing. */ 512 HSET4(sc, PPB_REG_IOSTATUS, 513 PPB_IO_32BIT | (PPB_IO_32BIT << PPB_IOLIMIT_SHIFT)); 514 515 /* Make sure read-only bits are write-protected. */ 516 HCLR4(sc, MISC_CONTROL_1, MISC_CONTROL_1_DBI_RO_WR_EN); 517 518 /* Set up bus range. */ 519 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range, 520 sizeof(bus_range)) != sizeof(bus_range) || 521 bus_range[0] >= 32 || bus_range[1] >= 32) { 522 bus_range[0] = 0; 523 bus_range[1] = 31; 524 } 525 sc->sc_bus = bus_range[0]; 526 527 /* Initialize bus range. */ 528 bir = bus_range[0]; 529 bir |= ((bus_range[0] + 1) << 8); 530 bir |= (bus_range[1] << 16); 531 HWRITE4(sc, PPB_REG_BUSINFO, bir); 532 533 /* Initialize memory mapped I/O window. */ 534 membase = sc->sc_mem_bus_addr; 535 memlimit = membase + sc->sc_mem_size - 1; 536 blr = memlimit & PPB_MEM_MASK; 537 blr |= (membase >> PPB_MEM_SHIFT); 538 HWRITE4(sc, PPB_REG_MEM, blr); 539 540 /* Initialize I/O window. */ 541 if (sc->sc_io_size > 0) { 542 iobase = sc->sc_io_bus_addr; 543 iolimit = iobase + sc->sc_io_size - 1; 544 blr = iolimit & PPB_IO_MASK; 545 blr |= (iobase >> PPB_IO_SHIFT); 546 HWRITE4(sc, PPB_REG_IOSTATUS, blr); 547 blr = (iobase & 0xffff0000) >> 16; 548 blr |= iolimit & 0xffff0000; 549 HWRITE4(sc, PPB_REG_IO_HI, blr); 550 } else { 551 HWRITE4(sc, PPB_REG_IOSTATUS, 0x000000ff); 552 HWRITE4(sc, PPB_REG_IO_HI, 0x0000ffff); 553 } 554 555 /* Initialize prefetchable memory mapped I/O window. */ 556 if (sc->sc_pmem_size > 0) { 557 pmembase = sc->sc_pmem_bus_addr; 558 pmemlimit = pmembase + sc->sc_pmem_size - 1; 559 blr = pmemlimit & PPB_MEM_MASK; 560 blr |= (pmembase >> PPB_MEM_SHIFT); 561 HWRITE4(sc, PPB_REG_PREFMEM, blr); 562 HWRITE4(sc, PPB_REG_PREFBASE_HI32, pmembase >> 32); 563 HWRITE4(sc, PPB_REG_PREFLIM_HI32, pmemlimit >> 32); 564 } else { 565 HWRITE4(sc, PPB_REG_PREFMEM, 0x0000ffff); 566 HWRITE4(sc, PPB_REG_PREFBASE_HI32, 0); 567 HWRITE4(sc, PPB_REG_PREFLIM_HI32, 0); 568 } 569 570 csr = PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 571 if (sc->sc_io_size > 0) 572 csr |= PCI_COMMAND_IO_ENABLE; 573 HWRITE4(sc, PCI_COMMAND_STATUS_REG, csr); 574 575 memcpy(&sc->sc_bus_iot, sc->sc_iot, sizeof(sc->sc_bus_iot)); 576 sc->sc_bus_iot.bus_private = sc; 577 sc->sc_bus_iot._space_map = dwpcie_bs_iomap; 578 memcpy(&sc->sc_bus_memt, sc->sc_iot, sizeof(sc->sc_bus_memt)); 579 sc->sc_bus_memt.bus_private = sc; 580 sc->sc_bus_memt._space_map = dwpcie_bs_memmap; 581 582 sc->sc_pc.pc_conf_v = sc; 583 sc->sc_pc.pc_attach_hook = dwpcie_attach_hook; 584 sc->sc_pc.pc_bus_maxdevs = dwpcie_bus_maxdevs; 585 sc->sc_pc.pc_make_tag = dwpcie_make_tag; 586 sc->sc_pc.pc_decompose_tag = dwpcie_decompose_tag; 587 sc->sc_pc.pc_conf_size = dwpcie_conf_size; 588 sc->sc_pc.pc_conf_read = dwpcie_conf_read; 589 sc->sc_pc.pc_conf_write = dwpcie_conf_write; 590 sc->sc_pc.pc_probe_device_hook = dwpcie_probe_device_hook; 591 592 sc->sc_pc.pc_intr_v = sc; 593 sc->sc_pc.pc_intr_map = dwpcie_intr_map; 594 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi; 595 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix; 596 sc->sc_pc.pc_intr_string = dwpcie_intr_string; 597 sc->sc_pc.pc_intr_establish = dwpcie_intr_establish; 598 sc->sc_pc.pc_intr_disestablish = dwpcie_intr_disestablish; 599 600 memset(&pba, 0, sizeof(pba)); 601 pba.pba_busname = "pci"; 602 pba.pba_iot = &sc->sc_bus_iot; 603 pba.pba_memt = &sc->sc_bus_memt; 604 pba.pba_dmat = sc->sc_dmat; 605 pba.pba_pc = &sc->sc_pc; 606 pba.pba_domain = pci_ndomains++; 607 pba.pba_bus = sc->sc_bus; 608 if (OF_is_compatible(sc->sc_node, "marvell,armada8k-pcie")) 609 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED; 610 611 config_found(self, &pba, NULL); 612 } 613 614 void 615 dwpcie_link_config(struct dwpcie_softc *sc) 616 { 617 uint32_t mode, width, reg; 618 int lanes; 619 620 lanes = OF_getpropint(sc->sc_node, "num-lanes", 0); 621 622 switch (lanes) { 623 case 1: 624 mode = PCIE_PORT_LINK_CTRL_LANES_1; 625 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_1; 626 break; 627 case 2: 628 mode = PCIE_PORT_LINK_CTRL_LANES_2; 629 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_2; 630 break; 631 case 4: 632 mode = PCIE_PORT_LINK_CTRL_LANES_4; 633 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_4; 634 break; 635 case 8: 636 mode = PCIE_PORT_LINK_CTRL_LANES_8; 637 width = PCIE_LINK_WIDTH_SPEED_CTRL_LANES_8; 638 break; 639 default: 640 printf("%s: %d lanes not supported\n", __func__, lanes); 641 return; 642 } 643 644 reg = HREAD4(sc, PCIE_PORT_LINK_CTRL); 645 reg &= ~PCIE_PORT_LINK_CTRL_LANES_MASK; 646 reg |= mode; 647 HWRITE4(sc, PCIE_PORT_LINK_CTRL, reg); 648 649 reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL); 650 reg &= ~PCIE_LINK_WIDTH_SPEED_CTRL_LANES_MASK; 651 reg |= width; 652 HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg); 653 654 reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL); 655 reg |= PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE; 656 HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg); 657 } 658 659 int 660 dwpcie_armada8k_init(struct dwpcie_softc *sc) 661 { 662 uint32_t reg; 663 int timo; 664 665 clock_enable_all(sc->sc_node); 666 667 dwpcie_link_config(sc); 668 669 if (!dwpcie_armada8k_link_up(sc)) { 670 reg = HREAD4(sc, PCIE_GLOBAL_CTRL); 671 reg &= ~PCIE_GLOBAL_CTRL_APP_LTSSM_EN; 672 HWRITE4(sc, PCIE_GLOBAL_CTRL, reg); 673 } 674 675 /* 676 * Setup Requester-ID to Stream-ID mapping 677 * XXX: TF-A is supposed to set this up, but doesn't! 678 */ 679 HWRITE4(sc, PCIE_STREAMID, PCIE_STREAMID_8040); 680 681 /* Enable Root Complex mode. */ 682 reg = HREAD4(sc, PCIE_GLOBAL_CTRL); 683 reg &= ~PCIE_GLOBAL_CTRL_DEVICE_TYPE_MASK; 684 reg |= PCIE_GLOBAL_CTRL_DEVICE_TYPE_RC; 685 HWRITE4(sc, PCIE_GLOBAL_CTRL, reg); 686 687 HWRITE4(sc, PCIE_ARCACHE_TRC, PCIE_ARCACHE_TRC_DEFAULT); 688 HWRITE4(sc, PCIE_AWCACHE_TRC, PCIE_AWCACHE_TRC_DEFAULT); 689 reg = HREAD4(sc, PCIE_ARUSER); 690 reg &= ~PCIE_AXUSER_DOMAIN_MASK; 691 reg |= PCIE_AXUSER_DOMAIN_OUTER_SHARABLE; 692 HWRITE4(sc, PCIE_ARUSER, reg); 693 reg = HREAD4(sc, PCIE_AWUSER); 694 reg &= ~PCIE_AXUSER_DOMAIN_MASK; 695 reg |= PCIE_AXUSER_DOMAIN_OUTER_SHARABLE; 696 HWRITE4(sc, PCIE_AWUSER, reg); 697 698 if (!dwpcie_armada8k_link_up(sc)) { 699 reg = HREAD4(sc, PCIE_GLOBAL_CTRL); 700 reg |= PCIE_GLOBAL_CTRL_APP_LTSSM_EN; 701 HWRITE4(sc, PCIE_GLOBAL_CTRL, reg); 702 } 703 704 for (timo = 40; timo > 0; timo--) { 705 if (dwpcie_armada8k_link_up(sc)) 706 break; 707 delay(1000); 708 } 709 if (timo == 0) 710 return ETIMEDOUT; 711 712 sc->sc_ih = fdt_intr_establish(sc->sc_node, IPL_AUDIO | IPL_MPSAFE, 713 dwpcie_armada8k_intr, sc, sc->sc_dev.dv_xname); 714 715 /* Unmask INTx interrupts. */ 716 HWRITE4(sc, PCIE_GLOBAL_INT_MASK, 717 PCIE_GLOBAL_INT_MASK_INT_A | PCIE_GLOBAL_INT_MASK_INT_B | 718 PCIE_GLOBAL_INT_MASK_INT_C | PCIE_GLOBAL_INT_MASK_INT_D); 719 720 return 0; 721 } 722 723 int 724 dwpcie_armada8k_link_up(struct dwpcie_softc *sc) 725 { 726 uint32_t reg, mask; 727 728 mask = PCIE_GLOBAL_STATUS_RDLH_LINK_UP; 729 mask |= PCIE_GLOBAL_STATUS_PHY_LINK_UP; 730 reg = HREAD4(sc, PCIE_GLOBAL_STATUS); 731 return ((reg & mask) == mask); 732 } 733 734 int 735 dwpcie_armada8k_intr(void *arg) 736 { 737 struct dwpcie_softc *sc = arg; 738 uint32_t cause; 739 740 /* Acknowledge interrupts. */ 741 cause = HREAD4(sc, PCIE_GLOBAL_INT_CAUSE); 742 HWRITE4(sc, PCIE_GLOBAL_INT_CAUSE, cause); 743 744 /* INTx interrupt, so not really ours. */ 745 return 0; 746 } 747 748 int 749 dwpcie_g12a_init(struct dwpcie_softc *sc) 750 { 751 uint32_t *reset_gpio; 752 ssize_t reset_gpiolen; 753 uint32_t reg; 754 int timo; 755 756 reset_gpiolen = OF_getproplen(sc->sc_node, "reset-gpios"); 757 if (reset_gpiolen <= 0) 758 return ENXIO; 759 760 if (bus_space_map(sc->sc_iot, sc->sc_glue_base, 761 sc->sc_glue_size, 0, &sc->sc_glue_ioh)) 762 return ENOMEM; 763 764 power_domain_enable(sc->sc_node); 765 766 phy_enable(sc->sc_node, "pcie"); 767 768 reset_assert_all(sc->sc_node); 769 delay(500); 770 reset_deassert_all(sc->sc_node); 771 delay(500); 772 773 clock_set_frequency(sc->sc_node, "port", 100000000UL); 774 clock_enable_all(sc->sc_node); 775 776 reset_gpio = malloc(reset_gpiolen, M_TEMP, M_WAITOK); 777 OF_getpropintarray(sc->sc_node, "reset-gpios", reset_gpio, 778 reset_gpiolen); 779 gpio_controller_config_pin(reset_gpio, GPIO_CONFIG_OUTPUT); 780 gpio_controller_set_pin(reset_gpio, 1); 781 782 dwpcie_link_config(sc); 783 784 reg = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_CFG0); 785 reg |= PCIE_CFG0_APP_LTSSM_EN; 786 bus_space_write_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_CFG0, reg); 787 788 gpio_controller_set_pin(reset_gpio, 1); 789 delay(500); 790 gpio_controller_set_pin(reset_gpio, 0); 791 792 free(reset_gpio, M_TEMP, reset_gpiolen); 793 794 for (timo = 40; timo > 0; timo--) { 795 if (dwpcie_g12a_link_up(sc)) 796 break; 797 delay(1000); 798 } 799 if (timo == 0) 800 return ETIMEDOUT; 801 802 return 0; 803 } 804 805 int 806 dwpcie_g12a_link_up(struct dwpcie_softc *sc) 807 { 808 uint32_t reg; 809 810 reg = bus_space_read_4(sc->sc_iot, sc->sc_glue_ioh, PCIE_STATUS12); 811 if ((reg & PCIE_STATUS12_SMLH_LINK_UP) && 812 (reg & PCIE_STATUS12_RDLH_LINK_UP) && 813 (reg & PCIE_STATUS12_LTSSM_MASK) == PCIE_STATUS12_LTSSM_UP) 814 return 1; 815 return 0; 816 } 817 818 int 819 dwpcie_imx8mq_init(struct dwpcie_softc *sc) 820 { 821 uint32_t *clkreq_gpio, *disable_gpio, *reset_gpio; 822 ssize_t clkreq_gpiolen, disable_gpiolen, reset_gpiolen; 823 struct regmap *anatop, *gpr, *phy; 824 uint32_t off, reg; 825 int error, timo; 826 827 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie")) { 828 anatop = regmap_bycompatible("fsl,imx8mm-anatop"); 829 gpr = regmap_bycompatible("fsl,imx8mm-iomuxc-gpr"); 830 phy = regmap_bycompatible("fsl,imx7d-pcie-phy"); 831 KASSERT(phy != NULL); 832 } else { 833 anatop = regmap_bycompatible("fsl,imx8mq-anatop"); 834 gpr = regmap_bycompatible("fsl,imx8mq-iomuxc-gpr"); 835 } 836 KASSERT(anatop != NULL); 837 KASSERT(gpr != NULL); 838 839 clkreq_gpiolen = OF_getproplen(sc->sc_node, "clkreq-gpio"); 840 disable_gpiolen = OF_getproplen(sc->sc_node, "disable-gpio"); 841 reset_gpiolen = OF_getproplen(sc->sc_node, "reset-gpio"); 842 843 if (clkreq_gpiolen > 0) { 844 clkreq_gpio = malloc(clkreq_gpiolen, M_TEMP, M_WAITOK); 845 OF_getpropintarray(sc->sc_node, "clkreq-gpio", clkreq_gpio, 846 clkreq_gpiolen); 847 gpio_controller_config_pin(clkreq_gpio, GPIO_CONFIG_OUTPUT); 848 gpio_controller_set_pin(clkreq_gpio, 1); 849 } 850 851 if (disable_gpiolen > 0) { 852 disable_gpio = malloc(disable_gpiolen, M_TEMP, M_WAITOK); 853 OF_getpropintarray(sc->sc_node, "disable-gpio", disable_gpio, 854 disable_gpiolen); 855 gpio_controller_config_pin(disable_gpio, GPIO_CONFIG_OUTPUT); 856 gpio_controller_set_pin(disable_gpio, 0); 857 } 858 859 if (reset_gpiolen > 0) { 860 reset_gpio = malloc(reset_gpiolen, M_TEMP, M_WAITOK); 861 OF_getpropintarray(sc->sc_node, "reset-gpio", reset_gpio, 862 reset_gpiolen); 863 gpio_controller_config_pin(reset_gpio, GPIO_CONFIG_OUTPUT); 864 gpio_controller_set_pin(reset_gpio, 1); 865 } 866 867 power_domain_enable(sc->sc_node); 868 reset_assert(sc->sc_node, "pciephy"); 869 reset_assert(sc->sc_node, "apps"); 870 871 reg = regmap_read_4(gpr, IOMUXC_GPR12); 872 if (OF_getpropint(sc->sc_node, "ctrl-id", 0) == 0) { 873 off = IOMUXC_GPR14; 874 reg &= ~IMX8MQ_GPR_PCIE1_DEVICE_TYPE_MASK; 875 reg |= IMX8MQ_GPR_PCIE1_DEVICE_TYPE_RC; 876 } else { 877 off = IOMUXC_GPR16; 878 reg &= ~IMX8MQ_GPR_PCIE2_DEVICE_TYPE_MASK; 879 reg |= IMX8MQ_GPR_PCIE2_DEVICE_TYPE_RC; 880 } 881 regmap_write_4(gpr, IOMUXC_GPR12, reg); 882 883 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie")) { 884 if (OF_getproplen(sc->sc_node, "ext_osc") == 0 || 885 OF_getpropint(sc->sc_node, "ext_osc", 0)) { 886 reg = regmap_read_4(gpr, off); 887 reg &= ~(IMX8MQ_GPR_PCIE_REF_USE_PAD | 888 IMX8MM_GPR_PCIE_SSC_EN | 889 IMX8MM_GPR_PCIE_POWER_OFF | 890 IMX8MM_GPR_PCIE_REF_CLK_MASK); 891 reg |= (IMX8MM_GPR_PCIE_AUX_EN | 892 IMX8MM_GPR_PCIE_REF_CLK_EXT); 893 regmap_write_4(gpr, off, reg); 894 delay(100); 895 reg = regmap_read_4(gpr, off); 896 reg |= IMX8MM_GPR_PCIE_CMN_RST; 897 regmap_write_4(gpr, off, reg); 898 delay(200); 899 } else { 900 reg = regmap_read_4(gpr, off); 901 reg &= ~(IMX8MQ_GPR_PCIE_REF_USE_PAD | 902 IMX8MM_GPR_PCIE_SSC_EN | 903 IMX8MM_GPR_PCIE_POWER_OFF | 904 IMX8MM_GPR_PCIE_REF_CLK_MASK); 905 reg |= (IMX8MM_GPR_PCIE_AUX_EN | 906 IMX8MM_GPR_PCIE_REF_CLK_PLL); 907 regmap_write_4(gpr, off, reg); 908 delay(100); 909 regmap_write_4(phy, IMX8MM_PCIE_PHY_CMN_REG62, 910 IMX8MM_PCIE_PHY_CMN_REG62_PLL_CLK_OUT); 911 regmap_write_4(phy, IMX8MM_PCIE_PHY_CMN_REG64, 912 IMX8MM_PCIE_PHY_CMN_REG64_AUX_RX_TX_TERM); 913 reg = regmap_read_4(gpr, off); 914 reg |= IMX8MM_GPR_PCIE_CMN_RST; 915 regmap_write_4(gpr, off, reg); 916 delay(200); 917 regmap_write_4(phy, IMX8MM_PCIE_PHY_TRSV_REG5, 918 IMX8MM_PCIE_PHY_TRSV_REG5_GEN1_DEEMP); 919 regmap_write_4(phy, IMX8MM_PCIE_PHY_TRSV_REG6, 920 IMX8MM_PCIE_PHY_TRSV_REG6_GEN2_DEEMP); 921 } 922 } else { 923 if (OF_getproplen(sc->sc_node, "ext_osc") == 0 || 924 OF_getpropint(sc->sc_node, "ext_osc", 0)) { 925 reg = regmap_read_4(gpr, off); 926 reg |= IMX8MQ_GPR_PCIE_REF_USE_PAD; 927 regmap_write_4(gpr, off, reg); 928 } else { 929 reg = regmap_read_4(gpr, off); 930 reg &= ~IMX8MQ_GPR_PCIE_REF_USE_PAD; 931 regmap_write_4(gpr, off, reg); 932 933 regmap_write_4(anatop, ANATOP_PLLOUT_CTL, 934 ANATOP_PLLOUT_CTL_CKE | 935 ANATOP_PLLOUT_CTL_SEL_SYSPLL1); 936 regmap_write_4(anatop, ANATOP_PLLOUT_DIV, 937 ANATOP_PLLOUT_DIV_SYSPLL1); 938 } 939 } 940 941 clock_enable(sc->sc_node, "pcie_phy"); 942 clock_enable(sc->sc_node, "pcie_bus"); 943 clock_enable(sc->sc_node, "pcie"); 944 clock_enable(sc->sc_node, "pcie_aux"); 945 946 /* Allow clocks to stabilize. */ 947 delay(200); 948 949 if (reset_gpiolen > 0) { 950 gpio_controller_set_pin(reset_gpio, 1); 951 delay(100000); 952 gpio_controller_set_pin(reset_gpio, 0); 953 } 954 955 reset_deassert(sc->sc_node, "pciephy"); 956 957 if (OF_is_compatible(sc->sc_node, "fsl,imx8mm-pcie")) { 958 for (timo = 2000; timo > 0; timo--) { 959 if (regmap_read_4(phy, IMX8MM_PCIE_PHY_CMN_REG75) == 960 IMX8MM_PCIE_PHY_CMN_REG75_PLL_DONE) 961 break; 962 delay(10); 963 } 964 if (timo == 0) { 965 error = ETIMEDOUT; 966 goto err; 967 } 968 } 969 970 reg = HREAD4(sc, 0x100000 + PCIE_RC_LCR); 971 reg &= ~PCIE_RC_LCR_L1EL_MASK; 972 reg |= PCIE_RC_LCR_L1EL_64US; 973 HWRITE4(sc, 0x100000 + PCIE_RC_LCR, reg); 974 975 dwpcie_link_config(sc); 976 977 reg = HREAD4(sc, PCIE_RC_LCR); 978 reg &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 979 reg |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; 980 HWRITE4(sc, PCIE_RC_LCR, reg); 981 982 reset_deassert(sc->sc_node, "apps"); 983 984 for (timo = 20000; timo > 0; timo--) { 985 if (dwpcie_link_up(sc)) 986 break; 987 delay(10); 988 } 989 if (timo == 0) { 990 error = ETIMEDOUT; 991 goto err; 992 } 993 994 if (OF_getpropint(sc->sc_node, "fsl,max-link-speed", 1) >= 2) { 995 reg = HREAD4(sc, PCIE_RC_LCR); 996 reg &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 997 reg |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; 998 HWRITE4(sc, PCIE_RC_LCR, reg); 999 1000 reg = HREAD4(sc, PCIE_LINK_WIDTH_SPEED_CTRL); 1001 reg |= PCIE_LINK_WIDTH_SPEED_CTRL_CHANGE; 1002 HWRITE4(sc, PCIE_LINK_WIDTH_SPEED_CTRL, reg); 1003 1004 for (timo = 20000; timo > 0; timo--) { 1005 if (dwpcie_link_up(sc)) 1006 break; 1007 delay(10); 1008 } 1009 if (timo == 0) { 1010 error = ETIMEDOUT; 1011 goto err; 1012 } 1013 } 1014 1015 sc->sc_ih = fdt_intr_establish(sc->sc_node, IPL_AUDIO | IPL_MPSAFE, 1016 dwpcie_imx8mq_intr, sc, sc->sc_dev.dv_xname); 1017 1018 /* Unmask INTx interrupts. */ 1019 HWRITE4(sc, PCIE_GLOBAL_INT_MASK, 1020 PCIE_GLOBAL_INT_MASK_INT_A | PCIE_GLOBAL_INT_MASK_INT_B | 1021 PCIE_GLOBAL_INT_MASK_INT_C | PCIE_GLOBAL_INT_MASK_INT_D); 1022 1023 error = 0; 1024 err: 1025 if (clkreq_gpiolen > 0) 1026 free(clkreq_gpio, M_TEMP, clkreq_gpiolen); 1027 if (disable_gpiolen > 0) 1028 free(disable_gpio, M_TEMP, disable_gpiolen); 1029 if (reset_gpiolen > 0) 1030 free(reset_gpio, M_TEMP, reset_gpiolen); 1031 return error; 1032 } 1033 1034 int 1035 dwpcie_imx8mq_intr(void *arg) 1036 { 1037 struct dwpcie_softc *sc = arg; 1038 uint32_t cause; 1039 1040 /* Acknowledge interrupts. */ 1041 cause = HREAD4(sc, PCIE_GLOBAL_INT_CAUSE); 1042 HWRITE4(sc, PCIE_GLOBAL_INT_CAUSE, cause); 1043 1044 /* INTx interrupt, so not really ours. */ 1045 return 0; 1046 } 1047 1048 int 1049 dwpcie_fu740_init(struct dwpcie_softc *sc) 1050 { 1051 sc->sc_num_viewport = 8; 1052 1053 return 0; 1054 } 1055 1056 void 1057 dwpcie_atu_config(struct dwpcie_softc *sc, int index, int type, 1058 uint64_t cpu_addr, uint64_t pci_addr, uint64_t size) 1059 { 1060 uint32_t reg, off; 1061 int timo; 1062 1063 off = sc->sc_atu_base + IATU_OFFSET_UNROLL(index); 1064 if (!sc->sc_atu_unroll) { 1065 off = IATU_OFFSET_VIEWPORT; 1066 HWRITE4(sc, IATU_VIEWPORT, index); 1067 } 1068 1069 HWRITE4(sc, off + IATU_LWR_BASE_ADDR, cpu_addr); 1070 HWRITE4(sc, off + IATU_UPPER_BASE_ADDR, cpu_addr >> 32); 1071 HWRITE4(sc, off + IATU_LIMIT_ADDR, cpu_addr + size - 1); 1072 HWRITE4(sc, off + IATU_LWR_TARGET_ADDR, pci_addr); 1073 HWRITE4(sc, off + IATU_UPPER_TARGET_ADDR, pci_addr >> 32); 1074 HWRITE4(sc, off + IATU_REGION_CTRL_1, type); 1075 HWRITE4(sc, off + IATU_REGION_CTRL_2, IATU_REGION_CTRL_2_REGION_EN); 1076 1077 for (timo = 5; timo > 0; timo--) { 1078 reg = HREAD4(sc, off + IATU_REGION_CTRL_2); 1079 if (reg & IATU_REGION_CTRL_2_REGION_EN) 1080 break; 1081 delay(9000); 1082 } 1083 if (timo == 0) 1084 printf("%s:%d: timeout\n", __func__, __LINE__); 1085 } 1086 1087 int 1088 dwpcie_link_up(struct dwpcie_softc *sc) 1089 { 1090 uint32_t reg; 1091 1092 reg = HREAD4(sc, PCIE_PHY_DEBUG_R1); 1093 if ((reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) != 0 && 1094 (reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING) == 0) 1095 return 1; 1096 return 0; 1097 } 1098 1099 void 1100 dwpcie_attach_hook(struct device *parent, struct device *self, 1101 struct pcibus_attach_args *pba) 1102 { 1103 } 1104 1105 int 1106 dwpcie_bus_maxdevs(void *v, int bus) 1107 { 1108 struct dwpcie_softc *sc = v; 1109 1110 if (bus == sc->sc_bus || bus == sc->sc_bus + 1) 1111 return 1; 1112 return 32; 1113 } 1114 1115 pcitag_t 1116 dwpcie_make_tag(void *v, int bus, int device, int function) 1117 { 1118 return ((bus << 24) | (device << 19) | (function << 16)); 1119 } 1120 1121 void 1122 dwpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 1123 { 1124 if (bp != NULL) 1125 *bp = (tag >> 24) & 0xff; 1126 if (dp != NULL) 1127 *dp = (tag >> 19) & 0x1f; 1128 if (fp != NULL) 1129 *fp = (tag >> 16) & 0x7; 1130 } 1131 1132 int 1133 dwpcie_conf_size(void *v, pcitag_t tag) 1134 { 1135 return PCIE_CONFIG_SPACE_SIZE; 1136 } 1137 1138 pcireg_t 1139 dwpcie_conf_read(void *v, pcitag_t tag, int reg) 1140 { 1141 struct dwpcie_softc *sc = v; 1142 int bus, dev, fn; 1143 uint32_t ret; 1144 1145 dwpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 1146 if (bus == sc->sc_bus) { 1147 KASSERT(dev == 0); 1148 return HREAD4(sc, tag | reg); 1149 } 1150 1151 if (bus == sc->sc_bus + 1) { 1152 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1153 IATU_REGION_CTRL_1_TYPE_CFG0, 1154 sc->sc_conf_base, tag, sc->sc_conf_size); 1155 } else { 1156 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1157 IATU_REGION_CTRL_1_TYPE_CFG1, 1158 sc->sc_conf_base, tag, sc->sc_conf_size); 1159 } 1160 1161 ret = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh, reg); 1162 1163 if (sc->sc_num_viewport <= 2 && sc->sc_io_size > 0) { 1164 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1165 IATU_REGION_CTRL_1_TYPE_IO, sc->sc_io_base, 1166 sc->sc_io_bus_addr, sc->sc_io_size); 1167 } 1168 1169 return ret; 1170 } 1171 1172 void 1173 dwpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 1174 { 1175 struct dwpcie_softc *sc = v; 1176 int bus, dev, fn; 1177 1178 dwpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 1179 if (bus == sc->sc_bus) { 1180 KASSERT(dev == 0); 1181 HWRITE4(sc, tag | reg, data); 1182 return; 1183 } 1184 1185 if (bus == sc->sc_bus + 1) { 1186 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1187 IATU_REGION_CTRL_1_TYPE_CFG0, 1188 sc->sc_conf_base, tag, sc->sc_conf_size); 1189 } else { 1190 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1191 IATU_REGION_CTRL_1_TYPE_CFG1, 1192 sc->sc_conf_base, tag, sc->sc_conf_size); 1193 } 1194 1195 bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, reg, data); 1196 1197 if (sc->sc_num_viewport <= 2 && sc->sc_io_size > 0) { 1198 dwpcie_atu_config(sc, IATU_VIEWPORT_INDEX1, 1199 IATU_REGION_CTRL_1_TYPE_IO, sc->sc_io_base, 1200 sc->sc_io_bus_addr, sc->sc_io_size); 1201 } 1202 } 1203 1204 int 1205 dwpcie_probe_device_hook(void *v, struct pci_attach_args *pa) 1206 { 1207 struct dwpcie_softc *sc = v; 1208 uint16_t rid; 1209 int i; 1210 1211 rid = pci_requester_id(pa->pa_pc, pa->pa_tag); 1212 pa->pa_dmat = iommu_device_map_pci(sc->sc_node, rid, pa->pa_dmat); 1213 1214 for (i = 0; i < sc->sc_nranges; i++) { 1215 iommu_reserve_region_pci(sc->sc_node, rid, 1216 sc->sc_ranges[i].pci_base, sc->sc_ranges[i].size); 1217 } 1218 1219 return 0; 1220 } 1221 1222 int 1223 dwpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1224 { 1225 int pin = pa->pa_rawintrpin; 1226 1227 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX) 1228 return -1; 1229 1230 if (pa->pa_tag == 0) 1231 return -1; 1232 1233 ihp->ih_pc = pa->pa_pc; 1234 ihp->ih_tag = pa->pa_intrtag; 1235 ihp->ih_intrpin = pa->pa_intrpin; 1236 ihp->ih_type = PCI_INTX; 1237 1238 return 0; 1239 } 1240 1241 const char * 1242 dwpcie_intr_string(void *v, pci_intr_handle_t ih) 1243 { 1244 switch (ih.ih_type) { 1245 case PCI_MSI: 1246 return "msi"; 1247 case PCI_MSIX: 1248 return "msix"; 1249 } 1250 1251 return "intx"; 1252 } 1253 1254 void * 1255 dwpcie_intr_establish(void *v, pci_intr_handle_t ih, int level, 1256 struct cpu_info *ci, int (*func)(void *), void *arg, char *name) 1257 { 1258 struct dwpcie_softc *sc = v; 1259 struct dwpcie_intr_handle *pih; 1260 bus_dma_segment_t seg; 1261 void *cookie; 1262 1263 KASSERT(ih.ih_type != PCI_NONE); 1264 1265 if (ih.ih_type != PCI_INTX) { 1266 uint64_t addr, data; 1267 1268 /* Assume hardware passes Requester ID as sideband data. */ 1269 data = pci_requester_id(ih.ih_pc, ih.ih_tag); 1270 cookie = fdt_intr_establish_msi_cpu(sc->sc_node, &addr, 1271 &data, level, ci, func, arg, (void *)name); 1272 if (cookie == NULL) 1273 return NULL; 1274 1275 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK); 1276 pih->pih_ih.ih_ic = &dwpcie_ic; 1277 pih->pih_ih.ih_ih = cookie; 1278 pih->pih_dmat = ih.ih_dmat; 1279 1280 if (bus_dmamap_create(pih->pih_dmat, sizeof(uint32_t), 1, 1281 sizeof(uint32_t), 0, BUS_DMA_WAITOK, &pih->pih_map)) { 1282 free(pih, M_DEVBUF, sizeof(*pih)); 1283 fdt_intr_disestablish(cookie); 1284 return NULL; 1285 } 1286 1287 memset(&seg, 0, sizeof(seg)); 1288 seg.ds_addr = addr; 1289 seg.ds_len = sizeof(uint32_t); 1290 1291 if (bus_dmamap_load_raw(pih->pih_dmat, pih->pih_map, 1292 &seg, 1, sizeof(uint32_t), BUS_DMA_WAITOK)) { 1293 bus_dmamap_destroy(pih->pih_dmat, pih->pih_map); 1294 free(pih, M_DEVBUF, sizeof(*pih)); 1295 fdt_intr_disestablish(cookie); 1296 return NULL; 1297 } 1298 1299 addr = pih->pih_map->dm_segs[0].ds_addr; 1300 if (ih.ih_type == PCI_MSIX) { 1301 pci_msix_enable(ih.ih_pc, ih.ih_tag, 1302 &sc->sc_bus_memt, ih.ih_intrpin, addr, data); 1303 } else 1304 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data); 1305 } else { 1306 int bus, dev, fn; 1307 uint32_t reg[4]; 1308 1309 dwpcie_decompose_tag(sc, ih.ih_tag, &bus, &dev, &fn); 1310 1311 reg[0] = bus << 16 | dev << 11 | fn << 8; 1312 reg[1] = reg[2] = 0; 1313 reg[3] = ih.ih_intrpin; 1314 1315 cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg, 1316 sizeof(reg), level, ci, func, arg, name); 1317 if (cookie == NULL) 1318 return NULL; 1319 1320 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK); 1321 pih->pih_ih.ih_ic = &dwpcie_ic; 1322 pih->pih_ih.ih_ih = cookie; 1323 pih->pih_dmat = NULL; 1324 } 1325 1326 return pih; 1327 } 1328 1329 void 1330 dwpcie_intr_disestablish(void *v, void *cookie) 1331 { 1332 struct dwpcie_intr_handle *pih = cookie; 1333 1334 fdt_intr_disestablish(pih->pih_ih.ih_ih); 1335 if (pih->pih_dmat) { 1336 bus_dmamap_unload(pih->pih_dmat, pih->pih_map); 1337 bus_dmamap_destroy(pih->pih_dmat, pih->pih_map); 1338 } 1339 free(pih, M_DEVBUF, sizeof(*pih)); 1340 } 1341 1342 int 1343 dwpcie_bs_iomap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 1344 int flags, bus_space_handle_t *bshp) 1345 { 1346 struct dwpcie_softc *sc = t->bus_private; 1347 int i; 1348 1349 for (i = 0; i < sc->sc_nranges; i++) { 1350 uint64_t pci_start = sc->sc_ranges[i].pci_base; 1351 uint64_t pci_end = pci_start + sc->sc_ranges[i].size; 1352 uint64_t phys_start = sc->sc_ranges[i].phys_base; 1353 1354 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000 && 1355 addr >= pci_start && addr + size <= pci_end) { 1356 return bus_space_map(sc->sc_iot, 1357 addr - pci_start + phys_start, size, flags, bshp); 1358 } 1359 } 1360 1361 return ENXIO; 1362 } 1363 1364 int 1365 dwpcie_bs_memmap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size, 1366 int flags, bus_space_handle_t *bshp) 1367 { 1368 struct dwpcie_softc *sc = t->bus_private; 1369 int i; 1370 1371 for (i = 0; i < sc->sc_nranges; i++) { 1372 uint64_t pci_start = sc->sc_ranges[i].pci_base; 1373 uint64_t pci_end = pci_start + sc->sc_ranges[i].size; 1374 uint64_t phys_start = sc->sc_ranges[i].phys_base; 1375 1376 if ((sc->sc_ranges[i].flags & 0x02000000) == 0x02000000 && 1377 addr >= pci_start && addr + size <= pci_end) { 1378 return bus_space_map(sc->sc_iot, 1379 addr - pci_start + phys_start, size, flags, bshp); 1380 } 1381 } 1382 1383 return ENXIO; 1384 } 1385