1 /* $OpenBSD: if_mvppreg.h,v 1.11 2020/08/17 22:03:32 patrick Exp $ */ 2 /* 3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> 4 * Copyright (c) 2017, 2020 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 /* 19 * Copyright (C) 2016 Marvell International Ltd. 20 * 21 * Marvell BSD License Option 22 * 23 * If you received this File from Marvell, you may opt to use, redistribute 24 * and/or modify this File under the following licensing terms. 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions are met: 27 * 28 * * Redistributions of source code must retain the above copyright notice, 29 * this list of conditions and the following disclaimer. 30 * 31 * * Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 35 * * Neither the name of Marvell nor the names of its contributors may be 36 * used to endorse or promote products derived from this software without 37 * specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 43 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 49 * POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 #ifndef __MVPP2_LIB_HW__ 53 #define __MVPP2_LIB_HW__ 54 55 #define BIT(nr) (1U << (nr)) 56 57 /* PP2v2 registers offsets */ 58 #define MVPP22_SMI_OFFSET 0x1200 59 #define MVPP22_MPCS_OFFSET 0x7000 60 #define MVPP22_MPCS_REG_SIZE 0x1000 61 #define MVPP22_XPCS_OFFSET 0x7400 62 #define MVPP22_XPCS_REG_SIZE 0x1000 63 #define MVPP22_GMAC_OFFSET 0x7e00 64 #define MVPP22_GMAC_REG_SIZE 0x1000 65 #define MVPP22_XLG_OFFSET 0x7f00 66 #define MVPP22_XLG_REG_SIZE 0x1000 67 #define MVPP22_RFU1_OFFSET 0x318000 68 #define MVPP22_ADDR_SPACE_SIZE 0x10000 69 70 /* RX Fifo Registers */ 71 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 72 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 73 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 74 #define MVPP2_RX_FIFO_INIT_REG 0x64 75 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 76 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 77 78 /* RX DMA Top Registers */ 79 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 80 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) 81 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) 82 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) 83 #define MVPP2_POOL_BUF_SIZE_OFFSET 5 84 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) 85 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff 86 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) 87 #define MVPP2_RXQ_POOL_SHORT_OFFS 20 88 #define MVPP2_RXQ_POOL_SHORT_MASK 0xf00000 89 #define MVPP2_RXQ_POOL_LONG_OFFS 24 90 #define MVPP2_RXQ_POOL_LONG_MASK 0xf000000 91 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 92 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 93 #define MVPP2_RXQ_DISABLE_MASK BIT(31) 94 95 /* Parser Registers */ 96 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 97 #define MVPP2_PRS_PORT_LU_MAX 0xf 98 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) 99 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) 100 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) 101 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) 102 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) 103 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) 104 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) 105 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) 106 #define MVPP2_PRS_TCAM_IDX_REG 0x1100 107 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) 108 #define MVPP2_PRS_TCAM_INV_MASK BIT(31) 109 #define MVPP2_PRS_SRAM_IDX_REG 0x1200 110 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) 111 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 112 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) 113 114 /* Classifier Registers */ 115 #define MVPP2_CLS_MODE_REG 0x1800 116 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) 117 #define MVPP2_CLS_PORT_WAY_REG 0x1810 118 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) 119 #define MVPP2_CLS_LKP_INDEX_REG 0x1814 120 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 121 #define MVPP2_CLS_LKP_TBL_REG 0x1818 122 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff 123 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) 124 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 125 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 126 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 127 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c 128 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) 129 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 130 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 131 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) 132 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 133 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) 134 135 /* Descriptor Manager Top Registers */ 136 #define MVPP2_RXQ_NUM_REG 0x2040 137 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 138 #define MVPP22_DESC_ADDR_OFFS 8 139 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 140 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 141 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) 142 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 143 #define MVPP2_RXQ_NUM_NEW_OFFSET 16 144 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) 145 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff 146 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 147 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 148 #define MVPP2_RXQ_THRESH_REG 0x204c 149 #define MVPP2_OCCUPIED_THRESH_OFFSET 0 150 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff 151 #define MVPP2_RXQ_INDEX_REG 0x2050 152 #define MVPP2_TXQ_NUM_REG 0x2080 153 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 154 #define MVPP22_TXQ_DESC_ADDR_HIGH_REG 0x20a8 155 #define MVPP22_TXQ_DESC_ADDR_HIGH_MASK 0xff 156 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 157 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 158 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 159 #define MVPP2_TXQ_THRESH_REG 0x2094 160 #define MVPP2_TRANSMITTED_THRESH_OFFSET 16 161 #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff 162 #define MVPP2_TXQ_INDEX_REG 0x2098 163 #define MVPP2_TXQ_PREF_BUF_REG 0x209c 164 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) 165 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) 166 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) 167 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) 168 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) 169 #define MVPP2_TXQ_PENDING_REG 0x20a0 170 #define MVPP2_TXQ_PENDING_MASK 0x3fff 171 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 172 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) 173 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 174 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 175 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 176 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 177 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 178 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff 179 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 180 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 181 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) 182 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) 183 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 184 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) 185 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff 186 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) 187 188 /* MBUS bridge registers */ 189 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) 190 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) 191 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) 192 #define MVPP2_BASE_ADDR_ENABLE 0x4060 193 194 /* AXI Bridge Registers */ 195 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 196 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 197 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 198 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 199 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 200 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c 201 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 202 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 203 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 204 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 205 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 206 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 207 208 #define MVPP22_AXI_ATTR_CACHE_OFFS 0 209 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 210 211 #define MVPP22_AXI_CODE_CACHE_OFFS 0 212 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 213 214 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 215 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 216 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb 217 218 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 219 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 220 221 /* Interrupt Cause and Mask registers */ 222 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) 223 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) 224 #define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq)) 225 #define MVPP2_ISR_RXQ_GROUP_INDEX_REG 0x5400 226 #define MVPP2_ISR_RXQ_GROUP_INDEX_GROUP_SHIFT 7 227 #define MVPP2_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 228 #define MVPP2_ISR_RXQ_SUB_GROUP_CONFIG_SIZE_SHIFT 8 229 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) 230 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) 231 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) 232 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) 233 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xff 234 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 235 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 236 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) 237 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) 238 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) 239 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) 240 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) 241 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) 242 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) 243 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc 244 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 245 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 246 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) 247 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 248 249 /* Buffer Manager registers */ 250 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) 251 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 252 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) 253 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 254 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) 255 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 256 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) 257 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff8 258 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) 259 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) 260 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff 261 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) 262 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) 263 #define MVPP2_BM_START_MASK BIT(0) 264 #define MVPP2_BM_STOP_MASK BIT(1) 265 #define MVPP2_BM_STATE_MASK BIT(4) 266 #define MVPP2_BM_LOW_THRESH_OFFS 8 267 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 268 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ 269 MVPP2_BM_LOW_THRESH_OFFS) 270 #define MVPP2_BM_HIGH_THRESH_OFFS 16 271 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 272 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ 273 MVPP2_BM_HIGH_THRESH_OFFS) 274 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) 275 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) 276 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) 277 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) 278 #define MVPP2_BM_BPPE_FULL_MASK BIT(3) 279 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) 280 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) 281 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) 282 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) 283 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 284 #define MVPP22_BM_ADDR_HIGH_ALLOC_REG 0x6444 285 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff 286 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 287 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 288 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) 289 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) 290 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) 291 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) 292 #define MVPP2_BM_VIRT_RLS_REG 0x64c0 293 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 294 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff 295 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 296 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 297 298 #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310 299 #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff 300 #define MVPP2_BM_PRIO_CTRL_REG 0x6800 301 302 /* TX Scheduler registers */ 303 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 304 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 305 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff 306 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 307 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 308 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 309 #define MVPP2_TXP_SCHED_MTU_REG 0x801c 310 #define MVPP2_TXP_MTU_MAX 0x7FFFF 311 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 312 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff 313 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 314 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) 315 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 316 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff 317 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) 318 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff 319 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 320 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) 321 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) 322 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff 323 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) 324 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff 325 326 /* TX general registers */ 327 #define MVPP2_TX_SNOOP_REG 0x8800 328 #define MVPP2_TX_PORT_FLUSH_REG 0x8810 329 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) 330 331 /* LMS registers */ 332 #define MVPP2_SRC_ADDR_MIDDLE 0x24 333 #define MVPP2_SRC_ADDR_HIGH 0x28 334 #define MVPP2_PHY_AN_CFG0_REG 0x34 335 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) 336 #define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * 0x400 + (port) * 0x400) 337 #define MVPP2_MIB_LATE_COLLISION 0x7c 338 #define MVPP2_ISR_SUM_MASK_REG 0x220c 339 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c 340 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 341 342 /* Per-port registers */ 343 #define MVPP2_GMAC_CTRL_0_REG 0x0 344 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) 345 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) 346 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 347 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc 348 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) 349 #define MVPP2_GMAC_CTRL_1_REG 0x4 350 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) 351 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) 352 #define MVPP2_GMAC_PCS_LB_EN_BIT 6 353 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) 354 #define MVPP2_GMAC_SA_LOW_OFFS 7 355 #define MVPP2_GMAC_CTRL_2_REG 0x8 356 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) 357 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) 358 #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4) 359 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) 360 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc 361 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) 362 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) 363 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) 364 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) 365 #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) 366 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) 367 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) 368 #define MVPP2_GMAC_AN_SPEED_EN BIT(7) 369 #define MVPP2_GMAC_FC_ADV_EN BIT(9) 370 #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) 371 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) 372 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) 373 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) 374 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c 375 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 376 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 377 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ 378 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) 379 #define MVPP2_GMAC_INT_CAUSE_REG 0x20 380 #define MVPP2_GMAC_INT_MASK_REG 0x24 381 #define MVPP2_GMAC_INT_CAUSE_LINK_CHANGE BIT(1) 382 #define MVPP2_GMAC_INT_SUM_CAUSE_REG 0xa0 383 #define MVPP2_GMAC_INT_SUM_MASK_REG 0xa4 384 #define MVPP2_GMAC_INT_SUM_CAUSE_LINK_CHANGE BIT(1) 385 386 /* Port Mac Control0 */ 387 #define MVPP2_PORT_CTRL0_REG 0x0000 388 #define MVPP2_PORT_CTRL0_PORTEN BIT(0) 389 #define MVPP2_PORT_CTRL0_PORTTYPE BIT(1) 390 #define MVPP2_PORT_CTRL0_FRAMESIZELIMIT (0x1fff << 2) 391 #define MVPP2_PORT_CTRL0_COUNT_EN BIT(15) 392 393 /* Port Mac Control1 */ 394 #define MVPP2_PORT_CTRL1_REG 0x0004 395 #define MVPP2_PORT_CTRL1_EN_RX_CRC_CHECK BIT(0) 396 #define MVPP2_PORT_CTRL1_EN_PERIODIC_FC_XON BIT(1) 397 #define MVPP2_PORT_CTRL1_MGMII_MODE BIT(2) 398 #define MVPP2_PORT_CTRL1_PFC_CASCADE_PORT_ENABLE BIT(3) 399 #define MVPP2_PORT_CTRL1_DIS_EXCESSIVE_COL BIT(4) 400 #define MVPP2_PORT_CTRL1_GMII_LOOPBACK BIT(5) 401 #define MVPP2_PORT_CTRL1_PCS_LOOPBACK BIT(6) 402 #define MVPP2_PORT_CTRL1_FC_SA_ADDR_LO (0xff << 7) 403 #define MVPP2_PORT_CTRL1_EN_SHORT_PREAMBLE BIT(15) 404 405 /* Port Mac Control2 */ 406 #define MVPP2_PORT_CTRL2_REG 0x0008 407 #define MVPP2_PORT_CTRL2_SGMII_MODE BIT(0) 408 #define MVPP2_PORT_CTRL2_FC_MODE (0x3 << 1) 409 #define MVPP2_PORT_CTRL2_PCS_EN BIT(3) 410 #define MVPP2_PORT_CTRL2_RGMII_MODE BIT(4) 411 #define MVPP2_PORT_CTRL2_DIS_PADING BIT(5) 412 #define MVPP2_PORT_CTRL2_PORTMACRESET BIT(6) 413 #define MVPP2_PORT_CTRL2_TX_DRAIN BIT(7) 414 #define MVPP2_PORT_CTRL2_EN_MII_ODD_PRE BIT(8) 415 #define MVPP2_PORT_CTRL2_CLK_125_BYPS_EN BIT(9) 416 #define MVPP2_PORT_CTRL2_PRBS_CHECK_EN BIT(10) 417 #define MVPP2_PORT_CTRL2_PRBS_GEN_EN BIT(11) 418 #define MVPP2_PORT_CTRL2_SELECT_DATA_TO_TX (0x3 << 12) 419 #define MVPP2_PORT_CTRL2_EN_COL_ON_BP BIT(14) 420 #define MVPP2_PORT_CTRL2_EARLY_REJECT_MODE BIT(15) 421 422 /* Port Auto-negotiation Configuration */ 423 #define MVPP2_PORT_AUTO_NEG_CFG_REG 0x000c 424 #define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN BIT(0) 425 #define MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP BIT(1) 426 #define MVPP2_PORT_AUTO_NEG_CFG_EN_PCS_AN BIT(2) 427 #define MVPP2_PORT_AUTO_NEG_CFG_AN_BYPASS_EN BIT(3) 428 #define MVPP2_PORT_AUTO_NEG_CFG_INBAND_RESTARTAN BIT(4) 429 #define MVPP2_PORT_AUTO_NEG_CFG_SET_MII_SPEED BIT(5) 430 #define MVPP2_PORT_AUTO_NEG_CFG_SET_GMII_SPEED BIT(6) 431 #define MVPP2_PORT_AUTO_NEG_CFG_EN_AN_SPEED BIT(7) 432 #define MVPP2_PORT_AUTO_NEG_CFG_ADV_PAUSE BIT(9) 433 #define MVPP2_PORT_AUTO_NEG_CFG_ADV_ASM_PAUSE BIT(10) 434 #define MVPP2_PORT_AUTO_NEG_CFG_EN_FC_AN BIT(11) 435 #define MVPP2_PORT_AUTO_NEG_CFG_SET_FULL_DX BIT(12) 436 #define MVPP2_PORT_AUTO_NEG_CFG_EN_FDX_AN BIT(13) 437 #define MVPP2_PORT_AUTO_NEG_CFG_PHY_MODE BIT(14) 438 #define MVPP2_PORT_AUTO_NEG_CFG_CHOOSE_SAMPLE_TX_CONFIG BIT(15) 439 440 /* Port Status0 */ 441 #define MVPP2_PORT_STATUS0_REG 0x0010 442 #define MVPP2_PORT_STATUS0_LINKUP BIT(0) 443 #define MVPP2_PORT_STATUS0_GMIISPEED BIT(1) 444 #define MVPP2_PORT_STATUS0_MIISPEED BIT(2) 445 #define MVPP2_PORT_STATUS0_FULLDX BIT(3) 446 #define MVPP2_PORT_STATUS0_RXFCEN BIT(4) 447 #define MVPP2_PORT_STATUS0_TXFCEN BIT(5) 448 #define MVPP2_PORT_STATUS0_PORTRXPAUSE BIT(6) 449 #define MVPP2_PORT_STATUS0_PORTTXPAUSE BIT(7) 450 #define MVPP2_PORT_STATUS0_PORTIS_DOINGPRESSURE BIT(8) 451 #define MVPP2_PORT_STATUS0_PORTBUFFULL BIT(9) 452 #define MVPP2_PORT_STATUS0_SYNCFAIL10MS BIT(10) 453 #define MVPP2_PORT_STATUS0_ANDONE BIT(11) 454 #define MVPP2_PORT_STATUS0_INBAND_AUTONEG_BYPASSAC BIT(12) 455 #define MVPP2_PORT_STATUS0_SERDESPLL_LOCKED BIT(13) 456 #define MVPP2_PORT_STATUS0_SYNCOK BIT(14) 457 #define MVPP2_PORT_STATUS0_SQUELCHNOT_DETECTED BIT(15) 458 459 /* Port Serial Parameters Configuration */ 460 #define MVPP2_PORT_SERIAL_PARAM_CFG_REG 0x0014 461 #define MVPP2_PORT_SERIAL_PARAM_CFG_UNIDIRECTIONAL_ENABLE BIT(0) 462 #define MVPP2_PORT_SERIAL_PARAM_CFG_RETRANSMIT_COLLISION_DOMAIN BIT(1) 463 #define MVPP2_PORT_SERIAL_PARAM_CFG_PUMA2_BTS1444_EN BIT(2) 464 #define MVPP2_PORT_SERIAL_PARAM_CFG_FORWARD_802_3X_FC_EN BIT(3) 465 #define MVPP2_PORT_SERIAL_PARAM_CFG_BP_EN BIT(4) 466 #define MVPP2_PORT_SERIAL_PARAM_CFG_RX_NEGEDGE_SAMPLE_EN BIT(5) 467 #define MVPP2_PORT_SERIAL_PARAM_CFG_COL_DOMAIN_LIMIT (0x3f << 6) 468 #define MVPP2_PORT_SERIAL_PARAM_CFG_PERIODIC_TYPE_SELECT BIT(12) 469 #define MVPP2_PORT_SERIAL_PARAM_CFG_PER_PRIORITY_FC_EN BIT(13) 470 #define MVPP2_PORT_SERIAL_PARAM_CFG_TX_STANDARD_PRBS7 BIT(14) 471 #define MVPP2_PORT_SERIAL_PARAM_CFG_REVERSE_PRBS_RX BIT(15) 472 473 /* Port Fifo Configuration 0 */ 474 #define MVPP2_PORT_FIFO_CFG_0_REG 0x0018 475 #define MVPP2_PORT_FIFO_CFG_0_TX_FIFO_HIGH_WM (0xff << 0) 476 #define MVPP2_PORT_FIFO_CFG_0_TX_FIFO_LOW_WM (0xff << 8) 477 478 /* Port Fifo Configuration 1 */ 479 #define MVPP2_PORT_FIFO_CFG_1_REG 0x001c 480 #define MVPP2_PORT_FIFO_CFG_1_RX_FIFO_MAX_TH (0x3f << 0) 481 #define MVPP2_PORT_FIFO_CFG_1_TX_FIFO_MIN_TH (0xff << 6) 482 #define MVPP2_PORT_FIFO_CFG_1_PORT_EN_FIX_EN BIT(15) 483 484 /* Port Serdes Configuration0 */ 485 #define MVPP2_PORT_SERDES_CFG0_REG 0x0028 486 #define MVPP2_PORT_SERDES_CFG0_SERDESRESET BIT(0) 487 #define MVPP2_PORT_SERDES_CFG0_PU_TX BIT(1) 488 #define MVPP2_PORT_SERDES_CFG0_PU_RX BIT(2) 489 #define MVPP2_PORT_SERDES_CFG0_PU_PLL BIT(3) 490 #define MVPP2_PORT_SERDES_CFG0_PU_IVREF BIT(4) 491 #define MVPP2_PORT_SERDES_CFG0_TESTEN BIT(5) 492 #define MVPP2_PORT_SERDES_CFG0_DPHER_EN BIT(6) 493 #define MVPP2_PORT_SERDES_CFG0_RUDI_INVALID_ENABLE BIT(7) 494 #define MVPP2_PORT_SERDES_CFG0_ACK_OVERRIDE_ENABLE BIT(8) 495 #define MVPP2_PORT_SERDES_CFG0_CONFIG_WORD_ENABLE BIT(9) 496 #define MVPP2_PORT_SERDES_CFG0_SYNC_FAIL_INT_ENABLE BIT(10) 497 #define MVPP2_PORT_SERDES_CFG0_MASTER_MODE_ENABLE BIT(11) 498 #define MVPP2_PORT_SERDES_CFG0_TERM75_TX BIT(12) 499 #define MVPP2_PORT_SERDES_CFG0_OUTAMP BIT(13) 500 #define MVPP2_PORT_SERDES_CFG0_BTS712_FIX_EN BIT(14) 501 #define MVPP2_PORT_SERDES_CFG0_BTS156_FIX_EN BIT(15) 502 503 /* Port Serdes Configuration1 */ 504 #define MVPP2_PORT_SERDES_CFG1_REG 0x002c 505 #define MVPP2_PORT_SERDES_CFG1_SMII_RX_10MB_CLK_EDGE_SEL BIT(0) 506 #define MVPP2_GMAC_PORT_SERDES_CFG1_SMII_TX_10MB_CLK_EDGE_SEL BIT(1) 507 #define MVPP2_GMAC_PORT_SERDES_CFG1_MEN (0x3 << 2) 508 #define MVPP2_GMAC_PORT_SERDES_CFG1_VCMS BIT(4) 509 #define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_USE_SIGDET BIT(5) 510 #define MVPP2_GMAC_PORT_SERDES_CFG1_EN_CRS_MASK_TX BIT(6) 511 #define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_ENABLE BIT(7) 512 #define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_PHY_ADDRESS (0x1f << 8) 513 #define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SIGDET_POLARITY BIT(13) 514 #define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_INTERRUPT_POLARITY BIT(14) 515 #define MVPP2_GMAC_PORT_SERDES_CFG1_100FX_PCS_SERDES_POLARITY BIT(15) 516 517 /* Port Serdes Configuration2 */ 518 #define MVPP2_PORT_SERDES_CFG2_REG 0x0030 519 #define MVPP2_PORT_SERDES_CFG2_AN_ADV_CONFIGURATION (0xffff << 0) 520 521 /* Port Serdes Configuration3 */ 522 #define MVPP2_PORT_SERDES_CFG3_REG 0x0034 523 #define MVPP2_PORT_SERDES_CFG3_ABILITY_MATCH_STATUS (0xffff << 0) 524 525 /* Port Prbs Status */ 526 #define MVPP2_PORT_PRBS_STATUS_REG 0x0038 527 #define MVPP2_PORT_PRBS_STATUS_PRBSCHECK_LOCKED BIT(0) 528 #define MVPP2_PORT_PRBS_STATUS_PRBSCHECKRDY BIT(1) 529 530 /* Port Prbs Error Counter */ 531 #define MVPP2_PORT_PRBS_ERR_CNTR_REG 0x003c 532 #define MVPP2_PORT_PRBS_ERR_CNTR_PRBSBITERRCNT (0xffff << 0) 533 534 /* Port Status1 */ 535 #define MVPP2_PORT_STATUS1_REG 0x0040 536 #define MVPP2_PORT_STATUS1_MEDIAACTIVE BIT(0) 537 538 /* Port Mib Counters Control */ 539 #define MVPP2_PORT_MIB_CNTRS_CTRL_REG 0x0044 540 #define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_COPY_TRIGGER BIT(0) 541 #define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_CLEAR_ON_READ BIT(1) 542 #define MVPP2_PORT_MIB_CNTRS_CTRL_RX_HISTOGRAM_EN BIT(2) 543 #define MVPP2_PORT_MIB_CNTRS_CTRL_TX_HISTOGRAM_EN BIT(3) 544 #define MVPP2_PORT_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE BIT(4) 545 #define MVPP2_PORT_MIB_CNTRS_CTRL_XCAT_BTS_340_EN BIT(5) 546 #define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST BIT(6) 547 #define MVPP2_PORT_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522 BIT(7) 548 549 /* Port Mac Control3 */ 550 #define MVPP2_PORT_CTRL3_REG 0x0048 551 #define MVPP2_PORT_CTRL3_BUF_SIZE (0x3f << 0) 552 #define MVPP2_PORT_CTRL3_IPG_DATA (0x1ff << 6) 553 #define MVPP2_PORT_CTRL3_LLFC_GLOBAL_FC_ENABLE BIT(15) 554 555 /* Port Mac Control4 */ 556 #define MVPP2_PORT_CTRL4_REG 0x0090 557 #define MVPP2_PORT_CTRL4_EXT_PIN_GMII_SEL BIT(0) 558 #define MVPP2_PORT_CTRL4_PREAMBLE_FIX BIT(1) 559 #define MVPP2_PORT_CTRL4_SQ_DETECT_FIX_EN BIT(2) 560 #define MVPP2_PORT_CTRL4_FC_EN_RX BIT(3) 561 #define MVPP2_PORT_CTRL4_FC_EN_TX BIT(4) 562 #define MVPP2_PORT_CTRL4_DP_CLK_SEL BIT(5) 563 #define MVPP2_PORT_CTRL4_SYNC_BYPASS BIT(6) 564 #define MVPP2_PORT_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) 565 #define MVPP2_PORT_CTRL4_COUNT_EXTERNAL_FC_EN BIT(8) 566 #define MVPP2_PORT_CTRL4_MARVELL_HEADER_EN BIT(9) 567 #define MVPP2_PORT_CTRL4_LEDS_NUMBER BIT(10) 568 569 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 570 571 /* MPCS registers */ 572 #define MVPP22_MPCS40G_COMMON_CONTROL 0x14 573 #define MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK BIT(10) 574 #define MVPP22_MPCS_CLOCK_RESET 0x14c 575 #define MVPP22_MPCS_TX_SD_CLK_RESET BIT(0) 576 #define MVPP22_MPCS_RX_SD_CLK_RESET BIT(1) 577 #define MVPP22_MPCS_MAC_CLK_RESET BIT(2) 578 #define MVPP22_MPCS_CLK_DIVISION_RATIO_MASK (0x7 << 4) 579 #define MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT (0x1 << 4) 580 #define MVPP22_MPCS_CLK_DIV_PHASE_SET BIT(11) 581 582 /* XPCS registers */ 583 #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0 584 #define MVPP22_XPCS_PCSRESET BIT(0) 585 #define MVPP22_XPCS_PCSMODE_OFFS 3 586 #define MVPP22_XPCS_PCSMODE_MASK (0x3 << MVPP22_XPCS_PCSMODE_OFFS) 587 #define MVPP22_XPCS_LANEACTIVE_OFFS 5 588 #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << MVPP22_XPCS_LANEACTIVE_OFFS) 589 590 /* System controller registers. Accessed through a regmap. */ 591 #define GENCONF_SOFT_RESET1 0x1108 592 #define GENCONF_SOFT_RESET1_GOP BIT(6) 593 #define GENCONF_PORT_CTRL0 0x1110 594 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) 595 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) 596 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) 597 #define GENCONF_PORT_CTRL1 0x1114 598 #define GENCONF_PORT_CTRL1_EN(p) BIT(p) 599 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) 600 #define GENCONF_CTRL0 0x1120 601 #define GENCONF_CTRL0_PORT0_RGMII BIT(0) 602 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) 603 #define GENCONF_CTRL0_PORT1_RGMII BIT(2) 604 605 /* Various constants */ 606 607 /* Coalescing */ 608 #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 609 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL 610 #define MVPP2_TXDONE_COAL_USEC 1000 611 #define MVPP2_RX_COAL_PKTS 32 612 #define MVPP2_RX_COAL_USEC 64 613 614 /* 615 * The two bytes Marvell header. Either contains a special value used 616 * by Marvell switches when a specific hardware mode is enabled (not 617 * supported by this driver) or is filled automatically by zeroes on 618 * the RX side. Those two bytes being at the front of the Ethernet 619 * header, they allow to have the IP header aligned on a 4 bytes 620 * boundary automatically: the hardware skips those two bytes on its 621 * own. 622 */ 623 #define MVPP2_MH_SIZE 2 624 #define MVPP2_ETH_TYPE_LEN 2 625 #define MVPP2_PPPOE_HDR_SIZE 8 626 #define MVPP2_VLAN_TAG_LEN 4 627 628 /* Lbtd 802.3 type */ 629 #define MVPP2_IP_LBDT_TYPE 0xfffa 630 631 #define MVPP2_CPU_D_CACHE_LINE_SIZE 32 632 #define MVPP2_TX_CSUM_MAX_SIZE 9800 633 634 /* Timeout constants */ 635 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 636 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 637 638 #define MVPP2_TX_MTU_MAX 0x7ffff 639 640 /* Maximum number of T-CONTs of PON port */ 641 #define MVPP2_MAX_TCONT 16 642 643 /* Maximum number of supported ports */ 644 #define MVPP2_MAX_PORTS 4 645 646 /* Maximum number of TXQs used by single port */ 647 #define MVPP2_MAX_TXQ 8 648 649 /* Maximum number of RXQs used by single port */ 650 #define MVPP2_MAX_RXQ 8 651 652 /* Dfault number of RXQs in use */ 653 #define MVPP2_DEFAULT_RXQ 4 654 655 /* Total number of RXQs available to all ports */ 656 #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ) 657 658 /* Max number of Rx descriptors */ 659 #define MVPP2_MAX_RXD 64 660 661 /* Max number of Tx descriptors */ 662 #define MVPP2_MAX_TXD 32 663 664 /* Amount of Tx descriptors that can be reserved at once by CPU */ 665 #define MVPP2_CPU_DESC_CHUNK 64 666 667 /* Max number of Tx descriptors in each aggregated queue */ 668 #define MVPP2_AGGR_TXQ_SIZE 256 669 670 /* Descriptor aligned size */ 671 #define MVPP2_DESC_ALIGNED_SIZE 32 672 673 /* Descriptor alignment mask */ 674 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) 675 676 /* RX FIFO constants */ 677 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 678 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 679 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 680 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 681 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 682 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 683 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 684 685 /* TX FIFO constants */ 686 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa 687 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 688 #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 689 #define MVPP2_TX_FIFO_THRESHOLD_10KB \ 690 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 691 #define MVPP2_TX_FIFO_THRESHOLD_3KB \ 692 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 693 694 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 695 696 /* IPv6 max L3 address size */ 697 #define MVPP2_MAX_L3_ADDR_SIZE 16 698 699 /* Port flags */ 700 #define MVPP2_F_LOOPBACK BIT(0) 701 702 /* SD1 Control1 */ 703 #define SD1_CONTROL_1_REG 0x148 704 #define SD1_CONTROL_RXAUI1_L45_EN_MASK BIT(26) 705 #define SD1_CONTROL_RXAUI0_L23_EN_MASK BIT(27) 706 #define SD1_CONTROL_XAUI_EN_MASK BIT(28) 707 708 /* System Soft Reset 1 */ 709 #define MV_GOP_SOFT_RESET_1_REG 0x108 710 #define NETC_GOP_SOFT_RESET BIT(6) 711 712 /* Ports Control 0 */ 713 #define MV_NETCOMP_PORTS_CONTROL_0 0x110 714 #define NETC_GOP_ENABLE_MASK BIT(0) 715 #define NETC_BUS_WIDTH_SELECT_MASK BIT(1) 716 #define NETC_GIG_RX_DATA_SAMPLE_MASK BIT(29) 717 #define NETC_CLK_DIV_PHASE_MASK BIT(31) 718 719 /* Ports Control 1 */ 720 #define MV_NETCOMP_PORTS_CONTROL_1 0x114 721 #define NETC_PORTS_ACTIVE_MASK(port) (1 << (port)) 722 #define NETC_PORT_GIG_RF_RESET_MASK(port) (1 << (28 + (port))) 723 724 /* Ports Status */ 725 #define MV_NETCOMP_PORTS_STATUS 0x11C 726 #define NETC_PORTS_STATUS_MASK(port) (1 << (port)) 727 728 /* Networking Complex Control 0 */ 729 #define MV_NETCOMP_CONTROL_0 0x120 730 #define NETC_GBE_PORT0_SGMII_MODE_MASK BIT(0) 731 #define NETC_GBE_PORT1_SGMII_MODE_MASK BIT(1) 732 #define NETC_GBE_PORT1_MII_MODE_MASK BIT(2) 733 734 /* Port Mac Control0 */ 735 #define MV_XLG_PORT_MAC_CTRL0_REG 0x0000 736 #define MV_XLG_MAC_CTRL0_PORTEN BIT(0) 737 #define MV_XLG_MAC_CTRL0_MACRESETN BIT(1) 738 #define MV_XLG_MAC_CTRL0_FORCELINKDOWN BIT(2) 739 #define MV_XLG_MAC_CTRL0_FORCELINKPASS BIT(3) 740 #define MV_XLG_MAC_CTRL0_TXIPGMODE (0x3 << 5) 741 #define MV_XLG_MAC_CTRL0_RXFCEN BIT(7) 742 #define MV_XLG_MAC_CTRL0_TXFCEN BIT(8) 743 #define MV_XLG_MAC_CTRL0_RXCRCCHECKEN BIT(9) 744 #define MV_XLG_MAC_CTRL0_PERIODICXONEN BIT(10) 745 #define MV_XLG_MAC_CTRL0_RXCRCSTRIPEN BIT(11) 746 #define MV_XLG_MAC_CTRL0_PADDINGDIS BIT(13) 747 #define MV_XLG_MAC_CTRL0_MIBCNTDIS BIT(14) 748 #define MV_XLG_MAC_CTRL0_PFC_CASCADE_PORT_ENABLE BIT(15) 749 750 /* Port Mac Control1 */ 751 #define MV_XLG_PORT_MAC_CTRL1_REG 0x0004 752 #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS 0 753 #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK 0x1fff 754 #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT 0x1400 755 #define MV_XLG_MAC_CTRL1_MACLOOPBACKEN BIT(13) 756 #define MV_XLG_MAC_CTRL1_XGMIILOOPBACKEN BIT(14) 757 #define MV_XLG_MAC_CTRL1_LOOPBACKCLOCKSELECT BIT(15) 758 759 /* Port Mac Control2 */ 760 #define MV_XLG_PORT_MAC_CTRL2_REG 0x0008 761 #define MV_XLG_MAC_CTRL2_SALOW_7_0 (0xff << 0) 762 #define MV_XLG_MAC_CTRL2_UNIDIRECTIONALEN BIT(8) 763 #define MV_XLG_MAC_CTRL2_FIXEDIPGBASE BIT(9) 764 #define MV_XLG_MAC_CTRL2_PERIODICXOFFEN BIT(10) 765 #define MV_XLG_MAC_CTRL2_SIMPLEXMODEEN BIT(13) 766 #define MV_XLG_MAC_CTRL2_FC_MODE (0x3 << 14) 767 768 /* Port Status */ 769 #define MV_XLG_MAC_PORT_STATUS_REG 0x000c 770 #define MV_XLG_MAC_PORT_STATUS_LINKSTATUS BIT(0) 771 #define MV_XLG_MAC_PORT_STATUS_REMOTEFAULT BIT(1) 772 #define MV_XLG_MAC_PORT_STATUS_LOCALFAULT BIT(2) 773 #define MV_XLG_MAC_PORT_STATUS_LINKSTATUSCLEAN BIT(3) 774 #define MV_XLG_MAC_PORT_STATUS_LOCALFAULTCLEAN BIT(4) 775 #define MV_XLG_MAC_PORT_STATUS_REMOTEFAULTCLEAN BIT(5) 776 #define MV_XLG_MAC_PORT_STATUS_PORTRXPAUSE BIT(6) 777 #define MV_XLG_MAC_PORT_STATUS_PORTTXPAUSE BIT(7) 778 #define MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL BIT(8) 779 780 /* Port Fifos Thresholds Configuration */ 781 #define MV_XLG_PORT_FIFOS_THRS_CFG_REG 0x0010 782 #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR (0x1f << 0) 783 #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXFIFOSIZE (0x3f << 5) 784 #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_TXRDTHR (0x1f << 11) 785 786 /* Port Mac Control3 */ 787 #define MV_XLG_PORT_MAC_CTRL3_REG 0x001c 788 #define MV_XLG_MAC_CTRL3_BUFSIZE (0x3f << 0) 789 #define MV_XLG_MAC_CTRL3_XTRAIPG (0x7f << 6) 790 #define MV_XLG_MAC_CTRL3_MACMODESELECT_MASK (0x7 << 13) 791 #define MV_XLG_MAC_CTRL3_MACMODESELECT_GMAC (0x0 << 13) 792 #define MV_XLG_MAC_CTRL3_MACMODESELECT_10G (0x1 << 13) 793 794 /* Port Per Prio Flow Control Status */ 795 #define MV_XLG_PORT_PER_PRIO_FLOW_CTRL_STATUS_REG 0x0020 796 #define MV_XLG_MAC_PORT_PER_PRIO_FLOW_CTRL_STATUS_PRIONSTATUS BIT(0) 797 798 /* Debug Bus Status */ 799 #define MV_XLG_DEBUG_BUS_STATUS_REG 0x0024 800 #define MV_XLG_MAC_DEBUG_BUS_STATUS_DEBUG_BUS (0xffff << 0) 801 802 /* Port Metal Fix */ 803 #define MV_XLG_PORT_METAL_FIX_REG 0x002c 804 #define MV_XLG_MAC_PORT_METAL_FIX_EN_EOP_IN_FIFO BIT(0) 805 #define MV_XLG_MAC_PORT_METAL_FIX_EN_LTF_FIX BIT(1) 806 #define MV_XLG_MAC_PORT_METAL_FIX_EN_HOLD_FIX BIT(2) 807 #define MV_XLG_MAC_PORT_METAL_FIX_EN_LED_FIX BIT(3) 808 #define MV_XLG_MAC_PORT_METAL_FIX_EN_PAD_PROTECT BIT(4) 809 #define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS44 BIT(5) 810 #define MV_XLG_MAC_PORT_METAL_FIX_EN_NX_BTS42 BIT(6) 811 #define MV_XLG_MAC_PORT_METAL_FIX_EN_FLUSH_FIX BIT(7) 812 #define MV_XLG_MAC_PORT_METAL_FIX_EN_PORT_EN_FIX BIT(8) 813 #define MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF0_BITS (0xf << 9) 814 #define MV_XLG_MAC_PORT_METAL_FIX_SPARE_DEF1_BITS (0x7 << 13) 815 816 /* Xg Mib Counters Control */ 817 #define MV_XLG_MIB_CNTRS_CTRL_REG 0x0030 818 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGCAPTURETRIGGER BIT(0) 819 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGDONTCLEARAFTERREAD BIT(1) 820 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGRXHISTOGRAMEN BIT(2) 821 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_XGTXHISTOGRAMEN BIT(3) 822 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MFA1_BTT940_FIX_ENABLE BIT(4) 823 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_LEDS_NUMBER (0x3f << 5) 824 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_COUNT_HIST BIT(11) 825 #define MV_XLG_MAC_XG_MIB_CNTRS_CTRL_MIB_4_LIMIT_1518_1522 BIT(12) 826 827 /* Cn/ccfc Timer%i */ 828 #define MV_XLG_CNCCFC_TIMERI_REG(t) ((0x0038 + (t) * 4)) 829 #define MV_XLG_MAC_CNCCFC_TIMERI_PORTSPEEDTIMER (0xffff << 0) 830 831 /* Ppfc Control */ 832 #define MV_XLG_MAC_PPFC_CTRL_REG 0x0060 833 #define MV_XLG_MAC_PPFC_CTRL_GLOBAL_PAUSE_ENI BIT(0) 834 #define MV_XLG_MAC_PPFC_CTRL_DIP_BTS_677_EN BIT(9) 835 836 /* Fc Dsa Tag 0 */ 837 #define MV_XLG_MAC_FC_DSA_TAG_0_REG 0x0068 838 #define MV_XLG_MAC_FC_DSA_TAG_0_DSATAGREG0 (0xffff << 0) 839 840 /* Fc Dsa Tag 1 */ 841 #define MV_XLG_MAC_FC_DSA_TAG_1_REG 0x006c 842 #define MV_XLG_MAC_FC_DSA_TAG_1_DSATAGREG1 (0xffff << 0) 843 844 /* Fc Dsa Tag 2 */ 845 #define MV_XLG_MAC_FC_DSA_TAG_2_REG 0x0070 846 #define MV_XLG_MAC_FC_DSA_TAG_2_DSATAGREG2 (0xffff << 0) 847 848 /* Fc Dsa Tag 3 */ 849 #define MV_XLG_MAC_FC_DSA_TAG_3_REG 0x0074 850 #define MV_XLG_MAC_FC_DSA_TAG_3_DSATAGREG3 (0xffff << 0) 851 852 /* Dic Budget Compensation */ 853 #define MV_XLG_MAC_DIC_BUDGET_COMPENSATION_REG 0x0080 854 #define MV_XLG_MAC_DIC_BUDGET_COMPENSATION_DIC_COUNTER_TO_ADD_8BYTES (0xffff << 0) 855 856 /* Port Mac Control4 */ 857 #define MV_XLG_PORT_MAC_CTRL4_REG 0x0084 858 #define MV_XLG_MAC_CTRL4_LLFC_GLOBAL_FC_ENABLE BIT(0) 859 #define MV_XLG_MAC_CTRL4_LED_STREAM_SELECT BIT(1) 860 #define MV_XLG_MAC_CTRL4_DEBUG_BUS_SELECT BIT(2) 861 #define MV_XLG_MAC_CTRL4_MASK_PCS_RESET BIT(3) 862 #define MV_XLG_MAC_CTRL4_ENABLE_SHORT_PREAMBLE_FOR_XLG BIT(4) 863 #define MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN BIT(5) 864 #define MV_XLG_MAC_CTRL4_FORWARD_PFC_EN BIT(6) 865 #define MV_XLG_MAC_CTRL4_FORWARD_UNKNOWN_FC_EN BIT(7) 866 #define MV_XLG_MAC_CTRL4_USE_XPCS BIT(8) 867 #define MV_XLG_MAC_CTRL4_DMA_INTERFACE_IS_64_BIT BIT(9) 868 #define MV_XLG_MAC_CTRL4_TX_DMA_INTERFACE_BITS (0x3 << 10) 869 #define MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G BIT(12) 870 #define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK BIT(14) 871 872 /* Port Mac Control5 */ 873 #define MV_XLG_PORT_MAC_CTRL5_REG 0x0088 874 #define MV_XLG_MAC_CTRL5_TXIPGLENGTH (0xf << 0) 875 #define MV_XLG_MAC_CTRL5_PREAMBLELENGTHTX (0x7 << 4) 876 #define MV_XLG_MAC_CTRL5_PREAMBLELENGTHRX (0x7 << 7) 877 #define MV_XLG_MAC_CTRL5_TXNUMCRCBYTES (0x7 << 10) 878 #define MV_XLG_MAC_CTRL5_RXNUMCRCBYTES (0x7 << 13) 879 880 /* External Control */ 881 #define MV_XLG_MAC_EXT_CTRL_REG 0x0090 882 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL0 BIT(0) 883 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL1 BIT(1) 884 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL2 BIT(2) 885 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL3 BIT(3) 886 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL4 BIT(4) 887 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL5 BIT(5) 888 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL6 BIT(6) 889 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL7 BIT(7) 890 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL8 BIT(8) 891 #define MV_XLG_MAC_EXT_CTRL_EXTERNAL_CTRL9 BIT(9) 892 #define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_10 BIT(10) 893 #define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_11 BIT(11) 894 #define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_12 BIT(12) 895 #define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_13 BIT(13) 896 #define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_14 BIT(14) 897 #define MV_XLG_MAC_EXT_CTRL_EXT_CTRL_15 BIT(15) 898 899 /* Macro Control */ 900 #define MV_XLG_MAC_MACRO_CTRL_REG 0x0094 901 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_0 BIT(0) 902 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_1 BIT(1) 903 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_2 BIT(2) 904 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_3 BIT(3) 905 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_4 BIT(4) 906 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_5 BIT(5) 907 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_6 BIT(6) 908 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_7 BIT(7) 909 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_8 BIT(8) 910 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_9 BIT(9) 911 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_10 BIT(10) 912 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_11 BIT(11) 913 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_12 BIT(12) 914 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_13 BIT(13) 915 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_14 BIT(14) 916 #define MV_XLG_MAC_MACRO_CTRL_MACRO_CTRL_15 BIT(15) 917 918 #define MV_XLG_MAC_DIC_PPM_IPG_REDUCE_REG 0x0094 919 920 /* Port Interrupt Cause */ 921 #define MV_XLG_INTERRUPT_CAUSE_REG 0x0014 922 /* Port Interrupt Mask */ 923 #define MV_XLG_INTERRUPT_MASK_REG 0x0018 924 #define MV_XLG_SUMMARY_INTERRUPT_MASK BIT(0) 925 #define MV_XLG_INTERRUPT_LINK_CHANGE BIT(1) 926 927 /* Port Interrupt Summary Cause */ 928 #define MV_XLG_EXTERNAL_INTERRUPT_CAUSE_REG 0x0058 929 /* Port Interrupt Summary Mask */ 930 #define MV_XLG_EXTERNAL_INTERRUPT_MASK_REG 0x005C 931 #define MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_XLG BIT(1) 932 #define MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_GIG BIT(2) 933 934 /*All PPV22 Addresses are 40-bit */ 935 #define MVPP22_ADDR_HIGH_SIZE 8 936 #define MVPP22_ADDR_HIGH_MASK ((1 << MVPP22_ADDR_HIGH_SIZE) - 1) 937 #define MVPP22_ADDR_MASK (0xFFFFFFFFFF) 938 939 /* PHY address register */ 940 #define MV_SMI_PHY_ADDRESS_REG(n) (0xC + 0x4 * (n)) 941 #define MV_SMI_PHY_ADDRESS_PHYAD_OFFS 0 942 #define MV_SMI_PHY_ADDRESS_PHYAD_MASK (0x1F << MV_SMI_PHY_ADDRESS_PHYAD_OFFS) 943 944 /* Marvell tag types */ 945 enum mvpp2_tag_type { 946 MVPP2_TAG_TYPE_NONE = 0, 947 MVPP2_TAG_TYPE_MH = 1, 948 MVPP2_TAG_TYPE_DSA = 2, 949 MVPP2_TAG_TYPE_EDSA = 3, 950 MVPP2_TAG_TYPE_VLAN = 4, 951 MVPP2_TAG_TYPE_LAST = 5 952 }; 953 954 /* L2 cast enum */ 955 enum mvpp2_prs_l2_cast { 956 MVPP2_PRS_L2_UNI_CAST, 957 MVPP2_PRS_L2_MULTI_CAST, 958 }; 959 960 /* L3 cast enum */ 961 enum mvpp2_prs_l3_cast { 962 MVPP2_PRS_L3_UNI_CAST, 963 MVPP2_PRS_L3_MULTI_CAST, 964 MVPP2_PRS_L3_BROAD_CAST 965 }; 966 967 /* Parser constants */ 968 #define MVPP2_PRS_TCAM_SRAM_SIZE 256 969 #define MVPP2_PRS_TCAM_WORDS 6 970 #define MVPP2_PRS_SRAM_WORDS 4 971 #define MVPP2_PRS_FLOW_ID_SIZE 64 972 #define MVPP2_PRS_FLOW_ID_MASK 0x3f 973 #define MVPP2_PRS_TCAM_ENTRY_INVALID 1 974 #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) 975 #define MVPP2_PRS_IPV4_HEAD 0x40 976 #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0 977 #define MVPP2_PRS_IPV4_MC 0xe0 978 #define MVPP2_PRS_IPV4_MC_MASK 0xf0 979 #define MVPP2_PRS_IPV4_BC_MASK 0xff 980 #define MVPP2_PRS_IPV4_IHL 0x5 981 #define MVPP2_PRS_IPV4_IHL_MASK 0xf 982 #define MVPP2_PRS_IPV6_MC 0xff 983 #define MVPP2_PRS_IPV6_MC_MASK 0xff 984 #define MVPP2_PRS_IPV6_HOP_MASK 0xff 985 #define MVPP2_PRS_TCAM_PROTO_MASK 0xff 986 #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f 987 #define MVPP2_PRS_DBL_VLANS_MAX 100 988 989 /* 990 * Tcam structure: 991 * - lookup ID - 4 bits 992 * - port ID - 1 byte 993 * - additional information - 1 byte 994 * - header data - 8 bytes 995 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). 996 */ 997 #define MVPP2_PRS_AI_BITS 8 998 #define MVPP2_PRS_PORT_MASK 0xff 999 #define MVPP2_PRS_LU_MASK 0xf 1000 #define MVPP2_PRS_TCAM_DATA_BYTE(offs) (((offs) - ((offs) % 2)) * 2 + ((offs) % 2)) 1001 #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) (((offs) * 2) - ((offs) % 2) + 2) 1002 #define MVPP2_PRS_TCAM_AI_BYTE 16 1003 #define MVPP2_PRS_TCAM_PORT_BYTE 17 1004 #define MVPP2_PRS_TCAM_LU_BYTE 20 1005 #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2) 1006 #define MVPP2_PRS_TCAM_INV_WORD 5 1007 /* Tcam entries ID */ 1008 #define MVPP2_PE_DROP_ALL 0 1009 #define MVPP2_PE_FIRST_FREE_TID 1 1010 #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31) 1011 #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30) 1012 #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29) 1013 #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28) 1014 #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27) 1015 #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26) 1016 #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19) 1017 #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18) 1018 #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17) 1019 #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16) 1020 #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15) 1021 #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14) 1022 #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13) 1023 #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12) 1024 #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11) 1025 #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10) 1026 #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9) 1027 #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8) 1028 #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7) 1029 #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6) 1030 #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5) 1031 #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4) 1032 #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3) 1033 #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2) 1034 #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1) 1035 1036 /* 1037 * Sram structure 1038 * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). 1039 */ 1040 #define MVPP2_PRS_SRAM_RI_OFFS 0 1041 #define MVPP2_PRS_SRAM_RI_WORD 0 1042 #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32 1043 #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1 1044 #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32 1045 #define MVPP2_PRS_SRAM_SHIFT_OFFS 64 1046 #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72 1047 #define MVPP2_PRS_SRAM_SHIFT_MASK 0xff 1048 #define MVPP2_PRS_SRAM_UDF_OFFS 73 1049 #define MVPP2_PRS_SRAM_UDF_BITS 8 1050 #define MVPP2_PRS_SRAM_UDF_MASK 0xff 1051 #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81 1052 #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82 1053 #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7 1054 #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1 1055 #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4 1056 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85 1057 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3 1058 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1 1059 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2 1060 #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3 1061 #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87 1062 #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2 1063 #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3 1064 #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0 1065 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2 1066 #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3 1067 #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89 1068 #define MVPP2_PRS_SRAM_AI_OFFS 90 1069 #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98 1070 #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8 1071 #define MVPP2_PRS_SRAM_AI_MASK 0xff 1072 #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106 1073 #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf 1074 #define MVPP2_PRS_SRAM_LU_DONE_BIT 110 1075 #define MVPP2_PRS_SRAM_LU_GEN_BIT 111 1076 1077 /* Sram result info bits assignment */ 1078 #define MVPP2_PRS_RI_MAC_ME_MASK 0x1 1079 #define MVPP2_PRS_RI_DSA_MASK 0x2 1080 #define MVPP2_PRS_RI_VLAN_MASK 0xc 1081 #define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3)) 1082 #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) 1083 #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) 1084 #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) 1085 #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 1086 #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) 1087 #define MVPP2_PRS_RI_L2_CAST_MASK 0x600 1088 #define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) 1089 #define MVPP2_PRS_RI_L2_MCAST BIT(9) 1090 #define MVPP2_PRS_RI_L2_BCAST BIT(10) 1091 #define MVPP2_PRS_RI_PPPOE_MASK 0x800 1092 #define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000 1093 #define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14)) 1094 #define MVPP2_PRS_RI_L3_IP4 BIT(12) 1095 #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) 1096 #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) 1097 #define MVPP2_PRS_RI_L3_IP6 BIT(14) 1098 #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) 1099 #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) 1100 #define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000 1101 #define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16)) 1102 #define MVPP2_PRS_RI_L3_MCAST BIT(15) 1103 #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) 1104 #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 1105 #define MVPP2_PRS_RI_UDF3_MASK 0x300000 1106 #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) 1107 #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000 1108 #define MVPP2_PRS_RI_L4_TCP BIT(22) 1109 #define MVPP2_PRS_RI_L4_UDP BIT(23) 1110 #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) 1111 #define MVPP2_PRS_RI_UDF7_MASK 0x60000000 1112 #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) 1113 #define MVPP2_PRS_RI_DROP_MASK 0x80000000 1114 1115 /* Sram additional info bits assignment */ 1116 #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) 1117 #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) 1118 #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) 1119 #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) 1120 #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) 1121 #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) 1122 #define MVPP2_PRS_SINGLE_VLAN_AI 0 1123 #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) 1124 1125 /* DSA/EDSA type */ 1126 #define MVPP2_PRS_TAGGED 1 1127 #define MVPP2_PRS_UNTAGGED 0 1128 #define MVPP2_PRS_EDSA 1 1129 #define MVPP2_PRS_DSA 0 1130 1131 /* MAC entries, shadow udf */ 1132 enum mvpp2_prs_udf { 1133 MVPP2_PRS_UDF_MAC_DEF, 1134 MVPP2_PRS_UDF_MAC_RANGE, 1135 MVPP2_PRS_UDF_L2_DEF, 1136 MVPP2_PRS_UDF_L2_DEF_COPY, 1137 MVPP2_PRS_UDF_L2_USER, 1138 }; 1139 1140 /* Lookup ID */ 1141 enum mvpp2_prs_lookup { 1142 MVPP2_PRS_LU_MH, 1143 MVPP2_PRS_LU_MAC, 1144 MVPP2_PRS_LU_DSA, 1145 MVPP2_PRS_LU_VLAN, 1146 MVPP2_PRS_LU_L2, 1147 MVPP2_PRS_LU_PPPOE, 1148 MVPP2_PRS_LU_IP4, 1149 MVPP2_PRS_LU_IP6, 1150 MVPP2_PRS_LU_FLOWS, 1151 MVPP2_PRS_LU_LAST, 1152 }; 1153 1154 /* Classifier constants */ 1155 #define MVPP2_CLS_FLOWS_TBL_SIZE 512 1156 #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3 1157 #define MVPP2_CLS_LKP_TBL_SIZE 64 1158 1159 /* BM cookie (32 bits) definition */ 1160 #define MVPP2_BM_COOKIE_POOL_OFFS 8 1161 #define MVPP2_BM_COOKIE_CPU_OFFS 24 1162 1163 /* 1164 * The MVPP2_TX_DESC and MVPP2_RX_DESC structures describe the 1165 * layout of the transmit and reception DMA descriptors, and their 1166 * layout is therefore defined by the hardware design 1167 */ 1168 #define MVPP2_TXD_L3_OFF_SHIFT 0 1169 #define MVPP2_TXD_IP_HLEN_SHIFT 8 1170 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) 1171 #define MVPP2_TXD_L4_CSUM_NOT BIT(14) 1172 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) 1173 #define MVPP2_TXD_PADDING_DISABLE BIT(23) 1174 #define MVPP2_TXD_L4_UDP BIT(24) 1175 #define MVPP2_TXD_L3_IP6 BIT(26) 1176 #define MVPP2_TXD_L_DESC BIT(28) 1177 #define MVPP2_TXD_F_DESC BIT(29) 1178 1179 #define MVPP2_RXD_ERR_SUMMARY BIT(15) 1180 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) 1181 #define MVPP2_RXD_ERR_CRC 0x0 1182 #define MVPP2_RXD_ERR_OVERRUN BIT(13) 1183 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) 1184 #define MVPP2_RXD_BM_POOL_ID_OFFS 16 1185 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) 1186 #define MVPP2_RXD_HWF_SYNC BIT(21) 1187 #define MVPP2_RXD_L4_CSUM_OK BIT(22) 1188 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) 1189 #define MVPP2_RXD_L4_TCP BIT(25) 1190 #define MVPP2_RXD_L4_UDP BIT(26) 1191 #define MVPP2_RXD_L3_IP4 BIT(28) 1192 #define MVPP2_RXD_L3_IP6 BIT(30) 1193 #define MVPP2_RXD_BUF_HDR BIT(31) 1194 1195 struct mvpp2_tx_desc { 1196 uint32_t command; /* Options used by HW for packet transmitting.*/ 1197 uint8_t packet_offset; /* the offset from the buffer beginning */ 1198 uint8_t phys_txq; /* destination queue ID */ 1199 uint16_t data_size; /* data size of transmitted packet in bytes */ 1200 uint64_t rsrvd_hw_cmd1; /* HwCmd (BM, PON, PNC) */ 1201 uint64_t buf_phys_addr_hw_cmd2; 1202 uint64_t buf_cookie_bm_qset_hw_cmd3; 1203 }; 1204 1205 struct mvpp2_rx_desc { 1206 uint32_t status; /* info about received packet */ 1207 uint16_t reserved1; /* ParserInfo (for future use, PnC) */ 1208 uint16_t data_size; /* size of received packet in bytes */ 1209 uint16_t rsrvd_gem; /* GemPortId (for future use, PON) */ 1210 uint16_t rsrvd_l4_csum; /* CsumL4 (for future use, PnC) */ 1211 uint32_t rsrvd_timestamp; 1212 uint64_t buf_phys_addr_key_hash; 1213 uint64_t buf_cookie_bm_qset_cls_info; 1214 }; 1215 1216 union mvpp2_prs_tcam_entry { 1217 uint32_t word[MVPP2_PRS_TCAM_WORDS]; 1218 uint8_t byte[MVPP2_PRS_TCAM_WORDS * 4]; 1219 }; 1220 1221 union mvpp2_prs_sram_entry { 1222 uint32_t word[MVPP2_PRS_SRAM_WORDS]; 1223 uint8_t byte[MVPP2_PRS_SRAM_WORDS * 4]; 1224 }; 1225 1226 struct mvpp2_prs_entry { 1227 uint32_t index; 1228 union mvpp2_prs_tcam_entry tcam; 1229 union mvpp2_prs_sram_entry sram; 1230 }; 1231 1232 struct mvpp2_prs_shadow { 1233 int valid; 1234 int finish; 1235 1236 /* Lookup ID */ 1237 int32_t lu; 1238 1239 /* User defined offset */ 1240 int32_t udf; 1241 1242 /* Result info */ 1243 uint32_t ri; 1244 uint32_t ri_mask; 1245 }; 1246 1247 struct mvpp2_cls_flow_entry { 1248 uint32_t index; 1249 uint32_t data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS]; 1250 }; 1251 1252 struct mvpp2_cls_lookup_entry { 1253 uint32_t lkpid; 1254 uint32_t way; 1255 uint32_t data; 1256 }; 1257 1258 typedef struct { 1259 uint32_t NextBuffPhysAddr; 1260 uint32_t NextBuffVirtAddr; 1261 uint16_t ByteCount; 1262 uint16_t info; 1263 uint8_t reserved1; /* BmQset (for future use, BM) */ 1264 } MVPP2_BUFF_HDR; 1265 1266 /* Buffer header info bits */ 1267 #define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff 1268 #define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK) 1269 #define MVPP2_B_HDR_INFO_LAST_OFFS 12 1270 #define MVPP2_B_HDR_INFO_LAST_MASK BIT(12) 1271 #define MVPP2_B_HDR_INFO_IS_LAST(info) ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS) 1272 1273 /* SerDes */ 1274 #define MVPP2_SFI_LANE_COUNT 1 1275 1276 #endif /* __MVPP2_LIB_HW__ */ 1277