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feedback and ok tb@ jmc@ ok ratchov@

Implement multicast support in mvpp(4) to make IPv6 work. With this
change it's also not necessary to remember the old lladdr, since the
old one will be purged automatically prior to installing the

Implement multicast support in mvpp(4) to make IPv6 work. With this
change it's also not necessary to remember the old lladdr, since the
old one will be purged automatically prior to installing the current
set of multicast addresses.

Complaint filed by matthieu@

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U-Boot might not have cleaned its pools. The pool needs to be empty
before we fill it, otherwise our packets are written to wherever U-Boot
allocated memory. Cleaning it up ourselves is worrying as

U-Boot might not have cleaned its pools. The pool needs to be empty
before we fill it, otherwise our packets are written to wherever U-Boot
allocated memory. Cleaning it up ourselves is worrying as well, since
the BM's pages are probably in our own memory. Best we can do is stop
the BM, set new memory and drain the pool. Tests show that this still
returns U-Boot's entries. Now, where have those been stored... in HW
or in memory?

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Disable HW PHY polling. It's enabled by default.

Rework unicast/multicast configuration. Keep note that this only changes
the code configuring the parser, we do not yet add the proper multicast
filters.

Remove unnecessary BM cookie defines.

Rename gmac interrupt register defines to stay consistent with other gmac
register defines.

Add enum for L2 cast like for L3.

Some register define renaming.

Remove an unnecessary define.

Even more whitespace and header changes.

More whitespace and enum cleanup.

Plenty of whitespace fixups.

Init GOP and COMPHY.

Use correct ethertype and IP proto defines.

Use 1U for BIT(x), always define it and use it in four more places.

Add mvpp(4), a driver for the Marvell Packet Processor v2, as used on
the Armada 7K and 8K SoCs. Additionally, it seems to be used on the
upcoming CN9K SoCs. This only supports version v2.2, since

Add mvpp(4), a driver for the Marvell Packet Processor v2, as used on
the Armada 7K and 8K SoCs. Additionally, it seems to be used on the
upcoming CN9K SoCs. This only supports version v2.2, since the older
v2.1 is only used on some old ARMv7 we have no support for, and where
there is no hardware for us to support.

A huge part of this driver is configuring the TCAM/SRAM-based "parser".
Thus most of the code, especially the parser handling, was ported from
EDK2 with a sed script doing plenty of automatic renaming and un-camel-
casing.

The controller supports multiple TX/RX queues/vectors and RSS, so this
would be a nice platform for testing network processing improvement on
arm64. For now though we only configure and use a single queue.

The driver is still unfinished, but it's time to continue the work in
tree. At least we can already send and receive packets, good enough
for dhclient to work.

Since the MACCHIATObin uses Clause 45 10G PHYs and SFPs, link state
handling is still a bit bogus, as we have no support for that. The
1G RJ45 port works fine though.

ok dlg@

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