1 /* $OpenBSD: wdcvar.h,v 1.44 2009/10/13 19:33:16 pirofti Exp $ */ 2 /* $NetBSD: wdcvar.h,v 1.17 1999/04/11 20:50:29 bouyer Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_IC_WDCVAR_H_ 34 #define _DEV_IC_WDCVAR_H_ 35 36 #include <sys/timeout.h> 37 38 struct channel_queue { /* per channel queue (may be shared) */ 39 TAILQ_HEAD(xferhead, wdc_xfer) sc_xfer; 40 }; 41 42 struct channel_softc_vtbl; 43 44 45 #define WDC_OPTION_PROBE_VERBOSE 0x10000 46 47 struct channel_softc { /* Per channel data */ 48 struct channel_softc_vtbl *_vtbl; 49 50 /* Our location */ 51 int channel; 52 /* Our controller's softc */ 53 struct wdc_softc *wdc; 54 /* Our registers */ 55 bus_space_tag_t cmd_iot; 56 bus_space_handle_t cmd_ioh; 57 bus_size_t cmd_iosz; 58 bus_space_tag_t ctl_iot; 59 bus_space_handle_t ctl_ioh; 60 bus_size_t ctl_iosz; 61 /* data32{iot,ioh} are only used for 32 bit xfers */ 62 bus_space_tag_t data32iot; 63 bus_space_handle_t data32ioh; 64 /* Our state */ 65 int ch_flags; 66 #define WDCF_ACTIVE 0x01 /* channel is active */ 67 #define WDCF_ONESLAVE 0x02 /* slave-only channel */ 68 #define WDCF_IRQ_WAIT 0x10 /* controller is waiting for irq */ 69 #define WDCF_DMA_WAIT 0x20 /* controller is waiting for DMA */ 70 #define WDCF_VERBOSE_PROBE 0x40 /* verbose probe */ 71 u_int8_t ch_status; /* copy of status register */ 72 u_int8_t ch_prev_log_status; /* previous logged value of status reg */ 73 u_int8_t ch_log_idx; 74 u_int8_t ch_error; /* copy of error register */ 75 /* per-drive infos */ 76 struct ata_drive_datas ch_drive[2]; 77 78 /* 79 * channel queues. May be the same for all channels, if hw channels 80 * are not independent. 81 */ 82 struct channel_queue *ch_queue; 83 struct timeout ch_timo; 84 }; 85 86 /* 87 * Disk Controller register definitions. 88 */ 89 #define _WDC_REGMASK 7 90 #define _WDC_AUX 8 91 #define _WDC_RDONLY 16 92 #define _WDC_WRONLY 32 93 enum wdc_regs { 94 wdr_error = _WDC_RDONLY | 1, 95 wdr_precomp = _WDC_WRONLY | 1, 96 wdr_features = _WDC_WRONLY | 1, 97 wdr_seccnt = 2, 98 wdr_ireason = 2, 99 wdr_sector = 3, 100 wdr_lba_lo = 3, 101 wdr_cyl_lo = 4, 102 wdr_lba_mi = 4, 103 wdr_cyl_hi = 5, 104 wdr_lba_hi = 5, 105 wdr_sdh = 6, 106 wdr_status = _WDC_RDONLY | 7, 107 wdr_command = _WDC_WRONLY | 7, 108 wdr_altsts = _WDC_RDONLY | _WDC_AUX, 109 wdr_ctlr = _WDC_WRONLY | _WDC_AUX 110 }; 111 112 #define WDC_NREG 8 /* number of command registers */ 113 #define WDC_NSHADOWREG 2 /* number of command "shadow" registers */ 114 115 struct channel_softc_vtbl { 116 u_int8_t (*read_reg)(struct channel_softc *, enum wdc_regs reg); 117 void (*write_reg)(struct channel_softc *, enum wdc_regs reg, 118 u_int8_t var); 119 void (*lba48_write_reg)(struct channel_softc *, enum wdc_regs reg, 120 u_int16_t var); 121 122 void (*read_raw_multi_2)(struct channel_softc *, 123 void *data, unsigned int nbytes); 124 void (*write_raw_multi_2)(struct channel_softc *, 125 void *data, unsigned int nbytes); 126 127 void (*read_raw_multi_4)(struct channel_softc *, 128 void *data, unsigned int nbytes); 129 void (*write_raw_multi_4)(struct channel_softc *, 130 void *data, unsigned int nbytes); 131 }; 132 133 134 #define CHP_READ_REG(chp, a) ((chp)->_vtbl->read_reg)(chp, a) 135 #define CHP_WRITE_REG(chp, a, b) ((chp)->_vtbl->write_reg)(chp, a, b) 136 #define CHP_LBA48_WRITE_REG(chp, a, b) \ 137 ((chp)->_vtbl->lba48_write_reg)(chp, a, b) 138 139 #define CHP_READ_RAW_MULTI_2(chp, a, b) \ 140 ((chp)->_vtbl->read_raw_multi_2)(chp, a, b) 141 #define CHP_WRITE_RAW_MULTI_2(chp, a, b) \ 142 ((chp)->_vtbl->write_raw_multi_2)(chp, a, b) 143 #define CHP_READ_RAW_MULTI_4(chp, a, b) \ 144 ((chp)->_vtbl->read_raw_multi_4)(chp, a, b) 145 #define CHP_WRITE_RAW_MULTI_4(chp, a, b) \ 146 ((chp)->_vtbl->write_raw_multi_4)(chp, a, b) 147 148 struct wdc_softc { /* Per controller state */ 149 struct device sc_dev; 150 /* mandatory fields */ 151 int cap; 152 /* Capabilities supported by the controller */ 153 #define WDC_CAPABILITY_DATA16 0x0001 /* can do 16-bit data access */ 154 #define WDC_CAPABILITY_DATA32 0x0002 /* can do 32-bit data access */ 155 #define WDC_CAPABILITY_MODE 0x0004 /* controller knows its PIO/DMA modes */ 156 #define WDC_CAPABILITY_DMA 0x0008 /* DMA */ 157 #define WDC_CAPABILITY_UDMA 0x0010 /* Ultra-DMA/33 */ 158 #define WDC_CAPABILITY_HWLOCK 0x0020 /* Needs to lock HW */ 159 #define WDC_CAPABILITY_ATA_NOSTREAM 0x0040 /* Don't use stream funcs on ATA */ 160 #define WDC_CAPABILITY_ATAPI_NOSTREAM 0x0080 /* Don't use stream f on ATAPI */ 161 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */ 162 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */ 163 #define WDC_CAPABILITY_IRQACK 0x0400 /* callback to ack interrupt */ 164 #define WDC_CAPABILITY_SINGLE_DRIVE 0x800 /* Don't proble second drive */ 165 #define WDC_CAPABILITY_NO_ATAPI_DMA 0x1000 /* Don't do DMA with ATAPI */ 166 #define WDC_CAPABILITY_SATA 0x2000 /* SATA controller */ 167 u_int8_t PIO_cap; /* highest PIO mode supported */ 168 u_int8_t DMA_cap; /* highest DMA mode supported */ 169 u_int8_t UDMA_cap; /* highest UDMA mode supported */ 170 int nchannels; /* Number of channels on this controller */ 171 struct channel_softc **channels; /* channels-specific datas (array) */ 172 u_int16_t quirks; /* per-device oddities */ 173 #define WDC_QUIRK_NOSHORTDMA 0x0001 /* can't do short DMA transfers */ 174 175 #if 0 176 /* 177 * The reference count here is used for both IDE and ATAPI devices. 178 */ 179 struct scsipi_adapter sc_atapi_adapter; 180 #endif 181 182 /* if WDC_CAPABILITY_DMA set in 'cap' */ 183 void *dma_arg; 184 int (*dma_init)(void *, int, int, void *, size_t, 185 int); 186 void (*dma_start)(void *, int, int); 187 int (*dma_finish)(void *, int, int, int); 188 /* flags passed to DMA functions */ 189 #define WDC_DMA_READ 0x01 190 #define WDC_DMA_IRQW 0x02 191 #define WDC_DMA_LBA48 0x04 192 int dma_status; /* status return from dma_finish() */ 193 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */ 194 #define WDC_DMAST_ERR 0x02 /* DMA error */ 195 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */ 196 197 /* if WDC_CAPABILITY_HWLOCK set in 'cap' */ 198 int (*claim_hw)(void *, int); 199 void (*free_hw)(void *); 200 201 /* if WDC_CAPABILITY_MODE set in 'cap' */ 202 void (*set_modes)(struct channel_softc *); 203 204 /* if WDC_CAPABILITY_IRQACK set in 'cap' */ 205 void (*irqack)(struct channel_softc *); 206 207 void (*reset)(struct channel_softc *); 208 209 /* Driver callback to probe for drives */ 210 void (*drv_probe)(struct channel_softc *); 211 }; 212 213 /* 214 * Description of a command to be handled by a controller. 215 * These commands are queued in a list. 216 */ 217 struct atapi_return_args; 218 219 struct wdc_xfer { 220 volatile u_int c_flags; 221 #define C_ATAPI 0x0002 /* xfer is ATAPI request */ 222 #define C_TIMEOU 0x0004 /* xfer processing timed out */ 223 #define C_NEEDDONE 0x0010 /* need to call upper-level done */ 224 #define C_POLL 0x0020 /* cmd is polled */ 225 #define C_DMA 0x0040 /* cmd uses DMA */ 226 #define C_SENSE 0x0080 /* cmd is a internal command */ 227 #define C_MEDIA_ACCESS 0x0100 /* is a media access command */ 228 #define C_POLL_MACHINE 0x0200 /* machine has a poll hander */ 229 230 /* Informations about our location */ 231 struct channel_softc *chp; 232 u_int8_t drive; 233 234 /* Information about the current transfer */ 235 void *cmd; /* wdc, ata or scsipi command structure */ 236 void *databuf; 237 int c_bcount; /* byte count left */ 238 int c_skip; /* bytes already transferred */ 239 TAILQ_ENTRY(wdc_xfer) c_xferchain; 240 LIST_ENTRY(wdc_xfer) free_list; 241 void (*c_start)(struct channel_softc *, struct wdc_xfer *); 242 int (*c_intr)(struct channel_softc *, struct wdc_xfer *, int); 243 void (*c_kill_xfer)(struct channel_softc *, struct wdc_xfer *); 244 245 /* Used by ATAPISCSI */ 246 volatile int endticks; 247 struct timeout atapi_poll_to; 248 void (*next)(struct channel_softc *, struct wdc_xfer *, int, 249 struct atapi_return_args *); 250 void (*c_done)(struct channel_softc *, struct wdc_xfer *, int, 251 struct atapi_return_args *); 252 253 /* Used for tape devices */ 254 int transfer_len; 255 }; 256 257 /* 258 * Public functions which can be called by ATA or ATAPI specific parts, 259 * or bus-specific backends. 260 */ 261 262 int wdcprobe(struct channel_softc *); 263 void wdcattach(struct channel_softc *); 264 int wdcdetach(struct channel_softc *, int); 265 int wdcactivate(struct device *, int); 266 int wdcintr(void *); 267 void wdc_exec_xfer(struct channel_softc *, struct wdc_xfer *); 268 struct wdc_xfer *wdc_get_xfer(int); /* int = WDC_NOSLEEP/CANSLEEP */ 269 #define WDC_CANSLEEP 0x00 270 #define WDC_NOSLEEP 0x01 271 void wdc_free_xfer(struct channel_softc *, struct wdc_xfer *); 272 void wdcstart(struct channel_softc *); 273 int wdcreset(struct channel_softc *, int); 274 #define VERBOSE 1 275 #define SILENT 0 /* wdcreset will not print errors */ 276 int wdc_wait_for_status(struct channel_softc *, int, int, int); 277 int wdc_dmawait(struct channel_softc *, struct wdc_xfer *, int); 278 void wdcbit_bucket(struct channel_softc *, int); 279 280 void wdccommand(struct channel_softc *, u_int8_t, u_int8_t, u_int16_t, 281 u_int8_t, u_int8_t, u_int8_t, u_int8_t); 282 void wdccommandext(struct channel_softc *, u_int8_t, u_int8_t, u_int64_t, 283 u_int16_t); 284 void wdccommandshort(struct channel_softc *, int, int); 285 void wdctimeout(void *arg); 286 void wdc_do_reset(struct channel_softc *); 287 288 int wdc_addref(struct channel_softc *); 289 void wdc_delref(struct channel_softc *); 290 291 /* 292 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write 293 * command is aborted. 294 */ 295 #define wdcwait(chp, status, mask, timeout) ((wdc_wait_for_status((chp), (status), (mask), (timeout)) >= 0) ? 0 : -1) 296 #define wait_for_drq(chp, timeout) wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout)) 297 #define wait_for_unbusy(chp, timeout) wdcwait((chp), 0, 0, (timeout)) 298 #define wait_for_ready(chp, timeout) wdcwait((chp), WDCS_DRDY, \ 299 WDCS_DRDY, (timeout)) 300 301 /* ATA/ATAPI specs says a device can take 31s to reset */ 302 #define WDC_RESET_WAIT 31000 303 304 void wdc_disable_intr(struct channel_softc *); 305 void wdc_enable_intr(struct channel_softc *); 306 int wdc_select_drive(struct channel_softc *, int, int); 307 void wdc_set_drive(struct channel_softc *, int drive); 308 void wdc_output_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 309 void wdc_input_bytes(struct ata_drive_datas *drvp, void *, unsigned int); 310 311 void wdc_print_current_modes(struct channel_softc *); 312 313 int wdc_ioctl(struct ata_drive_datas *, u_long, caddr_t, int, struct proc *); 314 315 u_int8_t wdc_default_read_reg(struct channel_softc *, 316 enum wdc_regs); 317 void wdc_default_write_reg(struct channel_softc *, 318 enum wdc_regs, u_int8_t); 319 void wdc_default_lba48_write_reg(struct channel_softc *, 320 enum wdc_regs, u_int16_t); 321 void wdc_default_read_raw_multi_2(struct channel_softc *, 322 void *, unsigned int); 323 void wdc_default_write_raw_multi_2(struct channel_softc *, 324 void *, unsigned int); 325 void wdc_default_read_raw_multi_4(struct channel_softc *, 326 void *, unsigned int); 327 void wdc_default_write_raw_multi_4(struct channel_softc *, 328 void *, unsigned int); 329 330 #endif /* !_DEV_IC_WDCVAR_H_ */ 331