1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "../dmub_srv.h"
27 #include "dmub_reg.h"
28 #include "dmub_dcn32.h"
29 
30 #include "dcn/dcn_3_2_0_offset.h"
31 #include "dcn/dcn_3_2_0_sh_mask.h"
32 
33 #define DCN_BASE__INST0_SEG2                       0x000034C0
34 
35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
36 #define CTX dmub
37 #define REGS dmub->regs_dcn32
38 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
39 
40 const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
41 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
42 	{
43 		DMUB_DCN32_REGS()
44 		DMCUB_INTERNAL_REGS()
45 	},
46 #undef DMUB_SR
47 
48 #define DMUB_SF(reg, field) FD_MASK(reg, field),
49 		{ DMUB_DCN32_FIELDS() },
50 #undef DMUB_SF
51 
52 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
53 		{ DMUB_DCN32_FIELDS() },
54 #undef DMUB_SF
55 };
56 
dmub_dcn32_get_fb_base_offset(struct dmub_srv * dmub,uint64_t * fb_base,uint64_t * fb_offset)57 static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
58 		uint64_t *fb_base,
59 		uint64_t *fb_offset)
60 {
61 	uint32_t tmp;
62 
63 	if (dmub->fb_base || dmub->fb_offset) {
64 		*fb_base = dmub->fb_base;
65 		*fb_offset = dmub->fb_offset;
66 		return;
67 	}
68 
69 	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
70 	*fb_base = (uint64_t)tmp << 24;
71 
72 	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
73 	*fb_offset = (uint64_t)tmp << 24;
74 }
75 
dmub_dcn32_translate_addr(const union dmub_addr * addr_in,uint64_t fb_base,uint64_t fb_offset,union dmub_addr * addr_out)76 static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in,
77 		uint64_t fb_base,
78 		uint64_t fb_offset,
79 		union dmub_addr *addr_out)
80 {
81 	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
82 }
83 
dmub_dcn32_reset(struct dmub_srv * dmub)84 void dmub_dcn32_reset(struct dmub_srv *dmub)
85 {
86 	union dmub_gpint_data_register cmd;
87 	const uint32_t timeout = 30;
88 	uint32_t in_reset, scratch, i;
89 
90 	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
91 
92 	if (in_reset == 0) {
93 		cmd.bits.status = 1;
94 		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
95 		cmd.bits.param = 0;
96 
97 		dmub->hw_funcs.set_gpint(dmub, cmd);
98 
99 		/**
100 		 * Timeout covers both the ACK and the wait
101 		 * for remaining work to finish.
102 		 *
103 		 * This is mostly bound by the PHY disable sequence.
104 		 * Each register check will be greater than 1us, so
105 		 * don't bother using udelay.
106 		 */
107 
108 		for (i = 0; i < timeout; ++i) {
109 			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
110 				break;
111 		}
112 
113 		for (i = 0; i < timeout; ++i) {
114 			scratch = dmub->hw_funcs.get_gpint_response(dmub);
115 			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
116 				break;
117 		}
118 
119 		/* Force reset in case we timed out, DMCUB is likely hung. */
120 	}
121 
122 	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
123 	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
124 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
125 	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
126 	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
127 	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
128 	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
129 	REG_WRITE(DMCUB_OUTBOX0_RPTR, 0);
130 	REG_WRITE(DMCUB_OUTBOX0_WPTR, 0);
131 	REG_WRITE(DMCUB_SCRATCH0, 0);
132 
133 	/* Clear the GPINT command manually so we don't reset again. */
134 	cmd.all = 0;
135 	dmub->hw_funcs.set_gpint(dmub, cmd);
136 }
137 
dmub_dcn32_reset_release(struct dmub_srv * dmub)138 void dmub_dcn32_reset_release(struct dmub_srv *dmub)
139 {
140 	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
141 	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
142 	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
143 	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
144 }
145 
dmub_dcn32_backdoor_load(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)146 void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
147 		const struct dmub_window *cw0,
148 		const struct dmub_window *cw1)
149 {
150 	union dmub_addr offset;
151 	uint64_t fb_base, fb_offset;
152 
153 	dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset);
154 
155 	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
156 
157 	dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
158 
159 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
160 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
161 	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
162 	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
163 			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
164 			DMCUB_REGION3_CW0_ENABLE, 1);
165 
166 	dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
167 
168 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
169 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
170 	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
171 	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
172 			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
173 			DMCUB_REGION3_CW1_ENABLE, 1);
174 
175 	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
176 			0x20);
177 }
178 
dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)179 void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
180 		      const struct dmub_window *cw0,
181 		      const struct dmub_window *cw1)
182 {
183 	union dmub_addr offset;
184 
185 	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
186 
187 	offset = cw0->offset;
188 
189 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
190 	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
191 	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
192 	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
193 			DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
194 			DMCUB_REGION3_CW0_ENABLE, 1);
195 
196 	offset = cw1->offset;
197 
198 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
199 	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
200 	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
201 	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
202 			DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
203 			DMCUB_REGION3_CW1_ENABLE, 1);
204 
205 	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
206 			0x20);
207 }
208 
dmub_dcn32_setup_windows(struct dmub_srv * dmub,const struct dmub_window * cw2,const struct dmub_window * cw3,const struct dmub_window * cw4,const struct dmub_window * cw5,const struct dmub_window * cw6)209 void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
210 		const struct dmub_window *cw2,
211 		const struct dmub_window *cw3,
212 		const struct dmub_window *cw4,
213 		const struct dmub_window *cw5,
214 		const struct dmub_window *cw6)
215 {
216 	union dmub_addr offset;
217 
218 	offset = cw3->offset;
219 
220 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
221 	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
222 	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
223 	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
224 			DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
225 			DMCUB_REGION3_CW3_ENABLE, 1);
226 
227 	offset = cw4->offset;
228 
229 	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
230 	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
231 	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
232 	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
233 			DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
234 			DMCUB_REGION3_CW4_ENABLE, 1);
235 
236 	offset = cw5->offset;
237 
238 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
239 	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
240 	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
241 	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
242 			DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
243 			DMCUB_REGION3_CW5_ENABLE, 1);
244 
245 	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
246 	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
247 	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
248 			DMCUB_REGION5_TOP_ADDRESS,
249 			cw5->region.top - cw5->region.base - 1,
250 			DMCUB_REGION5_ENABLE, 1);
251 
252 	offset = cw6->offset;
253 
254 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
255 	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
256 	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
257 	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
258 			DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
259 			DMCUB_REGION3_CW6_ENABLE, 1);
260 }
261 
dmub_dcn32_setup_mailbox(struct dmub_srv * dmub,const struct dmub_region * inbox1)262 void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
263 		const struct dmub_region *inbox1)
264 {
265 	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
266 	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
267 }
268 
dmub_dcn32_get_inbox1_wptr(struct dmub_srv * dmub)269 uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)
270 {
271 	return REG_READ(DMCUB_INBOX1_WPTR);
272 }
273 
dmub_dcn32_get_inbox1_rptr(struct dmub_srv * dmub)274 uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)
275 {
276 	return REG_READ(DMCUB_INBOX1_RPTR);
277 }
278 
dmub_dcn32_set_inbox1_wptr(struct dmub_srv * dmub,uint32_t wptr_offset)279 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
280 {
281 	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
282 }
283 
dmub_dcn32_setup_out_mailbox(struct dmub_srv * dmub,const struct dmub_region * outbox1)284 void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
285 		const struct dmub_region *outbox1)
286 {
287 	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
288 	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
289 }
290 
dmub_dcn32_get_outbox1_wptr(struct dmub_srv * dmub)291 uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)
292 {
293 	/**
294 	 * outbox1 wptr register is accessed without locks (dal & dc)
295 	 * and to be called only by dmub_srv_stat_get_notification()
296 	 */
297 	return REG_READ(DMCUB_OUTBOX1_WPTR);
298 }
299 
dmub_dcn32_set_outbox1_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)300 void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
301 {
302 	/**
303 	 * outbox1 rptr register is accessed without locks (dal & dc)
304 	 * and to be called only by dmub_srv_stat_get_notification()
305 	 */
306 	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
307 }
308 
dmub_dcn32_is_hw_init(struct dmub_srv * dmub)309 bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
310 {
311 	union dmub_fw_boot_status status;
312 	uint32_t is_hw_init;
313 
314 	status.all = REG_READ(DMCUB_SCRATCH0);
315 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
316 
317 	return is_hw_init != 0 && status.bits.dal_fw;
318 }
319 
dmub_dcn32_is_supported(struct dmub_srv * dmub)320 bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
321 {
322 	uint32_t supported = 0;
323 
324 	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
325 
326 	return supported;
327 }
328 
dmub_dcn32_set_gpint(struct dmub_srv * dmub,union dmub_gpint_data_register reg)329 void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
330 		union dmub_gpint_data_register reg)
331 {
332 	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
333 }
334 
dmub_dcn32_is_gpint_acked(struct dmub_srv * dmub,union dmub_gpint_data_register reg)335 bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
336 		union dmub_gpint_data_register reg)
337 {
338 	union dmub_gpint_data_register test;
339 
340 	reg.bits.status = 0;
341 	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
342 
343 	return test.all == reg.all;
344 }
345 
dmub_dcn32_get_gpint_response(struct dmub_srv * dmub)346 uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)
347 {
348 	return REG_READ(DMCUB_SCRATCH7);
349 }
350 
dmub_dcn32_get_gpint_dataout(struct dmub_srv * dmub)351 uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)
352 {
353 	uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
354 
355 	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
356 
357 	REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
358 	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
359 	REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
360 
361 	REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
362 
363 	return dataout;
364 }
365 
dmub_dcn32_get_fw_boot_status(struct dmub_srv * dmub)366 union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)
367 {
368 	union dmub_fw_boot_status status;
369 
370 	status.all = REG_READ(DMCUB_SCRATCH0);
371 	return status;
372 }
373 
dmub_dcn32_enable_dmub_boot_options(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)374 void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
375 {
376 	union dmub_fw_boot_options boot_options = {0};
377 
378 	boot_options.bits.z10_disable = params->disable_z10;
379 
380 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
381 }
382 
dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv * dmub,bool skip)383 void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
384 {
385 	union dmub_fw_boot_options boot_options;
386 	boot_options.all = REG_READ(DMCUB_SCRATCH14);
387 	boot_options.bits.skip_phy_init_panel_sequence = skip;
388 	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
389 }
390 
dmub_dcn32_setup_outbox0(struct dmub_srv * dmub,const struct dmub_region * outbox0)391 void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
392 		const struct dmub_region *outbox0)
393 {
394 	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
395 
396 	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
397 }
398 
dmub_dcn32_get_outbox0_wptr(struct dmub_srv * dmub)399 uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)
400 {
401 	return REG_READ(DMCUB_OUTBOX0_WPTR);
402 }
403 
dmub_dcn32_set_outbox0_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)404 void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
405 {
406 	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
407 }
408 
dmub_dcn32_get_current_time(struct dmub_srv * dmub)409 uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)
410 {
411 	return REG_READ(DMCUB_TIMER_CURRENT);
412 }
413 
dmub_dcn32_get_diagnostic_data(struct dmub_srv * dmub,struct dmub_diagnostic_data * diag_data)414 void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
415 {
416 	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
417 	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
418 
419 	if (!dmub || !diag_data)
420 		return;
421 
422 	memset(diag_data, 0, sizeof(*diag_data));
423 
424 	diag_data->dmcub_version = dmub->fw_version;
425 
426 	diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
427 	diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
428 	diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
429 	diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
430 	diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
431 	diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
432 	diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
433 	diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
434 	diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
435 	diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
436 	diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
437 	diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
438 	diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
439 	diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
440 	diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
441 	diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
442 	diag_data->scratch[16] = REG_READ(DMCUB_SCRATCH16);
443 
444 	diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
445 	diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
446 	diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
447 
448 	diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
449 	diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
450 	diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
451 
452 	diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
453 	diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
454 	diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
455 
456 	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
457 	diag_data->is_dmcub_enabled = is_dmub_enabled;
458 
459 	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
460 	diag_data->is_dmcub_soft_reset = is_soft_reset;
461 
462 	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
463 	diag_data->is_dmcub_secure_reset = is_sec_reset;
464 
465 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
466 	diag_data->is_traceport_en  = is_traceport_enabled;
467 
468 	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
469 	diag_data->is_cw0_enabled = is_cw0_enabled;
470 
471 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
472 	diag_data->is_cw6_enabled = is_cw6_enabled;
473 
474 	diag_data->gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0);
475 }
dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv * dmub)476 void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)
477 {
478 	/* DMCUB_REGION3_TMR_AXI_SPACE values:
479 	 * 0b011 (0x3) - FB physical address
480 	 * 0b100 (0x4) - GPU virtual address
481 	 *
482 	 * Default value is 0x3 (FB Physical address for TMR). When programming
483 	 * DMUB to be in system memory, change to 0x4. The system memory allocated
484 	 * is accessible by both GPU and CPU, so we use GPU virtual address.
485 	 */
486 	REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
487 }
488 
dmub_dcn32_send_inbox0_cmd(struct dmub_srv * dmub,union dmub_inbox0_data_register data)489 void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
490 {
491 	REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
492 }
493 
dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv * dmub)494 void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)
495 {
496 	REG_WRITE(DMCUB_SCRATCH17, 0);
497 }
498 
dmub_dcn32_read_inbox0_ack_register(struct dmub_srv * dmub)499 uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)
500 {
501 	return REG_READ(DMCUB_SCRATCH17);
502 }
503