1 /* $OpenBSD: if_vrreg.h,v 1.37 2015/10/20 17:08:39 chrisz Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_vrreg.h,v 1.17 2003/02/01 01:27:05 silby Exp $ 35 */ 36 37 /* 38 * Rhine register definitions. 39 */ 40 41 #define VR_PAR0 0x00 /* node address 0 to 4 */ 42 #define VR_PAR1 0x04 /* node address 2 to 6 */ 43 #define VR_RXCFG 0x06 /* receiver config register */ 44 #define VR_TXCFG 0x07 /* transmit config register */ 45 #define VR_COMMAND 0x08 /* command register */ 46 #define VR_TQWK 0x0A /* transmit queue wake */ 47 #define VR_ISR 0x0C /* interrupt/status register */ 48 #define VR_IMR 0x0E /* interrupt mask register */ 49 #define VR_MAR0 0x10 /* multicast hash 0 */ 50 #define VR_MAR1 0x14 /* multicast hash 1 */ 51 #define VR_RXADDR 0x18 /* rx descriptor list start addr */ 52 #define VR_TXADDR 0x1C /* tx descriptor list start addr */ 53 #define VR_CURRXDESC0 0x20 54 #define VR_CURRXDESC1 0x24 55 #define VR_CURRXDESC2 0x28 56 #define VR_CURRXDESC3 0x2C 57 #define VR_NEXTRXDESC0 0x30 58 #define VR_NEXTRXDESC1 0x34 59 #define VR_NEXTRXDESC2 0x38 60 #define VR_NEXTRXDESC3 0x3C 61 #define VR_CURTXDESC0 0x40 62 #define VR_CURTXDESC1 0x44 63 #define VR_CURTXDESC2 0x48 64 #define VR_CURTXDESC3 0x4C 65 #define VR_NEXTTXDESC0 0x50 66 #define VR_NEXTTXDESC1 0x54 67 #define VR_NEXTTXDESC2 0x58 68 #define VR_NEXTTXDESC3 0x5C 69 #define VR_CURRXDMA 0x60 /* current RX DMA address */ 70 #define VR_CURTXDMA 0x64 /* current TX DMA address */ 71 #define VR_TALLYCNT 0x68 /* tally counter test register */ 72 #define VR_PHYADDR 0x6C 73 #define VR_MIISTAT 0x6D 74 #define VR_BCR0 0x6E 75 #define VR_BCR1 0x6F 76 #define VR_MIICMD 0x70 77 #define VR_MIIADDR 0x71 78 #define VR_MIIDATA 0x72 79 #define VR_EECSR 0x74 80 #define VR_TEST 0x75 81 #define VR_GPIO 0x76 82 #define VR_CONFIG 0x78 83 #define VR_MPA_CNT 0x7C 84 #define VR_CRC_CNT 0x7E 85 #define VR_STICKHW 0x83 86 #define VR_CAMMASK 0x88 /* length 4 bytes */ 87 #define VR_CAMCTRL 0x92 88 #define VR_CAMADDR 0x93 89 90 /* Misc Registers */ 91 #define VR_MISC_CR1 0x81 92 #define VR_MISCCR1_FORSRST 0x40 93 94 /* 95 * RX config bits. 96 */ 97 #define VR_RXCFG_RX_ERRPKTS 0x01 98 #define VR_RXCFG_RX_RUNT 0x02 99 #define VR_RXCFG_RX_MULTI 0x04 100 #define VR_RXCFG_RX_BROAD 0x08 101 #define VR_RXCFG_RX_PROMISC 0x10 102 #define VR_RXCFG_RX_THRESH 0xE0 103 104 #define VR_RXTHRESH_32BYTES 0x00 105 #define VR_RXTHRESH_64BYTES 0x20 106 #define VR_RXTHRESH_128BYTES 0x40 107 #define VR_RXTHRESH_256BYTES 0x60 108 #define VR_RXTHRESH_512BYTES 0x80 109 #define VR_RXTHRESH_768BYTES 0xA0 110 #define VR_RXTHRESH_1024BYTES 0xC0 111 #define VR_RXTHRESH_STORENFWD 0xE0 112 113 /* 114 * TX config bits. 115 */ 116 #define VR_TXCFG_TXTAGEN 0x01 /* 6105M */ 117 #define VR_TXCFG_LOOPBKMODE 0x06 118 #define VR_TXCFG_BACKOFF 0x08 119 #define VR_TXCFG_TX_THRESH 0xE0 120 121 #define VR_TXTHRESH_32BYTES 0x00 122 #define VR_TXTHRESH_64BYTES 0x20 123 #define VR_TXTHRESH_128BYTES 0x40 124 #define VR_TXTHRESH_256BYTES 0x60 125 #define VR_TXTHRESH_512BYTES 0x80 126 #define VR_TXTHRESH_768BYTES 0xA0 127 #define VR_TXTHRESH_1024BYTES 0xC0 128 #define VR_TXTHRESH_STORENFWD 0xE0 129 130 /* 131 * Command register bits. 132 */ 133 #define VR_CMD_INIT 0x0001 134 #define VR_CMD_START 0x0002 135 #define VR_CMD_STOP 0x0004 136 #define VR_CMD_RX_ON 0x0008 137 #define VR_CMD_TX_ON 0x0010 138 #define VR_CMD_TX_GO 0x0020 139 #define VR_CMD_RX_GO 0x0040 140 #define VR_CMD_RSVD 0x0080 141 #define VR_CMD_RX_EARLY 0x0100 142 #define VR_CMD_TX_EARLY 0x0200 143 #define VR_CMD_FULLDUPLEX 0x0400 144 #define VR_CMD_TX_NOPOLL 0x0800 145 146 #define VR_CMD_RESET 0x8000 147 148 /* 149 * Interrupt status bits. 150 */ 151 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 152 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 153 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 154 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 155 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 156 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 157 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 158 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 159 #define VR_ISR_RX_EARLY 0x0100 /* rx early */ 160 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 161 #define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */ 162 #define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (3065) */ 163 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 164 #define VR_ISR_RX_DROPPED 0x0800 165 #define VR_ISR_RX_NOBUF2 0x1000 166 #define VR_ISR_TX_ABRT2 0x2000 167 #define VR_ISR_LINKSTAT2 0x4000 168 #define VR_ISR_MAGICPACKET 0x8000 169 170 /* 171 * Interrupt mask bits. 172 */ 173 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 174 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 175 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 176 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 177 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 178 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 179 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 180 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 181 #define VR_IMR_RX_EARLY 0x0100 /* rx early */ 182 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 183 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 184 #define VR_IMR_RX_DROPPED 0x0800 185 #define VR_IMR_RX_NOBUF2 0x1000 186 #define VR_IMR_TX_ABRT2 0x2000 187 #define VR_IMR_LINKSTAT2 0x4000 188 #define VR_IMR_MAGICPACKET 0x8000 189 190 #define VR_INTRS \ 191 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 192 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 193 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 194 195 /* 196 * MII status register. 197 */ 198 199 #define VR_MIISTAT_SPEED 0x01 200 #define VR_MIISTAT_LINKFAULT 0x02 201 #define VR_MIISTAT_MGTREADERR 0x04 202 #define VR_MIISTAT_MIIERR 0x08 203 #define VR_MIISTAT_PHYOPT 0x10 204 #define VR_MIISTAT_MDC_SPEED 0x20 205 #define VR_MIISTAT_RSVD 0x40 206 #define VR_MIISTAT_GPIO1POLL 0x80 207 208 /* 209 * MII command register bits. 210 */ 211 #define VR_MIICMD_CLK 0x01 212 #define VR_MIICMD_DATAOUT 0x02 213 #define VR_MIICMD_DATAIN 0x04 214 #define VR_MIICMD_DIR 0x08 215 #define VR_MIICMD_DIRECTPGM 0x10 216 #define VR_MIICMD_WRITE_ENB 0x20 217 #define VR_MIICMD_READ_ENB 0x40 218 #define VR_MIICMD_AUTOPOLL 0x80 219 220 /* 221 * EEPROM control bits. 222 */ 223 #define VR_EECSR_DATAIN 0x01 /* data out */ 224 #define VR_EECSR_DATAOUT 0x02 /* data in */ 225 #define VR_EECSR_CLK 0x04 /* clock */ 226 #define VR_EECSR_CS 0x08 /* chip select */ 227 #define VR_EECSR_DPM 0x10 228 #define VR_EECSR_LOAD 0x20 229 #define VR_EECSR_EMBP 0x40 230 #define VR_EECSR_EEPR 0x80 231 232 #define VR_EECMD_WRITE 0x140 233 #define VR_EECMD_READ 0x180 234 #define VR_EECMD_ERASE 0x1c0 235 236 /* 237 * Test register bits. 238 */ 239 #define VR_TEST_TEST0 0x01 240 #define VR_TEST_TEST1 0x02 241 #define VR_TEST_TEST2 0x04 242 #define VR_TEST_TSTUD 0x08 243 #define VR_TEST_TSTOV 0x10 244 #define VR_TEST_BKOFF 0x20 245 #define VR_TEST_FCOL 0x40 246 #define VR_TEST_HBDES 0x80 247 248 /* 249 * Config register bits. 250 */ 251 #define VR_CFG_PREACPIWAKE 0x00000001 /* pre-acpi wake */ 252 #define VR_CFG_ABNORMALWAKE 0x00000002 /* abnormal shut down wake */ 253 #define VR_CFG_RSVD0 0x00000004 254 #define VR_CFG_LED0 0x00000008 255 #define VR_CFG_LED1 0x00000010 256 #define VR_CFG_TAGCRC 0x00000020 /* 6105M tag in CRC */ 257 #define VR_CFG_MIIOPT 0x00000040 /* MII extension clock */ 258 #define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ 259 #define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ 260 #define VR_CFG_MRREADWAIT 0x00000200 261 #define VR_CFG_MRWRITEWAIT 0x00000400 262 #define VR_CFG_RX_ARB 0x00000800 263 #define VR_CFG_TX_ARB 0x00001000 264 #define VR_CFG_READMULTI 0x00002000 265 #define VR_CFG_TX_PACE 0x00004000 266 #define VR_CFG_TX_QDIS 0x00008000 267 #define VR_CFG_ROMSEL0 0x00010000 268 #define VR_CFG_ROMSEL1 0x00020000 269 #define VR_CFG_ROMSEL2 0x00040000 270 #define VR_CFG_ROMTIMESEL 0x00080000 271 #define VR_CFG_RSVD1 0x00100000 272 #define VR_CFG_ROMDLY 0x00200000 273 #define VR_CFG_ROMOPT 0x00400000 274 #define VR_CFG_RSVD2 0x00800000 275 #define VR_CFG_BACKOFFOPT 0x01000000 276 #define VR_CFG_BACKOFFMOD 0x02000000 277 #define VR_CFG_CAPEFFECT 0x04000000 278 #define VR_CFG_BACKOFFRAND 0x08000000 279 #define VR_CFG_MAGICKPACKET 0x10000000 280 #define VR_CFG_PCIREADLINE 0x20000000 281 #define VR_CFG_DIAG 0x40000000 282 #define VR_CFG_GPIOEN 0x80000000 283 284 /* Sticky HW bits */ 285 #define VR_STICKHW_DS0 0x01 286 #define VR_STICKHW_DS1 0x02 287 #define VR_STICKHW_WOL_ENB 0x04 288 #define VR_STICKHW_WOL_STS 0x08 289 #define VR_STICKHW_LEGWOL_ENB 0x80 290 291 /* Wake on Lan */ 292 #define VR_WOLCRSET 0xA0 293 #define VR_PWRCFGSET 0xA1 294 #define VR_WOLCFGSET 0xA3 295 #define VR_WOLCRCLR 0xA4 296 #define VR_PWRCFGCLR 0xA5 297 #define VR_WOLCFGCLR 0xA7 298 #define VR_PWRCSRSET 0xA8 299 #define VR_PWRCSRCLR 0xAC 300 #define VR_WOLCR_UCAST 0x10 301 #define VR_WOLCR_MAGIC 0x20 302 #define VR_WOLCR_LINKON 0x40 303 #define VR_WOLCR_LINKOFF 0x80 304 #define VR_WOLCFG_PMEOVR 0x80 305 306 /* 307 * BCR0 register bits. (At least for the VT6102 chip.) 308 */ 309 #define VR_BCR0_DMA_LENGTH 0x07 310 311 #define VR_BCR0_DMA_32BYTES 0x00 312 #define VR_BCR0_DMA_64BYTES 0x01 313 #define VR_BCR0_DMA_128BYTES 0x02 314 #define VR_BCR0_DMA_256BYTES 0x03 315 #define VR_BCR0_DMA_512BYTES 0x04 316 #define VR_BCR0_DMA_1024BYTES 0x05 317 #define VR_BCR0_DMA_STORENFWD 0x07 318 319 #define VR_BCR0_RX_THRESH 0x38 320 321 #define VR_BCR0_RXTHRESHCFG 0x00 322 #define VR_BCR0_RXTHRESH64BYTES 0x08 323 #define VR_BCR0_RXTHRESH128BYTES 0x10 324 #define VR_BCR0_RXTHRESH256BYTES 0x18 325 #define VR_BCR0_RXTHRESH512BYTES 0x20 326 #define VR_BCR0_RXTHRESH1024BYTES 0x28 327 #define VR_BCR0_RXTHRESHSTORENFWD 0x38 328 #define VR_BCR0_EXTLED 0x40 329 #define VR_BCR0_MED2 0x80 330 331 /* 332 * BCR1 register bits. (At least for the VT6102 chip.) 333 */ 334 #define VR_BCR1_POT0 0x01 335 #define VR_BCR1_POT1 0x02 336 #define VR_BCR1_POT2 0x04 337 #define VR_BCR1_TX_THRESH 0x38 338 #define VR_BCR1_TXTHRESHCFG 0x00 339 #define VR_BCR1_TXTHRESH64BYTES 0x08 340 #define VR_BCR1_TXTHRESH128BYTES 0x10 341 #define VR_BCR1_TXTHRESH256BYTES 0x18 342 #define VR_BCR1_TXTHRESH512BYTES 0x20 343 #define VR_BCR1_TXTHRESH1024BYTES 0x28 344 #define VR_BCR1_TXTHRESHSTORENFWD 0x38 345 #define VR_BCR1_VLANFILT_ENB 0x80 /* 6105M */ 346 347 /* 348 * CAM Control registers (VT6105M) 349 */ 350 #define VR_CAMCTRL_WREN 0x01 351 #define VR_CAMCTRL_VCAMSEL 0x02 352 #define VR_CAMCTRL_WRITE 0x04 353 #define VR_CAMCTRL_READ 0x08 354 355 /* 356 * Rhine TX/RX list structure. 357 */ 358 359 struct vr_desc { 360 u_int32_t vr_status; 361 u_int32_t vr_ctl; 362 u_int32_t vr_data; 363 u_int32_t vr_next; 364 }; 365 366 #define VR_RXSTAT_RXERR 0x00000001 367 #define VR_RXSTAT_CRCERR 0x00000002 368 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004 369 #define VR_RXSTAT_FIFOOFLOW 0x00000008 370 #define VR_RXSTAT_GIANT 0x00000010 371 #define VR_RXSTAT_RUNT 0x00000020 372 #define VR_RXSTAT_BUSERR 0x00000040 373 #define VR_RXSTAT_FRAG 0x00000040 /* 6105M */ 374 #define VR_RXSTAT_BUFFERR 0x00000080 375 #define VR_RXSTAT_LASTFRAG 0x00000100 376 #define VR_RXSTAT_FIRSTFRAG 0x00000200 377 #define VR_RXSTAT_RLINK 0x00000400 378 #define VR_RXSTAT_RX_PHYS 0x00000800 379 #define VR_RXSTAT_RX_BROAD 0x00001000 380 #define VR_RXSTAT_RX_MULTI 0x00002000 381 #define VR_RXSTAT_RX_VIDHIT 0x00004000 /* 6105M */ 382 #define VR_RXSTAT_RX_OK 0x00008000 383 #define VR_RXSTAT_RXLEN 0x07FF0000 384 #define VR_RXSTAT_RXLEN_EXT 0x78000000 385 #define VR_RXSTAT_OWN 0x80000000 386 387 #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 388 #define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN) 389 390 #define VR_RXCTL_BUFLEN 0x000007FF 391 #define VR_RXCTL_BUFLEN_EXT 0x00007800 392 #define VR_RXCTL_CHAIN 0x00008000 393 #define VR_RXCTL_TAG 0x00010000 394 #define VR_RXCTL_UDP 0x00020000 395 #define VR_RXCTL_TCP 0x00040000 396 #define VR_RXCTL_IP 0x00080000 397 #define VR_RXCTL_TCPUDPOK 0x00100000 398 #define VR_RXCTL_IPOK 0x00200000 399 #define VR_RXCTL_SNAPTAG 0x00400000 400 #define VR_RXCTL_RXLERR 0x00800000 /* 6105M */ 401 #define VR_RXCTL_RX_INTR 0x00800000 402 403 #define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 404 405 #define VR_TXSTAT_DEFER 0x00000001 406 #define VR_TXSTAT_UNDERRUN 0x00000002 407 #define VR_TXSTAT_COLLCNT 0x00000078 408 #define VR_TXSTAT_SQE 0x00000080 409 #define VR_TXSTAT_ABRT 0x00000100 410 #define VR_TXSTAT_LATECOLL 0x00000200 411 #define VR_TXSTAT_CARRLOST 0x00000400 412 #define VR_TXSTAT_UDF 0x00000800 413 #define VR_TXSTAT_BUSERR 0x00002000 414 #define VR_TXSTAT_JABTIMEO 0x00004000 415 #define VR_TXSTAT_ERRSUM 0x00008000 416 /* 417 * Note there are only 15 bits total. 418 * The drop eligible indicator is left out. 419 * VLAN ID at the lower 12 bits 0x0FFF; 420 * priority code point at the upper 3 bits 0x7000. 421 */ 422 #define VR_TXSTAT_PQMASK 0x7FFF0000 423 #define VR_TXSTAT_OWN 0x80000000 424 #define VR_TXSTAT_PQSHIFT 16 425 426 #define VR_TXCTL_BUFLEN 0x000007FF 427 #define VR_TXCTL_BUFLEN_EXT 0x00007800 428 #define VR_TXCTL_TLINK 0x00008000 429 #define VR_TXCTL_NOCRC 0x00010000 430 #define VR_TXCTL_INSERTTAG 0x00020000 431 #define VR_TXCTL_IPCSUM 0x00040000 432 #define VR_TXCTL_UDPCSUM 0x00080000 433 #define VR_TXCTL_TCPCSUM 0x00100000 434 #define VR_TXCTL_FIRSTFRAG 0x00200000 435 #define VR_TXCTL_LASTFRAG 0x00400000 436 #define VR_TXCTL_FINT 0x00800000 437 438 /* TDES3 aka vr_next */ 439 #define VR_TXNEXT_INTDISABLE 0x00000001 440 441 #define VR_MAXFRAGS 8 442 #define VR_RX_LIST_CNT 128 443 #define VR_TX_LIST_CNT 128 444 #define VR_MIN_FRAMELEN 60 445 #define VR_RXLEN 1524 446 /* determined experimentally; seems intermittent with higher values */ 447 #define VR_RXLEN_BABYJUMBO 1758 448 #define VR_TX_INTR_THRESH 8 449 450 struct vr_list_data { 451 struct vr_desc vr_rx_list[VR_RX_LIST_CNT]; 452 struct vr_desc vr_tx_list[VR_TX_LIST_CNT]; 453 }; 454 455 struct vr_chain { 456 struct vr_desc *vr_ptr; 457 struct mbuf *vr_mbuf; 458 struct vr_chain *vr_nextdesc; 459 bus_addr_t vr_paddr; 460 bus_dmamap_t vr_map; 461 }; 462 463 struct vr_chain_onefrag { 464 struct vr_desc *vr_ptr; 465 struct vr_chain_onefrag *vr_nextdesc; 466 struct mbuf *vr_mbuf; 467 bus_addr_t vr_paddr; 468 bus_dmamap_t vr_map; 469 }; 470 471 struct vr_chain_data { 472 struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT]; 473 struct vr_chain vr_tx_chain[VR_TX_LIST_CNT]; 474 475 struct vr_chain_onefrag *vr_rx_cons; 476 struct vr_chain_onefrag *vr_rx_prod; 477 478 struct vr_chain *vr_tx_cons; 479 struct vr_chain *vr_tx_prod; 480 int vr_tx_cnt; 481 unsigned int vr_tx_pkts; 482 }; 483 484 struct vr_mii_frame { 485 u_int8_t mii_stdelim; 486 u_int8_t mii_opcode; 487 u_int8_t mii_phyaddr; 488 u_int8_t mii_regaddr; 489 u_int8_t mii_turnaround; 490 u_int16_t mii_data; 491 }; 492 493 /* 494 * MII constants 495 */ 496 #define VR_MII_STARTDELIM 0x01 497 #define VR_MII_READOP 0x02 498 #define VR_MII_WRITEOP 0x01 499 #define VR_MII_TURNAROUND 0x02 500 501 #define VR_FLAG_FORCEDELAY 1 502 #define VR_FLAG_SCHEDDELAY 2 503 #define VR_FLAG_DELAYTIMEO 3 504 505 struct vr_dmamem { 506 bus_dmamap_t vrm_map; 507 bus_dma_segment_t vrm_seg; 508 int vrm_nsegs; 509 size_t vrm_size; 510 caddr_t vrm_kva; 511 }; 512 513 struct vr_softc { 514 struct device sc_dev; /* generic device structure */ 515 pci_chipset_tag_t sc_pc; /* PCI registers info */ 516 pcitag_t sc_tag; 517 void * sc_ih; /* interrupt handler cookie */ 518 struct arpcom arpcom; /* interface info */ 519 bus_space_handle_t vr_bhandle; /* bus space handle */ 520 bus_space_tag_t vr_btag; /* bus space tag */ 521 bus_dma_tag_t sc_dmat; 522 struct vr_type *vr_info; /* Rhine adapter info */ 523 u_int8_t vr_revid; /* Rhine chip revision */ 524 u_int8_t vr_flags; /* See VR_F_* below */ 525 struct vr_list_data *vr_ldata; 526 struct vr_chain_data vr_cdata; 527 struct mii_data sc_mii; 528 struct timeout sc_to; 529 struct timeout sc_rxto; 530 struct vr_dmamem sc_listmap; /* descriptor list map */ 531 struct vr_dmamem sc_zeromap; /* zero pad map */ 532 struct if_rxring sc_rxring; 533 int sc_rxbufs; 534 int vr_link; 535 int vr_quirks; 536 }; 537 538 #define VR_F_RESTART 0x01 /* Restart unit on next tick */ 539 540 /* 541 * register space access macros 542 */ 543 #define CSR_WRITE_4(sc, reg, val) \ 544 bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val) 545 #define CSR_WRITE_2(sc, reg, val) \ 546 bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val) 547 #define CSR_WRITE_1(sc, reg, val) \ 548 bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val) 549 550 #define CSR_READ_4(sc, reg) \ 551 bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg) 552 #define CSR_READ_2(sc, reg) \ 553 bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg) 554 #define CSR_READ_1(sc, reg) \ 555 bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg) 556 557 #define VR_TIMEOUT 1000 558 559 /* 560 * VIA Rhine revision IDs 561 */ 562 563 #define REV_ID_VT3043_E 0x04 564 #define REV_ID_VT3071_A 0x20 565 #define REV_ID_VT3071_B 0x21 566 #define REV_ID_VT3065_A 0x40 567 #define REV_ID_VT3065_B 0x41 568 #define REV_ID_VT3065_C 0x42 569 #define REV_ID_VT6102_APOLLO 0x74 570 #define REV_ID_VT6103 0x78 571 #define REV_ID_VT3106 0x80 572 #define REV_ID_VT3106_J 0x80 /* 0x80-0x8F */ 573 #define REV_ID_VT3106_S 0x90 /* 0x90-0xA0 */ 574 #define REV_ID_VT6105M_A0 0x90 575 #define REV_ID_VT6105M_B1 0x94 576 577 /* 578 * PCI low memory base and low I/O base register, and 579 * other PCI registers. 580 */ 581 582 #define VR_PCI_VENDOR_ID 0x00 583 #define VR_PCI_DEVICE_ID 0x02 584 #define VR_PCI_COMMAND 0x04 585 #define VR_PCI_STATUS 0x06 586 #define VR_PCI_REVID 0x08 587 #define VR_PCI_CLASSCODE 0x09 588 #define VR_PCI_LATENCY_TIMER 0x0D 589 #define VR_PCI_HEADER_TYPE 0x0E 590 #define VR_PCI_LOIO 0x10 591 #define VR_PCI_LOMEM 0x14 592 #define VR_PCI_BIOSROM 0x30 593 #define VR_PCI_INTLINE 0x3C 594 #define VR_PCI_INTPIN 0x3D 595 #define VR_PCI_MINGNT 0x3E 596 #define VR_PCI_MINLAT 0x0F 597 #define VR_PCI_RESETOPT 0x48 598 #define VR_PCI_EEPROM_DATA 0x4C 599 #define VR_PCI_MODE 0x50 600 601 #define VR_MODE3_MIION 0x04 602 603 /* power management registers */ 604 #define VR_PCI_CAPID 0xDC /* 8 bits */ 605 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 606 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 607 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 608 609 #define VR_PME_EN 0x0010 610 #define VR_PME_STATUS 0x8000 611