1 /* $OpenBSD: dwc2_hcdqueue.c,v 1.12 2021/09/04 10:19:28 mglocker Exp $ */ 2 /* $NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $ */ 3 4 /* 5 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * This file contains the functions to manage Queue Heads and Queue 42 * Transfer Descriptors for Host mode 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/pool.h> 49 50 #include <machine/bus.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <dev/usb/dwc2/dwc2.h> 58 #include <dev/usb/dwc2/dwc2var.h> 59 60 #include <dev/usb/dwc2/dwc2_core.h> 61 #include <dev/usb/dwc2/dwc2_hcd.h> 62 63 STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *, int, int, int, int); 64 STATIC void dwc2_wait_timer_fn(void *); 65 66 /* If we get a NAK, wait this long before retrying */ 67 #define DWC2_RETRY_WAIT_DELAY 1 /* msec */ 68 69 /** 70 * dwc2_qh_init() - Initializes a QH structure 71 * 72 * @hsotg: The HCD state structure for the DWC OTG controller 73 * @qh: The QH to init 74 * @urb: Holds the information about the device/endpoint needed to initialize 75 * the QH 76 */ 77 #define SCHEDULE_SLOP 10 78 STATIC void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 79 struct dwc2_hcd_urb *urb) 80 { 81 int dev_speed, hub_addr, hub_port; 82 83 dev_vdbg(hsotg->dev, "%s()\n", __func__); 84 85 /* Initialize QH */ 86 qh->hsotg = hsotg; 87 /* XXX timer_setup(&qh->wait_timer, dwc2_wait_timer_fn, 0); */ 88 timeout_set(&qh->wait_timer, dwc2_wait_timer_fn, qh); 89 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 90 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 91 92 qh->data_toggle = DWC2_HC_PID_DATA0; 93 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 94 INIT_LIST_HEAD(&qh->qtd_list); 95 INIT_LIST_HEAD(&qh->qh_list_entry); 96 97 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 98 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 99 100 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 101 qh->nak_frame = 0xffff; 102 103 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 104 hub_addr != 0 && hub_addr != 1) { 105 dev_vdbg(hsotg->dev, 106 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 107 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, 108 hub_port); 109 qh->do_split = 1; 110 } 111 112 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 113 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 114 /* Compute scheduling parameters once and save them */ 115 u32 hprt, prtspd; 116 117 /* Todo: Account for split transfers in the bus time */ 118 int bytecount = 119 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 120 121 qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ? 122 USB_SPEED_HIGH : dev_speed, qh->ep_is_in, 123 qh->ep_type == USB_ENDPOINT_XFER_ISOC, 124 bytecount); 125 126 /* Ensure frame_number corresponds to the reality */ 127 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg); 128 /* Start in a slightly future (micro)frame */ 129 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 130 SCHEDULE_SLOP); 131 qh->interval = urb->interval; 132 #if 0 133 /* Increase interrupt polling rate for debugging */ 134 if (qh->ep_type == USB_ENDPOINT_XFER_INT) 135 qh->interval = 8; 136 #endif 137 hprt = DWC2_READ_4(hsotg, HPRT0); 138 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 139 if (prtspd == HPRT0_SPD_HIGH_SPEED && 140 (dev_speed == USB_SPEED_LOW || 141 dev_speed == USB_SPEED_FULL)) { 142 qh->interval *= 8; 143 qh->sched_frame |= 0x7; 144 qh->start_split_frame = qh->sched_frame; 145 } 146 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); 147 } 148 149 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 150 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 151 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", 152 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 153 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", 154 dwc2_hcd_get_ep_num(&urb->pipe_info), 155 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 156 157 qh->dev_speed = dev_speed; 158 159 #ifdef DWC2_DEBUG 160 const char *speed, *type; 161 switch (dev_speed) { 162 case USB_SPEED_LOW: 163 speed = "low"; 164 break; 165 case USB_SPEED_FULL: 166 speed = "full"; 167 break; 168 case USB_SPEED_HIGH: 169 speed = "high"; 170 break; 171 default: 172 speed = "?"; 173 break; 174 } 175 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); 176 177 switch (qh->ep_type) { 178 case USB_ENDPOINT_XFER_ISOC: 179 type = "isochronous"; 180 break; 181 case USB_ENDPOINT_XFER_INT: 182 type = "interrupt"; 183 break; 184 case USB_ENDPOINT_XFER_CONTROL: 185 type = "control"; 186 break; 187 case USB_ENDPOINT_XFER_BULK: 188 type = "bulk"; 189 break; 190 default: 191 type = "?"; 192 break; 193 } 194 195 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 196 #endif 197 198 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 199 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 200 qh->usecs); 201 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 202 qh->interval); 203 } 204 } 205 206 /** 207 * dwc2_hcd_qh_create() - Allocates and initializes a QH 208 * 209 * @hsotg: The HCD state structure for the DWC OTG controller 210 * @urb: Holds the information about the device/endpoint needed 211 * to initialize the QH 212 * @mem_flags: Flag to do atomic allocation if needed 213 * 214 * Return: Pointer to the newly allocated QH, or NULL on error 215 */ 216 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 217 struct dwc2_hcd_urb *urb, 218 gfp_t mem_flags) 219 { 220 struct dwc2_softc *sc = hsotg->hsotg_sc; 221 struct dwc2_qh *qh; 222 223 if (!urb->priv) 224 return NULL; 225 226 /* Allocate memory */ 227 qh = pool_get(&sc->sc_qhpool, PR_NOWAIT); 228 if (!qh) 229 return NULL; 230 231 memset(qh, 0, sizeof(*qh)); 232 dwc2_qh_init(hsotg, qh, urb); 233 234 if (hsotg->core_params->dma_desc_enable > 0 && 235 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 236 dwc2_hcd_qh_free(hsotg, qh); 237 return NULL; 238 } 239 240 return qh; 241 } 242 243 /** 244 * dwc2_hcd_qh_free() - Frees the QH 245 * 246 * @hsotg: HCD instance 247 * @qh: The QH to free 248 * 249 * QH should already be removed from the list. QTD list should already be empty 250 * if called from URB Dequeue. 251 * 252 * Must NOT be called with interrupt disabled or spinlock held 253 */ 254 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 255 { 256 struct dwc2_softc *sc = hsotg->hsotg_sc; 257 258 /* 259 * We don't have the lock so we can safely wait until the wait timer 260 * finishes. Of course, at this point in time we'd better have set 261 * wait_timer_active to false so if this timer was still pending it 262 * won't do anything anyway, but we want it to finish before we free 263 * memory. 264 */ 265 /* XXX del_timer_sync(&qh->wait_timer); */ 266 267 timeout_del(&qh->wait_timer); 268 if (qh->desc_list) { 269 dwc2_hcd_qh_free_ddma(hsotg, qh); 270 } else if (qh->dw_align_buf) { 271 usb_freemem(&sc->sc_bus, &qh->dw_align_buf_usbdma); 272 qh->dw_align_buf_dma = (dma_addr_t)0; 273 } 274 275 pool_put(&sc->sc_qhpool, qh); 276 } 277 278 /** 279 * dwc2_periodic_channel_available() - Checks that a channel is available for a 280 * periodic transfer 281 * 282 * @hsotg: The HCD state structure for the DWC OTG controller 283 * 284 * Return: 0 if successful, negative error code otherwise 285 */ 286 STATIC int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 287 { 288 /* 289 * Currently assuming that there is a dedicated host channel for 290 * each periodic transaction plus at least one host channel for 291 * non-periodic transactions 292 */ 293 int status; 294 int num_channels; 295 296 num_channels = hsotg->core_params->host_channels; 297 if (hsotg->periodic_channels + hsotg->non_periodic_channels < 298 num_channels 299 && hsotg->periodic_channels < num_channels - 1) { 300 status = 0; 301 } else { 302 dev_dbg(hsotg->dev, 303 "%s: Total channels: %d, Periodic: %d, " 304 "Non-periodic: %d\n", __func__, num_channels, 305 hsotg->periodic_channels, hsotg->non_periodic_channels); 306 status = -ENOSPC; 307 } 308 309 return status; 310 } 311 312 /** 313 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 314 * for the specified QH in the periodic schedule 315 * 316 * @hsotg: The HCD state structure for the DWC OTG controller 317 * @qh: QH containing periodic bandwidth required 318 * 319 * Return: 0 if successful, negative error code otherwise 320 * 321 * For simplicity, this calculation assumes that all the transfers in the 322 * periodic schedule may occur in the same (micro)frame 323 */ 324 STATIC int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 325 struct dwc2_qh *qh) 326 { 327 int status; 328 s16 max_claimed_usecs; 329 330 status = 0; 331 332 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 333 /* 334 * High speed mode 335 * Max periodic usecs is 80% x 125 usec = 100 usec 336 */ 337 max_claimed_usecs = 100 - qh->usecs; 338 } else { 339 /* 340 * Full speed mode 341 * Max periodic usecs is 90% x 1000 usec = 900 usec 342 */ 343 max_claimed_usecs = 900 - qh->usecs; 344 } 345 346 if (hsotg->periodic_usecs > max_claimed_usecs) { 347 dev_err(hsotg->dev, 348 "%s: already claimed usecs %d, required usecs %d\n", 349 __func__, hsotg->periodic_usecs, qh->usecs); 350 status = -ENOSPC; 351 } 352 353 return status; 354 } 355 356 /** 357 * Microframe scheduler 358 * track the total use in hsotg->frame_usecs 359 * keep each qh use in qh->frame_usecs 360 * when surrendering the qh then donate the time back 361 */ 362 STATIC const unsigned short max_uframe_usecs[] = { 363 100, 100, 100, 100, 100, 100, 30, 0 364 }; 365 366 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 367 { 368 int i; 369 370 for (i = 0; i < 8; i++) 371 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 372 } 373 374 STATIC int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 375 { 376 unsigned short utime = qh->usecs; 377 int i; 378 379 for (i = 0; i < 8; i++) { 380 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 381 if (utime <= hsotg->frame_usecs[i]) { 382 hsotg->frame_usecs[i] -= utime; 383 qh->frame_usecs[i] += utime; 384 return i; 385 } 386 } 387 return -ENOSPC; 388 } 389 390 /* 391 * use this for FS apps that can span multiple uframes 392 */ 393 STATIC int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 394 { 395 unsigned short utime = qh->usecs; 396 unsigned short xtime; 397 int t_left; 398 int i; 399 int j; 400 int k; 401 402 for (i = 0; i < 8; i++) { 403 if (hsotg->frame_usecs[i] <= 0) 404 continue; 405 406 /* 407 * we need n consecutive slots so use j as a start slot 408 * j plus j+1 must be enough time (for now) 409 */ 410 xtime = hsotg->frame_usecs[i]; 411 for (j = i + 1; j < 8; j++) { 412 /* 413 * if we add this frame remaining time to xtime we may 414 * be OK, if not we need to test j for a complete frame 415 */ 416 if (xtime + hsotg->frame_usecs[j] < utime) { 417 if (hsotg->frame_usecs[j] < 418 max_uframe_usecs[j]) 419 continue; 420 } 421 if (xtime >= utime) { 422 t_left = utime; 423 for (k = i; k < 8; k++) { 424 t_left -= hsotg->frame_usecs[k]; 425 if (t_left <= 0) { 426 qh->frame_usecs[k] += 427 hsotg->frame_usecs[k] 428 + t_left; 429 hsotg->frame_usecs[k] = -t_left; 430 return i; 431 } else { 432 qh->frame_usecs[k] += 433 hsotg->frame_usecs[k]; 434 hsotg->frame_usecs[k] = 0; 435 } 436 } 437 } 438 /* add the frame time to x time */ 439 xtime += hsotg->frame_usecs[j]; 440 /* we must have a fully available next frame or break */ 441 if (xtime < utime && 442 hsotg->frame_usecs[j] == max_uframe_usecs[j]) 443 continue; 444 } 445 } 446 return -ENOSPC; 447 } 448 449 STATIC int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 450 { 451 int ret; 452 453 if (qh->dev_speed == USB_SPEED_HIGH) { 454 /* if this is a hs transaction we need a full frame */ 455 ret = dwc2_find_single_uframe(hsotg, qh); 456 } else { 457 /* 458 * if this is a fs transaction we may need a sequence 459 * of frames 460 */ 461 ret = dwc2_find_multi_uframe(hsotg, qh); 462 } 463 return ret; 464 } 465 466 /** 467 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 468 * host channel is large enough to handle the maximum data transfer in a single 469 * (micro)frame for a periodic transfer 470 * 471 * @hsotg: The HCD state structure for the DWC OTG controller 472 * @qh: QH for a periodic endpoint 473 * 474 * Return: 0 if successful, negative error code otherwise 475 */ 476 STATIC int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 477 struct dwc2_qh *qh) 478 { 479 u32 max_xfer_size; 480 u32 max_channel_xfer_size; 481 int status = 0; 482 483 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 484 max_channel_xfer_size = hsotg->core_params->max_transfer_size; 485 486 if (max_xfer_size > max_channel_xfer_size) { 487 dev_err(hsotg->dev, 488 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 489 __func__, max_xfer_size, max_channel_xfer_size); 490 status = -ENOSPC; 491 } 492 493 return status; 494 } 495 496 /** 497 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 498 * the periodic schedule 499 * 500 * @hsotg: The HCD state structure for the DWC OTG controller 501 * @qh: QH for the periodic transfer. The QH should already contain the 502 * scheduling information. 503 * 504 * Return: 0 if successful, negative error code otherwise 505 */ 506 STATIC int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 507 { 508 int status; 509 510 if (hsotg->core_params->uframe_sched > 0) { 511 int frame = -1; 512 513 status = dwc2_find_uframe(hsotg, qh); 514 if (status == 0) 515 frame = 7; 516 else if (status > 0) 517 frame = status - 1; 518 519 /* Set the new frame up */ 520 if (frame >= 0) { 521 qh->sched_frame &= ~0x7; 522 qh->sched_frame |= (frame & 7); 523 } 524 525 if (status > 0) 526 status = 0; 527 } else { 528 status = dwc2_periodic_channel_available(hsotg); 529 if (status) { 530 dev_info(hsotg->dev, 531 "%s: No host channel available for periodic transfer\n", 532 __func__); 533 return status; 534 } 535 536 status = dwc2_check_periodic_bandwidth(hsotg, qh); 537 } 538 539 if (status) { 540 dev_dbg(hsotg->dev, 541 "%s: Insufficient periodic bandwidth for periodic transfer\n", 542 __func__); 543 return status; 544 } 545 546 status = dwc2_check_max_xfer_size(hsotg, qh); 547 if (status) { 548 dev_dbg(hsotg->dev, 549 "%s: Channel max transfer size too small for periodic transfer\n", 550 __func__); 551 return status; 552 } 553 554 if (hsotg->core_params->dma_desc_enable > 0) 555 /* Don't rely on SOF and start in ready schedule */ 556 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 557 else 558 /* Always start in inactive schedule */ 559 list_add_tail(&qh->qh_list_entry, 560 &hsotg->periodic_sched_inactive); 561 562 if (hsotg->core_params->uframe_sched <= 0) 563 /* Reserve periodic channel */ 564 hsotg->periodic_channels++; 565 566 /* Update claimed usecs per (micro)frame */ 567 hsotg->periodic_usecs += qh->usecs; 568 569 return status; 570 } 571 572 /** 573 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 574 * from the periodic schedule 575 * 576 * @hsotg: The HCD state structure for the DWC OTG controller 577 * @qh: QH for the periodic transfer 578 */ 579 STATIC void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 580 struct dwc2_qh *qh) 581 { 582 int i; 583 584 list_del_init(&qh->qh_list_entry); 585 586 /* Update claimed usecs per (micro)frame */ 587 hsotg->periodic_usecs -= qh->usecs; 588 589 if (hsotg->core_params->uframe_sched > 0) { 590 for (i = 0; i < 8; i++) { 591 hsotg->frame_usecs[i] += qh->frame_usecs[i]; 592 qh->frame_usecs[i] = 0; 593 } 594 } else { 595 /* Release periodic channel reservation */ 596 hsotg->periodic_channels--; 597 } 598 } 599 600 /** 601 * dwc2_wait_timer_fn() - Timer function to re-queue after waiting 602 * 603 * As per the spec, a NAK indicates that "a function is temporarily unable to 604 * transmit or receive data, but will eventually be able to do so without need 605 * of host intervention". 606 * 607 * That means that when we encounter a NAK we're supposed to retry. 608 * 609 * ...but if we retry right away (from the interrupt handler that saw the NAK) 610 * then we can end up with an interrupt storm (if the other side keeps NAKing 611 * us) because on slow enough CPUs it could take us longer to get out of the 612 * interrupt routine than it takes for the device to send another NAK. That 613 * leads to a constant stream of NAK interrupts and the CPU locks. 614 * 615 * ...so instead of retrying right away in the case of a NAK we'll set a timer 616 * to retry some time later. This function handles that timer and moves the 617 * qh back to the "inactive" list, then queues transactions. 618 * 619 * @t: Pointer to wait_timer in a qh. 620 */ 621 STATIC void dwc2_wait_timer_fn(void *arg) 622 { 623 struct dwc2_qh *qh = arg; 624 struct dwc2_hsotg *hsotg = qh->hsotg; 625 unsigned long flags; 626 627 spin_lock_irqsave(&hsotg->lock, flags); 628 629 /* 630 * We'll set wait_timer_cancel to true if we want to cancel this 631 * operation in dwc2_hcd_qh_unlink(). 632 */ 633 if (!qh->wait_timer_cancel) { 634 enum dwc2_transaction_type tr_type; 635 636 qh->want_wait = false; 637 638 list_move(&qh->qh_list_entry, 639 &hsotg->non_periodic_sched_inactive); 640 641 tr_type = dwc2_hcd_select_transactions(hsotg); 642 if (tr_type != DWC2_TRANSACTION_NONE) 643 dwc2_hcd_queue_transactions(hsotg, tr_type); 644 } 645 646 spin_unlock_irqrestore(&hsotg->lock, flags); 647 } 648 649 /** 650 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 651 * schedule if it is not already in the schedule. If the QH is already in 652 * the schedule, no action is taken. 653 * 654 * @hsotg: The HCD state structure for the DWC OTG controller 655 * @qh: The QH to add 656 * 657 * Return: 0 if successful, negative error code otherwise 658 */ 659 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 660 { 661 int status; 662 u32 intr_mask; 663 664 if (dbg_qh(qh)) 665 dev_vdbg(hsotg->dev, "%s()\n", __func__); 666 667 if (!list_empty(&qh->qh_list_entry)) 668 /* QH already in a schedule */ 669 return 0; 670 671 if (!dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number) && 672 !hsotg->frame_number) { 673 dev_dbg(hsotg->dev, 674 "reset frame number counter\n"); 675 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 676 SCHEDULE_SLOP); 677 } 678 679 /* Add the new QH to the appropriate schedule */ 680 if (dwc2_qh_is_non_per(qh)) { 681 if (qh->want_wait) { 682 list_add_tail(&qh->qh_list_entry, 683 &hsotg->non_periodic_sched_waiting); 684 qh->wait_timer_cancel = false; 685 /* XXX mod_timer(&qh->wait_timer, 686 jiffies + DWC2_RETRY_WAIT_DELAY + 1); */ 687 timeout_add_msec(&qh->wait_timer, 688 DWC2_RETRY_WAIT_DELAY); 689 } else { 690 list_add_tail(&qh->qh_list_entry, 691 &hsotg->non_periodic_sched_inactive); 692 } 693 return 0; 694 } 695 696 status = dwc2_schedule_periodic(hsotg, qh); 697 if (status) 698 return status; 699 if (!hsotg->periodic_qh_count) { 700 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 701 intr_mask |= GINTSTS_SOF; 702 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 703 } 704 hsotg->periodic_qh_count++; 705 706 return 0; 707 } 708 709 /** 710 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 711 * schedule. Memory is not freed. 712 * 713 * @hsotg: The HCD state structure 714 * @qh: QH to remove from schedule 715 */ 716 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 717 { 718 u32 intr_mask; 719 720 dev_vdbg(hsotg->dev, "%s()\n", __func__); 721 722 /* If the wait_timer is pending, this will stop it from acting */ 723 qh->wait_timer_cancel = true; 724 725 if (list_empty(&qh->qh_list_entry)) 726 /* QH is not in a schedule */ 727 return; 728 729 if (dwc2_qh_is_non_per(qh)) { 730 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) 731 hsotg->non_periodic_qh_ptr = 732 hsotg->non_periodic_qh_ptr->next; 733 list_del_init(&qh->qh_list_entry); 734 return; 735 } 736 737 dwc2_deschedule_periodic(hsotg, qh); 738 hsotg->periodic_qh_count--; 739 if (!hsotg->periodic_qh_count) { 740 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 741 intr_mask &= ~GINTSTS_SOF; 742 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 743 } 744 } 745 746 /* 747 * Schedule the next continuing periodic split transfer 748 */ 749 STATIC void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, 750 struct dwc2_qh *qh, u16 frame_number, 751 int sched_next_periodic_split) 752 { 753 u16 incr; 754 755 if (sched_next_periodic_split) { 756 qh->sched_frame = frame_number; 757 incr = dwc2_frame_num_inc(qh->start_split_frame, 1); 758 if (dwc2_frame_num_le(frame_number, incr)) { 759 /* 760 * Allow one frame to elapse after start split 761 * microframe before scheduling complete split, but 762 * DON'T if we are doing the next start split in the 763 * same frame for an ISOC out 764 */ 765 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || 766 qh->ep_is_in != 0) { 767 qh->sched_frame = 768 dwc2_frame_num_inc(qh->sched_frame, 1); 769 } 770 } 771 } else { 772 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, 773 qh->interval); 774 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 775 qh->sched_frame = frame_number; 776 qh->sched_frame |= 0x7; 777 qh->start_split_frame = qh->sched_frame; 778 } 779 } 780 781 /* 782 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 783 * non-periodic schedule. The QH is added to the inactive non-periodic 784 * schedule if any QTDs are still attached to the QH. 785 * 786 * For periodic QHs, the QH is removed from the periodic queued schedule. If 787 * there are any QTDs still attached to the QH, the QH is added to either the 788 * periodic inactive schedule or the periodic ready schedule and its next 789 * scheduled frame is calculated. The QH is placed in the ready schedule if 790 * the scheduled frame has been reached already. Otherwise it's placed in the 791 * inactive schedule. If there are no QTDs attached to the QH, the QH is 792 * completely removed from the periodic schedule. 793 */ 794 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 795 int sched_next_periodic_split) 796 { 797 u16 frame_number; 798 799 if (dbg_qh(qh)) 800 dev_vdbg(hsotg->dev, "%s()\n", __func__); 801 802 if (dwc2_qh_is_non_per(qh)) { 803 dwc2_hcd_qh_unlink(hsotg, qh); 804 if (!list_empty(&qh->qtd_list)) 805 /* Add back to inactive/waiting non-periodic schedule */ 806 dwc2_hcd_qh_add(hsotg, qh); 807 return; 808 } 809 810 frame_number = dwc2_hcd_get_frame_number(hsotg); 811 812 if (qh->do_split) { 813 dwc2_sched_periodic_split(hsotg, qh, frame_number, 814 sched_next_periodic_split); 815 } else { 816 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, 817 qh->interval); 818 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 819 qh->sched_frame = frame_number; 820 } 821 822 if (list_empty(&qh->qtd_list)) { 823 dwc2_hcd_qh_unlink(hsotg, qh); 824 return; 825 } 826 /* 827 * Remove from periodic_sched_queued and move to 828 * appropriate queue 829 */ 830 if ((hsotg->core_params->uframe_sched > 0 && 831 dwc2_frame_num_le(qh->sched_frame, frame_number)) || 832 (hsotg->core_params->uframe_sched <= 0 && 833 qh->sched_frame == frame_number)) 834 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 835 else 836 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive); 837 } 838 839 /** 840 * dwc2_hcd_qtd_init() - Initializes a QTD structure 841 * 842 * @qtd: The QTD to initialize 843 * @urb: The associated URB 844 */ 845 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 846 { 847 qtd->urb = urb; 848 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 849 USB_ENDPOINT_XFER_CONTROL) { 850 /* 851 * The only time the QTD data toggle is used is on the data 852 * phase of control transfers. This phase always starts with 853 * DATA1. 854 */ 855 qtd->data_toggle = DWC2_HC_PID_DATA1; 856 qtd->control_phase = DWC2_CONTROL_SETUP; 857 } 858 859 /* Start split */ 860 qtd->complete_split = 0; 861 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 862 qtd->isoc_split_offset = 0; 863 qtd->in_process = 0; 864 865 /* Store the qtd ptr in the urb to reference the QTD */ 866 urb->qtd = qtd; 867 } 868 869 /** 870 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 871 * Caller must hold driver lock. 872 * 873 * @hsotg: The DWC HCD structure 874 * @qtd: The QTD to add 875 * @qh: Queue head to add qtd to 876 * 877 * Return: 0 if successful, negative error code otherwise 878 * 879 * If the QH to which the QTD is added is not currently scheduled, it is placed 880 * into the proper schedule based on its EP type. 881 */ 882 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 883 struct dwc2_qh *qh) 884 { 885 886 MUTEX_ASSERT_LOCKED(&hsotg->lock); 887 int retval; 888 889 if (!qh) { 890 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__); 891 retval = -EINVAL; 892 goto fail; 893 } 894 895 retval = dwc2_hcd_qh_add(hsotg, qh); 896 if (retval) 897 goto fail; 898 899 qtd->qh = qh; 900 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); 901 902 return 0; 903 fail: 904 return retval; 905 } 906 907 void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 908 struct dwc2_qtd *qtd, 909 struct dwc2_qh *qh) 910 { 911 struct dwc2_softc *sc = hsotg->hsotg_sc; 912 913 list_del_init(&qtd->qtd_list_entry); 914 pool_put(&sc->sc_qtdpool, qtd); 915 } 916 917 #define BITSTUFFTIME(bytecount) ((8 * 7 * (bytecount)) / 6) 918 #define HS_HOST_DELAY 5 /* nanoseconds */ 919 #define FS_LS_HOST_DELAY 1000 /* nanoseconds */ 920 #define HUB_LS_SETUP 333 /* nanoseconds */ 921 922 STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in, 923 int is_isoc, int bytecount) 924 { 925 unsigned long retval; 926 927 switch (speed) { 928 case USB_SPEED_HIGH: 929 if (is_isoc) 930 retval = 931 ((38 * 8 * 2083) + 932 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 933 HS_HOST_DELAY; 934 else 935 retval = 936 ((55 * 8 * 2083) + 937 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 938 HS_HOST_DELAY; 939 break; 940 case USB_SPEED_FULL: 941 if (is_isoc) { 942 retval = 943 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 944 if (is_in) 945 retval = 7268 + FS_LS_HOST_DELAY + retval; 946 else 947 retval = 6265 + FS_LS_HOST_DELAY + retval; 948 } else { 949 retval = 950 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 951 retval = 9107 + FS_LS_HOST_DELAY + retval; 952 } 953 break; 954 case USB_SPEED_LOW: 955 if (is_in) { 956 retval = 957 (67667 * (31 + 10 * BITSTUFFTIME(bytecount))) / 958 1000; 959 retval = 960 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 961 retval; 962 } else { 963 retval = 964 (66700 * (31 + 10 * BITSTUFFTIME(bytecount))) / 965 1000; 966 retval = 967 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 968 retval; 969 } 970 break; 971 default: 972 dev_warn(hsotg->dev, "Unknown device speed\n"); 973 retval = -1; 974 } 975 976 return NS_TO_US(retval); 977 } 978