1 /* 2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> 3 * 4 * i.MX6UL SOC emulation. 5 * 6 * Based on hw/arm/fsl-imx7.c 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qapi/error.h" 21 #include "hw/arm/fsl-imx6ul.h" 22 #include "hw/misc/unimp.h" 23 #include "hw/usb/imx-usb-phy.h" 24 #include "hw/boards.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/error-report.h" 27 #include "qemu/module.h" 28 29 #define NAME_SIZE 20 30 31 static void fsl_imx6ul_init(Object *obj) 32 { 33 FslIMX6ULState *s = FSL_IMX6UL(obj); 34 char name[NAME_SIZE]; 35 int i; 36 37 object_initialize_child(obj, "cpu0", &s->cpu, 38 ARM_CPU_TYPE_NAME("cortex-a7")); 39 40 /* 41 * A7MPCORE 42 */ 43 object_initialize_child(obj, "a7mpcore", &s->a7mpcore, 44 TYPE_A15MPCORE_PRIV); 45 46 /* 47 * CCM 48 */ 49 object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6UL_CCM); 50 51 /* 52 * SRC 53 */ 54 object_initialize_child(obj, "src", &s->src, TYPE_IMX6_SRC); 55 56 /* 57 * GPCv2 58 */ 59 object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); 60 61 /* 62 * SNVS 63 */ 64 object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); 65 66 /* 67 * GPIOs 1 to 5 68 */ 69 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 70 snprintf(name, NAME_SIZE, "gpio%d", i); 71 object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); 72 } 73 74 /* 75 * GPT 1, 2 76 */ 77 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 78 snprintf(name, NAME_SIZE, "gpt%d", i); 79 object_initialize_child(obj, name, &s->gpt[i], TYPE_IMX6UL_GPT); 80 } 81 82 /* 83 * EPIT 1, 2 84 */ 85 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 86 snprintf(name, NAME_SIZE, "epit%d", i + 1); 87 object_initialize_child(obj, name, &s->epit[i], TYPE_IMX_EPIT); 88 } 89 90 /* 91 * eCSPI 92 */ 93 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 94 snprintf(name, NAME_SIZE, "spi%d", i + 1); 95 object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); 96 } 97 98 /* 99 * I2C 100 */ 101 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 102 snprintf(name, NAME_SIZE, "i2c%d", i + 1); 103 object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); 104 } 105 106 /* 107 * UART 108 */ 109 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 110 snprintf(name, NAME_SIZE, "uart%d", i); 111 object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); 112 } 113 114 /* 115 * Ethernet 116 */ 117 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 118 snprintf(name, NAME_SIZE, "eth%d", i); 119 object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); 120 } 121 122 /* USB */ 123 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 124 snprintf(name, NAME_SIZE, "usbphy%d", i); 125 object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); 126 } 127 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 128 snprintf(name, NAME_SIZE, "usb%d", i); 129 object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); 130 } 131 132 /* 133 * SDHCI 134 */ 135 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 136 snprintf(name, NAME_SIZE, "usdhc%d", i); 137 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); 138 } 139 140 /* 141 * Watchdog 142 */ 143 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 144 snprintf(name, NAME_SIZE, "wdt%d", i); 145 object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); 146 } 147 } 148 149 static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) 150 { 151 MachineState *ms = MACHINE(qdev_get_machine()); 152 FslIMX6ULState *s = FSL_IMX6UL(dev); 153 int i; 154 char name[NAME_SIZE]; 155 SysBusDevice *sbd; 156 DeviceState *d; 157 158 if (ms->smp.cpus > 1) { 159 error_setg(errp, "%s: Only a single CPU is supported (%d requested)", 160 TYPE_FSL_IMX6UL, ms->smp.cpus); 161 return; 162 } 163 164 qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); 165 166 /* 167 * A7MPCORE 168 */ 169 object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort); 170 object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", 171 FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort); 172 sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); 173 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); 174 175 sbd = SYS_BUS_DEVICE(&s->a7mpcore); 176 d = DEVICE(&s->cpu); 177 178 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); 179 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); 180 sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); 181 sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); 182 183 /* 184 * A7MPCORE DAP 185 */ 186 create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, 187 0x100000); 188 189 /* 190 * GPT 1, 2 191 */ 192 for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { 193 static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { 194 FSL_IMX6UL_GPT1_ADDR, 195 FSL_IMX6UL_GPT2_ADDR, 196 }; 197 198 static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = { 199 FSL_IMX6UL_GPT1_IRQ, 200 FSL_IMX6UL_GPT2_IRQ, 201 }; 202 203 s->gpt[i].ccm = IMX_CCM(&s->ccm); 204 sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); 205 206 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, 207 FSL_IMX6UL_GPTn_ADDR[i]); 208 209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, 210 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 211 FSL_IMX6UL_GPTn_IRQ[i])); 212 } 213 214 /* 215 * EPIT 1, 2 216 */ 217 for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { 218 static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { 219 FSL_IMX6UL_EPIT1_ADDR, 220 FSL_IMX6UL_EPIT2_ADDR, 221 }; 222 223 static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = { 224 FSL_IMX6UL_EPIT1_IRQ, 225 FSL_IMX6UL_EPIT2_IRQ, 226 }; 227 228 s->epit[i].ccm = IMX_CCM(&s->ccm); 229 sysbus_realize(SYS_BUS_DEVICE(&s->epit[i]), &error_abort); 230 231 sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, 232 FSL_IMX6UL_EPITn_ADDR[i]); 233 234 sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, 235 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 236 FSL_IMX6UL_EPITn_IRQ[i])); 237 } 238 239 /* 240 * GPIO 241 */ 242 for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { 243 static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { 244 FSL_IMX6UL_GPIO1_ADDR, 245 FSL_IMX6UL_GPIO2_ADDR, 246 FSL_IMX6UL_GPIO3_ADDR, 247 FSL_IMX6UL_GPIO4_ADDR, 248 FSL_IMX6UL_GPIO5_ADDR, 249 }; 250 251 static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 252 FSL_IMX6UL_GPIO1_LOW_IRQ, 253 FSL_IMX6UL_GPIO2_LOW_IRQ, 254 FSL_IMX6UL_GPIO3_LOW_IRQ, 255 FSL_IMX6UL_GPIO4_LOW_IRQ, 256 FSL_IMX6UL_GPIO5_LOW_IRQ, 257 }; 258 259 static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = { 260 FSL_IMX6UL_GPIO1_HIGH_IRQ, 261 FSL_IMX6UL_GPIO2_HIGH_IRQ, 262 FSL_IMX6UL_GPIO3_HIGH_IRQ, 263 FSL_IMX6UL_GPIO4_HIGH_IRQ, 264 FSL_IMX6UL_GPIO5_HIGH_IRQ, 265 }; 266 267 sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); 268 269 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, 270 FSL_IMX6UL_GPIOn_ADDR[i]); 271 272 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, 273 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 274 FSL_IMX6UL_GPIOn_LOW_IRQ[i])); 275 276 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, 277 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 278 FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); 279 } 280 281 /* 282 * IOMUXC and IOMUXC_GPR 283 */ 284 for (i = 0; i < 1; i++) { 285 static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { 286 FSL_IMX6UL_IOMUXC_ADDR, 287 FSL_IMX6UL_IOMUXC_GPR_ADDR, 288 }; 289 290 snprintf(name, NAME_SIZE, "iomuxc%d", i); 291 create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); 292 } 293 294 /* 295 * CCM 296 */ 297 sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_abort); 298 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR); 299 300 /* 301 * SRC 302 */ 303 sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); 304 sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR); 305 306 /* 307 * GPCv2 308 */ 309 sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); 310 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); 311 312 /* Initialize all ECSPI */ 313 for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { 314 static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { 315 FSL_IMX6UL_ECSPI1_ADDR, 316 FSL_IMX6UL_ECSPI2_ADDR, 317 FSL_IMX6UL_ECSPI3_ADDR, 318 FSL_IMX6UL_ECSPI4_ADDR, 319 }; 320 321 static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { 322 FSL_IMX6UL_ECSPI1_IRQ, 323 FSL_IMX6UL_ECSPI2_IRQ, 324 FSL_IMX6UL_ECSPI3_IRQ, 325 FSL_IMX6UL_ECSPI4_IRQ, 326 }; 327 328 /* Initialize the SPI */ 329 sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &error_abort); 330 331 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, 332 FSL_IMX6UL_SPIn_ADDR[i]); 333 334 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, 335 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 336 FSL_IMX6UL_SPIn_IRQ[i])); 337 } 338 339 /* 340 * I2C 341 */ 342 for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { 343 static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { 344 FSL_IMX6UL_I2C1_ADDR, 345 FSL_IMX6UL_I2C2_ADDR, 346 FSL_IMX6UL_I2C3_ADDR, 347 FSL_IMX6UL_I2C4_ADDR, 348 }; 349 350 static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { 351 FSL_IMX6UL_I2C1_IRQ, 352 FSL_IMX6UL_I2C2_IRQ, 353 FSL_IMX6UL_I2C3_IRQ, 354 FSL_IMX6UL_I2C4_IRQ, 355 }; 356 357 sysbus_realize(SYS_BUS_DEVICE(&s->i2c[i]), &error_abort); 358 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); 359 360 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, 361 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 362 FSL_IMX6UL_I2Cn_IRQ[i])); 363 } 364 365 /* 366 * UART 367 */ 368 for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { 369 static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { 370 FSL_IMX6UL_UART1_ADDR, 371 FSL_IMX6UL_UART2_ADDR, 372 FSL_IMX6UL_UART3_ADDR, 373 FSL_IMX6UL_UART4_ADDR, 374 FSL_IMX6UL_UART5_ADDR, 375 FSL_IMX6UL_UART6_ADDR, 376 FSL_IMX6UL_UART7_ADDR, 377 FSL_IMX6UL_UART8_ADDR, 378 }; 379 380 static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = { 381 FSL_IMX6UL_UART1_IRQ, 382 FSL_IMX6UL_UART2_IRQ, 383 FSL_IMX6UL_UART3_IRQ, 384 FSL_IMX6UL_UART4_IRQ, 385 FSL_IMX6UL_UART5_IRQ, 386 FSL_IMX6UL_UART6_IRQ, 387 FSL_IMX6UL_UART7_IRQ, 388 FSL_IMX6UL_UART8_IRQ, 389 }; 390 391 qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); 392 393 sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), &error_abort); 394 395 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, 396 FSL_IMX6UL_UARTn_ADDR[i]); 397 398 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, 399 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 400 FSL_IMX6UL_UARTn_IRQ[i])); 401 } 402 403 /* 404 * Ethernet 405 * 406 * We must use two loops since phy_connected affects the other interface 407 * and we have to set all properties before calling sysbus_realize(). 408 */ 409 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 410 object_property_set_bool(OBJECT(&s->eth[i]), "phy-connected", 411 s->phy_connected[i], &error_abort); 412 /* 413 * If the MDIO bus on this controller is not connected, assume the 414 * other controller provides support for it. 415 */ 416 if (!s->phy_connected[i]) { 417 object_property_set_link(OBJECT(&s->eth[1 - i]), "phy-consumer", 418 OBJECT(&s->eth[i]), &error_abort); 419 } 420 } 421 422 for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { 423 static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = { 424 FSL_IMX6UL_ENET1_ADDR, 425 FSL_IMX6UL_ENET2_ADDR, 426 }; 427 428 static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = { 429 FSL_IMX6UL_ENET1_IRQ, 430 FSL_IMX6UL_ENET2_IRQ, 431 }; 432 433 static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = { 434 FSL_IMX6UL_ENET1_TIMER_IRQ, 435 FSL_IMX6UL_ENET2_TIMER_IRQ, 436 }; 437 438 object_property_set_uint(OBJECT(&s->eth[i]), "phy-num", 439 s->phy_num[i], &error_abort); 440 object_property_set_uint(OBJECT(&s->eth[i]), "tx-ring-num", 441 FSL_IMX6UL_ETH_NUM_TX_RINGS, &error_abort); 442 qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); 443 sysbus_realize(SYS_BUS_DEVICE(&s->eth[i]), &error_abort); 444 445 sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, 446 FSL_IMX6UL_ENETn_ADDR[i]); 447 448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, 449 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 450 FSL_IMX6UL_ENETn_IRQ[i])); 451 452 sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, 453 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 454 FSL_IMX6UL_ENETn_TIMER_IRQ[i])); 455 } 456 457 /* USB */ 458 for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { 459 sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); 460 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, 461 FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); 462 } 463 464 for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { 465 static const int FSL_IMX6UL_USBn_IRQ[] = { 466 FSL_IMX6UL_USB1_IRQ, 467 FSL_IMX6UL_USB2_IRQ, 468 }; 469 sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); 470 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, 471 FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); 472 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, 473 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 474 FSL_IMX6UL_USBn_IRQ[i])); 475 } 476 477 /* 478 * USDHC 479 */ 480 for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { 481 static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { 482 FSL_IMX6UL_USDHC1_ADDR, 483 FSL_IMX6UL_USDHC2_ADDR, 484 }; 485 486 static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = { 487 FSL_IMX6UL_USDHC1_IRQ, 488 FSL_IMX6UL_USDHC2_IRQ, 489 }; 490 491 object_property_set_uint(OBJECT(&s->usdhc[i]), "vendor", 492 SDHCI_VENDOR_IMX, &error_abort); 493 sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort); 494 495 sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 496 FSL_IMX6UL_USDHCn_ADDR[i]); 497 498 sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, 499 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 500 FSL_IMX6UL_USDHCn_IRQ[i])); 501 } 502 503 /* 504 * SNVS 505 */ 506 sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); 507 sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); 508 509 /* 510 * Watchdog 511 */ 512 for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { 513 static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { 514 FSL_IMX6UL_WDOG1_ADDR, 515 FSL_IMX6UL_WDOG2_ADDR, 516 FSL_IMX6UL_WDOG3_ADDR, 517 }; 518 static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { 519 FSL_IMX6UL_WDOG1_IRQ, 520 FSL_IMX6UL_WDOG2_IRQ, 521 FSL_IMX6UL_WDOG3_IRQ, 522 }; 523 524 object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", 525 true, &error_abort); 526 sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &error_abort); 527 528 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, 529 FSL_IMX6UL_WDOGn_ADDR[i]); 530 sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, 531 qdev_get_gpio_in(DEVICE(&s->a7mpcore), 532 FSL_IMX6UL_WDOGn_IRQ[i])); 533 } 534 535 /* 536 * SDMA 537 */ 538 create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); 539 540 /* 541 * SAI (Audio SSI (Synchronous Serial Interface)) 542 */ 543 create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); 544 create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); 545 create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); 546 547 /* 548 * PWM 549 */ 550 create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); 551 create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); 552 create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); 553 create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); 554 555 /* 556 * Audio ASRC (asynchronous sample rate converter) 557 */ 558 create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); 559 560 /* 561 * CAN 562 */ 563 create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); 564 create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); 565 566 /* 567 * APHB_DMA 568 */ 569 create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR, 570 FSL_IMX6UL_APBH_DMA_SIZE); 571 572 /* 573 * ADCs 574 */ 575 for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) { 576 static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = { 577 FSL_IMX6UL_ADC1_ADDR, 578 FSL_IMX6UL_ADC2_ADDR, 579 }; 580 581 snprintf(name, NAME_SIZE, "adc%d", i); 582 create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); 583 } 584 585 /* 586 * LCD 587 */ 588 create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); 589 590 /* 591 * ROM memory 592 */ 593 memory_region_init_rom(&s->rom, OBJECT(dev), "imx6ul.rom", 594 FSL_IMX6UL_ROM_SIZE, &error_abort); 595 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR, 596 &s->rom); 597 598 /* 599 * CAAM memory 600 */ 601 memory_region_init_rom(&s->caam, OBJECT(dev), "imx6ul.caam", 602 FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort); 603 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR, 604 &s->caam); 605 606 /* 607 * OCRAM memory 608 */ 609 memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram", 610 FSL_IMX6UL_OCRAM_MEM_SIZE, 611 &error_abort); 612 memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR, 613 &s->ocram); 614 615 /* 616 * internal OCRAM (128 KB) is aliased over 512 KB 617 */ 618 memory_region_init_alias(&s->ocram_alias, OBJECT(dev), 619 "imx6ul.ocram_alias", &s->ocram, 0, 620 FSL_IMX6UL_OCRAM_ALIAS_SIZE); 621 memory_region_add_subregion(get_system_memory(), 622 FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); 623 } 624 625 static Property fsl_imx6ul_properties[] = { 626 DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), 627 DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), 628 DEFINE_PROP_BOOL("fec1-phy-connected", FslIMX6ULState, phy_connected[0], 629 true), 630 DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1], 631 true), 632 DEFINE_PROP_END_OF_LIST(), 633 }; 634 635 static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) 636 { 637 DeviceClass *dc = DEVICE_CLASS(oc); 638 639 device_class_set_props(dc, fsl_imx6ul_properties); 640 dc->realize = fsl_imx6ul_realize; 641 dc->desc = "i.MX6UL SOC"; 642 /* Reason: Uses serial_hds and nd_table in realize() directly */ 643 dc->user_creatable = false; 644 } 645 646 static const TypeInfo fsl_imx6ul_type_info = { 647 .name = TYPE_FSL_IMX6UL, 648 .parent = TYPE_DEVICE, 649 .instance_size = sizeof(FslIMX6ULState), 650 .instance_init = fsl_imx6ul_init, 651 .class_init = fsl_imx6ul_class_init, 652 }; 653 654 static void fsl_imx6ul_register_types(void) 655 { 656 type_register_static(&fsl_imx6ul_type_info); 657 } 658 type_init(fsl_imx6ul_register_types) 659