1 /* 2 * ARM Nested Vectored Interrupt Controller 3 * 4 * Copyright (c) 2006-2007 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 * 9 * The ARMv7M System controller is fairly tightly tied in with the 10 * NVIC. Much of that is also implemented here. 11 */ 12 13 #include "hw/sysbus.h" 14 #include "qemu/timer.h" 15 #include "hw/arm/arm.h" 16 #include "exec/address-spaces.h" 17 #include "gic_internal.h" 18 19 typedef struct { 20 GICState gic; 21 struct { 22 uint32_t control; 23 uint32_t reload; 24 int64_t tick; 25 QEMUTimer *timer; 26 } systick; 27 MemoryRegion sysregmem; 28 MemoryRegion gic_iomem_alias; 29 MemoryRegion container; 30 uint32_t num_irq; 31 } nvic_state; 32 33 #define TYPE_NVIC "armv7m_nvic" 34 /** 35 * NVICClass: 36 * @parent_reset: the parent class' reset handler. 37 * 38 * A model of the v7M NVIC and System Controller 39 */ 40 typedef struct NVICClass { 41 /*< private >*/ 42 ARMGICClass parent_class; 43 /*< public >*/ 44 DeviceRealize parent_realize; 45 void (*parent_reset)(DeviceState *dev); 46 } NVICClass; 47 48 #define NVIC_CLASS(klass) \ 49 OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC) 50 #define NVIC_GET_CLASS(obj) \ 51 OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC) 52 #define NVIC(obj) \ 53 OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC) 54 55 static const uint8_t nvic_id[] = { 56 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1 57 }; 58 59 /* qemu timers run at 1GHz. We want something closer to 1MHz. */ 60 #define SYSTICK_SCALE 1000ULL 61 62 #define SYSTICK_ENABLE (1 << 0) 63 #define SYSTICK_TICKINT (1 << 1) 64 #define SYSTICK_CLKSOURCE (1 << 2) 65 #define SYSTICK_COUNTFLAG (1 << 16) 66 67 int system_clock_scale; 68 69 /* Conversion factor from qemu timer to SysTick frequencies. */ 70 static inline int64_t systick_scale(nvic_state *s) 71 { 72 if (s->systick.control & SYSTICK_CLKSOURCE) 73 return system_clock_scale; 74 else 75 return 1000; 76 } 77 78 static void systick_reload(nvic_state *s, int reset) 79 { 80 /* The Cortex-M3 Devices Generic User Guide says that "When the 81 * ENABLE bit is set to 1, the counter loads the RELOAD value from the 82 * SYST RVR register and then counts down". So, we need to check the 83 * ENABLE bit before reloading the value. 84 */ 85 if ((s->systick.control & SYSTICK_ENABLE) == 0) { 86 return; 87 } 88 89 if (reset) 90 s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 91 s->systick.tick += (s->systick.reload + 1) * systick_scale(s); 92 timer_mod(s->systick.timer, s->systick.tick); 93 } 94 95 static void systick_timer_tick(void * opaque) 96 { 97 nvic_state *s = (nvic_state *)opaque; 98 s->systick.control |= SYSTICK_COUNTFLAG; 99 if (s->systick.control & SYSTICK_TICKINT) { 100 /* Trigger the interrupt. */ 101 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK); 102 } 103 if (s->systick.reload == 0) { 104 s->systick.control &= ~SYSTICK_ENABLE; 105 } else { 106 systick_reload(s, 0); 107 } 108 } 109 110 static void systick_reset(nvic_state *s) 111 { 112 s->systick.control = 0; 113 s->systick.reload = 0; 114 s->systick.tick = 0; 115 timer_del(s->systick.timer); 116 } 117 118 /* The external routines use the hardware vector numbering, ie. the first 119 IRQ is #16. The internal GIC routines use #32 as the first IRQ. */ 120 void armv7m_nvic_set_pending(void *opaque, int irq) 121 { 122 nvic_state *s = (nvic_state *)opaque; 123 if (irq >= 16) 124 irq += 16; 125 gic_set_pending_private(&s->gic, 0, irq); 126 } 127 128 /* Make pending IRQ active. */ 129 int armv7m_nvic_acknowledge_irq(void *opaque) 130 { 131 nvic_state *s = (nvic_state *)opaque; 132 uint32_t irq; 133 134 irq = gic_acknowledge_irq(&s->gic, 0, MEMTXATTRS_UNSPECIFIED); 135 if (irq == 1023) 136 hw_error("Interrupt but no vector\n"); 137 if (irq >= 32) 138 irq -= 16; 139 return irq; 140 } 141 142 void armv7m_nvic_complete_irq(void *opaque, int irq) 143 { 144 nvic_state *s = (nvic_state *)opaque; 145 if (irq >= 16) 146 irq += 16; 147 gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED); 148 } 149 150 static uint32_t nvic_readl(nvic_state *s, uint32_t offset) 151 { 152 ARMCPU *cpu; 153 uint32_t val; 154 int irq; 155 156 switch (offset) { 157 case 4: /* Interrupt Control Type. */ 158 return (s->num_irq / 32) - 1; 159 case 0x10: /* SysTick Control and Status. */ 160 val = s->systick.control; 161 s->systick.control &= ~SYSTICK_COUNTFLAG; 162 return val; 163 case 0x14: /* SysTick Reload Value. */ 164 return s->systick.reload; 165 case 0x18: /* SysTick Current Value. */ 166 { 167 int64_t t; 168 if ((s->systick.control & SYSTICK_ENABLE) == 0) 169 return 0; 170 t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 171 if (t >= s->systick.tick) 172 return 0; 173 val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1; 174 /* The interrupt in triggered when the timer reaches zero. 175 However the counter is not reloaded until the next clock 176 tick. This is a hack to return zero during the first tick. */ 177 if (val > s->systick.reload) 178 val = 0; 179 return val; 180 } 181 case 0x1c: /* SysTick Calibration Value. */ 182 return 10000; 183 case 0xd00: /* CPUID Base. */ 184 cpu = ARM_CPU(current_cpu); 185 return cpu->midr; 186 case 0xd04: /* Interrupt Control State. */ 187 /* VECTACTIVE */ 188 val = s->gic.running_irq[0]; 189 if (val == 1023) { 190 val = 0; 191 } else if (val >= 32) { 192 val -= 16; 193 } 194 /* RETTOBASE */ 195 if (s->gic.running_irq[0] == 1023 196 || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) { 197 val |= (1 << 11); 198 } 199 /* VECTPENDING */ 200 if (s->gic.current_pending[0] != 1023) 201 val |= (s->gic.current_pending[0] << 12); 202 /* ISRPENDING */ 203 for (irq = 32; irq < s->num_irq; irq++) { 204 if (s->gic.irq_state[irq].pending) { 205 val |= (1 << 22); 206 break; 207 } 208 } 209 /* PENDSTSET */ 210 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending) 211 val |= (1 << 26); 212 /* PENDSVSET */ 213 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending) 214 val |= (1 << 28); 215 /* NMIPENDSET */ 216 if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending) 217 val |= (1 << 31); 218 return val; 219 case 0xd08: /* Vector Table Offset. */ 220 cpu = ARM_CPU(current_cpu); 221 return cpu->env.v7m.vecbase; 222 case 0xd0c: /* Application Interrupt/Reset Control. */ 223 return 0xfa050000; 224 case 0xd10: /* System Control. */ 225 /* TODO: Implement SLEEPONEXIT. */ 226 return 0; 227 case 0xd14: /* Configuration Control. */ 228 /* TODO: Implement Configuration Control bits. */ 229 return 0; 230 case 0xd24: /* System Handler Status. */ 231 val = 0; 232 if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); 233 if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1); 234 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3); 235 if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7); 236 if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8); 237 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10); 238 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11); 239 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12); 240 if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13); 241 if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14); 242 if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15); 243 if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16); 244 if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17); 245 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18); 246 return val; 247 case 0xd28: /* Configurable Fault Status. */ 248 /* TODO: Implement Fault Status. */ 249 qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n"); 250 return 0; 251 case 0xd2c: /* Hard Fault Status. */ 252 case 0xd30: /* Debug Fault Status. */ 253 case 0xd34: /* Mem Manage Address. */ 254 case 0xd38: /* Bus Fault Address. */ 255 case 0xd3c: /* Aux Fault Status. */ 256 /* TODO: Implement fault status registers. */ 257 qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n"); 258 return 0; 259 case 0xd40: /* PFR0. */ 260 return 0x00000030; 261 case 0xd44: /* PRF1. */ 262 return 0x00000200; 263 case 0xd48: /* DFR0. */ 264 return 0x00100000; 265 case 0xd4c: /* AFR0. */ 266 return 0x00000000; 267 case 0xd50: /* MMFR0. */ 268 return 0x00000030; 269 case 0xd54: /* MMFR1. */ 270 return 0x00000000; 271 case 0xd58: /* MMFR2. */ 272 return 0x00000000; 273 case 0xd5c: /* MMFR3. */ 274 return 0x00000000; 275 case 0xd60: /* ISAR0. */ 276 return 0x01141110; 277 case 0xd64: /* ISAR1. */ 278 return 0x02111000; 279 case 0xd68: /* ISAR2. */ 280 return 0x21112231; 281 case 0xd6c: /* ISAR3. */ 282 return 0x01111110; 283 case 0xd70: /* ISAR4. */ 284 return 0x01310102; 285 /* TODO: Implement debug registers. */ 286 default: 287 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); 288 return 0; 289 } 290 } 291 292 static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) 293 { 294 ARMCPU *cpu; 295 uint32_t oldval; 296 switch (offset) { 297 case 0x10: /* SysTick Control and Status. */ 298 oldval = s->systick.control; 299 s->systick.control &= 0xfffffff8; 300 s->systick.control |= value & 7; 301 if ((oldval ^ value) & SYSTICK_ENABLE) { 302 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 303 if (value & SYSTICK_ENABLE) { 304 if (s->systick.tick) { 305 s->systick.tick += now; 306 timer_mod(s->systick.timer, s->systick.tick); 307 } else { 308 systick_reload(s, 1); 309 } 310 } else { 311 timer_del(s->systick.timer); 312 s->systick.tick -= now; 313 if (s->systick.tick < 0) 314 s->systick.tick = 0; 315 } 316 } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) { 317 /* This is a hack. Force the timer to be reloaded 318 when the reference clock is changed. */ 319 systick_reload(s, 1); 320 } 321 break; 322 case 0x14: /* SysTick Reload Value. */ 323 s->systick.reload = value; 324 break; 325 case 0x18: /* SysTick Current Value. Writes reload the timer. */ 326 systick_reload(s, 1); 327 s->systick.control &= ~SYSTICK_COUNTFLAG; 328 break; 329 case 0xd04: /* Interrupt Control State. */ 330 if (value & (1 << 31)) { 331 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI); 332 } 333 if (value & (1 << 28)) { 334 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV); 335 } else if (value & (1 << 27)) { 336 s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0; 337 gic_update(&s->gic); 338 } 339 if (value & (1 << 26)) { 340 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK); 341 } else if (value & (1 << 25)) { 342 s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0; 343 gic_update(&s->gic); 344 } 345 break; 346 case 0xd08: /* Vector Table Offset. */ 347 cpu = ARM_CPU(current_cpu); 348 cpu->env.v7m.vecbase = value & 0xffffff80; 349 break; 350 case 0xd0c: /* Application Interrupt/Reset Control. */ 351 if ((value >> 16) == 0x05fa) { 352 if (value & 2) { 353 qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n"); 354 } 355 if (value & 5) { 356 qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n"); 357 } 358 if (value & 0x700) { 359 qemu_log_mask(LOG_UNIMP, "PRIGROUP unimplemented\n"); 360 } 361 } 362 break; 363 case 0xd10: /* System Control. */ 364 case 0xd14: /* Configuration Control. */ 365 /* TODO: Implement control registers. */ 366 qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n"); 367 break; 368 case 0xd24: /* System Handler Control. */ 369 /* TODO: Real hardware allows you to set/clear the active bits 370 under some circumstances. We don't implement this. */ 371 s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0; 372 s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0; 373 s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0; 374 break; 375 case 0xd28: /* Configurable Fault Status. */ 376 case 0xd2c: /* Hard Fault Status. */ 377 case 0xd30: /* Debug Fault Status. */ 378 case 0xd34: /* Mem Manage Address. */ 379 case 0xd38: /* Bus Fault Address. */ 380 case 0xd3c: /* Aux Fault Status. */ 381 qemu_log_mask(LOG_UNIMP, 382 "NVIC: fault status registers unimplemented\n"); 383 break; 384 case 0xf00: /* Software Triggered Interrupt Register */ 385 if ((value & 0x1ff) < s->num_irq) { 386 gic_set_pending_private(&s->gic, 0, value & 0x1ff); 387 } 388 break; 389 default: 390 qemu_log_mask(LOG_GUEST_ERROR, 391 "NVIC: Bad write offset 0x%x\n", offset); 392 } 393 } 394 395 static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, 396 unsigned size) 397 { 398 nvic_state *s = (nvic_state *)opaque; 399 uint32_t offset = addr; 400 int i; 401 uint32_t val; 402 403 switch (offset) { 404 case 0xd18 ... 0xd23: /* System Handler Priority. */ 405 val = 0; 406 for (i = 0; i < size; i++) { 407 val |= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8); 408 } 409 return val; 410 case 0xfe0 ... 0xfff: /* ID. */ 411 if (offset & 3) { 412 return 0; 413 } 414 return nvic_id[(offset - 0xfe0) >> 2]; 415 } 416 if (size == 4) { 417 return nvic_readl(s, offset); 418 } 419 qemu_log_mask(LOG_GUEST_ERROR, 420 "NVIC: Bad read of size %d at offset 0x%x\n", size, offset); 421 return 0; 422 } 423 424 static void nvic_sysreg_write(void *opaque, hwaddr addr, 425 uint64_t value, unsigned size) 426 { 427 nvic_state *s = (nvic_state *)opaque; 428 uint32_t offset = addr; 429 int i; 430 431 switch (offset) { 432 case 0xd18 ... 0xd23: /* System Handler Priority. */ 433 for (i = 0; i < size; i++) { 434 s->gic.priority1[(offset - 0xd14) + i][0] = 435 (value >> (i * 8)) & 0xff; 436 } 437 gic_update(&s->gic); 438 return; 439 } 440 if (size == 4) { 441 nvic_writel(s, offset, value); 442 return; 443 } 444 qemu_log_mask(LOG_GUEST_ERROR, 445 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); 446 } 447 448 static const MemoryRegionOps nvic_sysreg_ops = { 449 .read = nvic_sysreg_read, 450 .write = nvic_sysreg_write, 451 .endianness = DEVICE_NATIVE_ENDIAN, 452 }; 453 454 static const VMStateDescription vmstate_nvic = { 455 .name = "armv7m_nvic", 456 .version_id = 1, 457 .minimum_version_id = 1, 458 .fields = (VMStateField[]) { 459 VMSTATE_UINT32(systick.control, nvic_state), 460 VMSTATE_UINT32(systick.reload, nvic_state), 461 VMSTATE_INT64(systick.tick, nvic_state), 462 VMSTATE_TIMER_PTR(systick.timer, nvic_state), 463 VMSTATE_END_OF_LIST() 464 } 465 }; 466 467 static void armv7m_nvic_reset(DeviceState *dev) 468 { 469 nvic_state *s = NVIC(dev); 470 NVICClass *nc = NVIC_GET_CLASS(s); 471 nc->parent_reset(dev); 472 /* Common GIC reset resets to disabled; the NVIC doesn't have 473 * per-CPU interfaces so mark our non-existent CPU interface 474 * as enabled by default, and with a priority mask which allows 475 * all interrupts through. 476 */ 477 s->gic.cpu_ctlr[0] = GICC_CTLR_EN_GRP0; 478 s->gic.priority_mask[0] = 0x100; 479 /* The NVIC as a whole is always enabled. */ 480 s->gic.ctlr = 1; 481 systick_reset(s); 482 } 483 484 static void armv7m_nvic_realize(DeviceState *dev, Error **errp) 485 { 486 nvic_state *s = NVIC(dev); 487 NVICClass *nc = NVIC_GET_CLASS(s); 488 Error *local_err = NULL; 489 490 /* The NVIC always has only one CPU */ 491 s->gic.num_cpu = 1; 492 /* Tell the common code we're an NVIC */ 493 s->gic.revision = 0xffffffff; 494 s->num_irq = s->gic.num_irq; 495 nc->parent_realize(dev, &local_err); 496 if (local_err) { 497 error_propagate(errp, local_err); 498 return; 499 } 500 gic_init_irqs_and_distributor(&s->gic); 501 /* The NVIC and system controller register area looks like this: 502 * 0..0xff : system control registers, including systick 503 * 0x100..0xcff : GIC-like registers 504 * 0xd00..0xfff : system control registers 505 * We use overlaying to put the GIC like registers 506 * over the top of the system control register region. 507 */ 508 memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); 509 /* The system register region goes at the bottom of the priority 510 * stack as it covers the whole page. 511 */ 512 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, 513 "nvic_sysregs", 0x1000); 514 memory_region_add_subregion(&s->container, 0, &s->sysregmem); 515 /* Alias the GIC region so we can get only the section of it 516 * we need, and layer it on top of the system register region. 517 */ 518 memory_region_init_alias(&s->gic_iomem_alias, OBJECT(s), 519 "nvic-gic", &s->gic.iomem, 520 0x100, 0xc00); 521 memory_region_add_subregion_overlap(&s->container, 0x100, 522 &s->gic_iomem_alias, 1); 523 /* Map the whole thing into system memory at the location required 524 * by the v7M architecture. 525 */ 526 memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container); 527 s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s); 528 } 529 530 static void armv7m_nvic_instance_init(Object *obj) 531 { 532 /* We have a different default value for the num-irq property 533 * than our superclass. This function runs after qdev init 534 * has set the defaults from the Property array and before 535 * any user-specified property setting, so just modify the 536 * value in the GICState struct. 537 */ 538 GICState *s = ARM_GIC_COMMON(obj); 539 /* The ARM v7m may have anything from 0 to 496 external interrupt 540 * IRQ lines. We default to 64. Other boards may differ and should 541 * set the num-irq property appropriately. 542 */ 543 s->num_irq = 64; 544 } 545 546 static void armv7m_nvic_class_init(ObjectClass *klass, void *data) 547 { 548 NVICClass *nc = NVIC_CLASS(klass); 549 DeviceClass *dc = DEVICE_CLASS(klass); 550 551 nc->parent_reset = dc->reset; 552 nc->parent_realize = dc->realize; 553 dc->vmsd = &vmstate_nvic; 554 dc->reset = armv7m_nvic_reset; 555 dc->realize = armv7m_nvic_realize; 556 } 557 558 static const TypeInfo armv7m_nvic_info = { 559 .name = TYPE_NVIC, 560 .parent = TYPE_ARM_GIC_COMMON, 561 .instance_init = armv7m_nvic_instance_init, 562 .instance_size = sizeof(nvic_state), 563 .class_init = armv7m_nvic_class_init, 564 .class_size = sizeof(NVICClass), 565 }; 566 567 static void armv7m_nvic_register_types(void) 568 { 569 type_register_static(&armv7m_nvic_info); 570 } 571 572 type_init(armv7m_nvic_register_types) 573