147934d0aSPaolo Bonzini /* 247934d0aSPaolo Bonzini * VT82C686B south bridge support 347934d0aSPaolo Bonzini * 447934d0aSPaolo Bonzini * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 547934d0aSPaolo Bonzini * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 647934d0aSPaolo Bonzini * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 747934d0aSPaolo Bonzini * This code is licensed under the GNU GPL v2. 847934d0aSPaolo Bonzini * 947934d0aSPaolo Bonzini * Contributions after 2012-01-13 are licensed under the terms of the 1047934d0aSPaolo Bonzini * GNU GPL, version 2 or (at your option) any later version. 1147934d0aSPaolo Bonzini */ 1247934d0aSPaolo Bonzini 130430891cSPeter Maydell #include "qemu/osdep.h" 1447934d0aSPaolo Bonzini #include "hw/isa/vt82c686.h" 1547934d0aSPaolo Bonzini #include "hw/i2c/i2c.h" 1647934d0aSPaolo Bonzini #include "hw/pci/pci.h" 17a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 1847934d0aSPaolo Bonzini #include "hw/isa/isa.h" 1998cf824bSPhilippe Mathieu-Daudé #include "hw/isa/superio.h" 2047934d0aSPaolo Bonzini #include "hw/sysbus.h" 21d6454270SMarkus Armbruster #include "migration/vmstate.h" 2247934d0aSPaolo Bonzini #include "hw/mips/mips.h" 2347934d0aSPaolo Bonzini #include "hw/isa/apm.h" 2447934d0aSPaolo Bonzini #include "hw/acpi/acpi.h" 2547934d0aSPaolo Bonzini #include "hw/i2c/pm_smbus.h" 26*9307d06dSMarkus Armbruster #include "qapi/error.h" 270b8fa32fSMarkus Armbruster #include "qemu/module.h" 2847934d0aSPaolo Bonzini #include "qemu/timer.h" 2947934d0aSPaolo Bonzini #include "exec/address-spaces.h" 3047934d0aSPaolo Bonzini 31f3db354cSFilip Bozuta /* #define DEBUG_VT82C686B */ 3247934d0aSPaolo Bonzini 3347934d0aSPaolo Bonzini #ifdef DEBUG_VT82C686B 34a89f364aSAlistair Francis #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) 3547934d0aSPaolo Bonzini #else 3647934d0aSPaolo Bonzini #define DPRINTF(fmt, ...) 3747934d0aSPaolo Bonzini #endif 3847934d0aSPaolo Bonzini 39f3db354cSFilip Bozuta typedef struct SuperIOConfig { 409feb8adeSPaolo Bonzini uint8_t config[0x100]; 4147934d0aSPaolo Bonzini uint8_t index; 4247934d0aSPaolo Bonzini uint8_t data; 4347934d0aSPaolo Bonzini } SuperIOConfig; 4447934d0aSPaolo Bonzini 4547934d0aSPaolo Bonzini typedef struct VT82C686BState { 4647934d0aSPaolo Bonzini PCIDevice dev; 47bcc37e24SJan Kiszka MemoryRegion superio; 4847934d0aSPaolo Bonzini SuperIOConfig superio_conf; 4947934d0aSPaolo Bonzini } VT82C686BState; 5047934d0aSPaolo Bonzini 51417349e6SGonglei #define TYPE_VT82C686B_DEVICE "VT82C686B" 52417349e6SGonglei #define VT82C686B_DEVICE(obj) \ 53417349e6SGonglei OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE) 54417349e6SGonglei 55bcc37e24SJan Kiszka static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, 56bcc37e24SJan Kiszka unsigned size) 5747934d0aSPaolo Bonzini { 5847934d0aSPaolo Bonzini SuperIOConfig *superio_conf = opaque; 5947934d0aSPaolo Bonzini 6047934d0aSPaolo Bonzini DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); 6147934d0aSPaolo Bonzini if (addr == 0x3f0) { 6247934d0aSPaolo Bonzini superio_conf->index = data & 0xff; 6347934d0aSPaolo Bonzini } else { 64b196d969Szhanghailiang bool can_write = true; 6547934d0aSPaolo Bonzini /* 0x3f1 */ 6647934d0aSPaolo Bonzini switch (superio_conf->index) { 6747934d0aSPaolo Bonzini case 0x00 ... 0xdf: 6847934d0aSPaolo Bonzini case 0xe4: 6947934d0aSPaolo Bonzini case 0xe5: 7047934d0aSPaolo Bonzini case 0xe9 ... 0xed: 7147934d0aSPaolo Bonzini case 0xf3: 7247934d0aSPaolo Bonzini case 0xf5: 7347934d0aSPaolo Bonzini case 0xf7: 7447934d0aSPaolo Bonzini case 0xf9 ... 0xfb: 7547934d0aSPaolo Bonzini case 0xfd ... 0xff: 76b196d969Szhanghailiang can_write = false; 7747934d0aSPaolo Bonzini break; 7847934d0aSPaolo Bonzini case 0xe7: 7947934d0aSPaolo Bonzini if ((data & 0xff) != 0xfe) { 80b196d969Szhanghailiang DPRINTF("change uart 1 base. unsupported yet\n"); 81b196d969Szhanghailiang can_write = false; 8247934d0aSPaolo Bonzini } 8347934d0aSPaolo Bonzini break; 8447934d0aSPaolo Bonzini case 0xe8: 8547934d0aSPaolo Bonzini if ((data & 0xff) != 0xbe) { 86b196d969Szhanghailiang DPRINTF("change uart 2 base. unsupported yet\n"); 87b196d969Szhanghailiang can_write = false; 8847934d0aSPaolo Bonzini } 8947934d0aSPaolo Bonzini break; 9047934d0aSPaolo Bonzini default: 91b196d969Szhanghailiang break; 92b196d969Szhanghailiang 93b196d969Szhanghailiang } 94b196d969Szhanghailiang if (can_write) { 9547934d0aSPaolo Bonzini superio_conf->config[superio_conf->index] = data & 0xff; 9647934d0aSPaolo Bonzini } 9747934d0aSPaolo Bonzini } 9847934d0aSPaolo Bonzini } 9947934d0aSPaolo Bonzini 100bcc37e24SJan Kiszka static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) 10147934d0aSPaolo Bonzini { 10247934d0aSPaolo Bonzini SuperIOConfig *superio_conf = opaque; 10347934d0aSPaolo Bonzini 10447934d0aSPaolo Bonzini DPRINTF("superio_ioport_readb address 0x%x\n", addr); 105f3db354cSFilip Bozuta return superio_conf->config[superio_conf->index]; 10647934d0aSPaolo Bonzini } 10747934d0aSPaolo Bonzini 108bcc37e24SJan Kiszka static const MemoryRegionOps superio_ops = { 109bcc37e24SJan Kiszka .read = superio_ioport_readb, 110bcc37e24SJan Kiszka .write = superio_ioport_writeb, 111bcc37e24SJan Kiszka .endianness = DEVICE_NATIVE_ENDIAN, 112bcc37e24SJan Kiszka .impl = { 113bcc37e24SJan Kiszka .min_access_size = 1, 114bcc37e24SJan Kiszka .max_access_size = 1, 115bcc37e24SJan Kiszka }, 116bcc37e24SJan Kiszka }; 117bcc37e24SJan Kiszka 1189dc1a769SPhilippe Mathieu-Daudé static void vt82c686b_isa_reset(DeviceState *dev) 11947934d0aSPaolo Bonzini { 1209dc1a769SPhilippe Mathieu-Daudé VT82C686BState *vt82c = VT82C686B_DEVICE(dev); 1219dc1a769SPhilippe Mathieu-Daudé uint8_t *pci_conf = vt82c->dev.config; 12247934d0aSPaolo Bonzini 12347934d0aSPaolo Bonzini pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 12447934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 12547934d0aSPaolo Bonzini PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 12647934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 12747934d0aSPaolo Bonzini 12847934d0aSPaolo Bonzini pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 12947934d0aSPaolo Bonzini pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 13047934d0aSPaolo Bonzini pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 13147934d0aSPaolo Bonzini pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 13247934d0aSPaolo Bonzini pci_conf[0x59] = 0x04; 13347934d0aSPaolo Bonzini pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 13447934d0aSPaolo Bonzini pci_conf[0x5f] = 0x04; 13547934d0aSPaolo Bonzini pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 13647934d0aSPaolo Bonzini 13747934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe0] = 0x3c; 13847934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe2] = 0x03; 13947934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe3] = 0xfc; 14047934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe6] = 0xde; 14147934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe7] = 0xfe; 14247934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe8] = 0xbe; 14347934d0aSPaolo Bonzini } 14447934d0aSPaolo Bonzini 14547934d0aSPaolo Bonzini /* write config pci function0 registers. PCI-ISA bridge */ 14647934d0aSPaolo Bonzini static void vt82c686b_write_config(PCIDevice *d, uint32_t address, 14747934d0aSPaolo Bonzini uint32_t val, int len) 14847934d0aSPaolo Bonzini { 149417349e6SGonglei VT82C686BState *vt686 = VT82C686B_DEVICE(d); 15047934d0aSPaolo Bonzini 15147934d0aSPaolo Bonzini DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", 15247934d0aSPaolo Bonzini address, val, len); 15347934d0aSPaolo Bonzini 15447934d0aSPaolo Bonzini pci_default_write_config(d, address, val, len); 15547934d0aSPaolo Bonzini if (address == 0x85) { /* enable or disable super IO configure */ 156bcc37e24SJan Kiszka memory_region_set_enabled(&vt686->superio, val & 0x2); 15747934d0aSPaolo Bonzini } 15847934d0aSPaolo Bonzini } 15947934d0aSPaolo Bonzini 16047934d0aSPaolo Bonzini #define ACPI_DBG_IO_ADDR 0xb044 16147934d0aSPaolo Bonzini 16247934d0aSPaolo Bonzini typedef struct VT686PMState { 16347934d0aSPaolo Bonzini PCIDevice dev; 16447934d0aSPaolo Bonzini MemoryRegion io; 16547934d0aSPaolo Bonzini ACPIREGS ar; 16647934d0aSPaolo Bonzini APMState apm; 16747934d0aSPaolo Bonzini PMSMBus smb; 16847934d0aSPaolo Bonzini uint32_t smb_io_base; 16947934d0aSPaolo Bonzini } VT686PMState; 17047934d0aSPaolo Bonzini 17147934d0aSPaolo Bonzini typedef struct VT686AC97State { 17247934d0aSPaolo Bonzini PCIDevice dev; 17347934d0aSPaolo Bonzini } VT686AC97State; 17447934d0aSPaolo Bonzini 17547934d0aSPaolo Bonzini typedef struct VT686MC97State { 17647934d0aSPaolo Bonzini PCIDevice dev; 17747934d0aSPaolo Bonzini } VT686MC97State; 17847934d0aSPaolo Bonzini 179417349e6SGonglei #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM" 180417349e6SGonglei #define VT82C686B_PM_DEVICE(obj) \ 181417349e6SGonglei OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE) 182417349e6SGonglei 183417349e6SGonglei #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97" 184417349e6SGonglei #define VT82C686B_MC97_DEVICE(obj) \ 185417349e6SGonglei OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE) 186417349e6SGonglei 187417349e6SGonglei #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97" 188417349e6SGonglei #define VT82C686B_AC97_DEVICE(obj) \ 189417349e6SGonglei OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE) 190417349e6SGonglei 19147934d0aSPaolo Bonzini static void pm_update_sci(VT686PMState *s) 19247934d0aSPaolo Bonzini { 19347934d0aSPaolo Bonzini int sci_level, pmsts; 19447934d0aSPaolo Bonzini 19547934d0aSPaolo Bonzini pmsts = acpi_pm1_evt_get_sts(&s->ar); 19647934d0aSPaolo Bonzini sci_level = (((pmsts & s->ar.pm1.evt.en) & 19747934d0aSPaolo Bonzini (ACPI_BITMASK_RT_CLOCK_ENABLE | 19847934d0aSPaolo Bonzini ACPI_BITMASK_POWER_BUTTON_ENABLE | 19947934d0aSPaolo Bonzini ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 20047934d0aSPaolo Bonzini ACPI_BITMASK_TIMER_ENABLE)) != 0); 2019e64f8a3SMarcel Apfelbaum pci_set_irq(&s->dev, sci_level); 20247934d0aSPaolo Bonzini /* schedule a timer interruption if needed */ 20347934d0aSPaolo Bonzini acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 20447934d0aSPaolo Bonzini !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 20547934d0aSPaolo Bonzini } 20647934d0aSPaolo Bonzini 20747934d0aSPaolo Bonzini static void pm_tmr_timer(ACPIREGS *ar) 20847934d0aSPaolo Bonzini { 20947934d0aSPaolo Bonzini VT686PMState *s = container_of(ar, VT686PMState, ar); 21047934d0aSPaolo Bonzini pm_update_sci(s); 21147934d0aSPaolo Bonzini } 21247934d0aSPaolo Bonzini 21347934d0aSPaolo Bonzini static void pm_io_space_update(VT686PMState *s) 21447934d0aSPaolo Bonzini { 21547934d0aSPaolo Bonzini uint32_t pm_io_base; 21647934d0aSPaolo Bonzini 21747934d0aSPaolo Bonzini pm_io_base = pci_get_long(s->dev.config + 0x40); 21847934d0aSPaolo Bonzini pm_io_base &= 0xffc0; 21947934d0aSPaolo Bonzini 22047934d0aSPaolo Bonzini memory_region_transaction_begin(); 22147934d0aSPaolo Bonzini memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); 22247934d0aSPaolo Bonzini memory_region_set_address(&s->io, pm_io_base); 22347934d0aSPaolo Bonzini memory_region_transaction_commit(); 22447934d0aSPaolo Bonzini } 22547934d0aSPaolo Bonzini 22647934d0aSPaolo Bonzini static void pm_write_config(PCIDevice *d, 22747934d0aSPaolo Bonzini uint32_t address, uint32_t val, int len) 22847934d0aSPaolo Bonzini { 22947934d0aSPaolo Bonzini DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", 23047934d0aSPaolo Bonzini address, val, len); 23147934d0aSPaolo Bonzini pci_default_write_config(d, address, val, len); 23247934d0aSPaolo Bonzini } 23347934d0aSPaolo Bonzini 23447934d0aSPaolo Bonzini static int vmstate_acpi_post_load(void *opaque, int version_id) 23547934d0aSPaolo Bonzini { 23647934d0aSPaolo Bonzini VT686PMState *s = opaque; 23747934d0aSPaolo Bonzini 23847934d0aSPaolo Bonzini pm_io_space_update(s); 23947934d0aSPaolo Bonzini return 0; 24047934d0aSPaolo Bonzini } 24147934d0aSPaolo Bonzini 24247934d0aSPaolo Bonzini static const VMStateDescription vmstate_acpi = { 24347934d0aSPaolo Bonzini .name = "vt82c686b_pm", 24447934d0aSPaolo Bonzini .version_id = 1, 24547934d0aSPaolo Bonzini .minimum_version_id = 1, 24647934d0aSPaolo Bonzini .post_load = vmstate_acpi_post_load, 24747934d0aSPaolo Bonzini .fields = (VMStateField[]) { 24847934d0aSPaolo Bonzini VMSTATE_PCI_DEVICE(dev, VT686PMState), 24947934d0aSPaolo Bonzini VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), 25047934d0aSPaolo Bonzini VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), 25147934d0aSPaolo Bonzini VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), 25247934d0aSPaolo Bonzini VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), 253e720677eSPaolo Bonzini VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), 25447934d0aSPaolo Bonzini VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), 25547934d0aSPaolo Bonzini VMSTATE_END_OF_LIST() 25647934d0aSPaolo Bonzini } 25747934d0aSPaolo Bonzini }; 25847934d0aSPaolo Bonzini 25947934d0aSPaolo Bonzini /* 26047934d0aSPaolo Bonzini * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() 26147934d0aSPaolo Bonzini * just register a PCI device now, functionalities will be implemented later. 26247934d0aSPaolo Bonzini */ 26347934d0aSPaolo Bonzini 2649af21dbeSMarkus Armbruster static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) 26547934d0aSPaolo Bonzini { 266417349e6SGonglei VT686AC97State *s = VT82C686B_AC97_DEVICE(dev); 26747934d0aSPaolo Bonzini uint8_t *pci_conf = s->dev.config; 26847934d0aSPaolo Bonzini 26947934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 27047934d0aSPaolo Bonzini PCI_COMMAND_PARITY); 27147934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | 27247934d0aSPaolo Bonzini PCI_STATUS_DEVSEL_MEDIUM); 27347934d0aSPaolo Bonzini pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 27447934d0aSPaolo Bonzini } 27547934d0aSPaolo Bonzini 27647934d0aSPaolo Bonzini void vt82c686b_ac97_init(PCIBus *bus, int devfn) 27747934d0aSPaolo Bonzini { 27847934d0aSPaolo Bonzini PCIDevice *dev; 27947934d0aSPaolo Bonzini 280*9307d06dSMarkus Armbruster dev = pci_new(devfn, TYPE_VT82C686B_AC97_DEVICE); 281*9307d06dSMarkus Armbruster pci_realize_and_unref(dev, bus, &error_fatal); 28247934d0aSPaolo Bonzini } 28347934d0aSPaolo Bonzini 28447934d0aSPaolo Bonzini static void via_ac97_class_init(ObjectClass *klass, void *data) 28547934d0aSPaolo Bonzini { 28647934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 28747934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 28847934d0aSPaolo Bonzini 2899af21dbeSMarkus Armbruster k->realize = vt82c686b_ac97_realize; 29047934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 29147934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_AC97; 29247934d0aSPaolo Bonzini k->revision = 0x50; 29347934d0aSPaolo Bonzini k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 294125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 29547934d0aSPaolo Bonzini dc->desc = "AC97"; 29647934d0aSPaolo Bonzini } 29747934d0aSPaolo Bonzini 29847934d0aSPaolo Bonzini static const TypeInfo via_ac97_info = { 299417349e6SGonglei .name = TYPE_VT82C686B_AC97_DEVICE, 30047934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 30147934d0aSPaolo Bonzini .instance_size = sizeof(VT686AC97State), 30247934d0aSPaolo Bonzini .class_init = via_ac97_class_init, 303fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 304fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 305fd3b02c8SEduardo Habkost { }, 306fd3b02c8SEduardo Habkost }, 30747934d0aSPaolo Bonzini }; 30847934d0aSPaolo Bonzini 3099af21dbeSMarkus Armbruster static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) 31047934d0aSPaolo Bonzini { 311417349e6SGonglei VT686MC97State *s = VT82C686B_MC97_DEVICE(dev); 31247934d0aSPaolo Bonzini uint8_t *pci_conf = s->dev.config; 31347934d0aSPaolo Bonzini 31447934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 31547934d0aSPaolo Bonzini PCI_COMMAND_VGA_PALETTE); 31647934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 31747934d0aSPaolo Bonzini pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 31847934d0aSPaolo Bonzini } 31947934d0aSPaolo Bonzini 32047934d0aSPaolo Bonzini void vt82c686b_mc97_init(PCIBus *bus, int devfn) 32147934d0aSPaolo Bonzini { 32247934d0aSPaolo Bonzini PCIDevice *dev; 32347934d0aSPaolo Bonzini 324*9307d06dSMarkus Armbruster dev = pci_new(devfn, TYPE_VT82C686B_MC97_DEVICE); 325*9307d06dSMarkus Armbruster pci_realize_and_unref(dev, bus, &error_fatal); 32647934d0aSPaolo Bonzini } 32747934d0aSPaolo Bonzini 32847934d0aSPaolo Bonzini static void via_mc97_class_init(ObjectClass *klass, void *data) 32947934d0aSPaolo Bonzini { 33047934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 33147934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 33247934d0aSPaolo Bonzini 3339af21dbeSMarkus Armbruster k->realize = vt82c686b_mc97_realize; 33447934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 33547934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_MC97; 33647934d0aSPaolo Bonzini k->class_id = PCI_CLASS_COMMUNICATION_OTHER; 33747934d0aSPaolo Bonzini k->revision = 0x30; 338125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 33947934d0aSPaolo Bonzini dc->desc = "MC97"; 34047934d0aSPaolo Bonzini } 34147934d0aSPaolo Bonzini 34247934d0aSPaolo Bonzini static const TypeInfo via_mc97_info = { 343417349e6SGonglei .name = TYPE_VT82C686B_MC97_DEVICE, 34447934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 34547934d0aSPaolo Bonzini .instance_size = sizeof(VT686MC97State), 34647934d0aSPaolo Bonzini .class_init = via_mc97_class_init, 347fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 348fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 349fd3b02c8SEduardo Habkost { }, 350fd3b02c8SEduardo Habkost }, 35147934d0aSPaolo Bonzini }; 35247934d0aSPaolo Bonzini 35347934d0aSPaolo Bonzini /* vt82c686 pm init */ 3549af21dbeSMarkus Armbruster static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) 35547934d0aSPaolo Bonzini { 356417349e6SGonglei VT686PMState *s = VT82C686B_PM_DEVICE(dev); 35747934d0aSPaolo Bonzini uint8_t *pci_conf; 35847934d0aSPaolo Bonzini 35947934d0aSPaolo Bonzini pci_conf = s->dev.config; 36047934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, 0); 36147934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 36247934d0aSPaolo Bonzini PCI_STATUS_DEVSEL_MEDIUM); 36347934d0aSPaolo Bonzini 36447934d0aSPaolo Bonzini /* 0x48-0x4B is Power Management I/O Base */ 36547934d0aSPaolo Bonzini pci_set_long(pci_conf + 0x48, 0x00000001); 36647934d0aSPaolo Bonzini 36747934d0aSPaolo Bonzini /* SMB ports:0xeee0~0xeeef */ 36847934d0aSPaolo Bonzini s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0); 36947934d0aSPaolo Bonzini pci_conf[0x90] = s->smb_io_base | 1; 37047934d0aSPaolo Bonzini pci_conf[0x91] = s->smb_io_base >> 8; 37147934d0aSPaolo Bonzini pci_conf[0xd2] = 0x90; 372a30c34d2SPhilippe Mathieu-Daudé pm_smbus_init(DEVICE(s), &s->smb, false); 37347934d0aSPaolo Bonzini memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); 37447934d0aSPaolo Bonzini 37547934d0aSPaolo Bonzini apm_init(dev, &s->apm, NULL, s); 37647934d0aSPaolo Bonzini 3771437c94bSPaolo Bonzini memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); 37847934d0aSPaolo Bonzini memory_region_set_enabled(&s->io, false); 37947934d0aSPaolo Bonzini memory_region_add_subregion(get_system_io(), 0, &s->io); 38047934d0aSPaolo Bonzini 38147934d0aSPaolo Bonzini acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 38247934d0aSPaolo Bonzini acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 3839a10bbb4SLaszlo Ersek acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); 38447934d0aSPaolo Bonzini } 38547934d0aSPaolo Bonzini 386a5c82852SAndreas Färber I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 38747934d0aSPaolo Bonzini qemu_irq sci_irq) 38847934d0aSPaolo Bonzini { 38947934d0aSPaolo Bonzini PCIDevice *dev; 39047934d0aSPaolo Bonzini VT686PMState *s; 39147934d0aSPaolo Bonzini 392*9307d06dSMarkus Armbruster dev = pci_new(devfn, TYPE_VT82C686B_PM_DEVICE); 39347934d0aSPaolo Bonzini qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); 39447934d0aSPaolo Bonzini 395417349e6SGonglei s = VT82C686B_PM_DEVICE(dev); 39647934d0aSPaolo Bonzini 397*9307d06dSMarkus Armbruster pci_realize_and_unref(dev, bus, &error_fatal); 39847934d0aSPaolo Bonzini 39947934d0aSPaolo Bonzini return s->smb.smbus; 40047934d0aSPaolo Bonzini } 40147934d0aSPaolo Bonzini 40247934d0aSPaolo Bonzini static Property via_pm_properties[] = { 40347934d0aSPaolo Bonzini DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), 40447934d0aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 40547934d0aSPaolo Bonzini }; 40647934d0aSPaolo Bonzini 40747934d0aSPaolo Bonzini static void via_pm_class_init(ObjectClass *klass, void *data) 40847934d0aSPaolo Bonzini { 40947934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 41047934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 41147934d0aSPaolo Bonzini 4129af21dbeSMarkus Armbruster k->realize = vt82c686b_pm_realize; 41347934d0aSPaolo Bonzini k->config_write = pm_write_config; 41447934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 41547934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_ACPI; 41647934d0aSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_OTHER; 41747934d0aSPaolo Bonzini k->revision = 0x40; 41847934d0aSPaolo Bonzini dc->desc = "PM"; 41947934d0aSPaolo Bonzini dc->vmsd = &vmstate_acpi; 420125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 4214f67d30bSMarc-André Lureau device_class_set_props(dc, via_pm_properties); 42247934d0aSPaolo Bonzini } 42347934d0aSPaolo Bonzini 42447934d0aSPaolo Bonzini static const TypeInfo via_pm_info = { 425417349e6SGonglei .name = TYPE_VT82C686B_PM_DEVICE, 42647934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 42747934d0aSPaolo Bonzini .instance_size = sizeof(VT686PMState), 42847934d0aSPaolo Bonzini .class_init = via_pm_class_init, 429fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 430fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 431fd3b02c8SEduardo Habkost { }, 432fd3b02c8SEduardo Habkost }, 43347934d0aSPaolo Bonzini }; 43447934d0aSPaolo Bonzini 43547934d0aSPaolo Bonzini static const VMStateDescription vmstate_via = { 43647934d0aSPaolo Bonzini .name = "vt82c686b", 43747934d0aSPaolo Bonzini .version_id = 1, 43847934d0aSPaolo Bonzini .minimum_version_id = 1, 43947934d0aSPaolo Bonzini .fields = (VMStateField[]) { 44047934d0aSPaolo Bonzini VMSTATE_PCI_DEVICE(dev, VT82C686BState), 44147934d0aSPaolo Bonzini VMSTATE_END_OF_LIST() 44247934d0aSPaolo Bonzini } 44347934d0aSPaolo Bonzini }; 44447934d0aSPaolo Bonzini 44547934d0aSPaolo Bonzini /* init the PCI-to-ISA bridge */ 4469af21dbeSMarkus Armbruster static void vt82c686b_realize(PCIDevice *d, Error **errp) 44747934d0aSPaolo Bonzini { 448417349e6SGonglei VT82C686BState *vt82c = VT82C686B_DEVICE(d); 44947934d0aSPaolo Bonzini uint8_t *pci_conf; 450bcc37e24SJan Kiszka ISABus *isa_bus; 45147934d0aSPaolo Bonzini uint8_t *wmask; 45247934d0aSPaolo Bonzini int i; 45347934d0aSPaolo Bonzini 454bb2ed009SHervé Poussineau isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), 455d10e5432SMarkus Armbruster pci_address_space_io(d), errp); 456d10e5432SMarkus Armbruster if (!isa_bus) { 457d10e5432SMarkus Armbruster return; 458d10e5432SMarkus Armbruster } 45947934d0aSPaolo Bonzini 46047934d0aSPaolo Bonzini pci_conf = d->config; 46147934d0aSPaolo Bonzini pci_config_set_prog_interface(pci_conf, 0x0); 46247934d0aSPaolo Bonzini 46347934d0aSPaolo Bonzini wmask = d->wmask; 46447934d0aSPaolo Bonzini for (i = 0x00; i < 0xff; i++) { 46547934d0aSPaolo Bonzini if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) { 46647934d0aSPaolo Bonzini wmask[i] = 0x00; 46747934d0aSPaolo Bonzini } 46847934d0aSPaolo Bonzini } 46947934d0aSPaolo Bonzini 470db10ca90SPaolo Bonzini memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, 4712c9b15caSPaolo Bonzini &vt82c->superio_conf, "superio", 2); 472bcc37e24SJan Kiszka memory_region_set_enabled(&vt82c->superio, false); 473f3db354cSFilip Bozuta /* 474f3db354cSFilip Bozuta * The floppy also uses 0x3f0 and 0x3f1. 475f3db354cSFilip Bozuta * But we do not emulate a floppy, so just set it here. 476f3db354cSFilip Bozuta */ 477bcc37e24SJan Kiszka memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 478bcc37e24SJan Kiszka &vt82c->superio); 47947934d0aSPaolo Bonzini } 48047934d0aSPaolo Bonzini 481728d8910SPhilippe Mathieu-Daudé ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) 48247934d0aSPaolo Bonzini { 48347934d0aSPaolo Bonzini PCIDevice *d; 48447934d0aSPaolo Bonzini 485417349e6SGonglei d = pci_create_simple_multifunction(bus, devfn, true, 486417349e6SGonglei TYPE_VT82C686B_DEVICE); 48747934d0aSPaolo Bonzini 4882ae0e48dSAndreas Färber return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); 48947934d0aSPaolo Bonzini } 49047934d0aSPaolo Bonzini 49147934d0aSPaolo Bonzini static void via_class_init(ObjectClass *klass, void *data) 49247934d0aSPaolo Bonzini { 49347934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 49447934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 49547934d0aSPaolo Bonzini 4969af21dbeSMarkus Armbruster k->realize = vt82c686b_realize; 49747934d0aSPaolo Bonzini k->config_write = vt82c686b_write_config; 49847934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 49947934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 50047934d0aSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_ISA; 50147934d0aSPaolo Bonzini k->revision = 0x40; 5029dc1a769SPhilippe Mathieu-Daudé dc->reset = vt82c686b_isa_reset; 50347934d0aSPaolo Bonzini dc->desc = "ISA bridge"; 50447934d0aSPaolo Bonzini dc->vmsd = &vmstate_via; 50504916ee9SMarkus Armbruster /* 50604916ee9SMarkus Armbruster * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 507c3a09ff6SPhilippe Mathieu-Daudé * e.g. by mips_fuloong2e_init() 50804916ee9SMarkus Armbruster */ 509e90f2a8cSEduardo Habkost dc->user_creatable = false; 51047934d0aSPaolo Bonzini } 51147934d0aSPaolo Bonzini 51247934d0aSPaolo Bonzini static const TypeInfo via_info = { 513417349e6SGonglei .name = TYPE_VT82C686B_DEVICE, 51447934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 51547934d0aSPaolo Bonzini .instance_size = sizeof(VT82C686BState), 51647934d0aSPaolo Bonzini .class_init = via_class_init, 517fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 518fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 519fd3b02c8SEduardo Habkost { }, 520fd3b02c8SEduardo Habkost }, 52147934d0aSPaolo Bonzini }; 52247934d0aSPaolo Bonzini 52398cf824bSPhilippe Mathieu-Daudé static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 52498cf824bSPhilippe Mathieu-Daudé { 52598cf824bSPhilippe Mathieu-Daudé ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 52698cf824bSPhilippe Mathieu-Daudé 52798cf824bSPhilippe Mathieu-Daudé sc->serial.count = 2; 52898cf824bSPhilippe Mathieu-Daudé sc->parallel.count = 1; 52998cf824bSPhilippe Mathieu-Daudé sc->ide.count = 0; 53098cf824bSPhilippe Mathieu-Daudé sc->floppy.count = 1; 53198cf824bSPhilippe Mathieu-Daudé } 53298cf824bSPhilippe Mathieu-Daudé 53398cf824bSPhilippe Mathieu-Daudé static const TypeInfo via_superio_info = { 53498cf824bSPhilippe Mathieu-Daudé .name = TYPE_VT82C686B_SUPERIO, 53598cf824bSPhilippe Mathieu-Daudé .parent = TYPE_ISA_SUPERIO, 53698cf824bSPhilippe Mathieu-Daudé .instance_size = sizeof(ISASuperIODevice), 53798cf824bSPhilippe Mathieu-Daudé .class_size = sizeof(ISASuperIOClass), 53898cf824bSPhilippe Mathieu-Daudé .class_init = vt82c686b_superio_class_init, 53998cf824bSPhilippe Mathieu-Daudé }; 54098cf824bSPhilippe Mathieu-Daudé 54147934d0aSPaolo Bonzini static void vt82c686b_register_types(void) 54247934d0aSPaolo Bonzini { 54347934d0aSPaolo Bonzini type_register_static(&via_ac97_info); 54447934d0aSPaolo Bonzini type_register_static(&via_mc97_info); 54547934d0aSPaolo Bonzini type_register_static(&via_pm_info); 54698cf824bSPhilippe Mathieu-Daudé type_register_static(&via_superio_info); 54747934d0aSPaolo Bonzini type_register_static(&via_info); 54847934d0aSPaolo Bonzini } 54947934d0aSPaolo Bonzini 55047934d0aSPaolo Bonzini type_init(vt82c686b_register_types) 551