147934d0aSPaolo Bonzini /* 247934d0aSPaolo Bonzini * VT82C686B south bridge support 347934d0aSPaolo Bonzini * 447934d0aSPaolo Bonzini * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 547934d0aSPaolo Bonzini * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 647934d0aSPaolo Bonzini * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 747934d0aSPaolo Bonzini * This code is licensed under the GNU GPL v2. 847934d0aSPaolo Bonzini * 947934d0aSPaolo Bonzini * Contributions after 2012-01-13 are licensed under the terms of the 1047934d0aSPaolo Bonzini * GNU GPL, version 2 or (at your option) any later version. 1147934d0aSPaolo Bonzini */ 1247934d0aSPaolo Bonzini 130430891cSPeter Maydell #include "qemu/osdep.h" 1447934d0aSPaolo Bonzini #include "hw/hw.h" 1547934d0aSPaolo Bonzini #include "hw/isa/vt82c686.h" 1647934d0aSPaolo Bonzini #include "hw/i2c/i2c.h" 1747934d0aSPaolo Bonzini #include "hw/pci/pci.h" 1847934d0aSPaolo Bonzini #include "hw/isa/isa.h" 1998cf824bSPhilippe Mathieu-Daudé #include "hw/isa/superio.h" 2047934d0aSPaolo Bonzini #include "hw/sysbus.h" 21*d6454270SMarkus Armbruster #include "migration/vmstate.h" 2247934d0aSPaolo Bonzini #include "hw/mips/mips.h" 2347934d0aSPaolo Bonzini #include "hw/isa/apm.h" 2447934d0aSPaolo Bonzini #include "hw/acpi/acpi.h" 2547934d0aSPaolo Bonzini #include "hw/i2c/pm_smbus.h" 2671e8a915SMarkus Armbruster #include "sysemu/reset.h" 2747934d0aSPaolo Bonzini #include "sysemu/sysemu.h" 280b8fa32fSMarkus Armbruster #include "qemu/module.h" 2947934d0aSPaolo Bonzini #include "qemu/timer.h" 3047934d0aSPaolo Bonzini #include "exec/address-spaces.h" 3147934d0aSPaolo Bonzini 3247934d0aSPaolo Bonzini //#define DEBUG_VT82C686B 3347934d0aSPaolo Bonzini 3447934d0aSPaolo Bonzini #ifdef DEBUG_VT82C686B 35a89f364aSAlistair Francis #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) 3647934d0aSPaolo Bonzini #else 3747934d0aSPaolo Bonzini #define DPRINTF(fmt, ...) 3847934d0aSPaolo Bonzini #endif 3947934d0aSPaolo Bonzini 4047934d0aSPaolo Bonzini typedef struct SuperIOConfig 4147934d0aSPaolo Bonzini { 429feb8adeSPaolo Bonzini uint8_t config[0x100]; 4347934d0aSPaolo Bonzini uint8_t index; 4447934d0aSPaolo Bonzini uint8_t data; 4547934d0aSPaolo Bonzini } SuperIOConfig; 4647934d0aSPaolo Bonzini 4747934d0aSPaolo Bonzini typedef struct VT82C686BState { 4847934d0aSPaolo Bonzini PCIDevice dev; 49bcc37e24SJan Kiszka MemoryRegion superio; 5047934d0aSPaolo Bonzini SuperIOConfig superio_conf; 5147934d0aSPaolo Bonzini } VT82C686BState; 5247934d0aSPaolo Bonzini 53417349e6SGonglei #define TYPE_VT82C686B_DEVICE "VT82C686B" 54417349e6SGonglei #define VT82C686B_DEVICE(obj) \ 55417349e6SGonglei OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE) 56417349e6SGonglei 57bcc37e24SJan Kiszka static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, 58bcc37e24SJan Kiszka unsigned size) 5947934d0aSPaolo Bonzini { 6047934d0aSPaolo Bonzini SuperIOConfig *superio_conf = opaque; 6147934d0aSPaolo Bonzini 6247934d0aSPaolo Bonzini DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); 6347934d0aSPaolo Bonzini if (addr == 0x3f0) { 6447934d0aSPaolo Bonzini superio_conf->index = data & 0xff; 6547934d0aSPaolo Bonzini } else { 66b196d969Szhanghailiang bool can_write = true; 6747934d0aSPaolo Bonzini /* 0x3f1 */ 6847934d0aSPaolo Bonzini switch (superio_conf->index) { 6947934d0aSPaolo Bonzini case 0x00 ... 0xdf: 7047934d0aSPaolo Bonzini case 0xe4: 7147934d0aSPaolo Bonzini case 0xe5: 7247934d0aSPaolo Bonzini case 0xe9 ... 0xed: 7347934d0aSPaolo Bonzini case 0xf3: 7447934d0aSPaolo Bonzini case 0xf5: 7547934d0aSPaolo Bonzini case 0xf7: 7647934d0aSPaolo Bonzini case 0xf9 ... 0xfb: 7747934d0aSPaolo Bonzini case 0xfd ... 0xff: 78b196d969Szhanghailiang can_write = false; 7947934d0aSPaolo Bonzini break; 8047934d0aSPaolo Bonzini case 0xe7: 8147934d0aSPaolo Bonzini if ((data & 0xff) != 0xfe) { 82b196d969Szhanghailiang DPRINTF("change uart 1 base. unsupported yet\n"); 83b196d969Szhanghailiang can_write = false; 8447934d0aSPaolo Bonzini } 8547934d0aSPaolo Bonzini break; 8647934d0aSPaolo Bonzini case 0xe8: 8747934d0aSPaolo Bonzini if ((data & 0xff) != 0xbe) { 88b196d969Szhanghailiang DPRINTF("change uart 2 base. unsupported yet\n"); 89b196d969Szhanghailiang can_write = false; 9047934d0aSPaolo Bonzini } 9147934d0aSPaolo Bonzini break; 9247934d0aSPaolo Bonzini default: 93b196d969Szhanghailiang break; 94b196d969Szhanghailiang 95b196d969Szhanghailiang } 96b196d969Szhanghailiang if (can_write) { 9747934d0aSPaolo Bonzini superio_conf->config[superio_conf->index] = data & 0xff; 9847934d0aSPaolo Bonzini } 9947934d0aSPaolo Bonzini } 10047934d0aSPaolo Bonzini } 10147934d0aSPaolo Bonzini 102bcc37e24SJan Kiszka static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) 10347934d0aSPaolo Bonzini { 10447934d0aSPaolo Bonzini SuperIOConfig *superio_conf = opaque; 10547934d0aSPaolo Bonzini 10647934d0aSPaolo Bonzini DPRINTF("superio_ioport_readb address 0x%x\n", addr); 10747934d0aSPaolo Bonzini return (superio_conf->config[superio_conf->index]); 10847934d0aSPaolo Bonzini } 10947934d0aSPaolo Bonzini 110bcc37e24SJan Kiszka static const MemoryRegionOps superio_ops = { 111bcc37e24SJan Kiszka .read = superio_ioport_readb, 112bcc37e24SJan Kiszka .write = superio_ioport_writeb, 113bcc37e24SJan Kiszka .endianness = DEVICE_NATIVE_ENDIAN, 114bcc37e24SJan Kiszka .impl = { 115bcc37e24SJan Kiszka .min_access_size = 1, 116bcc37e24SJan Kiszka .max_access_size = 1, 117bcc37e24SJan Kiszka }, 118bcc37e24SJan Kiszka }; 119bcc37e24SJan Kiszka 12047934d0aSPaolo Bonzini static void vt82c686b_reset(void * opaque) 12147934d0aSPaolo Bonzini { 12247934d0aSPaolo Bonzini PCIDevice *d = opaque; 12347934d0aSPaolo Bonzini uint8_t *pci_conf = d->config; 124417349e6SGonglei VT82C686BState *vt82c = VT82C686B_DEVICE(d); 12547934d0aSPaolo Bonzini 12647934d0aSPaolo Bonzini pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 12747934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 12847934d0aSPaolo Bonzini PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 12947934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 13047934d0aSPaolo Bonzini 13147934d0aSPaolo Bonzini pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 13247934d0aSPaolo Bonzini pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 13347934d0aSPaolo Bonzini pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 13447934d0aSPaolo Bonzini pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 13547934d0aSPaolo Bonzini pci_conf[0x59] = 0x04; 13647934d0aSPaolo Bonzini pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 13747934d0aSPaolo Bonzini pci_conf[0x5f] = 0x04; 13847934d0aSPaolo Bonzini pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 13947934d0aSPaolo Bonzini 14047934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe0] = 0x3c; 14147934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe2] = 0x03; 14247934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe3] = 0xfc; 14347934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe6] = 0xde; 14447934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe7] = 0xfe; 14547934d0aSPaolo Bonzini vt82c->superio_conf.config[0xe8] = 0xbe; 14647934d0aSPaolo Bonzini } 14747934d0aSPaolo Bonzini 14847934d0aSPaolo Bonzini /* write config pci function0 registers. PCI-ISA bridge */ 14947934d0aSPaolo Bonzini static void vt82c686b_write_config(PCIDevice * d, uint32_t address, 15047934d0aSPaolo Bonzini uint32_t val, int len) 15147934d0aSPaolo Bonzini { 152417349e6SGonglei VT82C686BState *vt686 = VT82C686B_DEVICE(d); 15347934d0aSPaolo Bonzini 15447934d0aSPaolo Bonzini DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", 15547934d0aSPaolo Bonzini address, val, len); 15647934d0aSPaolo Bonzini 15747934d0aSPaolo Bonzini pci_default_write_config(d, address, val, len); 15847934d0aSPaolo Bonzini if (address == 0x85) { /* enable or disable super IO configure */ 159bcc37e24SJan Kiszka memory_region_set_enabled(&vt686->superio, val & 0x2); 16047934d0aSPaolo Bonzini } 16147934d0aSPaolo Bonzini } 16247934d0aSPaolo Bonzini 16347934d0aSPaolo Bonzini #define ACPI_DBG_IO_ADDR 0xb044 16447934d0aSPaolo Bonzini 16547934d0aSPaolo Bonzini typedef struct VT686PMState { 16647934d0aSPaolo Bonzini PCIDevice dev; 16747934d0aSPaolo Bonzini MemoryRegion io; 16847934d0aSPaolo Bonzini ACPIREGS ar; 16947934d0aSPaolo Bonzini APMState apm; 17047934d0aSPaolo Bonzini PMSMBus smb; 17147934d0aSPaolo Bonzini uint32_t smb_io_base; 17247934d0aSPaolo Bonzini } VT686PMState; 17347934d0aSPaolo Bonzini 17447934d0aSPaolo Bonzini typedef struct VT686AC97State { 17547934d0aSPaolo Bonzini PCIDevice dev; 17647934d0aSPaolo Bonzini } VT686AC97State; 17747934d0aSPaolo Bonzini 17847934d0aSPaolo Bonzini typedef struct VT686MC97State { 17947934d0aSPaolo Bonzini PCIDevice dev; 18047934d0aSPaolo Bonzini } VT686MC97State; 18147934d0aSPaolo Bonzini 182417349e6SGonglei #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM" 183417349e6SGonglei #define VT82C686B_PM_DEVICE(obj) \ 184417349e6SGonglei OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE) 185417349e6SGonglei 186417349e6SGonglei #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97" 187417349e6SGonglei #define VT82C686B_MC97_DEVICE(obj) \ 188417349e6SGonglei OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE) 189417349e6SGonglei 190417349e6SGonglei #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97" 191417349e6SGonglei #define VT82C686B_AC97_DEVICE(obj) \ 192417349e6SGonglei OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE) 193417349e6SGonglei 19447934d0aSPaolo Bonzini static void pm_update_sci(VT686PMState *s) 19547934d0aSPaolo Bonzini { 19647934d0aSPaolo Bonzini int sci_level, pmsts; 19747934d0aSPaolo Bonzini 19847934d0aSPaolo Bonzini pmsts = acpi_pm1_evt_get_sts(&s->ar); 19947934d0aSPaolo Bonzini sci_level = (((pmsts & s->ar.pm1.evt.en) & 20047934d0aSPaolo Bonzini (ACPI_BITMASK_RT_CLOCK_ENABLE | 20147934d0aSPaolo Bonzini ACPI_BITMASK_POWER_BUTTON_ENABLE | 20247934d0aSPaolo Bonzini ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 20347934d0aSPaolo Bonzini ACPI_BITMASK_TIMER_ENABLE)) != 0); 2049e64f8a3SMarcel Apfelbaum pci_set_irq(&s->dev, sci_level); 20547934d0aSPaolo Bonzini /* schedule a timer interruption if needed */ 20647934d0aSPaolo Bonzini acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 20747934d0aSPaolo Bonzini !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 20847934d0aSPaolo Bonzini } 20947934d0aSPaolo Bonzini 21047934d0aSPaolo Bonzini static void pm_tmr_timer(ACPIREGS *ar) 21147934d0aSPaolo Bonzini { 21247934d0aSPaolo Bonzini VT686PMState *s = container_of(ar, VT686PMState, ar); 21347934d0aSPaolo Bonzini pm_update_sci(s); 21447934d0aSPaolo Bonzini } 21547934d0aSPaolo Bonzini 21647934d0aSPaolo Bonzini static void pm_io_space_update(VT686PMState *s) 21747934d0aSPaolo Bonzini { 21847934d0aSPaolo Bonzini uint32_t pm_io_base; 21947934d0aSPaolo Bonzini 22047934d0aSPaolo Bonzini pm_io_base = pci_get_long(s->dev.config + 0x40); 22147934d0aSPaolo Bonzini pm_io_base &= 0xffc0; 22247934d0aSPaolo Bonzini 22347934d0aSPaolo Bonzini memory_region_transaction_begin(); 22447934d0aSPaolo Bonzini memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); 22547934d0aSPaolo Bonzini memory_region_set_address(&s->io, pm_io_base); 22647934d0aSPaolo Bonzini memory_region_transaction_commit(); 22747934d0aSPaolo Bonzini } 22847934d0aSPaolo Bonzini 22947934d0aSPaolo Bonzini static void pm_write_config(PCIDevice *d, 23047934d0aSPaolo Bonzini uint32_t address, uint32_t val, int len) 23147934d0aSPaolo Bonzini { 23247934d0aSPaolo Bonzini DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", 23347934d0aSPaolo Bonzini address, val, len); 23447934d0aSPaolo Bonzini pci_default_write_config(d, address, val, len); 23547934d0aSPaolo Bonzini } 23647934d0aSPaolo Bonzini 23747934d0aSPaolo Bonzini static int vmstate_acpi_post_load(void *opaque, int version_id) 23847934d0aSPaolo Bonzini { 23947934d0aSPaolo Bonzini VT686PMState *s = opaque; 24047934d0aSPaolo Bonzini 24147934d0aSPaolo Bonzini pm_io_space_update(s); 24247934d0aSPaolo Bonzini return 0; 24347934d0aSPaolo Bonzini } 24447934d0aSPaolo Bonzini 24547934d0aSPaolo Bonzini static const VMStateDescription vmstate_acpi = { 24647934d0aSPaolo Bonzini .name = "vt82c686b_pm", 24747934d0aSPaolo Bonzini .version_id = 1, 24847934d0aSPaolo Bonzini .minimum_version_id = 1, 24947934d0aSPaolo Bonzini .post_load = vmstate_acpi_post_load, 25047934d0aSPaolo Bonzini .fields = (VMStateField[]) { 25147934d0aSPaolo Bonzini VMSTATE_PCI_DEVICE(dev, VT686PMState), 25247934d0aSPaolo Bonzini VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), 25347934d0aSPaolo Bonzini VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), 25447934d0aSPaolo Bonzini VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), 25547934d0aSPaolo Bonzini VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), 256e720677eSPaolo Bonzini VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), 25747934d0aSPaolo Bonzini VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), 25847934d0aSPaolo Bonzini VMSTATE_END_OF_LIST() 25947934d0aSPaolo Bonzini } 26047934d0aSPaolo Bonzini }; 26147934d0aSPaolo Bonzini 26247934d0aSPaolo Bonzini /* 26347934d0aSPaolo Bonzini * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() 26447934d0aSPaolo Bonzini * just register a PCI device now, functionalities will be implemented later. 26547934d0aSPaolo Bonzini */ 26647934d0aSPaolo Bonzini 2679af21dbeSMarkus Armbruster static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) 26847934d0aSPaolo Bonzini { 269417349e6SGonglei VT686AC97State *s = VT82C686B_AC97_DEVICE(dev); 27047934d0aSPaolo Bonzini uint8_t *pci_conf = s->dev.config; 27147934d0aSPaolo Bonzini 27247934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 27347934d0aSPaolo Bonzini PCI_COMMAND_PARITY); 27447934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | 27547934d0aSPaolo Bonzini PCI_STATUS_DEVSEL_MEDIUM); 27647934d0aSPaolo Bonzini pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 27747934d0aSPaolo Bonzini } 27847934d0aSPaolo Bonzini 27947934d0aSPaolo Bonzini void vt82c686b_ac97_init(PCIBus *bus, int devfn) 28047934d0aSPaolo Bonzini { 28147934d0aSPaolo Bonzini PCIDevice *dev; 28247934d0aSPaolo Bonzini 283417349e6SGonglei dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE); 28447934d0aSPaolo Bonzini qdev_init_nofail(&dev->qdev); 28547934d0aSPaolo Bonzini } 28647934d0aSPaolo Bonzini 28747934d0aSPaolo Bonzini static void via_ac97_class_init(ObjectClass *klass, void *data) 28847934d0aSPaolo Bonzini { 28947934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 29047934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 29147934d0aSPaolo Bonzini 2929af21dbeSMarkus Armbruster k->realize = vt82c686b_ac97_realize; 29347934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 29447934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_AC97; 29547934d0aSPaolo Bonzini k->revision = 0x50; 29647934d0aSPaolo Bonzini k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 297125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 29847934d0aSPaolo Bonzini dc->desc = "AC97"; 29947934d0aSPaolo Bonzini } 30047934d0aSPaolo Bonzini 30147934d0aSPaolo Bonzini static const TypeInfo via_ac97_info = { 302417349e6SGonglei .name = TYPE_VT82C686B_AC97_DEVICE, 30347934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 30447934d0aSPaolo Bonzini .instance_size = sizeof(VT686AC97State), 30547934d0aSPaolo Bonzini .class_init = via_ac97_class_init, 306fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 307fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 308fd3b02c8SEduardo Habkost { }, 309fd3b02c8SEduardo Habkost }, 31047934d0aSPaolo Bonzini }; 31147934d0aSPaolo Bonzini 3129af21dbeSMarkus Armbruster static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) 31347934d0aSPaolo Bonzini { 314417349e6SGonglei VT686MC97State *s = VT82C686B_MC97_DEVICE(dev); 31547934d0aSPaolo Bonzini uint8_t *pci_conf = s->dev.config; 31647934d0aSPaolo Bonzini 31747934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 31847934d0aSPaolo Bonzini PCI_COMMAND_VGA_PALETTE); 31947934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 32047934d0aSPaolo Bonzini pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 32147934d0aSPaolo Bonzini } 32247934d0aSPaolo Bonzini 32347934d0aSPaolo Bonzini void vt82c686b_mc97_init(PCIBus *bus, int devfn) 32447934d0aSPaolo Bonzini { 32547934d0aSPaolo Bonzini PCIDevice *dev; 32647934d0aSPaolo Bonzini 327417349e6SGonglei dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE); 32847934d0aSPaolo Bonzini qdev_init_nofail(&dev->qdev); 32947934d0aSPaolo Bonzini } 33047934d0aSPaolo Bonzini 33147934d0aSPaolo Bonzini static void via_mc97_class_init(ObjectClass *klass, void *data) 33247934d0aSPaolo Bonzini { 33347934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 33447934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 33547934d0aSPaolo Bonzini 3369af21dbeSMarkus Armbruster k->realize = vt82c686b_mc97_realize; 33747934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 33847934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_MC97; 33947934d0aSPaolo Bonzini k->class_id = PCI_CLASS_COMMUNICATION_OTHER; 34047934d0aSPaolo Bonzini k->revision = 0x30; 341125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 34247934d0aSPaolo Bonzini dc->desc = "MC97"; 34347934d0aSPaolo Bonzini } 34447934d0aSPaolo Bonzini 34547934d0aSPaolo Bonzini static const TypeInfo via_mc97_info = { 346417349e6SGonglei .name = TYPE_VT82C686B_MC97_DEVICE, 34747934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 34847934d0aSPaolo Bonzini .instance_size = sizeof(VT686MC97State), 34947934d0aSPaolo Bonzini .class_init = via_mc97_class_init, 350fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 351fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 352fd3b02c8SEduardo Habkost { }, 353fd3b02c8SEduardo Habkost }, 35447934d0aSPaolo Bonzini }; 35547934d0aSPaolo Bonzini 35647934d0aSPaolo Bonzini /* vt82c686 pm init */ 3579af21dbeSMarkus Armbruster static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) 35847934d0aSPaolo Bonzini { 359417349e6SGonglei VT686PMState *s = VT82C686B_PM_DEVICE(dev); 36047934d0aSPaolo Bonzini uint8_t *pci_conf; 36147934d0aSPaolo Bonzini 36247934d0aSPaolo Bonzini pci_conf = s->dev.config; 36347934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_COMMAND, 0); 36447934d0aSPaolo Bonzini pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 36547934d0aSPaolo Bonzini PCI_STATUS_DEVSEL_MEDIUM); 36647934d0aSPaolo Bonzini 36747934d0aSPaolo Bonzini /* 0x48-0x4B is Power Management I/O Base */ 36847934d0aSPaolo Bonzini pci_set_long(pci_conf + 0x48, 0x00000001); 36947934d0aSPaolo Bonzini 37047934d0aSPaolo Bonzini /* SMB ports:0xeee0~0xeeef */ 37147934d0aSPaolo Bonzini s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); 37247934d0aSPaolo Bonzini pci_conf[0x90] = s->smb_io_base | 1; 37347934d0aSPaolo Bonzini pci_conf[0x91] = s->smb_io_base >> 8; 37447934d0aSPaolo Bonzini pci_conf[0xd2] = 0x90; 375a30c34d2SPhilippe Mathieu-Daudé pm_smbus_init(DEVICE(s), &s->smb, false); 37647934d0aSPaolo Bonzini memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); 37747934d0aSPaolo Bonzini 37847934d0aSPaolo Bonzini apm_init(dev, &s->apm, NULL, s); 37947934d0aSPaolo Bonzini 3801437c94bSPaolo Bonzini memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); 38147934d0aSPaolo Bonzini memory_region_set_enabled(&s->io, false); 38247934d0aSPaolo Bonzini memory_region_add_subregion(get_system_io(), 0, &s->io); 38347934d0aSPaolo Bonzini 38447934d0aSPaolo Bonzini acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 38547934d0aSPaolo Bonzini acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 3869a10bbb4SLaszlo Ersek acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); 38747934d0aSPaolo Bonzini } 38847934d0aSPaolo Bonzini 389a5c82852SAndreas Färber I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 39047934d0aSPaolo Bonzini qemu_irq sci_irq) 39147934d0aSPaolo Bonzini { 39247934d0aSPaolo Bonzini PCIDevice *dev; 39347934d0aSPaolo Bonzini VT686PMState *s; 39447934d0aSPaolo Bonzini 395417349e6SGonglei dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE); 39647934d0aSPaolo Bonzini qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); 39747934d0aSPaolo Bonzini 398417349e6SGonglei s = VT82C686B_PM_DEVICE(dev); 39947934d0aSPaolo Bonzini 40047934d0aSPaolo Bonzini qdev_init_nofail(&dev->qdev); 40147934d0aSPaolo Bonzini 40247934d0aSPaolo Bonzini return s->smb.smbus; 40347934d0aSPaolo Bonzini } 40447934d0aSPaolo Bonzini 40547934d0aSPaolo Bonzini static Property via_pm_properties[] = { 40647934d0aSPaolo Bonzini DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), 40747934d0aSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 40847934d0aSPaolo Bonzini }; 40947934d0aSPaolo Bonzini 41047934d0aSPaolo Bonzini static void via_pm_class_init(ObjectClass *klass, void *data) 41147934d0aSPaolo Bonzini { 41247934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 41347934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 41447934d0aSPaolo Bonzini 4159af21dbeSMarkus Armbruster k->realize = vt82c686b_pm_realize; 41647934d0aSPaolo Bonzini k->config_write = pm_write_config; 41747934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 41847934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_ACPI; 41947934d0aSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_OTHER; 42047934d0aSPaolo Bonzini k->revision = 0x40; 42147934d0aSPaolo Bonzini dc->desc = "PM"; 42247934d0aSPaolo Bonzini dc->vmsd = &vmstate_acpi; 423125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 42447934d0aSPaolo Bonzini dc->props = via_pm_properties; 42547934d0aSPaolo Bonzini } 42647934d0aSPaolo Bonzini 42747934d0aSPaolo Bonzini static const TypeInfo via_pm_info = { 428417349e6SGonglei .name = TYPE_VT82C686B_PM_DEVICE, 42947934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 43047934d0aSPaolo Bonzini .instance_size = sizeof(VT686PMState), 43147934d0aSPaolo Bonzini .class_init = via_pm_class_init, 432fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 433fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 434fd3b02c8SEduardo Habkost { }, 435fd3b02c8SEduardo Habkost }, 43647934d0aSPaolo Bonzini }; 43747934d0aSPaolo Bonzini 43847934d0aSPaolo Bonzini static const VMStateDescription vmstate_via = { 43947934d0aSPaolo Bonzini .name = "vt82c686b", 44047934d0aSPaolo Bonzini .version_id = 1, 44147934d0aSPaolo Bonzini .minimum_version_id = 1, 44247934d0aSPaolo Bonzini .fields = (VMStateField[]) { 44347934d0aSPaolo Bonzini VMSTATE_PCI_DEVICE(dev, VT82C686BState), 44447934d0aSPaolo Bonzini VMSTATE_END_OF_LIST() 44547934d0aSPaolo Bonzini } 44647934d0aSPaolo Bonzini }; 44747934d0aSPaolo Bonzini 44847934d0aSPaolo Bonzini /* init the PCI-to-ISA bridge */ 4499af21dbeSMarkus Armbruster static void vt82c686b_realize(PCIDevice *d, Error **errp) 45047934d0aSPaolo Bonzini { 451417349e6SGonglei VT82C686BState *vt82c = VT82C686B_DEVICE(d); 45247934d0aSPaolo Bonzini uint8_t *pci_conf; 453bcc37e24SJan Kiszka ISABus *isa_bus; 45447934d0aSPaolo Bonzini uint8_t *wmask; 45547934d0aSPaolo Bonzini int i; 45647934d0aSPaolo Bonzini 457bb2ed009SHervé Poussineau isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), 458d10e5432SMarkus Armbruster pci_address_space_io(d), errp); 459d10e5432SMarkus Armbruster if (!isa_bus) { 460d10e5432SMarkus Armbruster return; 461d10e5432SMarkus Armbruster } 46247934d0aSPaolo Bonzini 46347934d0aSPaolo Bonzini pci_conf = d->config; 46447934d0aSPaolo Bonzini pci_config_set_prog_interface(pci_conf, 0x0); 46547934d0aSPaolo Bonzini 46647934d0aSPaolo Bonzini wmask = d->wmask; 46747934d0aSPaolo Bonzini for (i = 0x00; i < 0xff; i++) { 46847934d0aSPaolo Bonzini if (i<=0x03 || (i>=0x08 && i<=0x3f)) { 46947934d0aSPaolo Bonzini wmask[i] = 0x00; 47047934d0aSPaolo Bonzini } 47147934d0aSPaolo Bonzini } 47247934d0aSPaolo Bonzini 473db10ca90SPaolo Bonzini memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, 4742c9b15caSPaolo Bonzini &vt82c->superio_conf, "superio", 2); 475bcc37e24SJan Kiszka memory_region_set_enabled(&vt82c->superio, false); 476bcc37e24SJan Kiszka /* The floppy also uses 0x3f0 and 0x3f1. 477bcc37e24SJan Kiszka * But we do not emulate a floppy, so just set it here. */ 478bcc37e24SJan Kiszka memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 479bcc37e24SJan Kiszka &vt82c->superio); 480bcc37e24SJan Kiszka 48147934d0aSPaolo Bonzini qemu_register_reset(vt82c686b_reset, d); 48247934d0aSPaolo Bonzini } 48347934d0aSPaolo Bonzini 484728d8910SPhilippe Mathieu-Daudé ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) 48547934d0aSPaolo Bonzini { 48647934d0aSPaolo Bonzini PCIDevice *d; 48747934d0aSPaolo Bonzini 488417349e6SGonglei d = pci_create_simple_multifunction(bus, devfn, true, 489417349e6SGonglei TYPE_VT82C686B_DEVICE); 49047934d0aSPaolo Bonzini 4912ae0e48dSAndreas Färber return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); 49247934d0aSPaolo Bonzini } 49347934d0aSPaolo Bonzini 49447934d0aSPaolo Bonzini static void via_class_init(ObjectClass *klass, void *data) 49547934d0aSPaolo Bonzini { 49647934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 49747934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 49847934d0aSPaolo Bonzini 4999af21dbeSMarkus Armbruster k->realize = vt82c686b_realize; 50047934d0aSPaolo Bonzini k->config_write = vt82c686b_write_config; 50147934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 50247934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 50347934d0aSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_ISA; 50447934d0aSPaolo Bonzini k->revision = 0x40; 50547934d0aSPaolo Bonzini dc->desc = "ISA bridge"; 50647934d0aSPaolo Bonzini dc->vmsd = &vmstate_via; 50704916ee9SMarkus Armbruster /* 50804916ee9SMarkus Armbruster * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 50904916ee9SMarkus Armbruster * e.g. by mips_fulong2e_init() 51004916ee9SMarkus Armbruster */ 511e90f2a8cSEduardo Habkost dc->user_creatable = false; 51247934d0aSPaolo Bonzini } 51347934d0aSPaolo Bonzini 51447934d0aSPaolo Bonzini static const TypeInfo via_info = { 515417349e6SGonglei .name = TYPE_VT82C686B_DEVICE, 51647934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 51747934d0aSPaolo Bonzini .instance_size = sizeof(VT82C686BState), 51847934d0aSPaolo Bonzini .class_init = via_class_init, 519fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 520fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 521fd3b02c8SEduardo Habkost { }, 522fd3b02c8SEduardo Habkost }, 52347934d0aSPaolo Bonzini }; 52447934d0aSPaolo Bonzini 52598cf824bSPhilippe Mathieu-Daudé static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 52698cf824bSPhilippe Mathieu-Daudé { 52798cf824bSPhilippe Mathieu-Daudé ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 52898cf824bSPhilippe Mathieu-Daudé 52998cf824bSPhilippe Mathieu-Daudé sc->serial.count = 2; 53098cf824bSPhilippe Mathieu-Daudé sc->parallel.count = 1; 53198cf824bSPhilippe Mathieu-Daudé sc->ide.count = 0; 53298cf824bSPhilippe Mathieu-Daudé sc->floppy.count = 1; 53398cf824bSPhilippe Mathieu-Daudé } 53498cf824bSPhilippe Mathieu-Daudé 53598cf824bSPhilippe Mathieu-Daudé static const TypeInfo via_superio_info = { 53698cf824bSPhilippe Mathieu-Daudé .name = TYPE_VT82C686B_SUPERIO, 53798cf824bSPhilippe Mathieu-Daudé .parent = TYPE_ISA_SUPERIO, 53898cf824bSPhilippe Mathieu-Daudé .instance_size = sizeof(ISASuperIODevice), 53998cf824bSPhilippe Mathieu-Daudé .class_size = sizeof(ISASuperIOClass), 54098cf824bSPhilippe Mathieu-Daudé .class_init = vt82c686b_superio_class_init, 54198cf824bSPhilippe Mathieu-Daudé }; 54298cf824bSPhilippe Mathieu-Daudé 54347934d0aSPaolo Bonzini static void vt82c686b_register_types(void) 54447934d0aSPaolo Bonzini { 54547934d0aSPaolo Bonzini type_register_static(&via_ac97_info); 54647934d0aSPaolo Bonzini type_register_static(&via_mc97_info); 54747934d0aSPaolo Bonzini type_register_static(&via_pm_info); 54898cf824bSPhilippe Mathieu-Daudé type_register_static(&via_superio_info); 54947934d0aSPaolo Bonzini type_register_static(&via_info); 55047934d0aSPaolo Bonzini } 55147934d0aSPaolo Bonzini 55247934d0aSPaolo Bonzini type_init(vt82c686b_register_types) 553