147934d0aSPaolo Bonzini /* 247934d0aSPaolo Bonzini * VT82C686B south bridge support 347934d0aSPaolo Bonzini * 447934d0aSPaolo Bonzini * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 547934d0aSPaolo Bonzini * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 647934d0aSPaolo Bonzini * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 747934d0aSPaolo Bonzini * This code is licensed under the GNU GPL v2. 847934d0aSPaolo Bonzini * 947934d0aSPaolo Bonzini * Contributions after 2012-01-13 are licensed under the terms of the 1047934d0aSPaolo Bonzini * GNU GPL, version 2 or (at your option) any later version. 1147934d0aSPaolo Bonzini */ 1247934d0aSPaolo Bonzini 130430891cSPeter Maydell #include "qemu/osdep.h" 1447934d0aSPaolo Bonzini #include "hw/isa/vt82c686.h" 1547934d0aSPaolo Bonzini #include "hw/pci/pci.h" 16a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 1747934d0aSPaolo Bonzini #include "hw/isa/isa.h" 1898cf824bSPhilippe Mathieu-Daudé #include "hw/isa/superio.h" 19d6454270SMarkus Armbruster #include "migration/vmstate.h" 2047934d0aSPaolo Bonzini #include "hw/isa/apm.h" 2147934d0aSPaolo Bonzini #include "hw/acpi/acpi.h" 2247934d0aSPaolo Bonzini #include "hw/i2c/pm_smbus.h" 239307d06dSMarkus Armbruster #include "qapi/error.h" 240b8fa32fSMarkus Armbruster #include "qemu/module.h" 25911629e6SBALATON Zoltan #include "qemu/range.h" 2647934d0aSPaolo Bonzini #include "qemu/timer.h" 2747934d0aSPaolo Bonzini #include "exec/address-spaces.h" 28ff413a1fSBALATON Zoltan #include "trace.h" 2947934d0aSPaolo Bonzini 30*e1a69736SBALATON Zoltan #define TYPE_VIA_PM "via-pm" 31*e1a69736SBALATON Zoltan OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) 3247934d0aSPaolo Bonzini 33*e1a69736SBALATON Zoltan struct ViaPMState { 3447934d0aSPaolo Bonzini PCIDevice dev; 3547934d0aSPaolo Bonzini MemoryRegion io; 3647934d0aSPaolo Bonzini ACPIREGS ar; 3747934d0aSPaolo Bonzini APMState apm; 3847934d0aSPaolo Bonzini PMSMBus smb; 39db1015e9SEduardo Habkost }; 4047934d0aSPaolo Bonzini 41*e1a69736SBALATON Zoltan static void pm_io_space_update(ViaPMState *s) 4247934d0aSPaolo Bonzini { 433ab1eea6SBALATON Zoltan uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; 4447934d0aSPaolo Bonzini 4547934d0aSPaolo Bonzini memory_region_transaction_begin(); 463ab1eea6SBALATON Zoltan memory_region_set_address(&s->io, pmbase); 473ab1eea6SBALATON Zoltan memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); 4847934d0aSPaolo Bonzini memory_region_transaction_commit(); 4947934d0aSPaolo Bonzini } 5047934d0aSPaolo Bonzini 51*e1a69736SBALATON Zoltan static void smb_io_space_update(ViaPMState *s) 52911629e6SBALATON Zoltan { 53911629e6SBALATON Zoltan uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; 54911629e6SBALATON Zoltan 55911629e6SBALATON Zoltan memory_region_transaction_begin(); 56911629e6SBALATON Zoltan memory_region_set_address(&s->smb.io, smbase); 57911629e6SBALATON Zoltan memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); 58911629e6SBALATON Zoltan memory_region_transaction_commit(); 59911629e6SBALATON Zoltan } 60911629e6SBALATON Zoltan 6147934d0aSPaolo Bonzini static int vmstate_acpi_post_load(void *opaque, int version_id) 6247934d0aSPaolo Bonzini { 63*e1a69736SBALATON Zoltan ViaPMState *s = opaque; 6447934d0aSPaolo Bonzini 6547934d0aSPaolo Bonzini pm_io_space_update(s); 66911629e6SBALATON Zoltan smb_io_space_update(s); 6747934d0aSPaolo Bonzini return 0; 6847934d0aSPaolo Bonzini } 6947934d0aSPaolo Bonzini 7047934d0aSPaolo Bonzini static const VMStateDescription vmstate_acpi = { 7147934d0aSPaolo Bonzini .name = "vt82c686b_pm", 7247934d0aSPaolo Bonzini .version_id = 1, 7347934d0aSPaolo Bonzini .minimum_version_id = 1, 7447934d0aSPaolo Bonzini .post_load = vmstate_acpi_post_load, 7547934d0aSPaolo Bonzini .fields = (VMStateField[]) { 76*e1a69736SBALATON Zoltan VMSTATE_PCI_DEVICE(dev, ViaPMState), 77*e1a69736SBALATON Zoltan VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), 78*e1a69736SBALATON Zoltan VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), 79*e1a69736SBALATON Zoltan VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), 80*e1a69736SBALATON Zoltan VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), 81*e1a69736SBALATON Zoltan VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), 82*e1a69736SBALATON Zoltan VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), 8347934d0aSPaolo Bonzini VMSTATE_END_OF_LIST() 8447934d0aSPaolo Bonzini } 8547934d0aSPaolo Bonzini }; 8647934d0aSPaolo Bonzini 8794349bffSBALATON Zoltan static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) 8894349bffSBALATON Zoltan { 89*e1a69736SBALATON Zoltan ViaPMState *s = VIA_PM(d); 90911629e6SBALATON Zoltan 9194349bffSBALATON Zoltan trace_via_pm_write(addr, val, len); 9294349bffSBALATON Zoltan pci_default_write_config(d, addr, val, len); 933ab1eea6SBALATON Zoltan if (ranges_overlap(addr, len, 0x48, 4)) { 943ab1eea6SBALATON Zoltan uint32_t v = pci_get_long(s->dev.config + 0x48); 953ab1eea6SBALATON Zoltan pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); 963ab1eea6SBALATON Zoltan } 973ab1eea6SBALATON Zoltan if (range_covers_byte(addr, len, 0x41)) { 983ab1eea6SBALATON Zoltan pm_io_space_update(s); 993ab1eea6SBALATON Zoltan } 100911629e6SBALATON Zoltan if (ranges_overlap(addr, len, 0x90, 4)) { 101911629e6SBALATON Zoltan uint32_t v = pci_get_long(s->dev.config + 0x90); 102911629e6SBALATON Zoltan pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); 103911629e6SBALATON Zoltan } 104911629e6SBALATON Zoltan if (range_covers_byte(addr, len, 0xd2)) { 105911629e6SBALATON Zoltan s->dev.config[0xd2] &= 0xf; 106911629e6SBALATON Zoltan smb_io_space_update(s); 107911629e6SBALATON Zoltan } 10894349bffSBALATON Zoltan } 10994349bffSBALATON Zoltan 11035e360edSBALATON Zoltan static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) 11135e360edSBALATON Zoltan { 11235e360edSBALATON Zoltan trace_via_pm_io_write(addr, data, size); 11335e360edSBALATON Zoltan } 11435e360edSBALATON Zoltan 11535e360edSBALATON Zoltan static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) 11635e360edSBALATON Zoltan { 11735e360edSBALATON Zoltan trace_via_pm_io_read(addr, 0, size); 11835e360edSBALATON Zoltan return 0; 11935e360edSBALATON Zoltan } 12035e360edSBALATON Zoltan 12135e360edSBALATON Zoltan static const MemoryRegionOps pm_io_ops = { 12235e360edSBALATON Zoltan .read = pm_io_read, 12335e360edSBALATON Zoltan .write = pm_io_write, 12435e360edSBALATON Zoltan .endianness = DEVICE_NATIVE_ENDIAN, 12535e360edSBALATON Zoltan .impl = { 12635e360edSBALATON Zoltan .min_access_size = 1, 12735e360edSBALATON Zoltan .max_access_size = 1, 12835e360edSBALATON Zoltan }, 12935e360edSBALATON Zoltan }; 13035e360edSBALATON Zoltan 131*e1a69736SBALATON Zoltan static void pm_update_sci(ViaPMState *s) 13294349bffSBALATON Zoltan { 13394349bffSBALATON Zoltan int sci_level, pmsts; 13494349bffSBALATON Zoltan 13594349bffSBALATON Zoltan pmsts = acpi_pm1_evt_get_sts(&s->ar); 13694349bffSBALATON Zoltan sci_level = (((pmsts & s->ar.pm1.evt.en) & 13794349bffSBALATON Zoltan (ACPI_BITMASK_RT_CLOCK_ENABLE | 13894349bffSBALATON Zoltan ACPI_BITMASK_POWER_BUTTON_ENABLE | 13994349bffSBALATON Zoltan ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 14094349bffSBALATON Zoltan ACPI_BITMASK_TIMER_ENABLE)) != 0); 14194349bffSBALATON Zoltan pci_set_irq(&s->dev, sci_level); 14294349bffSBALATON Zoltan /* schedule a timer interruption if needed */ 14394349bffSBALATON Zoltan acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 14494349bffSBALATON Zoltan !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 14594349bffSBALATON Zoltan } 14694349bffSBALATON Zoltan 14794349bffSBALATON Zoltan static void pm_tmr_timer(ACPIREGS *ar) 14894349bffSBALATON Zoltan { 149*e1a69736SBALATON Zoltan ViaPMState *s = container_of(ar, ViaPMState, ar); 15094349bffSBALATON Zoltan pm_update_sci(s); 15194349bffSBALATON Zoltan } 15294349bffSBALATON Zoltan 153*e1a69736SBALATON Zoltan static void via_pm_reset(DeviceState *d) 154911629e6SBALATON Zoltan { 155*e1a69736SBALATON Zoltan ViaPMState *s = VIA_PM(d); 156911629e6SBALATON Zoltan 1579af8e529SBALATON Zoltan memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, 1589af8e529SBALATON Zoltan PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); 1599af8e529SBALATON Zoltan /* Power Management IO base */ 1609af8e529SBALATON Zoltan pci_set_long(s->dev.config + 0x48, 1); 161911629e6SBALATON Zoltan /* SMBus IO base */ 162911629e6SBALATON Zoltan pci_set_long(s->dev.config + 0x90, 1); 163911629e6SBALATON Zoltan 1643ab1eea6SBALATON Zoltan pm_io_space_update(s); 165911629e6SBALATON Zoltan smb_io_space_update(s); 166911629e6SBALATON Zoltan } 167911629e6SBALATON Zoltan 168*e1a69736SBALATON Zoltan static void via_pm_realize(PCIDevice *dev, Error **errp) 16947934d0aSPaolo Bonzini { 170*e1a69736SBALATON Zoltan ViaPMState *s = VIA_PM(dev); 17147934d0aSPaolo Bonzini 1723ab1eea6SBALATON Zoltan pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | 17347934d0aSPaolo Bonzini PCI_STATUS_DEVSEL_MEDIUM); 17447934d0aSPaolo Bonzini 175a30c34d2SPhilippe Mathieu-Daudé pm_smbus_init(DEVICE(s), &s->smb, false); 176911629e6SBALATON Zoltan memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); 177911629e6SBALATON Zoltan memory_region_set_enabled(&s->smb.io, false); 17847934d0aSPaolo Bonzini 17947934d0aSPaolo Bonzini apm_init(dev, &s->apm, NULL, s); 18047934d0aSPaolo Bonzini 181*e1a69736SBALATON Zoltan memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); 18235e360edSBALATON Zoltan memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); 18347934d0aSPaolo Bonzini memory_region_set_enabled(&s->io, false); 18447934d0aSPaolo Bonzini 18547934d0aSPaolo Bonzini acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 18647934d0aSPaolo Bonzini acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 1879a10bbb4SLaszlo Ersek acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); 18847934d0aSPaolo Bonzini } 18947934d0aSPaolo Bonzini 190*e1a69736SBALATON Zoltan typedef struct via_pm_init_info { 191*e1a69736SBALATON Zoltan uint16_t device_id; 192*e1a69736SBALATON Zoltan } ViaPMInitInfo; 193*e1a69736SBALATON Zoltan 19447934d0aSPaolo Bonzini static void via_pm_class_init(ObjectClass *klass, void *data) 19547934d0aSPaolo Bonzini { 19647934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 19747934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 198*e1a69736SBALATON Zoltan ViaPMInitInfo *info = data; 19947934d0aSPaolo Bonzini 200*e1a69736SBALATON Zoltan k->realize = via_pm_realize; 20147934d0aSPaolo Bonzini k->config_write = pm_write_config; 20247934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 203*e1a69736SBALATON Zoltan k->device_id = info->device_id; 20447934d0aSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_OTHER; 20547934d0aSPaolo Bonzini k->revision = 0x40; 206*e1a69736SBALATON Zoltan dc->reset = via_pm_reset; 207084bf4b4SBALATON Zoltan /* Reason: part of VIA south bridge, does not exist stand alone */ 208084bf4b4SBALATON Zoltan dc->user_creatable = false; 20947934d0aSPaolo Bonzini dc->vmsd = &vmstate_acpi; 21047934d0aSPaolo Bonzini } 21147934d0aSPaolo Bonzini 21247934d0aSPaolo Bonzini static const TypeInfo via_pm_info = { 213*e1a69736SBALATON Zoltan .name = TYPE_VIA_PM, 21447934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 215*e1a69736SBALATON Zoltan .instance_size = sizeof(ViaPMState), 216*e1a69736SBALATON Zoltan .abstract = true, 217fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 218fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 219fd3b02c8SEduardo Habkost { }, 220fd3b02c8SEduardo Habkost }, 22147934d0aSPaolo Bonzini }; 22247934d0aSPaolo Bonzini 223*e1a69736SBALATON Zoltan static const ViaPMInitInfo vt82c686b_pm_init_info = { 224*e1a69736SBALATON Zoltan .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, 225*e1a69736SBALATON Zoltan }; 226*e1a69736SBALATON Zoltan 227*e1a69736SBALATON Zoltan static const TypeInfo vt82c686b_pm_info = { 228*e1a69736SBALATON Zoltan .name = TYPE_VT82C686B_PM, 229*e1a69736SBALATON Zoltan .parent = TYPE_VIA_PM, 230*e1a69736SBALATON Zoltan .class_init = via_pm_class_init, 231*e1a69736SBALATON Zoltan .class_data = (void *)&vt82c686b_pm_init_info, 232*e1a69736SBALATON Zoltan }; 233*e1a69736SBALATON Zoltan 234*e1a69736SBALATON Zoltan static const ViaPMInitInfo vt8231_pm_init_info = { 235*e1a69736SBALATON Zoltan .device_id = PCI_DEVICE_ID_VIA_8231_PM, 236*e1a69736SBALATON Zoltan }; 237*e1a69736SBALATON Zoltan 238*e1a69736SBALATON Zoltan static const TypeInfo vt8231_pm_info = { 239*e1a69736SBALATON Zoltan .name = TYPE_VT8231_PM, 240*e1a69736SBALATON Zoltan .parent = TYPE_VIA_PM, 241*e1a69736SBALATON Zoltan .class_init = via_pm_class_init, 242*e1a69736SBALATON Zoltan .class_data = (void *)&vt8231_pm_init_info, 243*e1a69736SBALATON Zoltan }; 244*e1a69736SBALATON Zoltan 24594349bffSBALATON Zoltan 24694349bffSBALATON Zoltan typedef struct SuperIOConfig { 24794349bffSBALATON Zoltan uint8_t regs[0x100]; 24894349bffSBALATON Zoltan uint8_t index; 24994349bffSBALATON Zoltan MemoryRegion io; 25094349bffSBALATON Zoltan } SuperIOConfig; 25194349bffSBALATON Zoltan 25294349bffSBALATON Zoltan static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, 25394349bffSBALATON Zoltan unsigned size) 25494349bffSBALATON Zoltan { 25594349bffSBALATON Zoltan SuperIOConfig *sc = opaque; 25694349bffSBALATON Zoltan 25794349bffSBALATON Zoltan if (addr == 0x3f0) { /* config index register */ 25894349bffSBALATON Zoltan sc->index = data & 0xff; 25994349bffSBALATON Zoltan } else { 26094349bffSBALATON Zoltan bool can_write = true; 26194349bffSBALATON Zoltan /* 0x3f1, config data register */ 26294349bffSBALATON Zoltan trace_via_superio_write(sc->index, data & 0xff); 26394349bffSBALATON Zoltan switch (sc->index) { 26494349bffSBALATON Zoltan case 0x00 ... 0xdf: 26594349bffSBALATON Zoltan case 0xe4: 26694349bffSBALATON Zoltan case 0xe5: 26794349bffSBALATON Zoltan case 0xe9 ... 0xed: 26894349bffSBALATON Zoltan case 0xf3: 26994349bffSBALATON Zoltan case 0xf5: 27094349bffSBALATON Zoltan case 0xf7: 27194349bffSBALATON Zoltan case 0xf9 ... 0xfb: 27294349bffSBALATON Zoltan case 0xfd ... 0xff: 27394349bffSBALATON Zoltan can_write = false; 27494349bffSBALATON Zoltan break; 27594349bffSBALATON Zoltan /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ 27694349bffSBALATON Zoltan default: 27794349bffSBALATON Zoltan break; 27894349bffSBALATON Zoltan 27994349bffSBALATON Zoltan } 28094349bffSBALATON Zoltan if (can_write) { 28194349bffSBALATON Zoltan sc->regs[sc->index] = data & 0xff; 28294349bffSBALATON Zoltan } 28394349bffSBALATON Zoltan } 28494349bffSBALATON Zoltan } 28594349bffSBALATON Zoltan 28694349bffSBALATON Zoltan static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) 28794349bffSBALATON Zoltan { 28894349bffSBALATON Zoltan SuperIOConfig *sc = opaque; 28994349bffSBALATON Zoltan uint8_t val = sc->regs[sc->index]; 29094349bffSBALATON Zoltan 29194349bffSBALATON Zoltan trace_via_superio_read(sc->index, val); 29294349bffSBALATON Zoltan return val; 29394349bffSBALATON Zoltan } 29494349bffSBALATON Zoltan 29594349bffSBALATON Zoltan static const MemoryRegionOps superio_cfg_ops = { 29694349bffSBALATON Zoltan .read = superio_cfg_read, 29794349bffSBALATON Zoltan .write = superio_cfg_write, 29894349bffSBALATON Zoltan .endianness = DEVICE_NATIVE_ENDIAN, 29994349bffSBALATON Zoltan .impl = { 30094349bffSBALATON Zoltan .min_access_size = 1, 30194349bffSBALATON Zoltan .max_access_size = 1, 30294349bffSBALATON Zoltan }, 30394349bffSBALATON Zoltan }; 30494349bffSBALATON Zoltan 30594349bffSBALATON Zoltan 30694349bffSBALATON Zoltan OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) 30794349bffSBALATON Zoltan 30894349bffSBALATON Zoltan struct VT82C686BISAState { 30994349bffSBALATON Zoltan PCIDevice dev; 31094349bffSBALATON Zoltan SuperIOConfig superio_cfg; 31194349bffSBALATON Zoltan }; 31294349bffSBALATON Zoltan 31394349bffSBALATON Zoltan static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, 31494349bffSBALATON Zoltan uint32_t val, int len) 31594349bffSBALATON Zoltan { 31694349bffSBALATON Zoltan VT82C686BISAState *s = VT82C686B_ISA(d); 31794349bffSBALATON Zoltan 31894349bffSBALATON Zoltan trace_via_isa_write(addr, val, len); 31994349bffSBALATON Zoltan pci_default_write_config(d, addr, val, len); 32094349bffSBALATON Zoltan if (addr == 0x85) { 32194349bffSBALATON Zoltan /* BIT(1): enable or disable superio config io ports */ 32294349bffSBALATON Zoltan memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); 32394349bffSBALATON Zoltan } 32494349bffSBALATON Zoltan } 32594349bffSBALATON Zoltan 32647934d0aSPaolo Bonzini static const VMStateDescription vmstate_via = { 32747934d0aSPaolo Bonzini .name = "vt82c686b", 32847934d0aSPaolo Bonzini .version_id = 1, 32947934d0aSPaolo Bonzini .minimum_version_id = 1, 33047934d0aSPaolo Bonzini .fields = (VMStateField[]) { 3310f798461SBALATON Zoltan VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), 33247934d0aSPaolo Bonzini VMSTATE_END_OF_LIST() 33347934d0aSPaolo Bonzini } 33447934d0aSPaolo Bonzini }; 33547934d0aSPaolo Bonzini 33694349bffSBALATON Zoltan static void vt82c686b_isa_reset(DeviceState *dev) 33794349bffSBALATON Zoltan { 33894349bffSBALATON Zoltan VT82C686BISAState *s = VT82C686B_ISA(dev); 33994349bffSBALATON Zoltan uint8_t *pci_conf = s->dev.config; 34094349bffSBALATON Zoltan 34194349bffSBALATON Zoltan pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 34294349bffSBALATON Zoltan pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 34394349bffSBALATON Zoltan PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 34494349bffSBALATON Zoltan pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 34594349bffSBALATON Zoltan 34694349bffSBALATON Zoltan pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 34794349bffSBALATON Zoltan pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 34894349bffSBALATON Zoltan pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 34994349bffSBALATON Zoltan pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 35094349bffSBALATON Zoltan pci_conf[0x59] = 0x04; 35194349bffSBALATON Zoltan pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 35294349bffSBALATON Zoltan pci_conf[0x5f] = 0x04; 35394349bffSBALATON Zoltan pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 35494349bffSBALATON Zoltan 35594349bffSBALATON Zoltan s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */ 35694349bffSBALATON Zoltan s->superio_cfg.regs[0xe2] = 0x03; /* Function select */ 35794349bffSBALATON Zoltan s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */ 35894349bffSBALATON Zoltan s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */ 35994349bffSBALATON Zoltan s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */ 36094349bffSBALATON Zoltan s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */ 36194349bffSBALATON Zoltan } 36294349bffSBALATON Zoltan 3639af21dbeSMarkus Armbruster static void vt82c686b_realize(PCIDevice *d, Error **errp) 36447934d0aSPaolo Bonzini { 365007b3103SBALATON Zoltan VT82C686BISAState *s = VT82C686B_ISA(d); 36647934d0aSPaolo Bonzini uint8_t *pci_conf; 367bcc37e24SJan Kiszka ISABus *isa_bus; 36847934d0aSPaolo Bonzini uint8_t *wmask; 36947934d0aSPaolo Bonzini int i; 37047934d0aSPaolo Bonzini 371bb2ed009SHervé Poussineau isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), 372d10e5432SMarkus Armbruster pci_address_space_io(d), errp); 373d10e5432SMarkus Armbruster if (!isa_bus) { 374d10e5432SMarkus Armbruster return; 375d10e5432SMarkus Armbruster } 37647934d0aSPaolo Bonzini 37747934d0aSPaolo Bonzini pci_conf = d->config; 37847934d0aSPaolo Bonzini pci_config_set_prog_interface(pci_conf, 0x0); 37947934d0aSPaolo Bonzini 38047934d0aSPaolo Bonzini wmask = d->wmask; 38147934d0aSPaolo Bonzini for (i = 0x00; i < 0xff; i++) { 38247934d0aSPaolo Bonzini if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) { 38347934d0aSPaolo Bonzini wmask[i] = 0x00; 38447934d0aSPaolo Bonzini } 38547934d0aSPaolo Bonzini } 38647934d0aSPaolo Bonzini 3876be6e4bcSBALATON Zoltan memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, 3886be6e4bcSBALATON Zoltan &s->superio_cfg, "superio_cfg", 2); 3896be6e4bcSBALATON Zoltan memory_region_set_enabled(&s->superio_cfg.io, false); 390f3db354cSFilip Bozuta /* 391f3db354cSFilip Bozuta * The floppy also uses 0x3f0 and 0x3f1. 392f3db354cSFilip Bozuta * But we do not emulate a floppy, so just set it here. 393f3db354cSFilip Bozuta */ 394bcc37e24SJan Kiszka memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 3956be6e4bcSBALATON Zoltan &s->superio_cfg.io); 39647934d0aSPaolo Bonzini } 39747934d0aSPaolo Bonzini 39847934d0aSPaolo Bonzini static void via_class_init(ObjectClass *klass, void *data) 39947934d0aSPaolo Bonzini { 40047934d0aSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 40147934d0aSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 40247934d0aSPaolo Bonzini 4039af21dbeSMarkus Armbruster k->realize = vt82c686b_realize; 40447934d0aSPaolo Bonzini k->config_write = vt82c686b_write_config; 40547934d0aSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_VIA; 40647934d0aSPaolo Bonzini k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 40747934d0aSPaolo Bonzini k->class_id = PCI_CLASS_BRIDGE_ISA; 40847934d0aSPaolo Bonzini k->revision = 0x40; 4099dc1a769SPhilippe Mathieu-Daudé dc->reset = vt82c686b_isa_reset; 41047934d0aSPaolo Bonzini dc->desc = "ISA bridge"; 41147934d0aSPaolo Bonzini dc->vmsd = &vmstate_via; 41204916ee9SMarkus Armbruster /* 41304916ee9SMarkus Armbruster * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 414c3a09ff6SPhilippe Mathieu-Daudé * e.g. by mips_fuloong2e_init() 41504916ee9SMarkus Armbruster */ 416e90f2a8cSEduardo Habkost dc->user_creatable = false; 41747934d0aSPaolo Bonzini } 41847934d0aSPaolo Bonzini 41947934d0aSPaolo Bonzini static const TypeInfo via_info = { 4200f798461SBALATON Zoltan .name = TYPE_VT82C686B_ISA, 42147934d0aSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 4220f798461SBALATON Zoltan .instance_size = sizeof(VT82C686BISAState), 42347934d0aSPaolo Bonzini .class_init = via_class_init, 424fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 425fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 426fd3b02c8SEduardo Habkost { }, 427fd3b02c8SEduardo Habkost }, 42847934d0aSPaolo Bonzini }; 42947934d0aSPaolo Bonzini 43094349bffSBALATON Zoltan 43198cf824bSPhilippe Mathieu-Daudé static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 43298cf824bSPhilippe Mathieu-Daudé { 43398cf824bSPhilippe Mathieu-Daudé ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 43498cf824bSPhilippe Mathieu-Daudé 43598cf824bSPhilippe Mathieu-Daudé sc->serial.count = 2; 43698cf824bSPhilippe Mathieu-Daudé sc->parallel.count = 1; 43798cf824bSPhilippe Mathieu-Daudé sc->ide.count = 0; 43898cf824bSPhilippe Mathieu-Daudé sc->floppy.count = 1; 43998cf824bSPhilippe Mathieu-Daudé } 44098cf824bSPhilippe Mathieu-Daudé 44198cf824bSPhilippe Mathieu-Daudé static const TypeInfo via_superio_info = { 44298cf824bSPhilippe Mathieu-Daudé .name = TYPE_VT82C686B_SUPERIO, 44398cf824bSPhilippe Mathieu-Daudé .parent = TYPE_ISA_SUPERIO, 44498cf824bSPhilippe Mathieu-Daudé .instance_size = sizeof(ISASuperIODevice), 44598cf824bSPhilippe Mathieu-Daudé .class_size = sizeof(ISASuperIOClass), 44698cf824bSPhilippe Mathieu-Daudé .class_init = vt82c686b_superio_class_init, 44798cf824bSPhilippe Mathieu-Daudé }; 44898cf824bSPhilippe Mathieu-Daudé 44994349bffSBALATON Zoltan 45047934d0aSPaolo Bonzini static void vt82c686b_register_types(void) 45147934d0aSPaolo Bonzini { 45247934d0aSPaolo Bonzini type_register_static(&via_pm_info); 453*e1a69736SBALATON Zoltan type_register_static(&vt82c686b_pm_info); 454*e1a69736SBALATON Zoltan type_register_static(&vt8231_pm_info); 45547934d0aSPaolo Bonzini type_register_static(&via_info); 45694349bffSBALATON Zoltan type_register_static(&via_superio_info); 45747934d0aSPaolo Bonzini } 45847934d0aSPaolo Bonzini 45947934d0aSPaolo Bonzini type_init(vt82c686b_register_types) 460