1 /* 2 * VT82C686B south bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/isa/vt82c686.h" 15 #include "hw/pci/pci.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/isa/isa.h" 18 #include "hw/isa/superio.h" 19 #include "migration/vmstate.h" 20 #include "hw/isa/apm.h" 21 #include "hw/acpi/acpi.h" 22 #include "hw/i2c/pm_smbus.h" 23 #include "qapi/error.h" 24 #include "qemu/module.h" 25 #include "qemu/timer.h" 26 #include "exec/address-spaces.h" 27 #include "trace.h" 28 29 typedef struct SuperIOConfig { 30 uint8_t regs[0x100]; 31 uint8_t index; 32 uint8_t data; 33 } SuperIOConfig; 34 35 struct VT82C686BISAState { 36 PCIDevice dev; 37 MemoryRegion superio; 38 SuperIOConfig superio_cfg; 39 }; 40 41 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) 42 43 static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, 44 unsigned size) 45 { 46 SuperIOConfig *sc = opaque; 47 48 if (addr == 0x3f0) { /* config index register */ 49 sc->index = data & 0xff; 50 } else { 51 bool can_write = true; 52 /* 0x3f1, config data register */ 53 trace_via_superio_write(sc->index, data & 0xff); 54 switch (sc->index) { 55 case 0x00 ... 0xdf: 56 case 0xe4: 57 case 0xe5: 58 case 0xe9 ... 0xed: 59 case 0xf3: 60 case 0xf5: 61 case 0xf7: 62 case 0xf9 ... 0xfb: 63 case 0xfd ... 0xff: 64 can_write = false; 65 break; 66 /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ 67 default: 68 break; 69 70 } 71 if (can_write) { 72 sc->regs[sc->index] = data & 0xff; 73 } 74 } 75 } 76 77 static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) 78 { 79 SuperIOConfig *sc = opaque; 80 uint8_t val = sc->regs[sc->index]; 81 82 trace_via_superio_read(sc->index, val); 83 return val; 84 } 85 86 static const MemoryRegionOps superio_cfg_ops = { 87 .read = superio_cfg_read, 88 .write = superio_cfg_write, 89 .endianness = DEVICE_NATIVE_ENDIAN, 90 .impl = { 91 .min_access_size = 1, 92 .max_access_size = 1, 93 }, 94 }; 95 96 static void vt82c686b_isa_reset(DeviceState *dev) 97 { 98 VT82C686BISAState *s = VT82C686B_ISA(dev); 99 uint8_t *pci_conf = s->dev.config; 100 101 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 102 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 103 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 104 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 105 106 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 107 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 108 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 109 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 110 pci_conf[0x59] = 0x04; 111 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 112 pci_conf[0x5f] = 0x04; 113 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 114 115 s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */ 116 s->superio_cfg.regs[0xe2] = 0x03; /* Function select */ 117 s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */ 118 s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */ 119 s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */ 120 s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */ 121 } 122 123 /* write config pci function0 registers. PCI-ISA bridge */ 124 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, 125 uint32_t val, int len) 126 { 127 VT82C686BISAState *s = VT82C686B_ISA(d); 128 129 trace_via_isa_write(addr, val, len); 130 pci_default_write_config(d, addr, val, len); 131 if (addr == 0x85) { /* enable or disable super IO configure */ 132 memory_region_set_enabled(&s->superio, val & 0x2); 133 } 134 } 135 136 struct VT686PMState { 137 PCIDevice dev; 138 MemoryRegion io; 139 ACPIREGS ar; 140 APMState apm; 141 PMSMBus smb; 142 uint32_t smb_io_base; 143 }; 144 145 OBJECT_DECLARE_SIMPLE_TYPE(VT686PMState, VT82C686B_PM) 146 147 static void pm_update_sci(VT686PMState *s) 148 { 149 int sci_level, pmsts; 150 151 pmsts = acpi_pm1_evt_get_sts(&s->ar); 152 sci_level = (((pmsts & s->ar.pm1.evt.en) & 153 (ACPI_BITMASK_RT_CLOCK_ENABLE | 154 ACPI_BITMASK_POWER_BUTTON_ENABLE | 155 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 156 ACPI_BITMASK_TIMER_ENABLE)) != 0); 157 pci_set_irq(&s->dev, sci_level); 158 /* schedule a timer interruption if needed */ 159 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 160 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 161 } 162 163 static void pm_tmr_timer(ACPIREGS *ar) 164 { 165 VT686PMState *s = container_of(ar, VT686PMState, ar); 166 pm_update_sci(s); 167 } 168 169 static void pm_io_space_update(VT686PMState *s) 170 { 171 uint32_t pm_io_base; 172 173 pm_io_base = pci_get_long(s->dev.config + 0x40); 174 pm_io_base &= 0xffc0; 175 176 memory_region_transaction_begin(); 177 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); 178 memory_region_set_address(&s->io, pm_io_base); 179 memory_region_transaction_commit(); 180 } 181 182 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) 183 { 184 trace_via_pm_write(addr, val, len); 185 pci_default_write_config(d, addr, val, len); 186 } 187 188 static int vmstate_acpi_post_load(void *opaque, int version_id) 189 { 190 VT686PMState *s = opaque; 191 192 pm_io_space_update(s); 193 return 0; 194 } 195 196 static const VMStateDescription vmstate_acpi = { 197 .name = "vt82c686b_pm", 198 .version_id = 1, 199 .minimum_version_id = 1, 200 .post_load = vmstate_acpi_post_load, 201 .fields = (VMStateField[]) { 202 VMSTATE_PCI_DEVICE(dev, VT686PMState), 203 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), 204 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), 205 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), 206 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), 207 VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), 208 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), 209 VMSTATE_END_OF_LIST() 210 } 211 }; 212 213 /* vt82c686 pm init */ 214 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) 215 { 216 VT686PMState *s = VT82C686B_PM(dev); 217 uint8_t *pci_conf; 218 219 pci_conf = s->dev.config; 220 pci_set_word(pci_conf + PCI_COMMAND, 0); 221 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 222 PCI_STATUS_DEVSEL_MEDIUM); 223 224 /* 0x48-0x4B is Power Management I/O Base */ 225 pci_set_long(pci_conf + 0x48, 0x00000001); 226 227 /* SMB ports:0xeee0~0xeeef */ 228 s->smb_io_base = ((s->smb_io_base & 0xfff0) + 0x0); 229 pci_conf[0x90] = s->smb_io_base | 1; 230 pci_conf[0x91] = s->smb_io_base >> 8; 231 pci_conf[0xd2] = 0x90; 232 pm_smbus_init(DEVICE(s), &s->smb, false); 233 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); 234 235 apm_init(dev, &s->apm, NULL, s); 236 237 memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); 238 memory_region_set_enabled(&s->io, false); 239 memory_region_add_subregion(get_system_io(), 0, &s->io); 240 241 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 242 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 243 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); 244 } 245 246 static Property via_pm_properties[] = { 247 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), 248 DEFINE_PROP_END_OF_LIST(), 249 }; 250 251 static void via_pm_class_init(ObjectClass *klass, void *data) 252 { 253 DeviceClass *dc = DEVICE_CLASS(klass); 254 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 255 256 k->realize = vt82c686b_pm_realize; 257 k->config_write = pm_write_config; 258 k->vendor_id = PCI_VENDOR_ID_VIA; 259 k->device_id = PCI_DEVICE_ID_VIA_ACPI; 260 k->class_id = PCI_CLASS_BRIDGE_OTHER; 261 k->revision = 0x40; 262 dc->desc = "PM"; 263 dc->vmsd = &vmstate_acpi; 264 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 265 device_class_set_props(dc, via_pm_properties); 266 } 267 268 static const TypeInfo via_pm_info = { 269 .name = TYPE_VT82C686B_PM, 270 .parent = TYPE_PCI_DEVICE, 271 .instance_size = sizeof(VT686PMState), 272 .class_init = via_pm_class_init, 273 .interfaces = (InterfaceInfo[]) { 274 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 275 { }, 276 }, 277 }; 278 279 static const VMStateDescription vmstate_via = { 280 .name = "vt82c686b", 281 .version_id = 1, 282 .minimum_version_id = 1, 283 .fields = (VMStateField[]) { 284 VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), 285 VMSTATE_END_OF_LIST() 286 } 287 }; 288 289 /* init the PCI-to-ISA bridge */ 290 static void vt82c686b_realize(PCIDevice *d, Error **errp) 291 { 292 VT82C686BISAState *s = VT82C686B_ISA(d); 293 uint8_t *pci_conf; 294 ISABus *isa_bus; 295 uint8_t *wmask; 296 int i; 297 298 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), 299 pci_address_space_io(d), errp); 300 if (!isa_bus) { 301 return; 302 } 303 304 pci_conf = d->config; 305 pci_config_set_prog_interface(pci_conf, 0x0); 306 307 wmask = d->wmask; 308 for (i = 0x00; i < 0xff; i++) { 309 if (i <= 0x03 || (i >= 0x08 && i <= 0x3f)) { 310 wmask[i] = 0x00; 311 } 312 } 313 314 memory_region_init_io(&s->superio, OBJECT(d), &superio_cfg_ops, 315 &s->superio_cfg, "superio", 2); 316 memory_region_set_enabled(&s->superio, false); 317 /* 318 * The floppy also uses 0x3f0 and 0x3f1. 319 * But we do not emulate a floppy, so just set it here. 320 */ 321 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 322 &s->superio); 323 } 324 325 static void via_class_init(ObjectClass *klass, void *data) 326 { 327 DeviceClass *dc = DEVICE_CLASS(klass); 328 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 329 330 k->realize = vt82c686b_realize; 331 k->config_write = vt82c686b_write_config; 332 k->vendor_id = PCI_VENDOR_ID_VIA; 333 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 334 k->class_id = PCI_CLASS_BRIDGE_ISA; 335 k->revision = 0x40; 336 dc->reset = vt82c686b_isa_reset; 337 dc->desc = "ISA bridge"; 338 dc->vmsd = &vmstate_via; 339 /* 340 * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 341 * e.g. by mips_fuloong2e_init() 342 */ 343 dc->user_creatable = false; 344 } 345 346 static const TypeInfo via_info = { 347 .name = TYPE_VT82C686B_ISA, 348 .parent = TYPE_PCI_DEVICE, 349 .instance_size = sizeof(VT82C686BISAState), 350 .class_init = via_class_init, 351 .interfaces = (InterfaceInfo[]) { 352 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 353 { }, 354 }, 355 }; 356 357 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 358 { 359 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 360 361 sc->serial.count = 2; 362 sc->parallel.count = 1; 363 sc->ide.count = 0; 364 sc->floppy.count = 1; 365 } 366 367 static const TypeInfo via_superio_info = { 368 .name = TYPE_VT82C686B_SUPERIO, 369 .parent = TYPE_ISA_SUPERIO, 370 .instance_size = sizeof(ISASuperIODevice), 371 .class_size = sizeof(ISASuperIOClass), 372 .class_init = vt82c686b_superio_class_init, 373 }; 374 375 static void vt82c686b_register_types(void) 376 { 377 type_register_static(&via_pm_info); 378 type_register_static(&via_superio_info); 379 type_register_static(&via_info); 380 } 381 382 type_init(vt82c686b_register_types) 383