1 /* 2 * VT82C686B south bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "hw/hw.h" 14 #include "hw/i386/pc.h" 15 #include "hw/isa/vt82c686.h" 16 #include "hw/i2c/i2c.h" 17 #include "hw/i2c/smbus.h" 18 #include "hw/pci/pci.h" 19 #include "hw/isa/isa.h" 20 #include "hw/sysbus.h" 21 #include "hw/mips/mips.h" 22 #include "hw/isa/apm.h" 23 #include "hw/acpi/acpi.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/timer.h" 27 #include "exec/address-spaces.h" 28 29 //#define DEBUG_VT82C686B 30 31 #ifdef DEBUG_VT82C686B 32 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) 33 #else 34 #define DPRINTF(fmt, ...) 35 #endif 36 37 typedef struct SuperIOConfig 38 { 39 uint8_t config[0x100]; 40 uint8_t index; 41 uint8_t data; 42 } SuperIOConfig; 43 44 typedef struct VT82C686BState { 45 PCIDevice dev; 46 MemoryRegion superio; 47 SuperIOConfig superio_conf; 48 } VT82C686BState; 49 50 static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, 51 unsigned size) 52 { 53 SuperIOConfig *superio_conf = opaque; 54 55 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); 56 if (addr == 0x3f0) { 57 superio_conf->index = data & 0xff; 58 } else { 59 bool can_write = true; 60 /* 0x3f1 */ 61 switch (superio_conf->index) { 62 case 0x00 ... 0xdf: 63 case 0xe4: 64 case 0xe5: 65 case 0xe9 ... 0xed: 66 case 0xf3: 67 case 0xf5: 68 case 0xf7: 69 case 0xf9 ... 0xfb: 70 case 0xfd ... 0xff: 71 can_write = false; 72 break; 73 case 0xe7: 74 if ((data & 0xff) != 0xfe) { 75 DPRINTF("change uart 1 base. unsupported yet\n"); 76 can_write = false; 77 } 78 break; 79 case 0xe8: 80 if ((data & 0xff) != 0xbe) { 81 DPRINTF("change uart 2 base. unsupported yet\n"); 82 can_write = false; 83 } 84 break; 85 default: 86 break; 87 88 } 89 if (can_write) { 90 superio_conf->config[superio_conf->index] = data & 0xff; 91 } 92 } 93 } 94 95 static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) 96 { 97 SuperIOConfig *superio_conf = opaque; 98 99 DPRINTF("superio_ioport_readb address 0x%x\n", addr); 100 return (superio_conf->config[superio_conf->index]); 101 } 102 103 static const MemoryRegionOps superio_ops = { 104 .read = superio_ioport_readb, 105 .write = superio_ioport_writeb, 106 .endianness = DEVICE_NATIVE_ENDIAN, 107 .impl = { 108 .min_access_size = 1, 109 .max_access_size = 1, 110 }, 111 }; 112 113 static void vt82c686b_reset(void * opaque) 114 { 115 PCIDevice *d = opaque; 116 uint8_t *pci_conf = d->config; 117 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); 118 119 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 120 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 121 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 122 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 123 124 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 125 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 126 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 127 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 128 pci_conf[0x59] = 0x04; 129 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 130 pci_conf[0x5f] = 0x04; 131 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 132 133 vt82c->superio_conf.config[0xe0] = 0x3c; 134 vt82c->superio_conf.config[0xe2] = 0x03; 135 vt82c->superio_conf.config[0xe3] = 0xfc; 136 vt82c->superio_conf.config[0xe6] = 0xde; 137 vt82c->superio_conf.config[0xe7] = 0xfe; 138 vt82c->superio_conf.config[0xe8] = 0xbe; 139 } 140 141 /* write config pci function0 registers. PCI-ISA bridge */ 142 static void vt82c686b_write_config(PCIDevice * d, uint32_t address, 143 uint32_t val, int len) 144 { 145 VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); 146 147 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", 148 address, val, len); 149 150 pci_default_write_config(d, address, val, len); 151 if (address == 0x85) { /* enable or disable super IO configure */ 152 memory_region_set_enabled(&vt686->superio, val & 0x2); 153 } 154 } 155 156 #define ACPI_DBG_IO_ADDR 0xb044 157 158 typedef struct VT686PMState { 159 PCIDevice dev; 160 MemoryRegion io; 161 ACPIREGS ar; 162 APMState apm; 163 PMSMBus smb; 164 uint32_t smb_io_base; 165 } VT686PMState; 166 167 typedef struct VT686AC97State { 168 PCIDevice dev; 169 } VT686AC97State; 170 171 typedef struct VT686MC97State { 172 PCIDevice dev; 173 } VT686MC97State; 174 175 static void pm_update_sci(VT686PMState *s) 176 { 177 int sci_level, pmsts; 178 179 pmsts = acpi_pm1_evt_get_sts(&s->ar); 180 sci_level = (((pmsts & s->ar.pm1.evt.en) & 181 (ACPI_BITMASK_RT_CLOCK_ENABLE | 182 ACPI_BITMASK_POWER_BUTTON_ENABLE | 183 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 184 ACPI_BITMASK_TIMER_ENABLE)) != 0); 185 pci_set_irq(&s->dev, sci_level); 186 /* schedule a timer interruption if needed */ 187 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 188 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 189 } 190 191 static void pm_tmr_timer(ACPIREGS *ar) 192 { 193 VT686PMState *s = container_of(ar, VT686PMState, ar); 194 pm_update_sci(s); 195 } 196 197 static void pm_io_space_update(VT686PMState *s) 198 { 199 uint32_t pm_io_base; 200 201 pm_io_base = pci_get_long(s->dev.config + 0x40); 202 pm_io_base &= 0xffc0; 203 204 memory_region_transaction_begin(); 205 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); 206 memory_region_set_address(&s->io, pm_io_base); 207 memory_region_transaction_commit(); 208 } 209 210 static void pm_write_config(PCIDevice *d, 211 uint32_t address, uint32_t val, int len) 212 { 213 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", 214 address, val, len); 215 pci_default_write_config(d, address, val, len); 216 } 217 218 static int vmstate_acpi_post_load(void *opaque, int version_id) 219 { 220 VT686PMState *s = opaque; 221 222 pm_io_space_update(s); 223 return 0; 224 } 225 226 static const VMStateDescription vmstate_acpi = { 227 .name = "vt82c686b_pm", 228 .version_id = 1, 229 .minimum_version_id = 1, 230 .post_load = vmstate_acpi_post_load, 231 .fields = (VMStateField[]) { 232 VMSTATE_PCI_DEVICE(dev, VT686PMState), 233 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), 234 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), 235 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), 236 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), 237 VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), 238 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), 239 VMSTATE_END_OF_LIST() 240 } 241 }; 242 243 /* 244 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() 245 * just register a PCI device now, functionalities will be implemented later. 246 */ 247 248 static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) 249 { 250 VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); 251 uint8_t *pci_conf = s->dev.config; 252 253 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 254 PCI_COMMAND_PARITY); 255 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | 256 PCI_STATUS_DEVSEL_MEDIUM); 257 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 258 } 259 260 void vt82c686b_ac97_init(PCIBus *bus, int devfn) 261 { 262 PCIDevice *dev; 263 264 dev = pci_create(bus, devfn, "VT82C686B_AC97"); 265 qdev_init_nofail(&dev->qdev); 266 } 267 268 static void via_ac97_class_init(ObjectClass *klass, void *data) 269 { 270 DeviceClass *dc = DEVICE_CLASS(klass); 271 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 272 273 k->realize = vt82c686b_ac97_realize; 274 k->vendor_id = PCI_VENDOR_ID_VIA; 275 k->device_id = PCI_DEVICE_ID_VIA_AC97; 276 k->revision = 0x50; 277 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 278 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 279 dc->desc = "AC97"; 280 } 281 282 static const TypeInfo via_ac97_info = { 283 .name = "VT82C686B_AC97", 284 .parent = TYPE_PCI_DEVICE, 285 .instance_size = sizeof(VT686AC97State), 286 .class_init = via_ac97_class_init, 287 }; 288 289 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) 290 { 291 VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); 292 uint8_t *pci_conf = s->dev.config; 293 294 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 295 PCI_COMMAND_VGA_PALETTE); 296 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 297 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 298 } 299 300 void vt82c686b_mc97_init(PCIBus *bus, int devfn) 301 { 302 PCIDevice *dev; 303 304 dev = pci_create(bus, devfn, "VT82C686B_MC97"); 305 qdev_init_nofail(&dev->qdev); 306 } 307 308 static void via_mc97_class_init(ObjectClass *klass, void *data) 309 { 310 DeviceClass *dc = DEVICE_CLASS(klass); 311 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 312 313 k->realize = vt82c686b_mc97_realize; 314 k->vendor_id = PCI_VENDOR_ID_VIA; 315 k->device_id = PCI_DEVICE_ID_VIA_MC97; 316 k->class_id = PCI_CLASS_COMMUNICATION_OTHER; 317 k->revision = 0x30; 318 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 319 dc->desc = "MC97"; 320 } 321 322 static const TypeInfo via_mc97_info = { 323 .name = "VT82C686B_MC97", 324 .parent = TYPE_PCI_DEVICE, 325 .instance_size = sizeof(VT686MC97State), 326 .class_init = via_mc97_class_init, 327 }; 328 329 /* vt82c686 pm init */ 330 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) 331 { 332 VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); 333 uint8_t *pci_conf; 334 335 pci_conf = s->dev.config; 336 pci_set_word(pci_conf + PCI_COMMAND, 0); 337 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 338 PCI_STATUS_DEVSEL_MEDIUM); 339 340 /* 0x48-0x4B is Power Management I/O Base */ 341 pci_set_long(pci_conf + 0x48, 0x00000001); 342 343 /* SMB ports:0xeee0~0xeeef */ 344 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); 345 pci_conf[0x90] = s->smb_io_base | 1; 346 pci_conf[0x91] = s->smb_io_base >> 8; 347 pci_conf[0xd2] = 0x90; 348 pm_smbus_init(&s->dev.qdev, &s->smb); 349 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); 350 351 apm_init(dev, &s->apm, NULL, s); 352 353 memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); 354 memory_region_set_enabled(&s->io, false); 355 memory_region_add_subregion(get_system_io(), 0, &s->io); 356 357 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 358 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 359 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); 360 } 361 362 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 363 qemu_irq sci_irq) 364 { 365 PCIDevice *dev; 366 VT686PMState *s; 367 368 dev = pci_create(bus, devfn, "VT82C686B_PM"); 369 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); 370 371 s = DO_UPCAST(VT686PMState, dev, dev); 372 373 qdev_init_nofail(&dev->qdev); 374 375 return s->smb.smbus; 376 } 377 378 static Property via_pm_properties[] = { 379 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), 380 DEFINE_PROP_END_OF_LIST(), 381 }; 382 383 static void via_pm_class_init(ObjectClass *klass, void *data) 384 { 385 DeviceClass *dc = DEVICE_CLASS(klass); 386 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 387 388 k->realize = vt82c686b_pm_realize; 389 k->config_write = pm_write_config; 390 k->vendor_id = PCI_VENDOR_ID_VIA; 391 k->device_id = PCI_DEVICE_ID_VIA_ACPI; 392 k->class_id = PCI_CLASS_BRIDGE_OTHER; 393 k->revision = 0x40; 394 dc->desc = "PM"; 395 dc->vmsd = &vmstate_acpi; 396 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 397 dc->props = via_pm_properties; 398 } 399 400 static const TypeInfo via_pm_info = { 401 .name = "VT82C686B_PM", 402 .parent = TYPE_PCI_DEVICE, 403 .instance_size = sizeof(VT686PMState), 404 .class_init = via_pm_class_init, 405 }; 406 407 static const VMStateDescription vmstate_via = { 408 .name = "vt82c686b", 409 .version_id = 1, 410 .minimum_version_id = 1, 411 .fields = (VMStateField[]) { 412 VMSTATE_PCI_DEVICE(dev, VT82C686BState), 413 VMSTATE_END_OF_LIST() 414 } 415 }; 416 417 /* init the PCI-to-ISA bridge */ 418 static void vt82c686b_realize(PCIDevice *d, Error **errp) 419 { 420 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); 421 uint8_t *pci_conf; 422 ISABus *isa_bus; 423 uint8_t *wmask; 424 int i; 425 426 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), 427 pci_address_space_io(d)); 428 429 pci_conf = d->config; 430 pci_config_set_prog_interface(pci_conf, 0x0); 431 432 wmask = d->wmask; 433 for (i = 0x00; i < 0xff; i++) { 434 if (i<=0x03 || (i>=0x08 && i<=0x3f)) { 435 wmask[i] = 0x00; 436 } 437 } 438 439 memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, 440 &vt82c->superio_conf, "superio", 2); 441 memory_region_set_enabled(&vt82c->superio, false); 442 /* The floppy also uses 0x3f0 and 0x3f1. 443 * But we do not emulate a floppy, so just set it here. */ 444 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 445 &vt82c->superio); 446 447 qemu_register_reset(vt82c686b_reset, d); 448 } 449 450 ISABus *vt82c686b_init(PCIBus *bus, int devfn) 451 { 452 PCIDevice *d; 453 454 d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); 455 456 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); 457 } 458 459 static void via_class_init(ObjectClass *klass, void *data) 460 { 461 DeviceClass *dc = DEVICE_CLASS(klass); 462 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 463 464 k->realize = vt82c686b_realize; 465 k->config_write = vt82c686b_write_config; 466 k->vendor_id = PCI_VENDOR_ID_VIA; 467 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 468 k->class_id = PCI_CLASS_BRIDGE_ISA; 469 k->revision = 0x40; 470 dc->desc = "ISA bridge"; 471 dc->vmsd = &vmstate_via; 472 /* 473 * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 474 * e.g. by mips_fulong2e_init() 475 */ 476 dc->cannot_instantiate_with_device_add_yet = true; 477 } 478 479 static const TypeInfo via_info = { 480 .name = "VT82C686B", 481 .parent = TYPE_PCI_DEVICE, 482 .instance_size = sizeof(VT82C686BState), 483 .class_init = via_class_init, 484 }; 485 486 static void vt82c686b_register_types(void) 487 { 488 type_register_static(&via_ac97_info); 489 type_register_static(&via_mc97_info); 490 type_register_static(&via_pm_info); 491 type_register_static(&via_info); 492 } 493 494 type_init(vt82c686b_register_types) 495