149ab747fSPaolo Bonzini /* 249ab747fSPaolo Bonzini * QEMU Xilinx GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 2549ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2649ab747fSPaolo Bonzini 2749ab747fSPaolo Bonzini #include "hw/sysbus.h" 2849ab747fSPaolo Bonzini #include "net/net.h" 2949ab747fSPaolo Bonzini #include "net/checksum.h" 3049ab747fSPaolo Bonzini 3149ab747fSPaolo Bonzini #ifdef CADENCE_GEM_ERR_DEBUG 3249ab747fSPaolo Bonzini #define DB_PRINT(...) do { \ 3349ab747fSPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 3449ab747fSPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 3549ab747fSPaolo Bonzini } while (0); 3649ab747fSPaolo Bonzini #else 3749ab747fSPaolo Bonzini #define DB_PRINT(...) 3849ab747fSPaolo Bonzini #endif 3949ab747fSPaolo Bonzini 4049ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 4149ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 4249ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 4349ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 4449ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 4549ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 4649ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 4749ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 4849ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 4949ab747fSPaolo Bonzini #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 5049ab747fSPaolo Bonzini #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 5149ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 5249ab747fSPaolo Bonzini #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 5349ab747fSPaolo Bonzini #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintaince reg */ 5449ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 5549ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 5649ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 5749ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 5849ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 5949ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 6049ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 6149ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 6249ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 6349ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 6449ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 6549ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 6649ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 6749ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 6849ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 6949ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 7049ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 7149ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 7249ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 7349ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 7449ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 7549ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 7649ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 7749ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 7849ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 7949ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 8049ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 8149ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 8249ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 8349ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 8449ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 8549ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 8649ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 8749ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 8849ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 8949ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 9049ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 9149ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 9249ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 9349ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 9449ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 9549ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 9649ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 9749ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 9849ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 9949ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 10049ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 10149ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 10249ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 10349ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 10449ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 10549ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 10649ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 10749ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 10849ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 10949ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 11049ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 11149ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 11249ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 11349ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 11449ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 11549ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 11649ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 11749ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 11849ab747fSPaolo Bonzini #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 11949ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 12149ab747fSPaolo Bonzini 12249ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 12349ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 12449ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 12549ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 12649ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 12749ab747fSPaolo Bonzini #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 12849ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 12949ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 13049ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 13149ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 13249ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 13349ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 13449ab747fSPaolo Bonzini 13549ab747fSPaolo Bonzini /* Design Configuration Registers */ 13649ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280/4) 13749ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284/4) 13849ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288/4) 13949ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C/4) 14049ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290/4) 14149ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294/4) 14249ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298/4) 14349ab747fSPaolo Bonzini 14449ab747fSPaolo Bonzini #define GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ 14549ab747fSPaolo Bonzini 14649ab747fSPaolo Bonzini /*****************************************/ 14749ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 14849ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 14949ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 15049ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 15149ab747fSPaolo Bonzini 15249ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 15349ab747fSPaolo Bonzini #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with lenth err */ 15449ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 15549ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 15649ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 15749ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 15849ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 15949ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 16049ab747fSPaolo Bonzini 16149ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_M 0x007F0000 /* DMA RX Buffer Size mask */ 16249ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 16349ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 16449ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 16549ab747fSPaolo Bonzini 16649ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 16749ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 16849ab747fSPaolo Bonzini 16949ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 17049ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 17149ab747fSPaolo Bonzini 17249ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 17349ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 17449ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 17549ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 17649ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 17749ab747fSPaolo Bonzini 17849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 17949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 18049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 18149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 18249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 18349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 18449ab747fSPaolo Bonzini 18549ab747fSPaolo Bonzini /* Marvell PHY definitions */ 18649ab747fSPaolo Bonzini #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 18749ab747fSPaolo Bonzini 18849ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 18949ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 19049ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 19149ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 19249ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 19349ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 19449ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 19549ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 19649ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 19749ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 19849ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 19949ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 20049ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 20149ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 20249ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 20349ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 20449ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 20549ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 20649ab747fSPaolo Bonzini #define PHY_REG_EACD 22 20749ab747fSPaolo Bonzini #define PHY_REG_LED 24 20849ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 20949ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 21049ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 21149ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 21249ab747fSPaolo Bonzini 21349ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 21449ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 21549ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 21649ab747fSPaolo Bonzini 21749ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 21849ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 21949ab747fSPaolo Bonzini 22049ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 22149ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 22249ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 22349ab747fSPaolo Bonzini 22449ab747fSPaolo Bonzini /***********************************************************************/ 22549ab747fSPaolo Bonzini #define GEM_RX_REJECT 1 22649ab747fSPaolo Bonzini #define GEM_RX_ACCEPT 0 22749ab747fSPaolo Bonzini 22849ab747fSPaolo Bonzini /***********************************************************************/ 22949ab747fSPaolo Bonzini 23049ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 23149ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 23249ab747fSPaolo Bonzini 23349ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 23449ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 23549ab747fSPaolo Bonzini 23649ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 23749ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 23849ab747fSPaolo Bonzini 23949ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 24049ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 24149ab747fSPaolo Bonzini 24249ab747fSPaolo Bonzini static inline unsigned tx_desc_get_buffer(unsigned *desc) 24349ab747fSPaolo Bonzini { 24449ab747fSPaolo Bonzini return desc[0]; 24549ab747fSPaolo Bonzini } 24649ab747fSPaolo Bonzini 24749ab747fSPaolo Bonzini static inline unsigned tx_desc_get_used(unsigned *desc) 24849ab747fSPaolo Bonzini { 24949ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 25049ab747fSPaolo Bonzini } 25149ab747fSPaolo Bonzini 25249ab747fSPaolo Bonzini static inline void tx_desc_set_used(unsigned *desc) 25349ab747fSPaolo Bonzini { 25449ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 25549ab747fSPaolo Bonzini } 25649ab747fSPaolo Bonzini 25749ab747fSPaolo Bonzini static inline unsigned tx_desc_get_wrap(unsigned *desc) 25849ab747fSPaolo Bonzini { 25949ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 26049ab747fSPaolo Bonzini } 26149ab747fSPaolo Bonzini 26249ab747fSPaolo Bonzini static inline unsigned tx_desc_get_last(unsigned *desc) 26349ab747fSPaolo Bonzini { 26449ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 26549ab747fSPaolo Bonzini } 26649ab747fSPaolo Bonzini 26749ab747fSPaolo Bonzini static inline unsigned tx_desc_get_length(unsigned *desc) 26849ab747fSPaolo Bonzini { 26949ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 27049ab747fSPaolo Bonzini } 27149ab747fSPaolo Bonzini 27249ab747fSPaolo Bonzini static inline void print_gem_tx_desc(unsigned *desc) 27349ab747fSPaolo Bonzini { 27449ab747fSPaolo Bonzini DB_PRINT("TXDESC:\n"); 27549ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 27649ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 27749ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 27849ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 27949ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 28049ab747fSPaolo Bonzini } 28149ab747fSPaolo Bonzini 28249ab747fSPaolo Bonzini static inline unsigned rx_desc_get_buffer(unsigned *desc) 28349ab747fSPaolo Bonzini { 28449ab747fSPaolo Bonzini return desc[0] & ~0x3UL; 28549ab747fSPaolo Bonzini } 28649ab747fSPaolo Bonzini 28749ab747fSPaolo Bonzini static inline unsigned rx_desc_get_wrap(unsigned *desc) 28849ab747fSPaolo Bonzini { 28949ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 29049ab747fSPaolo Bonzini } 29149ab747fSPaolo Bonzini 29249ab747fSPaolo Bonzini static inline unsigned rx_desc_get_ownership(unsigned *desc) 29349ab747fSPaolo Bonzini { 29449ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 29549ab747fSPaolo Bonzini } 29649ab747fSPaolo Bonzini 29749ab747fSPaolo Bonzini static inline void rx_desc_set_ownership(unsigned *desc) 29849ab747fSPaolo Bonzini { 29949ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 30049ab747fSPaolo Bonzini } 30149ab747fSPaolo Bonzini 30249ab747fSPaolo Bonzini static inline void rx_desc_set_sof(unsigned *desc) 30349ab747fSPaolo Bonzini { 30449ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 30549ab747fSPaolo Bonzini } 30649ab747fSPaolo Bonzini 30749ab747fSPaolo Bonzini static inline void rx_desc_set_eof(unsigned *desc) 30849ab747fSPaolo Bonzini { 30949ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 31049ab747fSPaolo Bonzini } 31149ab747fSPaolo Bonzini 31249ab747fSPaolo Bonzini static inline void rx_desc_set_length(unsigned *desc, unsigned len) 31349ab747fSPaolo Bonzini { 31449ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 31549ab747fSPaolo Bonzini desc[1] |= len; 31649ab747fSPaolo Bonzini } 31749ab747fSPaolo Bonzini 318318643beSAndreas Färber #define TYPE_CADENCE_GEM "cadence_gem" 319318643beSAndreas Färber #define GEM(obj) OBJECT_CHECK(GemState, (obj), TYPE_CADENCE_GEM) 320318643beSAndreas Färber 321318643beSAndreas Färber typedef struct GemState { 322318643beSAndreas Färber SysBusDevice parent_obj; 323318643beSAndreas Färber 32449ab747fSPaolo Bonzini MemoryRegion iomem; 32549ab747fSPaolo Bonzini NICState *nic; 32649ab747fSPaolo Bonzini NICConf conf; 32749ab747fSPaolo Bonzini qemu_irq irq; 32849ab747fSPaolo Bonzini 32949ab747fSPaolo Bonzini /* GEM registers backing store */ 33049ab747fSPaolo Bonzini uint32_t regs[GEM_MAXREG]; 33149ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 33249ab747fSPaolo Bonzini uint32_t regs_wo[GEM_MAXREG]; 33349ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 33449ab747fSPaolo Bonzini uint32_t regs_ro[GEM_MAXREG]; 33549ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 33649ab747fSPaolo Bonzini uint32_t regs_rtc[GEM_MAXREG]; 33749ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 33849ab747fSPaolo Bonzini uint32_t regs_w1c[GEM_MAXREG]; 33949ab747fSPaolo Bonzini 34049ab747fSPaolo Bonzini /* PHY registers backing store */ 34149ab747fSPaolo Bonzini uint16_t phy_regs[32]; 34249ab747fSPaolo Bonzini 34349ab747fSPaolo Bonzini uint8_t phy_loop; /* Are we in phy loopback? */ 34449ab747fSPaolo Bonzini 34549ab747fSPaolo Bonzini /* The current DMA descriptor pointers */ 34649ab747fSPaolo Bonzini uint32_t rx_desc_addr; 34749ab747fSPaolo Bonzini uint32_t tx_desc_addr; 34849ab747fSPaolo Bonzini 349*06c2fe95SPeter Crosthwaite unsigned rx_desc[2]; 350*06c2fe95SPeter Crosthwaite 35149ab747fSPaolo Bonzini } GemState; 35249ab747fSPaolo Bonzini 35349ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 35449ab747fSPaolo Bonzini const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 35549ab747fSPaolo Bonzini 35649ab747fSPaolo Bonzini /* 35749ab747fSPaolo Bonzini * gem_init_register_masks: 35849ab747fSPaolo Bonzini * One time initialization. 35949ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 36049ab747fSPaolo Bonzini */ 36149ab747fSPaolo Bonzini static void gem_init_register_masks(GemState *s) 36249ab747fSPaolo Bonzini { 36349ab747fSPaolo Bonzini /* Mask of register bits which are read only*/ 36449ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 36549ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 36649ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 36749ab747fSPaolo Bonzini s->regs_ro[GEM_DMACFG] = 0xFE00F000; 36849ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 36949ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 37049ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 37149ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 37249ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 37349ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 37449ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 37549ab747fSPaolo Bonzini 37649ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 37749ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 37849ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 37949ab747fSPaolo Bonzini 38049ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 38149ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 38249ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 38349ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 38449ab747fSPaolo Bonzini 38549ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 38649ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 38749ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 38849ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 38949ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 39049ab747fSPaolo Bonzini } 39149ab747fSPaolo Bonzini 39249ab747fSPaolo Bonzini /* 39349ab747fSPaolo Bonzini * phy_update_link: 39449ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 39549ab747fSPaolo Bonzini */ 39649ab747fSPaolo Bonzini static void phy_update_link(GemState *s) 39749ab747fSPaolo Bonzini { 39849ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 39949ab747fSPaolo Bonzini 40049ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 40149ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 40249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 40349ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 40449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 40549ab747fSPaolo Bonzini } else { 40649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 40749ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 40849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 40949ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 41049ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 41149ab747fSPaolo Bonzini } 41249ab747fSPaolo Bonzini } 41349ab747fSPaolo Bonzini 41449ab747fSPaolo Bonzini static int gem_can_receive(NetClientState *nc) 41549ab747fSPaolo Bonzini { 41649ab747fSPaolo Bonzini GemState *s; 41749ab747fSPaolo Bonzini 41849ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 41949ab747fSPaolo Bonzini 42049ab747fSPaolo Bonzini DB_PRINT("\n"); 42149ab747fSPaolo Bonzini 42249ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 42349ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 42449ab747fSPaolo Bonzini return 0; 42549ab747fSPaolo Bonzini } 42649ab747fSPaolo Bonzini 42749ab747fSPaolo Bonzini return 1; 42849ab747fSPaolo Bonzini } 42949ab747fSPaolo Bonzini 43049ab747fSPaolo Bonzini /* 43149ab747fSPaolo Bonzini * gem_update_int_status: 43249ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 43349ab747fSPaolo Bonzini */ 43449ab747fSPaolo Bonzini static void gem_update_int_status(GemState *s) 43549ab747fSPaolo Bonzini { 43649ab747fSPaolo Bonzini if (s->regs[GEM_ISR]) { 43749ab747fSPaolo Bonzini DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]); 43849ab747fSPaolo Bonzini qemu_set_irq(s->irq, 1); 43949ab747fSPaolo Bonzini } 44049ab747fSPaolo Bonzini } 44149ab747fSPaolo Bonzini 44249ab747fSPaolo Bonzini /* 44349ab747fSPaolo Bonzini * gem_receive_updatestats: 44449ab747fSPaolo Bonzini * Increment receive statistics. 44549ab747fSPaolo Bonzini */ 44649ab747fSPaolo Bonzini static void gem_receive_updatestats(GemState *s, const uint8_t *packet, 44749ab747fSPaolo Bonzini unsigned bytes) 44849ab747fSPaolo Bonzini { 44949ab747fSPaolo Bonzini uint64_t octets; 45049ab747fSPaolo Bonzini 45149ab747fSPaolo Bonzini /* Total octets (bytes) received */ 45249ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 45349ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 45449ab747fSPaolo Bonzini octets += bytes; 45549ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 45649ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 45749ab747fSPaolo Bonzini 45849ab747fSPaolo Bonzini /* Error-free Frames received */ 45949ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 46049ab747fSPaolo Bonzini 46149ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 46249ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 46349ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 46449ab747fSPaolo Bonzini } 46549ab747fSPaolo Bonzini 46649ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 46749ab747fSPaolo Bonzini if (packet[0] == 0x01) { 46849ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 46949ab747fSPaolo Bonzini } 47049ab747fSPaolo Bonzini 47149ab747fSPaolo Bonzini if (bytes <= 64) { 47249ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 47349ab747fSPaolo Bonzini } else if (bytes <= 127) { 47449ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 47549ab747fSPaolo Bonzini } else if (bytes <= 255) { 47649ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 47749ab747fSPaolo Bonzini } else if (bytes <= 511) { 47849ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 47949ab747fSPaolo Bonzini } else if (bytes <= 1023) { 48049ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 48149ab747fSPaolo Bonzini } else if (bytes <= 1518) { 48249ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 48349ab747fSPaolo Bonzini } else { 48449ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 48549ab747fSPaolo Bonzini } 48649ab747fSPaolo Bonzini } 48749ab747fSPaolo Bonzini 48849ab747fSPaolo Bonzini /* 48949ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 49049ab747fSPaolo Bonzini */ 49149ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 49249ab747fSPaolo Bonzini { 49349ab747fSPaolo Bonzini unsigned byte; 49449ab747fSPaolo Bonzini 49549ab747fSPaolo Bonzini byte = mac[bit / 8]; 49649ab747fSPaolo Bonzini byte >>= (bit & 0x7); 49749ab747fSPaolo Bonzini byte &= 1; 49849ab747fSPaolo Bonzini 49949ab747fSPaolo Bonzini return byte; 50049ab747fSPaolo Bonzini } 50149ab747fSPaolo Bonzini 50249ab747fSPaolo Bonzini /* 50349ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 50449ab747fSPaolo Bonzini */ 50549ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 50649ab747fSPaolo Bonzini { 50749ab747fSPaolo Bonzini int index_bit, mac_bit; 50849ab747fSPaolo Bonzini unsigned hash_index; 50949ab747fSPaolo Bonzini 51049ab747fSPaolo Bonzini hash_index = 0; 51149ab747fSPaolo Bonzini mac_bit = 5; 51249ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 51349ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 51449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 51549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 51649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 51749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 51849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 51949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 52049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 52149ab747fSPaolo Bonzini mac_bit--; 52249ab747fSPaolo Bonzini } 52349ab747fSPaolo Bonzini 52449ab747fSPaolo Bonzini return hash_index; 52549ab747fSPaolo Bonzini } 52649ab747fSPaolo Bonzini 52749ab747fSPaolo Bonzini /* 52849ab747fSPaolo Bonzini * gem_mac_address_filter: 52949ab747fSPaolo Bonzini * Accept or reject this destination address? 53049ab747fSPaolo Bonzini * Returns: 53149ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 53249ab747fSPaolo Bonzini * GEM_RX_ACCEPT: accept 53349ab747fSPaolo Bonzini */ 53449ab747fSPaolo Bonzini static int gem_mac_address_filter(GemState *s, const uint8_t *packet) 53549ab747fSPaolo Bonzini { 53649ab747fSPaolo Bonzini uint8_t *gem_spaddr; 53749ab747fSPaolo Bonzini int i; 53849ab747fSPaolo Bonzini 53949ab747fSPaolo Bonzini /* Promiscuous mode? */ 54049ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 54149ab747fSPaolo Bonzini return GEM_RX_ACCEPT; 54249ab747fSPaolo Bonzini } 54349ab747fSPaolo Bonzini 54449ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 54549ab747fSPaolo Bonzini /* Reject broadcast packets? */ 54649ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 54749ab747fSPaolo Bonzini return GEM_RX_REJECT; 54849ab747fSPaolo Bonzini } 54949ab747fSPaolo Bonzini return GEM_RX_ACCEPT; 55049ab747fSPaolo Bonzini } 55149ab747fSPaolo Bonzini 55249ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 55349ab747fSPaolo Bonzini if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 55449ab747fSPaolo Bonzini (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 55549ab747fSPaolo Bonzini unsigned hash_index; 55649ab747fSPaolo Bonzini 55749ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 55849ab747fSPaolo Bonzini if (hash_index < 32) { 55949ab747fSPaolo Bonzini if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 56049ab747fSPaolo Bonzini return GEM_RX_ACCEPT; 56149ab747fSPaolo Bonzini } 56249ab747fSPaolo Bonzini } else { 56349ab747fSPaolo Bonzini hash_index -= 32; 56449ab747fSPaolo Bonzini if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 56549ab747fSPaolo Bonzini return GEM_RX_ACCEPT; 56649ab747fSPaolo Bonzini } 56749ab747fSPaolo Bonzini } 56849ab747fSPaolo Bonzini } 56949ab747fSPaolo Bonzini 57049ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 57149ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 57249ab747fSPaolo Bonzini for (i = 0; i < 4; i++) { 57349ab747fSPaolo Bonzini if (!memcmp(packet, gem_spaddr, 6)) { 57449ab747fSPaolo Bonzini return GEM_RX_ACCEPT; 57549ab747fSPaolo Bonzini } 57649ab747fSPaolo Bonzini 57749ab747fSPaolo Bonzini gem_spaddr += 8; 57849ab747fSPaolo Bonzini } 57949ab747fSPaolo Bonzini 58049ab747fSPaolo Bonzini /* No address match; reject the packet */ 58149ab747fSPaolo Bonzini return GEM_RX_REJECT; 58249ab747fSPaolo Bonzini } 58349ab747fSPaolo Bonzini 584*06c2fe95SPeter Crosthwaite static void gem_get_rx_desc(GemState *s) 585*06c2fe95SPeter Crosthwaite { 586*06c2fe95SPeter Crosthwaite DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr); 587*06c2fe95SPeter Crosthwaite /* read current descriptor */ 588*06c2fe95SPeter Crosthwaite cpu_physical_memory_read(s->rx_desc_addr, 589*06c2fe95SPeter Crosthwaite (uint8_t *)s->rx_desc, sizeof(s->rx_desc)); 590*06c2fe95SPeter Crosthwaite 591*06c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 592*06c2fe95SPeter Crosthwaite if (rx_desc_get_ownership(s->rx_desc) == 1) { 593*06c2fe95SPeter Crosthwaite DB_PRINT("descriptor 0x%x owned by sw.\n", 594*06c2fe95SPeter Crosthwaite (unsigned)s->rx_desc_addr); 595*06c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 596*06c2fe95SPeter Crosthwaite s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 597*06c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 598*06c2fe95SPeter Crosthwaite gem_update_int_status(s); 599*06c2fe95SPeter Crosthwaite } 600*06c2fe95SPeter Crosthwaite } 601*06c2fe95SPeter Crosthwaite 60249ab747fSPaolo Bonzini /* 60349ab747fSPaolo Bonzini * gem_receive: 60449ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 60549ab747fSPaolo Bonzini */ 60649ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 60749ab747fSPaolo Bonzini { 60849ab747fSPaolo Bonzini GemState *s; 60949ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 61049ab747fSPaolo Bonzini unsigned rxbuf_offset; 61149ab747fSPaolo Bonzini uint8_t rxbuf[2048]; 61249ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 6133b2c97f9SEdgar E. Iglesias bool first_desc = true; 61449ab747fSPaolo Bonzini 61549ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 61649ab747fSPaolo Bonzini 61749ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 61849ab747fSPaolo Bonzini if (gem_mac_address_filter(s, buf) == GEM_RX_REJECT) { 61949ab747fSPaolo Bonzini return -1; 62049ab747fSPaolo Bonzini } 62149ab747fSPaolo Bonzini 62249ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 62349ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 62449ab747fSPaolo Bonzini unsigned type_len; 62549ab747fSPaolo Bonzini 62649ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 62749ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 62849ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 62949ab747fSPaolo Bonzini if (type_len < 0x600) { 63049ab747fSPaolo Bonzini if (size < type_len) { 63149ab747fSPaolo Bonzini /* discard */ 63249ab747fSPaolo Bonzini return -1; 63349ab747fSPaolo Bonzini } 63449ab747fSPaolo Bonzini } 63549ab747fSPaolo Bonzini } 63649ab747fSPaolo Bonzini 63749ab747fSPaolo Bonzini /* 63849ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 63949ab747fSPaolo Bonzini */ 64049ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 64149ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 64249ab747fSPaolo Bonzini 64349ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 64449ab747fSPaolo Bonzini * buffers needed to hold this packet. 64549ab747fSPaolo Bonzini */ 64649ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 64749ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 64849ab747fSPaolo Bonzini bytes_to_copy = size; 64949ab747fSPaolo Bonzini 65049ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 65149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 65249ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 65349ab747fSPaolo Bonzini } else { 65449ab747fSPaolo Bonzini unsigned crc_val; 65549ab747fSPaolo Bonzini int crc_offset; 65649ab747fSPaolo Bonzini 65749ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 65849ab747fSPaolo Bonzini * We must try and caclculate one. 65949ab747fSPaolo Bonzini */ 66049ab747fSPaolo Bonzini 66149ab747fSPaolo Bonzini memcpy(rxbuf, buf, size); 66249ab747fSPaolo Bonzini memset(rxbuf + size, 0, sizeof(rxbuf) - size); 66349ab747fSPaolo Bonzini rxbuf_ptr = rxbuf; 66449ab747fSPaolo Bonzini crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 66549ab747fSPaolo Bonzini if (size < 60) { 66649ab747fSPaolo Bonzini crc_offset = 60; 66749ab747fSPaolo Bonzini } else { 66849ab747fSPaolo Bonzini crc_offset = size; 66949ab747fSPaolo Bonzini } 67049ab747fSPaolo Bonzini memcpy(rxbuf + crc_offset, &crc_val, sizeof(crc_val)); 67149ab747fSPaolo Bonzini 67249ab747fSPaolo Bonzini bytes_to_copy += 4; 67349ab747fSPaolo Bonzini size += 4; 67449ab747fSPaolo Bonzini } 67549ab747fSPaolo Bonzini 67649ab747fSPaolo Bonzini /* Pad to minimum length */ 67749ab747fSPaolo Bonzini if (size < 64) { 67849ab747fSPaolo Bonzini size = 64; 67949ab747fSPaolo Bonzini } 68049ab747fSPaolo Bonzini 68149ab747fSPaolo Bonzini DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 68249ab747fSPaolo Bonzini 6837cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 684*06c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 685*06c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 686*06c2fe95SPeter Crosthwaite assert(!first_desc); 68749ab747fSPaolo Bonzini return -1; 68849ab747fSPaolo Bonzini } 68949ab747fSPaolo Bonzini 69049ab747fSPaolo Bonzini DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 691*06c2fe95SPeter Crosthwaite rx_desc_get_buffer(s->rx_desc)); 69249ab747fSPaolo Bonzini 69349ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 694*06c2fe95SPeter Crosthwaite cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc) + rxbuf_offset, 69549ab747fSPaolo Bonzini rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 69649ab747fSPaolo Bonzini bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 69749ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 6983b2c97f9SEdgar E. Iglesias 6993b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 7003b2c97f9SEdgar E. Iglesias if (first_desc) { 701*06c2fe95SPeter Crosthwaite rx_desc_set_sof(s->rx_desc); 7023b2c97f9SEdgar E. Iglesias first_desc = false; 7033b2c97f9SEdgar E. Iglesias } 7043b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 705*06c2fe95SPeter Crosthwaite rx_desc_set_eof(s->rx_desc); 706*06c2fe95SPeter Crosthwaite rx_desc_set_length(s->rx_desc, size); 7073b2c97f9SEdgar E. Iglesias } 708*06c2fe95SPeter Crosthwaite rx_desc_set_ownership(s->rx_desc); 7093b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 7107cfd65e4SPeter Crosthwaite cpu_physical_memory_write(s->rx_desc_addr, 711*06c2fe95SPeter Crosthwaite (uint8_t *)s->rx_desc, sizeof(s->rx_desc)); 7123b2c97f9SEdgar E. Iglesias 71349ab747fSPaolo Bonzini /* Next descriptor */ 714*06c2fe95SPeter Crosthwaite if (rx_desc_get_wrap(s->rx_desc)) { 71549ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 7167cfd65e4SPeter Crosthwaite s->rx_desc_addr = s->regs[GEM_RXQBASE]; 71749ab747fSPaolo Bonzini } else { 71849ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 71949ab747fSPaolo Bonzini s->rx_desc_addr += 8; 72049ab747fSPaolo Bonzini } 721*06c2fe95SPeter Crosthwaite gem_get_rx_desc(s); 7227cfd65e4SPeter Crosthwaite } 72349ab747fSPaolo Bonzini 72449ab747fSPaolo Bonzini /* Count it */ 72549ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 72649ab747fSPaolo Bonzini 72749ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 72849ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 72949ab747fSPaolo Bonzini 73049ab747fSPaolo Bonzini /* Handle interrupt consequences */ 73149ab747fSPaolo Bonzini gem_update_int_status(s); 73249ab747fSPaolo Bonzini 73349ab747fSPaolo Bonzini return size; 73449ab747fSPaolo Bonzini } 73549ab747fSPaolo Bonzini 73649ab747fSPaolo Bonzini /* 73749ab747fSPaolo Bonzini * gem_transmit_updatestats: 73849ab747fSPaolo Bonzini * Increment transmit statistics. 73949ab747fSPaolo Bonzini */ 74049ab747fSPaolo Bonzini static void gem_transmit_updatestats(GemState *s, const uint8_t *packet, 74149ab747fSPaolo Bonzini unsigned bytes) 74249ab747fSPaolo Bonzini { 74349ab747fSPaolo Bonzini uint64_t octets; 74449ab747fSPaolo Bonzini 74549ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 74649ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 74749ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 74849ab747fSPaolo Bonzini octets += bytes; 74949ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 75049ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 75149ab747fSPaolo Bonzini 75249ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 75349ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 75449ab747fSPaolo Bonzini 75549ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 75649ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 75749ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 75849ab747fSPaolo Bonzini } 75949ab747fSPaolo Bonzini 76049ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 76149ab747fSPaolo Bonzini if (packet[0] == 0x01) { 76249ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 76349ab747fSPaolo Bonzini } 76449ab747fSPaolo Bonzini 76549ab747fSPaolo Bonzini if (bytes <= 64) { 76649ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 76749ab747fSPaolo Bonzini } else if (bytes <= 127) { 76849ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 76949ab747fSPaolo Bonzini } else if (bytes <= 255) { 77049ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 77149ab747fSPaolo Bonzini } else if (bytes <= 511) { 77249ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 77349ab747fSPaolo Bonzini } else if (bytes <= 1023) { 77449ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 77549ab747fSPaolo Bonzini } else if (bytes <= 1518) { 77649ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 77749ab747fSPaolo Bonzini } else { 77849ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 77949ab747fSPaolo Bonzini } 78049ab747fSPaolo Bonzini } 78149ab747fSPaolo Bonzini 78249ab747fSPaolo Bonzini /* 78349ab747fSPaolo Bonzini * gem_transmit: 78449ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 78549ab747fSPaolo Bonzini */ 78649ab747fSPaolo Bonzini static void gem_transmit(GemState *s) 78749ab747fSPaolo Bonzini { 78849ab747fSPaolo Bonzini unsigned desc[2]; 78949ab747fSPaolo Bonzini hwaddr packet_desc_addr; 79049ab747fSPaolo Bonzini uint8_t tx_packet[2048]; 79149ab747fSPaolo Bonzini uint8_t *p; 79249ab747fSPaolo Bonzini unsigned total_bytes; 79349ab747fSPaolo Bonzini 79449ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 79549ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 79649ab747fSPaolo Bonzini return; 79749ab747fSPaolo Bonzini } 79849ab747fSPaolo Bonzini 79949ab747fSPaolo Bonzini DB_PRINT("\n"); 80049ab747fSPaolo Bonzini 80149ab747fSPaolo Bonzini /* The packet we will hand off to qemu. 80249ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 80349ab747fSPaolo Bonzini * one contiguous buffer first. 80449ab747fSPaolo Bonzini */ 80549ab747fSPaolo Bonzini p = tx_packet; 80649ab747fSPaolo Bonzini total_bytes = 0; 80749ab747fSPaolo Bonzini 80849ab747fSPaolo Bonzini /* read current descriptor */ 80949ab747fSPaolo Bonzini packet_desc_addr = s->tx_desc_addr; 81049ab747fSPaolo Bonzini cpu_physical_memory_read(packet_desc_addr, 81149ab747fSPaolo Bonzini (uint8_t *)&desc[0], sizeof(desc)); 81249ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 81349ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 81449ab747fSPaolo Bonzini 81549ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 81649ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 81749ab747fSPaolo Bonzini return; 81849ab747fSPaolo Bonzini } 81949ab747fSPaolo Bonzini print_gem_tx_desc(desc); 82049ab747fSPaolo Bonzini 82149ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 82249ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 82349ab747fSPaolo Bonzini */ 82449ab747fSPaolo Bonzini if ((tx_desc_get_buffer(desc) == 0) || 82549ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 82649ab747fSPaolo Bonzini DB_PRINT("Invalid TX descriptor @ 0x%x\n", 82749ab747fSPaolo Bonzini (unsigned)packet_desc_addr); 82849ab747fSPaolo Bonzini break; 82949ab747fSPaolo Bonzini } 83049ab747fSPaolo Bonzini 83149ab747fSPaolo Bonzini /* Gather this fragment of the packet from "dma memory" to our contig. 83249ab747fSPaolo Bonzini * buffer. 83349ab747fSPaolo Bonzini */ 83449ab747fSPaolo Bonzini cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 83549ab747fSPaolo Bonzini tx_desc_get_length(desc)); 83649ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 83749ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 83849ab747fSPaolo Bonzini 83949ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 84049ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 84149ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 84249ab747fSPaolo Bonzini * the processor. 84349ab747fSPaolo Bonzini */ 84449ab747fSPaolo Bonzini cpu_physical_memory_read(s->tx_desc_addr, 84549ab747fSPaolo Bonzini (uint8_t *)&desc[0], sizeof(desc)); 84649ab747fSPaolo Bonzini tx_desc_set_used(desc); 84749ab747fSPaolo Bonzini cpu_physical_memory_write(s->tx_desc_addr, 84849ab747fSPaolo Bonzini (uint8_t *)&desc[0], sizeof(desc)); 84949ab747fSPaolo Bonzini /* Advance the hardare current descriptor past this packet */ 85049ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 85149ab747fSPaolo Bonzini s->tx_desc_addr = s->regs[GEM_TXQBASE]; 85249ab747fSPaolo Bonzini } else { 85349ab747fSPaolo Bonzini s->tx_desc_addr = packet_desc_addr + 8; 85449ab747fSPaolo Bonzini } 85549ab747fSPaolo Bonzini DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr); 85649ab747fSPaolo Bonzini 85749ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 85849ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 85949ab747fSPaolo Bonzini 86049ab747fSPaolo Bonzini /* Handle interrupt consequences */ 86149ab747fSPaolo Bonzini gem_update_int_status(s); 86249ab747fSPaolo Bonzini 86349ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 86449ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 86549ab747fSPaolo Bonzini net_checksum_calculate(tx_packet, total_bytes); 86649ab747fSPaolo Bonzini } 86749ab747fSPaolo Bonzini 86849ab747fSPaolo Bonzini /* Update MAC statistics */ 86949ab747fSPaolo Bonzini gem_transmit_updatestats(s, tx_packet, total_bytes); 87049ab747fSPaolo Bonzini 87149ab747fSPaolo Bonzini /* Send the packet somewhere */ 87224e822eaSPeter Crosthwaite if (s->phy_loop || (s->regs[GEM_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) { 87349ab747fSPaolo Bonzini gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes); 87449ab747fSPaolo Bonzini } else { 87549ab747fSPaolo Bonzini qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 87649ab747fSPaolo Bonzini total_bytes); 87749ab747fSPaolo Bonzini } 87849ab747fSPaolo Bonzini 87949ab747fSPaolo Bonzini /* Prepare for next packet */ 88049ab747fSPaolo Bonzini p = tx_packet; 88149ab747fSPaolo Bonzini total_bytes = 0; 88249ab747fSPaolo Bonzini } 88349ab747fSPaolo Bonzini 88449ab747fSPaolo Bonzini /* read next descriptor */ 88549ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 88649ab747fSPaolo Bonzini packet_desc_addr = s->regs[GEM_TXQBASE]; 88749ab747fSPaolo Bonzini } else { 88849ab747fSPaolo Bonzini packet_desc_addr += 8; 88949ab747fSPaolo Bonzini } 89049ab747fSPaolo Bonzini cpu_physical_memory_read(packet_desc_addr, 89149ab747fSPaolo Bonzini (uint8_t *)&desc[0], sizeof(desc)); 89249ab747fSPaolo Bonzini } 89349ab747fSPaolo Bonzini 89449ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 89549ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 89649ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 89749ab747fSPaolo Bonzini gem_update_int_status(s); 89849ab747fSPaolo Bonzini } 89949ab747fSPaolo Bonzini } 90049ab747fSPaolo Bonzini 90149ab747fSPaolo Bonzini static void gem_phy_reset(GemState *s) 90249ab747fSPaolo Bonzini { 90349ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 90449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 90549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 90649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 90749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 90849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 90949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 91049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 91149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 91249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 91349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 91449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 91549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 91649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 91749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00; 91849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 91949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 92049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 92149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 92249ab747fSPaolo Bonzini 92349ab747fSPaolo Bonzini phy_update_link(s); 92449ab747fSPaolo Bonzini } 92549ab747fSPaolo Bonzini 92649ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 92749ab747fSPaolo Bonzini { 928318643beSAndreas Färber GemState *s = GEM(d); 92949ab747fSPaolo Bonzini 93049ab747fSPaolo Bonzini DB_PRINT("\n"); 93149ab747fSPaolo Bonzini 93249ab747fSPaolo Bonzini /* Set post reset register values */ 93349ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 93449ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 93549ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 93649ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 93749ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 93849ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 93949ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 94049ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 94149ab747fSPaolo Bonzini s->regs[GEM_MODID] = 0x00020118; 94249ab747fSPaolo Bonzini s->regs[GEM_DESCONF] = 0x02500111; 94349ab747fSPaolo Bonzini s->regs[GEM_DESCONF2] = 0x2ab13fff; 94449ab747fSPaolo Bonzini s->regs[GEM_DESCONF5] = 0x002f2145; 94549ab747fSPaolo Bonzini s->regs[GEM_DESCONF6] = 0x00000200; 94649ab747fSPaolo Bonzini 94749ab747fSPaolo Bonzini gem_phy_reset(s); 94849ab747fSPaolo Bonzini 94949ab747fSPaolo Bonzini gem_update_int_status(s); 95049ab747fSPaolo Bonzini } 95149ab747fSPaolo Bonzini 95249ab747fSPaolo Bonzini static uint16_t gem_phy_read(GemState *s, unsigned reg_num) 95349ab747fSPaolo Bonzini { 95449ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 95549ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 95649ab747fSPaolo Bonzini } 95749ab747fSPaolo Bonzini 95849ab747fSPaolo Bonzini static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val) 95949ab747fSPaolo Bonzini { 96049ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 96149ab747fSPaolo Bonzini 96249ab747fSPaolo Bonzini switch (reg_num) { 96349ab747fSPaolo Bonzini case PHY_REG_CONTROL: 96449ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 96549ab747fSPaolo Bonzini /* Phy reset */ 96649ab747fSPaolo Bonzini gem_phy_reset(s); 96749ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 96849ab747fSPaolo Bonzini s->phy_loop = 0; 96949ab747fSPaolo Bonzini } 97049ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 97149ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 97249ab747fSPaolo Bonzini val &= ~PHY_REG_CONTROL_ANEG; 97349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 97449ab747fSPaolo Bonzini } 97549ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 97649ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 97749ab747fSPaolo Bonzini s->phy_loop = 1; 97849ab747fSPaolo Bonzini } else { 97949ab747fSPaolo Bonzini s->phy_loop = 0; 98049ab747fSPaolo Bonzini } 98149ab747fSPaolo Bonzini break; 98249ab747fSPaolo Bonzini } 98349ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 98449ab747fSPaolo Bonzini } 98549ab747fSPaolo Bonzini 98649ab747fSPaolo Bonzini /* 98749ab747fSPaolo Bonzini * gem_read32: 98849ab747fSPaolo Bonzini * Read a GEM register. 98949ab747fSPaolo Bonzini */ 99049ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 99149ab747fSPaolo Bonzini { 99249ab747fSPaolo Bonzini GemState *s; 99349ab747fSPaolo Bonzini uint32_t retval; 99449ab747fSPaolo Bonzini 99549ab747fSPaolo Bonzini s = (GemState *)opaque; 99649ab747fSPaolo Bonzini 99749ab747fSPaolo Bonzini offset >>= 2; 99849ab747fSPaolo Bonzini retval = s->regs[offset]; 99949ab747fSPaolo Bonzini 100049ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 100149ab747fSPaolo Bonzini 100249ab747fSPaolo Bonzini switch (offset) { 100349ab747fSPaolo Bonzini case GEM_ISR: 100449ab747fSPaolo Bonzini DB_PRINT("lowering irq on ISR read\n"); 100549ab747fSPaolo Bonzini qemu_set_irq(s->irq, 0); 100649ab747fSPaolo Bonzini break; 100749ab747fSPaolo Bonzini case GEM_PHYMNTNC: 100849ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 100949ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 101049ab747fSPaolo Bonzini 101149ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 101249ab747fSPaolo Bonzini if (phy_addr == BOARD_PHY_ADDRESS) { 101349ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 101449ab747fSPaolo Bonzini retval &= 0xFFFF0000; 101549ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 101649ab747fSPaolo Bonzini } else { 101749ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 101849ab747fSPaolo Bonzini } 101949ab747fSPaolo Bonzini } 102049ab747fSPaolo Bonzini break; 102149ab747fSPaolo Bonzini } 102249ab747fSPaolo Bonzini 102349ab747fSPaolo Bonzini /* Squash read to clear bits */ 102449ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 102549ab747fSPaolo Bonzini 102649ab747fSPaolo Bonzini /* Do not provide write only bits */ 102749ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 102849ab747fSPaolo Bonzini 102949ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 103049ab747fSPaolo Bonzini return retval; 103149ab747fSPaolo Bonzini } 103249ab747fSPaolo Bonzini 103349ab747fSPaolo Bonzini /* 103449ab747fSPaolo Bonzini * gem_write32: 103549ab747fSPaolo Bonzini * Write a GEM register. 103649ab747fSPaolo Bonzini */ 103749ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 103849ab747fSPaolo Bonzini unsigned size) 103949ab747fSPaolo Bonzini { 104049ab747fSPaolo Bonzini GemState *s = (GemState *)opaque; 104149ab747fSPaolo Bonzini uint32_t readonly; 104249ab747fSPaolo Bonzini 104349ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 104449ab747fSPaolo Bonzini offset >>= 2; 104549ab747fSPaolo Bonzini 104649ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 104749ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 104849ab747fSPaolo Bonzini /* Preserve (only) bits which are read only in register */ 104949ab747fSPaolo Bonzini readonly = s->regs[offset]; 105049ab747fSPaolo Bonzini readonly &= s->regs_ro[offset]; 105149ab747fSPaolo Bonzini 105249ab747fSPaolo Bonzini /* Squash bits which are write 1 to clear */ 105349ab747fSPaolo Bonzini val &= ~(s->regs_w1c[offset] & val); 105449ab747fSPaolo Bonzini 105549ab747fSPaolo Bonzini /* Copy register write to backing store */ 105649ab747fSPaolo Bonzini s->regs[offset] = val | readonly; 105749ab747fSPaolo Bonzini 105849ab747fSPaolo Bonzini /* Handle register write side effects */ 105949ab747fSPaolo Bonzini switch (offset) { 106049ab747fSPaolo Bonzini case GEM_NWCTRL: 1061*06c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 1062*06c2fe95SPeter Crosthwaite gem_get_rx_desc(s); 1063*06c2fe95SPeter Crosthwaite } 106449ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 106549ab747fSPaolo Bonzini gem_transmit(s); 106649ab747fSPaolo Bonzini } 106749ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 106849ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 106949ab747fSPaolo Bonzini s->tx_desc_addr = s->regs[GEM_TXQBASE]; 107049ab747fSPaolo Bonzini } 107149ab747fSPaolo Bonzini if (val & GEM_NWCTRL_RXENA) { 107249ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 107349ab747fSPaolo Bonzini } 107449ab747fSPaolo Bonzini break; 107549ab747fSPaolo Bonzini 107649ab747fSPaolo Bonzini case GEM_TXSTATUS: 107749ab747fSPaolo Bonzini gem_update_int_status(s); 107849ab747fSPaolo Bonzini break; 107949ab747fSPaolo Bonzini case GEM_RXQBASE: 108049ab747fSPaolo Bonzini s->rx_desc_addr = val; 108149ab747fSPaolo Bonzini break; 108249ab747fSPaolo Bonzini case GEM_TXQBASE: 108349ab747fSPaolo Bonzini s->tx_desc_addr = val; 108449ab747fSPaolo Bonzini break; 108549ab747fSPaolo Bonzini case GEM_RXSTATUS: 108649ab747fSPaolo Bonzini gem_update_int_status(s); 108749ab747fSPaolo Bonzini break; 108849ab747fSPaolo Bonzini case GEM_IER: 108949ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 109049ab747fSPaolo Bonzini gem_update_int_status(s); 109149ab747fSPaolo Bonzini break; 109249ab747fSPaolo Bonzini case GEM_IDR: 109349ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 109449ab747fSPaolo Bonzini gem_update_int_status(s); 109549ab747fSPaolo Bonzini break; 109649ab747fSPaolo Bonzini case GEM_PHYMNTNC: 109749ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 109849ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 109949ab747fSPaolo Bonzini 110049ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 110149ab747fSPaolo Bonzini if (phy_addr == BOARD_PHY_ADDRESS) { 110249ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 110349ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 110449ab747fSPaolo Bonzini } 110549ab747fSPaolo Bonzini } 110649ab747fSPaolo Bonzini break; 110749ab747fSPaolo Bonzini } 110849ab747fSPaolo Bonzini 110949ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 111049ab747fSPaolo Bonzini } 111149ab747fSPaolo Bonzini 111249ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 111349ab747fSPaolo Bonzini .read = gem_read, 111449ab747fSPaolo Bonzini .write = gem_write, 111549ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 111649ab747fSPaolo Bonzini }; 111749ab747fSPaolo Bonzini 111849ab747fSPaolo Bonzini static void gem_cleanup(NetClientState *nc) 111949ab747fSPaolo Bonzini { 112049ab747fSPaolo Bonzini GemState *s = qemu_get_nic_opaque(nc); 112149ab747fSPaolo Bonzini 112249ab747fSPaolo Bonzini DB_PRINT("\n"); 112349ab747fSPaolo Bonzini s->nic = NULL; 112449ab747fSPaolo Bonzini } 112549ab747fSPaolo Bonzini 112649ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 112749ab747fSPaolo Bonzini { 112849ab747fSPaolo Bonzini DB_PRINT("\n"); 112949ab747fSPaolo Bonzini phy_update_link(qemu_get_nic_opaque(nc)); 113049ab747fSPaolo Bonzini } 113149ab747fSPaolo Bonzini 113249ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 113349ab747fSPaolo Bonzini .type = NET_CLIENT_OPTIONS_KIND_NIC, 113449ab747fSPaolo Bonzini .size = sizeof(NICState), 113549ab747fSPaolo Bonzini .can_receive = gem_can_receive, 113649ab747fSPaolo Bonzini .receive = gem_receive, 113749ab747fSPaolo Bonzini .cleanup = gem_cleanup, 113849ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 113949ab747fSPaolo Bonzini }; 114049ab747fSPaolo Bonzini 1141318643beSAndreas Färber static int gem_init(SysBusDevice *sbd) 114249ab747fSPaolo Bonzini { 1143318643beSAndreas Färber DeviceState *dev = DEVICE(sbd); 1144318643beSAndreas Färber GemState *s = GEM(dev); 114549ab747fSPaolo Bonzini 114649ab747fSPaolo Bonzini DB_PRINT("\n"); 114749ab747fSPaolo Bonzini 114849ab747fSPaolo Bonzini gem_init_register_masks(s); 1149eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1150eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 1151318643beSAndreas Färber sysbus_init_mmio(sbd, &s->iomem); 1152318643beSAndreas Färber sysbus_init_irq(sbd, &s->irq); 115349ab747fSPaolo Bonzini qemu_macaddr_default_if_unset(&s->conf.macaddr); 115449ab747fSPaolo Bonzini 115549ab747fSPaolo Bonzini s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1156318643beSAndreas Färber object_get_typename(OBJECT(dev)), dev->id, s); 115749ab747fSPaolo Bonzini 115849ab747fSPaolo Bonzini return 0; 115949ab747fSPaolo Bonzini } 116049ab747fSPaolo Bonzini 116149ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 116249ab747fSPaolo Bonzini .name = "cadence_gem", 116349ab747fSPaolo Bonzini .version_id = 1, 116449ab747fSPaolo Bonzini .minimum_version_id = 1, 116549ab747fSPaolo Bonzini .minimum_version_id_old = 1, 116649ab747fSPaolo Bonzini .fields = (VMStateField[]) { 116749ab747fSPaolo Bonzini VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG), 116849ab747fSPaolo Bonzini VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32), 116949ab747fSPaolo Bonzini VMSTATE_UINT8(phy_loop, GemState), 117049ab747fSPaolo Bonzini VMSTATE_UINT32(rx_desc_addr, GemState), 117149ab747fSPaolo Bonzini VMSTATE_UINT32(tx_desc_addr, GemState), 117249ab747fSPaolo Bonzini } 117349ab747fSPaolo Bonzini }; 117449ab747fSPaolo Bonzini 117549ab747fSPaolo Bonzini static Property gem_properties[] = { 117649ab747fSPaolo Bonzini DEFINE_NIC_PROPERTIES(GemState, conf), 117749ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 117849ab747fSPaolo Bonzini }; 117949ab747fSPaolo Bonzini 118049ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 118149ab747fSPaolo Bonzini { 118249ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 118349ab747fSPaolo Bonzini SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 118449ab747fSPaolo Bonzini 118549ab747fSPaolo Bonzini sdc->init = gem_init; 118649ab747fSPaolo Bonzini dc->props = gem_properties; 118749ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 118849ab747fSPaolo Bonzini dc->reset = gem_reset; 118949ab747fSPaolo Bonzini } 119049ab747fSPaolo Bonzini 119149ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1192318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 119349ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 119449ab747fSPaolo Bonzini .instance_size = sizeof(GemState), 1195318643beSAndreas Färber .class_init = gem_class_init, 119649ab747fSPaolo Bonzini }; 119749ab747fSPaolo Bonzini 119849ab747fSPaolo Bonzini static void gem_register_types(void) 119949ab747fSPaolo Bonzini { 120049ab747fSPaolo Bonzini type_register_static(&gem_info); 120149ab747fSPaolo Bonzini } 120249ab747fSPaolo Bonzini 120349ab747fSPaolo Bonzini type_init(gem_register_types) 1204