| #
0c7ffc97 |
| 02-Jan-2024 |
Bin Meng <bmeng@tinylab.org> |
hw/net: cadence_gem: Fix MDIO_OP_xxx values
Testing upstream U-Boot with 'sifive_u' machine we see:
=> dhcp
ethernet@10090000: PHY present at 0
Could not get PHY for ethernet@10090000: addr 0
hw/net: cadence_gem: Fix MDIO_OP_xxx values
Testing upstream U-Boot with 'sifive_u' machine we see:
=> dhcp
ethernet@10090000: PHY present at 0
Could not get PHY for ethernet@10090000: addr 0
phy_connect failed
This has been working till QEMU 8.1 but broken since QEMU 8.2.
Fixes: 1b09eeb122aa ("hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields")
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
show more ...
|
|
Revision tags: v8.1.4, v7.2.8 |
|
| #
1de81b42 |
| 21-Dec-2023 |
Richard Henderson <richard.henderson@linaro.org> |
hw/net: Constify VMState
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231221031652.119827-42-richard.henderson@linaro.org>
|
|
Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0, v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4 |
|
| #
7d0fefdf |
| 01-Jun-2023 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
net: Provide MemReentrancyGuard * to qemu_new_nic()
Recently MemReentrancyGuard was added to DeviceState to record that the
device is engaging in I/O. The network device backend needs to update it
w
net: Provide MemReentrancyGuard * to qemu_new_nic()
Recently MemReentrancyGuard was added to DeviceState to record that the
device is engaging in I/O. The network device backend needs to update it
when delivering a packet to a device.
In preparation for such a change, add MemReentrancyGuard * as a
parameter of qemu_new_nic().
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Jason Wang <jasowang@redhat.com>
show more ...
|
| #
315ebbd7 |
| 14-Nov-2023 |
Michael Tokarev <mjt@tls.msk.ru> |
hw/net/cadence_gem.c: spelling fixes: Octects
Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register definitions"
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Luc Michel <
hw/net/cadence_gem.c: spelling fixes: Octects
Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register definitions"
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
show more ...
|
| #
315ebbd7 |
| 14-Nov-2023 |
Michael Tokarev <mjt@tls.msk.ru> |
hw/net/cadence_gem.c: spelling fixes: Octects
Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register definitions"
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Luc Michel <
hw/net/cadence_gem.c: spelling fixes: Octects
Fixes: c755c943aa2e "hw/net/cadence_gem: use REG32 macro for register definitions"
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
show more ...
|
| #
df93de98 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: enforce 32 bits variable size for CRC
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signe
hw/net/cadence_gem: enforce 32 bits variable size for CRC
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-12-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
71a082a3 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: perform PHY access on write only
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO a
hw/net/cadence_gem: perform PHY access on write only
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO access by itself.
Refactor the PHY access logic to perform all accesses (MDIO reads and
writes) at PHYMNTNC write time.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-11-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
1b09eeb1 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pava
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-10-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
ce077875 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231017194422.4124691-9-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
987e8060 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe IRQ register fields
Use de FIELD macro to describe the IRQ related register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.b
hw/net/cadence_gem: use FIELD to describe IRQ register fields
Use de FIELD macro to describe the IRQ related register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-8-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
466da857 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Revi
hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-7-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
01f9175d |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.bod
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-6-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
87a49c3f |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-5-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
bd8a922d |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.bo
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-4-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
b46b526c |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD for screening registers
Describe screening registers fields using the FIELD macros.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
hw/net/cadence_gem: use FIELD for screening registers
Describe screening registers fields using the FIELD macros.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-3-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
c755c943 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use REG32 macro for register definitions
Replace register defines with the REG32 macro from registerfields.h in
the Cadence GEM device.
Signed-off-by: Luc Michel <luc.michel@amd
hw/net/cadence_gem: use REG32 macro for register definitions
Replace register defines with the REG32 macro from registerfields.h in
the Cadence GEM device.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-2-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
df93de98 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: enforce 32 bits variable size for CRC
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signe
hw/net/cadence_gem: enforce 32 bits variable size for CRC
The CRC was stored in an unsigned variable in gem_receive. Change it for
a uint32_t to ensure we have the correct variable size here.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-12-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
71a082a3 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: perform PHY access on write only
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO a
hw/net/cadence_gem: perform PHY access on write only
The MDIO access is done only on a write to the PHYMNTNC register. A
subsequent read is used to retrieve the result but does not trigger an
MDIO access by itself.
Refactor the PHY access logic to perform all accesses (MDIO reads and
writes) at PHYMNTNC write time.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-11-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
1b09eeb1 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pava
hw/net/cadence_gem: use FIELD to describe PHYMNTNC register fields
Use the FIELD macro to describe the PHYMNTNC register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-10-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
ce077875 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe
hw/net/cadence_gem: use FIELD to describe DESCONF6 register fields
Use the FIELD macro to describe the DESCONF6 register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20231017194422.4124691-9-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
987e8060 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe IRQ register fields
Use de FIELD macro to describe the IRQ related register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.b
hw/net/cadence_gem: use FIELD to describe IRQ register fields
Use de FIELD macro to describe the IRQ related register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-8-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
466da857 |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Revi
hw/net/cadence_gem: use FIELD to describe [TX|RX]STATUS register fields
Use de FIELD macro to describe the TXSTATUS and RXSTATUS register
fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-7-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
01f9175d |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.bod
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-6-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
87a49c3f |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-5-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
bd8a922d |
| 17-Oct-2023 |
Luc Michel <luc.michel@amd.com> |
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.bo
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id: 20231017194422.4124691-4-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|