1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/irq.h" 29 #include "hw/net/cadence_gem.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/registerfields.h" 32 #include "migration/vmstate.h" 33 #include "qapi/error.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "sysemu/dma.h" 37 #include "net/checksum.h" 38 #include "net/eth.h" 39 40 #define CADENCE_GEM_ERR_DEBUG 0 41 #define DB_PRINT(...) do {\ 42 if (CADENCE_GEM_ERR_DEBUG) { \ 43 qemu_log(": %s: ", __func__); \ 44 qemu_log(__VA_ARGS__); \ 45 } \ 46 } while (0) 47 48 REG32(NWCTRL, 0x0) /* Network Control reg */ 49 FIELD(NWCTRL, LOOPBACK , 0, 1) 50 FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) 51 FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) 52 FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) 53 FIELD(NWCTRL, MAN_PORT_EN , 4, 1) 54 FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) 55 FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) 56 FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) 57 FIELD(NWCTRL, BACK_PRESSURE, 8, 1) 58 FIELD(NWCTRL, TRANSMIT_START , 9, 1) 59 FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) 60 FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) 61 FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) 62 FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) 63 FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) 64 FIELD(NWCTRL, STORE_RX_TS, 15, 1) 65 FIELD(NWCTRL, PFC_ENABLE, 16, 1) 66 FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) 67 FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) 68 FIELD(NWCTRL, TX_LPI_EN, 19, 1) 69 FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) 70 FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) 71 FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) 72 FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) 73 FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) 74 FIELD(NWCTRL, PFC_CTRL , 25, 1) 75 FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) 76 FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) 77 FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) 78 FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) 79 FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) 80 81 REG32(NWCFG, 0x4) /* Network Config reg */ 82 REG32(NWSTATUS, 0x8) /* Network Status reg */ 83 REG32(USERIO, 0xc) /* User IO reg */ 84 REG32(DMACFG, 0x10) /* DMA Control reg */ 85 REG32(TXSTATUS, 0x14) /* TX Status reg */ 86 REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 87 REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 88 REG32(RXSTATUS, 0x20) /* RX Status reg */ 89 REG32(ISR, 0x24) /* Interrupt Status reg */ 90 REG32(IER, 0x28) /* Interrupt Enable reg */ 91 REG32(IDR, 0x2c) /* Interrupt Disable reg */ 92 REG32(IMR, 0x30) /* Interrupt Mask reg */ 93 REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 94 REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 95 REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 96 REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 97 REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 98 REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 99 REG32(HASHLO, 0x80) /* Hash Low address reg */ 100 REG32(HASHHI, 0x84) /* Hash High address reg */ 101 REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 102 REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 103 REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 104 REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 105 REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 106 REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 107 REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 108 REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 109 REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 110 REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 111 REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 112 REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 113 REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 114 REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 115 REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 116 REG32(MODID, 0xfc) /* Module ID reg */ 117 REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 118 REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 119 REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 120 REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 121 REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 122 REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 123 REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 124 REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 125 REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 126 REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 127 REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 128 REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 129 REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 130 REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 131 REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 132 REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 133 REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 134 REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 135 REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 136 REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 137 REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 138 REG32(OCTRXHI, 0x154) /* Octects Received register High */ 139 REG32(RXCNT, 0x158) /* Error-free Frames Received */ 140 REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 141 REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 142 REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 143 REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 144 REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 145 REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 146 REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 147 REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 148 REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 149 REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 150 REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 151 REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 152 REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 153 REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 154 REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 155 REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 156 REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 157 REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 158 REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 159 REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 160 REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 161 REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 162 163 REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 164 REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 165 REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 166 REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 167 REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 168 REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 169 REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 170 REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 171 REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 172 REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 173 REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 174 REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 175 176 /* Design Configuration Registers */ 177 REG32(DESCONF, 0x280) 178 REG32(DESCONF2, 0x284) 179 REG32(DESCONF3, 0x288) 180 REG32(DESCONF4, 0x28c) 181 REG32(DESCONF5, 0x290) 182 REG32(DESCONF6, 0x294) 183 #define GEM_DESCONF6_64B_MASK (1U << 23) 184 REG32(DESCONF7, 0x298) 185 186 REG32(INT_Q1_STATUS, 0x400) 187 REG32(INT_Q1_MASK, 0x640) 188 189 REG32(TRANSMIT_Q1_PTR, 0x440) 190 REG32(TRANSMIT_Q7_PTR, 0x458) 191 192 REG32(RECEIVE_Q1_PTR, 0x480) 193 REG32(RECEIVE_Q7_PTR, 0x498) 194 195 REG32(TBQPH, 0x4c8) 196 REG32(RBQPH, 0x4d4) 197 198 REG32(INT_Q1_ENABLE, 0x600) 199 REG32(INT_Q7_ENABLE, 0x618) 200 201 REG32(INT_Q1_DISABLE, 0x620) 202 REG32(INT_Q7_DISABLE, 0x638) 203 204 REG32(SCREENING_TYPE1_REG0, 0x500) 205 FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) 206 FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) 207 FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) 208 FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) 209 FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) 210 FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) 211 212 REG32(SCREENING_TYPE2_REG0, 0x540) 213 FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) 214 FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) 215 FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) 216 FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) 217 FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) 218 FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) 219 FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) 220 FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) 221 FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) 222 FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) 223 FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) 224 FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) 225 226 REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 227 228 REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 229 FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) 230 FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) 231 232 REG32(TYPE2_COMPARE_0_WORD_1, 0x704) 233 FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) 234 FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) 235 FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) 236 FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) 237 238 /*****************************************/ 239 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 240 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 241 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 242 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 243 #define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ 244 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 245 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 246 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 247 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 248 #define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ 249 250 #define GEM_DMACFG_ADDR_64B (1U << 30) 251 #define GEM_DMACFG_TX_BD_EXT (1U << 29) 252 #define GEM_DMACFG_RX_BD_EXT (1U << 28) 253 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 254 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 255 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 256 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 257 258 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 259 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 260 261 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 262 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 263 264 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 265 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 266 #define GEM_INT_AMBA_ERR 0x00000040 267 #define GEM_INT_TXUSED 0x00000008 268 #define GEM_INT_RXUSED 0x00000004 269 #define GEM_INT_RXCMPL 0x00000002 270 271 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 272 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 273 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 274 #define GEM_PHYMNTNC_ADDR_SHFT 23 275 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 276 #define GEM_PHYMNTNC_REG_SHIFT 18 277 278 /* Marvell PHY definitions */ 279 #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 280 281 #define PHY_REG_CONTROL 0 282 #define PHY_REG_STATUS 1 283 #define PHY_REG_PHYID1 2 284 #define PHY_REG_PHYID2 3 285 #define PHY_REG_ANEGADV 4 286 #define PHY_REG_LINKPABIL 5 287 #define PHY_REG_ANEGEXP 6 288 #define PHY_REG_NEXTP 7 289 #define PHY_REG_LINKPNEXTP 8 290 #define PHY_REG_100BTCTRL 9 291 #define PHY_REG_1000BTSTAT 10 292 #define PHY_REG_EXTSTAT 15 293 #define PHY_REG_PHYSPCFC_CTL 16 294 #define PHY_REG_PHYSPCFC_ST 17 295 #define PHY_REG_INT_EN 18 296 #define PHY_REG_INT_ST 19 297 #define PHY_REG_EXT_PHYSPCFC_CTL 20 298 #define PHY_REG_RXERR 21 299 #define PHY_REG_EACD 22 300 #define PHY_REG_LED 24 301 #define PHY_REG_LED_OVRD 25 302 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 303 #define PHY_REG_EXT_PHYSPCFC_ST 27 304 #define PHY_REG_CABLE_DIAG 28 305 306 #define PHY_REG_CONTROL_RST 0x8000 307 #define PHY_REG_CONTROL_LOOP 0x4000 308 #define PHY_REG_CONTROL_ANEG 0x1000 309 #define PHY_REG_CONTROL_ANRESTART 0x0200 310 311 #define PHY_REG_STATUS_LINK 0x0004 312 #define PHY_REG_STATUS_ANEGCMPL 0x0020 313 314 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 315 #define PHY_REG_INT_ST_LINKC 0x0400 316 #define PHY_REG_INT_ST_ENERGY 0x0010 317 318 /***********************************************************************/ 319 #define GEM_RX_REJECT (-1) 320 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 321 #define GEM_RX_BROADCAST_ACCEPT (-3) 322 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 323 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 324 325 #define GEM_RX_SAR_ACCEPT 0 326 327 /***********************************************************************/ 328 329 #define DESC_1_USED 0x80000000 330 #define DESC_1_LENGTH 0x00001FFF 331 332 #define DESC_1_TX_WRAP 0x40000000 333 #define DESC_1_TX_LAST 0x00008000 334 335 #define DESC_0_RX_WRAP 0x00000002 336 #define DESC_0_RX_OWNERSHIP 0x00000001 337 338 #define R_DESC_1_RX_SAR_SHIFT 25 339 #define R_DESC_1_RX_SAR_LENGTH 2 340 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 341 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 342 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 343 #define R_DESC_1_RX_BROADCAST (1 << 31) 344 345 #define DESC_1_RX_SOF 0x00004000 346 #define DESC_1_RX_EOF 0x00008000 347 348 #define GEM_MODID_VALUE 0x00020118 349 350 static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 351 { 352 uint64_t ret = desc[0]; 353 354 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 355 ret |= (uint64_t)desc[2] << 32; 356 } 357 return ret; 358 } 359 360 static inline unsigned tx_desc_get_used(uint32_t *desc) 361 { 362 return (desc[1] & DESC_1_USED) ? 1 : 0; 363 } 364 365 static inline void tx_desc_set_used(uint32_t *desc) 366 { 367 desc[1] |= DESC_1_USED; 368 } 369 370 static inline unsigned tx_desc_get_wrap(uint32_t *desc) 371 { 372 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 373 } 374 375 static inline unsigned tx_desc_get_last(uint32_t *desc) 376 { 377 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 378 } 379 380 static inline unsigned tx_desc_get_length(uint32_t *desc) 381 { 382 return desc[1] & DESC_1_LENGTH; 383 } 384 385 static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 386 { 387 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 388 DB_PRINT("bufaddr: 0x%08x\n", *desc); 389 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 390 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 391 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 392 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 393 } 394 395 static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 396 { 397 uint64_t ret = desc[0] & ~0x3UL; 398 399 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 400 ret |= (uint64_t)desc[2] << 32; 401 } 402 return ret; 403 } 404 405 static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 406 { 407 int ret = 2; 408 409 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 410 ret += 2; 411 } 412 if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 413 : GEM_DMACFG_TX_BD_EXT)) { 414 ret += 2; 415 } 416 417 assert(ret <= DESC_MAX_NUM_WORDS); 418 return ret; 419 } 420 421 static inline unsigned rx_desc_get_wrap(uint32_t *desc) 422 { 423 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 424 } 425 426 static inline unsigned rx_desc_get_ownership(uint32_t *desc) 427 { 428 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 429 } 430 431 static inline void rx_desc_set_ownership(uint32_t *desc) 432 { 433 desc[0] |= DESC_0_RX_OWNERSHIP; 434 } 435 436 static inline void rx_desc_set_sof(uint32_t *desc) 437 { 438 desc[1] |= DESC_1_RX_SOF; 439 } 440 441 static inline void rx_desc_clear_control(uint32_t *desc) 442 { 443 desc[1] = 0; 444 } 445 446 static inline void rx_desc_set_eof(uint32_t *desc) 447 { 448 desc[1] |= DESC_1_RX_EOF; 449 } 450 451 static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 452 { 453 desc[1] &= ~DESC_1_LENGTH; 454 desc[1] |= len; 455 } 456 457 static inline void rx_desc_set_broadcast(uint32_t *desc) 458 { 459 desc[1] |= R_DESC_1_RX_BROADCAST; 460 } 461 462 static inline void rx_desc_set_unicast_hash(uint32_t *desc) 463 { 464 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 465 } 466 467 static inline void rx_desc_set_multicast_hash(uint32_t *desc) 468 { 469 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 470 } 471 472 static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 473 { 474 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 475 sar_idx); 476 desc[1] |= R_DESC_1_RX_SAR_MATCH; 477 } 478 479 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 480 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 481 482 static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 483 { 484 uint32_t size; 485 if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { 486 size = s->regs[R_JUMBO_MAX_LEN]; 487 if (size > s->jumbo_max_len) { 488 size = s->jumbo_max_len; 489 qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 490 " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 491 } 492 } else if (tx) { 493 size = 1518; 494 } else { 495 size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; 496 } 497 return size; 498 } 499 500 static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 501 { 502 if (q == 0) { 503 s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 504 } else { 505 s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 506 ~(s->regs[R_INT_Q1_MASK + q - 1]); 507 } 508 } 509 510 /* 511 * gem_init_register_masks: 512 * One time initialization. 513 * Set masks to identify which register bits have magical clear properties 514 */ 515 static void gem_init_register_masks(CadenceGEMState *s) 516 { 517 unsigned int i; 518 /* Mask of register bits which are read only */ 519 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 520 s->regs_ro[R_NWCTRL] = 0xFFF80000; 521 s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 522 s->regs_ro[R_DMACFG] = 0x8E00F000; 523 s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 524 s->regs_ro[R_RXQBASE] = 0x00000003; 525 s->regs_ro[R_TXQBASE] = 0x00000003; 526 s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 527 s->regs_ro[R_ISR] = 0xFFFFFFFF; 528 s->regs_ro[R_IMR] = 0xFFFFFFFF; 529 s->regs_ro[R_MODID] = 0xFFFFFFFF; 530 for (i = 0; i < s->num_priority_queues; i++) { 531 s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 532 s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 533 s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 534 s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 535 } 536 537 /* Mask of register bits which are clear on read */ 538 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 539 s->regs_rtc[R_ISR] = 0xFFFFFFFF; 540 for (i = 0; i < s->num_priority_queues; i++) { 541 s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 542 } 543 544 /* Mask of register bits which are write 1 to clear */ 545 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 546 s->regs_w1c[R_TXSTATUS] = 0x000001F7; 547 s->regs_w1c[R_RXSTATUS] = 0x0000000F; 548 549 /* Mask of register bits which are write only */ 550 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 551 s->regs_wo[R_NWCTRL] = 0x00073E60; 552 s->regs_wo[R_IER] = 0x07FFFFFF; 553 s->regs_wo[R_IDR] = 0x07FFFFFF; 554 for (i = 0; i < s->num_priority_queues; i++) { 555 s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 556 s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 557 } 558 } 559 560 /* 561 * phy_update_link: 562 * Make the emulated PHY link state match the QEMU "interface" state. 563 */ 564 static void phy_update_link(CadenceGEMState *s) 565 { 566 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 567 568 /* Autonegotiation status mirrors link status. */ 569 if (qemu_get_queue(s->nic)->link_down) { 570 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 571 PHY_REG_STATUS_LINK); 572 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 573 } else { 574 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 575 PHY_REG_STATUS_LINK); 576 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 577 PHY_REG_INT_ST_ANEGCMPL | 578 PHY_REG_INT_ST_ENERGY); 579 } 580 } 581 582 static bool gem_can_receive(NetClientState *nc) 583 { 584 CadenceGEMState *s; 585 int i; 586 587 s = qemu_get_nic_opaque(nc); 588 589 /* Do nothing if receive is not enabled. */ 590 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { 591 if (s->can_rx_state != 1) { 592 s->can_rx_state = 1; 593 DB_PRINT("can't receive - no enable\n"); 594 } 595 return false; 596 } 597 598 for (i = 0; i < s->num_priority_queues; i++) { 599 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 600 break; 601 } 602 }; 603 604 if (i == s->num_priority_queues) { 605 if (s->can_rx_state != 2) { 606 s->can_rx_state = 2; 607 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 608 } 609 return false; 610 } 611 612 if (s->can_rx_state != 0) { 613 s->can_rx_state = 0; 614 DB_PRINT("can receive\n"); 615 } 616 return true; 617 } 618 619 /* 620 * gem_update_int_status: 621 * Raise or lower interrupt based on current status. 622 */ 623 static void gem_update_int_status(CadenceGEMState *s) 624 { 625 int i; 626 627 qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 628 629 for (i = 1; i < s->num_priority_queues; ++i) { 630 qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 631 } 632 } 633 634 /* 635 * gem_receive_updatestats: 636 * Increment receive statistics. 637 */ 638 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 639 unsigned bytes) 640 { 641 uint64_t octets; 642 643 /* Total octets (bytes) received */ 644 octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 645 s->regs[R_OCTRXHI]; 646 octets += bytes; 647 s->regs[R_OCTRXLO] = octets >> 32; 648 s->regs[R_OCTRXHI] = octets; 649 650 /* Error-free Frames received */ 651 s->regs[R_RXCNT]++; 652 653 /* Error-free Broadcast Frames counter */ 654 if (!memcmp(packet, broadcast_addr, 6)) { 655 s->regs[R_RXBROADCNT]++; 656 } 657 658 /* Error-free Multicast Frames counter */ 659 if (packet[0] == 0x01) { 660 s->regs[R_RXMULTICNT]++; 661 } 662 663 if (bytes <= 64) { 664 s->regs[R_RX64CNT]++; 665 } else if (bytes <= 127) { 666 s->regs[R_RX65CNT]++; 667 } else if (bytes <= 255) { 668 s->regs[R_RX128CNT]++; 669 } else if (bytes <= 511) { 670 s->regs[R_RX256CNT]++; 671 } else if (bytes <= 1023) { 672 s->regs[R_RX512CNT]++; 673 } else if (bytes <= 1518) { 674 s->regs[R_RX1024CNT]++; 675 } else { 676 s->regs[R_RX1519CNT]++; 677 } 678 } 679 680 /* 681 * Get the MAC Address bit from the specified position 682 */ 683 static unsigned get_bit(const uint8_t *mac, unsigned bit) 684 { 685 unsigned byte; 686 687 byte = mac[bit / 8]; 688 byte >>= (bit & 0x7); 689 byte &= 1; 690 691 return byte; 692 } 693 694 /* 695 * Calculate a GEM MAC Address hash index 696 */ 697 static unsigned calc_mac_hash(const uint8_t *mac) 698 { 699 int index_bit, mac_bit; 700 unsigned hash_index; 701 702 hash_index = 0; 703 mac_bit = 5; 704 for (index_bit = 5; index_bit >= 0; index_bit--) { 705 hash_index |= (get_bit(mac, mac_bit) ^ 706 get_bit(mac, mac_bit + 6) ^ 707 get_bit(mac, mac_bit + 12) ^ 708 get_bit(mac, mac_bit + 18) ^ 709 get_bit(mac, mac_bit + 24) ^ 710 get_bit(mac, mac_bit + 30) ^ 711 get_bit(mac, mac_bit + 36) ^ 712 get_bit(mac, mac_bit + 42)) << index_bit; 713 mac_bit--; 714 } 715 716 return hash_index; 717 } 718 719 /* 720 * gem_mac_address_filter: 721 * Accept or reject this destination address? 722 * Returns: 723 * GEM_RX_REJECT: reject 724 * >= 0: Specific address accept (which matched SAR is returned) 725 * others for various other modes of accept: 726 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 727 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 728 */ 729 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 730 { 731 uint8_t *gem_spaddr; 732 int i, is_mc; 733 734 /* Promiscuous mode? */ 735 if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { 736 return GEM_RX_PROMISCUOUS_ACCEPT; 737 } 738 739 if (!memcmp(packet, broadcast_addr, 6)) { 740 /* Reject broadcast packets? */ 741 if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { 742 return GEM_RX_REJECT; 743 } 744 return GEM_RX_BROADCAST_ACCEPT; 745 } 746 747 /* Accept packets -w- hash match? */ 748 is_mc = is_multicast_ether_addr(packet); 749 if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 750 (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 751 uint64_t buckets; 752 unsigned hash_index; 753 754 hash_index = calc_mac_hash(packet); 755 buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 756 if ((buckets >> hash_index) & 1) { 757 return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 758 : GEM_RX_UNICAST_HASH_ACCEPT; 759 } 760 } 761 762 /* Check all 4 specific addresses */ 763 gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 764 for (i = 3; i >= 0; i--) { 765 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 766 return GEM_RX_SAR_ACCEPT + i; 767 } 768 } 769 770 /* No address match; reject the packet */ 771 return GEM_RX_REJECT; 772 } 773 774 /* Figure out which queue the received data should be sent to */ 775 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 776 unsigned rxbufsize) 777 { 778 uint32_t reg; 779 bool matched, mismatched; 780 int i, j; 781 782 for (i = 0; i < s->num_type1_screeners; i++) { 783 reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 784 matched = false; 785 mismatched = false; 786 787 /* Screening is based on UDP Port */ 788 if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { 789 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 790 if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { 791 matched = true; 792 } else { 793 mismatched = true; 794 } 795 } 796 797 /* Screening is based on DS/TC */ 798 if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { 799 uint8_t dscp = rxbuf_ptr[14 + 1]; 800 if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { 801 matched = true; 802 } else { 803 mismatched = true; 804 } 805 } 806 807 if (matched && !mismatched) { 808 return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); 809 } 810 } 811 812 for (i = 0; i < s->num_type2_screeners; i++) { 813 reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 814 matched = false; 815 mismatched = false; 816 817 if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { 818 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 819 int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, 820 ETHERTYPE_REG_INDEX); 821 822 if (et_idx > s->num_type2_screeners) { 823 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 824 "register index: %d\n", et_idx); 825 } 826 if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 827 et_idx]) { 828 matched = true; 829 } else { 830 mismatched = true; 831 } 832 } 833 834 /* Compare A, B, C */ 835 for (j = 0; j < 3; j++) { 836 uint32_t cr0, cr1, mask, compare; 837 uint16_t rx_cmp; 838 int offset; 839 int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, 840 R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); 841 842 if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, 843 R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { 844 continue; 845 } 846 847 if (cr_idx > s->num_type2_screeners) { 848 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 849 "register index: %d\n", cr_idx); 850 } 851 852 cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 853 cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; 854 offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); 855 856 switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { 857 case 3: /* Skip UDP header */ 858 qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 859 "unimplemented - assuming UDP\n"); 860 offset += 8; 861 /* Fallthrough */ 862 case 2: /* skip the IP header */ 863 offset += 20; 864 /* Fallthrough */ 865 case 1: /* Count from after the ethertype */ 866 offset += 14; 867 break; 868 case 0: 869 /* Offset from start of frame */ 870 break; 871 } 872 873 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 874 mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); 875 compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); 876 877 if ((rx_cmp & mask) == (compare & mask)) { 878 matched = true; 879 } else { 880 mismatched = true; 881 } 882 } 883 884 if (matched && !mismatched) { 885 return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); 886 } 887 } 888 889 /* We made it here, assume it's queue 0 */ 890 return 0; 891 } 892 893 static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 894 { 895 uint32_t base_addr = 0; 896 897 switch (q) { 898 case 0: 899 base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 900 break; 901 case 1 ... (MAX_PRIORITY_QUEUES - 1): 902 base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 903 R_RECEIVE_Q1_PTR) + q - 1]; 904 break; 905 default: 906 g_assert_not_reached(); 907 }; 908 909 return base_addr; 910 } 911 912 static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 913 { 914 return gem_get_queue_base_addr(s, true, q); 915 } 916 917 static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 918 { 919 return gem_get_queue_base_addr(s, false, q); 920 } 921 922 static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 923 { 924 hwaddr desc_addr = 0; 925 926 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 927 desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 928 } 929 desc_addr <<= 32; 930 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 931 return desc_addr; 932 } 933 934 static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 935 { 936 return gem_get_desc_addr(s, true, q); 937 } 938 939 static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 940 { 941 return gem_get_desc_addr(s, false, q); 942 } 943 944 static void gem_get_rx_desc(CadenceGEMState *s, int q) 945 { 946 hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 947 948 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 949 950 /* read current descriptor */ 951 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 952 s->rx_desc[q], 953 sizeof(uint32_t) * gem_get_desc_len(s, true)); 954 955 /* Descriptor owned by software ? */ 956 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 957 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 958 s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 959 gem_set_isr(s, q, GEM_INT_RXUSED); 960 /* Handle interrupt consequences */ 961 gem_update_int_status(s); 962 } 963 } 964 965 /* 966 * gem_receive: 967 * Fit a packet handed to us by QEMU into the receive descriptor ring. 968 */ 969 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 970 { 971 CadenceGEMState *s = qemu_get_nic_opaque(nc); 972 unsigned rxbufsize, bytes_to_copy; 973 unsigned rxbuf_offset; 974 uint8_t *rxbuf_ptr; 975 bool first_desc = true; 976 int maf; 977 int q = 0; 978 979 /* Is this destination MAC address "for us" ? */ 980 maf = gem_mac_address_filter(s, buf); 981 if (maf == GEM_RX_REJECT) { 982 return size; /* no, drop silently b/c it's not an error */ 983 } 984 985 /* Discard packets with receive length error enabled ? */ 986 if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { 987 unsigned type_len; 988 989 /* Fish the ethertype / length field out of the RX packet */ 990 type_len = buf[12] << 8 | buf[13]; 991 /* It is a length field, not an ethertype */ 992 if (type_len < 0x600) { 993 if (size < type_len) { 994 /* discard */ 995 return -1; 996 } 997 } 998 } 999 1000 /* 1001 * Determine configured receive buffer offset (probably 0) 1002 */ 1003 rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 1004 GEM_NWCFG_BUFF_OFST_S; 1005 1006 /* The configure size of each receive buffer. Determines how many 1007 * buffers needed to hold this packet. 1008 */ 1009 rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 1010 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 1011 bytes_to_copy = size; 1012 1013 /* Hardware allows a zero value here but warns against it. To avoid QEMU 1014 * indefinite loops we enforce a minimum value here 1015 */ 1016 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1017 rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1018 } 1019 1020 /* Pad to minimum length. Assume FCS field is stripped, logic 1021 * below will increment it to the real minimum of 64 when 1022 * not FCS stripping 1023 */ 1024 if (size < 60) { 1025 size = 60; 1026 } 1027 1028 /* Strip of FCS field ? (usually yes) */ 1029 if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { 1030 rxbuf_ptr = (void *)buf; 1031 } else { 1032 unsigned crc_val; 1033 1034 if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 1035 size = MAX_FRAME_SIZE - sizeof(crc_val); 1036 } 1037 bytes_to_copy = size; 1038 /* The application wants the FCS field, which QEMU does not provide. 1039 * We must try and calculate one. 1040 */ 1041 1042 memcpy(s->rx_packet, buf, size); 1043 memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 1044 rxbuf_ptr = s->rx_packet; 1045 crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 1046 memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 1047 1048 bytes_to_copy += 4; 1049 size += 4; 1050 } 1051 1052 DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 1053 1054 /* Find which queue we are targeting */ 1055 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1056 1057 if (size > gem_get_max_buf_len(s, false)) { 1058 qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 1059 gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1060 return -1; 1061 } 1062 1063 while (bytes_to_copy) { 1064 hwaddr desc_addr; 1065 1066 /* Do nothing if receive is not enabled. */ 1067 if (!gem_can_receive(nc)) { 1068 return -1; 1069 } 1070 1071 DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1072 MIN(bytes_to_copy, rxbufsize), 1073 rx_desc_get_buffer(s, s->rx_desc[q])); 1074 1075 /* Copy packet data to emulated DMA buffer */ 1076 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 1077 rxbuf_offset, 1078 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1079 MIN(bytes_to_copy, rxbufsize)); 1080 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 1081 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 1082 1083 rx_desc_clear_control(s->rx_desc[q]); 1084 1085 /* Update the descriptor. */ 1086 if (first_desc) { 1087 rx_desc_set_sof(s->rx_desc[q]); 1088 first_desc = false; 1089 } 1090 if (bytes_to_copy == 0) { 1091 rx_desc_set_eof(s->rx_desc[q]); 1092 rx_desc_set_length(s->rx_desc[q], size); 1093 } 1094 rx_desc_set_ownership(s->rx_desc[q]); 1095 1096 switch (maf) { 1097 case GEM_RX_PROMISCUOUS_ACCEPT: 1098 break; 1099 case GEM_RX_BROADCAST_ACCEPT: 1100 rx_desc_set_broadcast(s->rx_desc[q]); 1101 break; 1102 case GEM_RX_UNICAST_HASH_ACCEPT: 1103 rx_desc_set_unicast_hash(s->rx_desc[q]); 1104 break; 1105 case GEM_RX_MULTICAST_HASH_ACCEPT: 1106 rx_desc_set_multicast_hash(s->rx_desc[q]); 1107 break; 1108 case GEM_RX_REJECT: 1109 abort(); 1110 default: /* SAR */ 1111 rx_desc_set_sar(s->rx_desc[q], maf); 1112 } 1113 1114 /* Descriptor write-back. */ 1115 desc_addr = gem_get_rx_desc_addr(s, q); 1116 address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1117 s->rx_desc[q], 1118 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1119 1120 /* Next descriptor */ 1121 if (rx_desc_get_wrap(s->rx_desc[q])) { 1122 DB_PRINT("wrapping RX descriptor list\n"); 1123 s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 1124 } else { 1125 DB_PRINT("incrementing RX descriptor list\n"); 1126 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 1127 } 1128 1129 gem_get_rx_desc(s, q); 1130 } 1131 1132 /* Count it */ 1133 gem_receive_updatestats(s, buf, size); 1134 1135 s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 1136 gem_set_isr(s, q, GEM_INT_RXCMPL); 1137 1138 /* Handle interrupt consequences */ 1139 gem_update_int_status(s); 1140 1141 return size; 1142 } 1143 1144 /* 1145 * gem_transmit_updatestats: 1146 * Increment transmit statistics. 1147 */ 1148 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 1149 unsigned bytes) 1150 { 1151 uint64_t octets; 1152 1153 /* Total octets (bytes) transmitted */ 1154 octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1155 s->regs[R_OCTTXHI]; 1156 octets += bytes; 1157 s->regs[R_OCTTXLO] = octets >> 32; 1158 s->regs[R_OCTTXHI] = octets; 1159 1160 /* Error-free Frames transmitted */ 1161 s->regs[R_TXCNT]++; 1162 1163 /* Error-free Broadcast Frames counter */ 1164 if (!memcmp(packet, broadcast_addr, 6)) { 1165 s->regs[R_TXBCNT]++; 1166 } 1167 1168 /* Error-free Multicast Frames counter */ 1169 if (packet[0] == 0x01) { 1170 s->regs[R_TXMCNT]++; 1171 } 1172 1173 if (bytes <= 64) { 1174 s->regs[R_TX64CNT]++; 1175 } else if (bytes <= 127) { 1176 s->regs[R_TX65CNT]++; 1177 } else if (bytes <= 255) { 1178 s->regs[R_TX128CNT]++; 1179 } else if (bytes <= 511) { 1180 s->regs[R_TX256CNT]++; 1181 } else if (bytes <= 1023) { 1182 s->regs[R_TX512CNT]++; 1183 } else if (bytes <= 1518) { 1184 s->regs[R_TX1024CNT]++; 1185 } else { 1186 s->regs[R_TX1519CNT]++; 1187 } 1188 } 1189 1190 /* 1191 * gem_transmit: 1192 * Fish packets out of the descriptor ring and feed them to QEMU 1193 */ 1194 static void gem_transmit(CadenceGEMState *s) 1195 { 1196 uint32_t desc[DESC_MAX_NUM_WORDS]; 1197 hwaddr packet_desc_addr; 1198 uint8_t *p; 1199 unsigned total_bytes; 1200 int q = 0; 1201 1202 /* Do nothing if transmit is not enabled. */ 1203 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 1204 return; 1205 } 1206 1207 DB_PRINT("\n"); 1208 1209 /* The packet we will hand off to QEMU. 1210 * Packets scattered across multiple descriptors are gathered to this 1211 * one contiguous buffer first. 1212 */ 1213 p = s->tx_packet; 1214 total_bytes = 0; 1215 1216 for (q = s->num_priority_queues - 1; q >= 0; q--) { 1217 /* read current descriptor */ 1218 packet_desc_addr = gem_get_tx_desc_addr(s, q); 1219 1220 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1221 address_space_read(&s->dma_as, packet_desc_addr, 1222 MEMTXATTRS_UNSPECIFIED, desc, 1223 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1224 /* Handle all descriptors owned by hardware */ 1225 while (tx_desc_get_used(desc) == 0) { 1226 1227 /* Do nothing if transmit is not enabled. */ 1228 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 1229 return; 1230 } 1231 print_gem_tx_desc(desc, q); 1232 1233 /* The real hardware would eat this (and possibly crash). 1234 * For QEMU let's lend a helping hand. 1235 */ 1236 if ((tx_desc_get_buffer(s, desc) == 0) || 1237 (tx_desc_get_length(desc) == 0)) { 1238 DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 1239 packet_desc_addr); 1240 break; 1241 } 1242 1243 if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 1244 (p - s->tx_packet)) { 1245 qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 1246 HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1247 packet_desc_addr, tx_desc_get_length(desc), 1248 gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 1249 gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1250 break; 1251 } 1252 1253 /* Gather this fragment of the packet from "dma memory" to our 1254 * contig buffer. 1255 */ 1256 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 1257 MEMTXATTRS_UNSPECIFIED, 1258 p, tx_desc_get_length(desc)); 1259 p += tx_desc_get_length(desc); 1260 total_bytes += tx_desc_get_length(desc); 1261 1262 /* Last descriptor for this packet; hand the whole thing off */ 1263 if (tx_desc_get_last(desc)) { 1264 uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1265 hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 1266 1267 /* Modify the 1st descriptor of this packet to be owned by 1268 * the processor. 1269 */ 1270 address_space_read(&s->dma_as, desc_addr, 1271 MEMTXATTRS_UNSPECIFIED, desc_first, 1272 sizeof(desc_first)); 1273 tx_desc_set_used(desc_first); 1274 address_space_write(&s->dma_as, desc_addr, 1275 MEMTXATTRS_UNSPECIFIED, desc_first, 1276 sizeof(desc_first)); 1277 /* Advance the hardware current descriptor past this packet */ 1278 if (tx_desc_get_wrap(desc)) { 1279 s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 1280 } else { 1281 s->tx_desc_addr[q] = packet_desc_addr + 1282 4 * gem_get_desc_len(s, false); 1283 } 1284 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 1285 1286 s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 1287 gem_set_isr(s, q, GEM_INT_TXCMPL); 1288 1289 /* Handle interrupt consequences */ 1290 gem_update_int_status(s); 1291 1292 /* Is checksum offload enabled? */ 1293 if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1294 net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 1295 } 1296 1297 /* Update MAC statistics */ 1298 gem_transmit_updatestats(s, s->tx_packet, total_bytes); 1299 1300 /* Send the packet somewhere */ 1301 if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, 1302 LOOPBACK_LOCAL)) { 1303 qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 1304 total_bytes); 1305 } else { 1306 qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 1307 total_bytes); 1308 } 1309 1310 /* Prepare for next packet */ 1311 p = s->tx_packet; 1312 total_bytes = 0; 1313 } 1314 1315 /* read next descriptor */ 1316 if (tx_desc_get_wrap(desc)) { 1317 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 1318 packet_desc_addr = s->regs[R_TBQPH]; 1319 packet_desc_addr <<= 32; 1320 } else { 1321 packet_desc_addr = 0; 1322 } 1323 packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 1324 } else { 1325 packet_desc_addr += 4 * gem_get_desc_len(s, false); 1326 } 1327 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1328 address_space_read(&s->dma_as, packet_desc_addr, 1329 MEMTXATTRS_UNSPECIFIED, desc, 1330 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1331 } 1332 1333 if (tx_desc_get_used(desc)) { 1334 s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; 1335 /* IRQ TXUSED is defined only for queue 0 */ 1336 if (q == 0) { 1337 gem_set_isr(s, 0, GEM_INT_TXUSED); 1338 } 1339 gem_update_int_status(s); 1340 } 1341 } 1342 } 1343 1344 static void gem_phy_reset(CadenceGEMState *s) 1345 { 1346 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 1347 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 1348 s->phy_regs[PHY_REG_STATUS] = 0x7969; 1349 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 1350 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 1351 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 1352 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 1353 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 1354 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 1355 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 1356 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 1357 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 1358 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 1359 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 1360 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 1361 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 1362 s->phy_regs[PHY_REG_LED] = 0x4100; 1363 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 1364 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 1365 1366 phy_update_link(s); 1367 } 1368 1369 static void gem_reset(DeviceState *d) 1370 { 1371 int i; 1372 CadenceGEMState *s = CADENCE_GEM(d); 1373 const uint8_t *a; 1374 uint32_t queues_mask = 0; 1375 1376 DB_PRINT("\n"); 1377 1378 /* Set post reset register values */ 1379 memset(&s->regs[0], 0, sizeof(s->regs)); 1380 s->regs[R_NWCFG] = 0x00080000; 1381 s->regs[R_NWSTATUS] = 0x00000006; 1382 s->regs[R_DMACFG] = 0x00020784; 1383 s->regs[R_IMR] = 0x07ffffff; 1384 s->regs[R_TXPAUSE] = 0x0000ffff; 1385 s->regs[R_TXPARTIALSF] = 0x000003ff; 1386 s->regs[R_RXPARTIALSF] = 0x000003ff; 1387 s->regs[R_MODID] = s->revision; 1388 s->regs[R_DESCONF] = 0x02D00111; 1389 s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1390 s->regs[R_DESCONF5] = 0x002f2045; 1391 s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; 1392 s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1393 s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1394 1395 if (s->num_priority_queues > 1) { 1396 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1397 s->regs[R_DESCONF6] |= queues_mask; 1398 } 1399 1400 /* Set MAC address */ 1401 a = &s->conf.macaddr.a[0]; 1402 s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1403 s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1404 1405 for (i = 0; i < 4; i++) { 1406 s->sar_active[i] = false; 1407 } 1408 1409 gem_phy_reset(s); 1410 1411 gem_update_int_status(s); 1412 } 1413 1414 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1415 { 1416 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1417 return s->phy_regs[reg_num]; 1418 } 1419 1420 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1421 { 1422 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1423 1424 switch (reg_num) { 1425 case PHY_REG_CONTROL: 1426 if (val & PHY_REG_CONTROL_RST) { 1427 /* Phy reset */ 1428 gem_phy_reset(s); 1429 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1430 s->phy_loop = 0; 1431 } 1432 if (val & PHY_REG_CONTROL_ANEG) { 1433 /* Complete autonegotiation immediately */ 1434 val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 1435 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1436 } 1437 if (val & PHY_REG_CONTROL_LOOP) { 1438 DB_PRINT("PHY placed in loopback\n"); 1439 s->phy_loop = 1; 1440 } else { 1441 s->phy_loop = 0; 1442 } 1443 break; 1444 } 1445 s->phy_regs[reg_num] = val; 1446 } 1447 1448 /* 1449 * gem_read32: 1450 * Read a GEM register. 1451 */ 1452 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1453 { 1454 CadenceGEMState *s; 1455 uint32_t retval; 1456 s = opaque; 1457 1458 offset >>= 2; 1459 retval = s->regs[offset]; 1460 1461 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1462 1463 switch (offset) { 1464 case R_ISR: 1465 DB_PRINT("lowering irqs on ISR read\n"); 1466 /* The interrupts get updated at the end of the function. */ 1467 break; 1468 case R_PHYMNTNC: 1469 if (retval & GEM_PHYMNTNC_OP_R) { 1470 uint32_t phy_addr, reg_num; 1471 1472 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1473 if (phy_addr == s->phy_addr) { 1474 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1475 retval &= 0xFFFF0000; 1476 retval |= gem_phy_read(s, reg_num); 1477 } else { 1478 retval |= 0xFFFF; /* No device at this address */ 1479 } 1480 } 1481 break; 1482 } 1483 1484 /* Squash read to clear bits */ 1485 s->regs[offset] &= ~(s->regs_rtc[offset]); 1486 1487 /* Do not provide write only bits */ 1488 retval &= ~(s->regs_wo[offset]); 1489 1490 DB_PRINT("0x%08x\n", retval); 1491 gem_update_int_status(s); 1492 return retval; 1493 } 1494 1495 /* 1496 * gem_write32: 1497 * Write a GEM register. 1498 */ 1499 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1500 unsigned size) 1501 { 1502 CadenceGEMState *s = (CadenceGEMState *)opaque; 1503 uint32_t readonly; 1504 int i; 1505 1506 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1507 offset >>= 2; 1508 1509 /* Squash bits which are read only in write value */ 1510 val &= ~(s->regs_ro[offset]); 1511 /* Preserve (only) bits which are read only and wtc in register */ 1512 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1513 1514 /* Copy register write to backing store */ 1515 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1516 1517 /* do w1c */ 1518 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1519 1520 /* Handle register write side effects */ 1521 switch (offset) { 1522 case R_NWCTRL: 1523 if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { 1524 for (i = 0; i < s->num_priority_queues; ++i) { 1525 gem_get_rx_desc(s, i); 1526 } 1527 } 1528 if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { 1529 gem_transmit(s); 1530 } 1531 if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { 1532 /* Reset to start of Q when transmit disabled. */ 1533 for (i = 0; i < s->num_priority_queues; i++) { 1534 s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 1535 } 1536 } 1537 if (gem_can_receive(qemu_get_queue(s->nic))) { 1538 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1539 } 1540 break; 1541 1542 case R_TXSTATUS: 1543 gem_update_int_status(s); 1544 break; 1545 case R_RXQBASE: 1546 s->rx_desc_addr[0] = val; 1547 break; 1548 case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1549 s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 1550 break; 1551 case R_TXQBASE: 1552 s->tx_desc_addr[0] = val; 1553 break; 1554 case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1555 s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 1556 break; 1557 case R_RXSTATUS: 1558 gem_update_int_status(s); 1559 break; 1560 case R_IER: 1561 s->regs[R_IMR] &= ~val; 1562 gem_update_int_status(s); 1563 break; 1564 case R_JUMBO_MAX_LEN: 1565 s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 1566 break; 1567 case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1568 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 1569 gem_update_int_status(s); 1570 break; 1571 case R_IDR: 1572 s->regs[R_IMR] |= val; 1573 gem_update_int_status(s); 1574 break; 1575 case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1576 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 1577 gem_update_int_status(s); 1578 break; 1579 case R_SPADDR1LO: 1580 case R_SPADDR2LO: 1581 case R_SPADDR3LO: 1582 case R_SPADDR4LO: 1583 s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 1584 break; 1585 case R_SPADDR1HI: 1586 case R_SPADDR2HI: 1587 case R_SPADDR3HI: 1588 case R_SPADDR4HI: 1589 s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 1590 break; 1591 case R_PHYMNTNC: 1592 if (val & GEM_PHYMNTNC_OP_W) { 1593 uint32_t phy_addr, reg_num; 1594 1595 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1596 if (phy_addr == s->phy_addr) { 1597 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1598 gem_phy_write(s, reg_num, val); 1599 } 1600 } 1601 break; 1602 } 1603 1604 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1605 } 1606 1607 static const MemoryRegionOps gem_ops = { 1608 .read = gem_read, 1609 .write = gem_write, 1610 .endianness = DEVICE_LITTLE_ENDIAN, 1611 }; 1612 1613 static void gem_set_link(NetClientState *nc) 1614 { 1615 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1616 1617 DB_PRINT("\n"); 1618 phy_update_link(s); 1619 gem_update_int_status(s); 1620 } 1621 1622 static NetClientInfo net_gem_info = { 1623 .type = NET_CLIENT_DRIVER_NIC, 1624 .size = sizeof(NICState), 1625 .can_receive = gem_can_receive, 1626 .receive = gem_receive, 1627 .link_status_changed = gem_set_link, 1628 }; 1629 1630 static void gem_realize(DeviceState *dev, Error **errp) 1631 { 1632 CadenceGEMState *s = CADENCE_GEM(dev); 1633 int i; 1634 1635 address_space_init(&s->dma_as, 1636 s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 1637 1638 if (s->num_priority_queues == 0 || 1639 s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1640 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1641 s->num_priority_queues); 1642 return; 1643 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1644 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1645 s->num_type1_screeners); 1646 return; 1647 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1648 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1649 s->num_type2_screeners); 1650 return; 1651 } 1652 1653 for (i = 0; i < s->num_priority_queues; ++i) { 1654 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1655 } 1656 1657 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1658 1659 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1660 object_get_typename(OBJECT(dev)), dev->id, s); 1661 1662 if (s->jumbo_max_len > MAX_FRAME_SIZE) { 1663 error_setg(errp, "jumbo-max-len is greater than %d", 1664 MAX_FRAME_SIZE); 1665 return; 1666 } 1667 } 1668 1669 static void gem_init(Object *obj) 1670 { 1671 CadenceGEMState *s = CADENCE_GEM(obj); 1672 DeviceState *dev = DEVICE(obj); 1673 1674 DB_PRINT("\n"); 1675 1676 gem_init_register_masks(s); 1677 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1678 "enet", sizeof(s->regs)); 1679 1680 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1681 } 1682 1683 static const VMStateDescription vmstate_cadence_gem = { 1684 .name = "cadence_gem", 1685 .version_id = 4, 1686 .minimum_version_id = 4, 1687 .fields = (VMStateField[]) { 1688 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1689 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1690 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1691 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1692 MAX_PRIORITY_QUEUES), 1693 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1694 MAX_PRIORITY_QUEUES), 1695 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1696 VMSTATE_END_OF_LIST(), 1697 } 1698 }; 1699 1700 static Property gem_properties[] = { 1701 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1702 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1703 GEM_MODID_VALUE), 1704 DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 1705 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1706 num_priority_queues, 1), 1707 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1708 num_type1_screeners, 4), 1709 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1710 num_type2_screeners, 4), 1711 DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 1712 jumbo_max_len, 10240), 1713 DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 1714 TYPE_MEMORY_REGION, MemoryRegion *), 1715 DEFINE_PROP_END_OF_LIST(), 1716 }; 1717 1718 static void gem_class_init(ObjectClass *klass, void *data) 1719 { 1720 DeviceClass *dc = DEVICE_CLASS(klass); 1721 1722 dc->realize = gem_realize; 1723 device_class_set_props(dc, gem_properties); 1724 dc->vmsd = &vmstate_cadence_gem; 1725 dc->reset = gem_reset; 1726 } 1727 1728 static const TypeInfo gem_info = { 1729 .name = TYPE_CADENCE_GEM, 1730 .parent = TYPE_SYS_BUS_DEVICE, 1731 .instance_size = sizeof(CadenceGEMState), 1732 .instance_init = gem_init, 1733 .class_init = gem_class_init, 1734 }; 1735 1736 static void gem_register_types(void) 1737 { 1738 type_register_static(&gem_info); 1739 } 1740 1741 type_init(gem_register_types) 1742