1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/irq.h" 29 #include "hw/net/cadence_gem.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/registerfields.h" 32 #include "migration/vmstate.h" 33 #include "qapi/error.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "sysemu/dma.h" 37 #include "net/checksum.h" 38 #include "net/eth.h" 39 40 #define CADENCE_GEM_ERR_DEBUG 0 41 #define DB_PRINT(...) do {\ 42 if (CADENCE_GEM_ERR_DEBUG) { \ 43 qemu_log(": %s: ", __func__); \ 44 qemu_log(__VA_ARGS__); \ 45 } \ 46 } while (0) 47 48 REG32(NWCTRL, 0x0) /* Network Control reg */ 49 REG32(NWCFG, 0x4) /* Network Config reg */ 50 REG32(NWSTATUS, 0x8) /* Network Status reg */ 51 REG32(USERIO, 0xc) /* User IO reg */ 52 REG32(DMACFG, 0x10) /* DMA Control reg */ 53 REG32(TXSTATUS, 0x14) /* TX Status reg */ 54 REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 55 REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 56 REG32(RXSTATUS, 0x20) /* RX Status reg */ 57 REG32(ISR, 0x24) /* Interrupt Status reg */ 58 REG32(IER, 0x28) /* Interrupt Enable reg */ 59 REG32(IDR, 0x2c) /* Interrupt Disable reg */ 60 REG32(IMR, 0x30) /* Interrupt Mask reg */ 61 REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 62 REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 63 REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 64 REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 65 REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 66 REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 67 REG32(HASHLO, 0x80) /* Hash Low address reg */ 68 REG32(HASHHI, 0x84) /* Hash High address reg */ 69 REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 70 REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 71 REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 72 REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 73 REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 74 REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 75 REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 76 REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 77 REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 78 REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 79 REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 80 REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 81 REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 82 REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 83 REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 84 REG32(MODID, 0xfc) /* Module ID reg */ 85 REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 86 REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 87 REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 88 REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 89 REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 90 REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 91 REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 92 REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 93 REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 94 REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 95 REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 96 REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 97 REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 98 REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 99 REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 100 REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 101 REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 102 REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 103 REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 104 REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 105 REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 106 REG32(OCTRXHI, 0x154) /* Octects Received register High */ 107 REG32(RXCNT, 0x158) /* Error-free Frames Received */ 108 REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 109 REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 110 REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 111 REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 112 REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 113 REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 114 REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 115 REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 116 REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 117 REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 118 REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 119 REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 120 REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 121 REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 122 REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 123 REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 124 REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 125 REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 126 REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 127 REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 128 REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 129 REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 130 131 REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 132 REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 133 REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 134 REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 135 REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 136 REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 137 REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 138 REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 139 REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 140 REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 141 REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 142 REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 143 144 /* Design Configuration Registers */ 145 REG32(DESCONF, 0x280) 146 REG32(DESCONF2, 0x284) 147 REG32(DESCONF3, 0x288) 148 REG32(DESCONF4, 0x28c) 149 REG32(DESCONF5, 0x290) 150 REG32(DESCONF6, 0x294) 151 #define GEM_DESCONF6_64B_MASK (1U << 23) 152 REG32(DESCONF7, 0x298) 153 154 REG32(INT_Q1_STATUS, 0x400) 155 REG32(INT_Q1_MASK, 0x640) 156 157 REG32(TRANSMIT_Q1_PTR, 0x440) 158 REG32(TRANSMIT_Q7_PTR, 0x458) 159 160 REG32(RECEIVE_Q1_PTR, 0x480) 161 REG32(RECEIVE_Q7_PTR, 0x498) 162 163 REG32(TBQPH, 0x4c8) 164 REG32(RBQPH, 0x4d4) 165 166 REG32(INT_Q1_ENABLE, 0x600) 167 REG32(INT_Q7_ENABLE, 0x618) 168 169 REG32(INT_Q1_DISABLE, 0x620) 170 REG32(INT_Q7_DISABLE, 0x638) 171 172 REG32(SCREENING_TYPE1_REG0, 0x500) 173 174 #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 175 #define GEM_ST1R_DSTC_ENABLE (1 << 28) 176 #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 177 #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 178 #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 179 #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 180 #define GEM_ST1R_QUEUE_SHIFT (0) 181 #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 182 183 REG32(SCREENING_TYPE2_REG0, 0x540) 184 185 #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 186 #define GEM_ST2R_COMPARE_A_SHIFT (13) 187 #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 188 #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 189 #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 190 #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 191 + 1) 192 #define GEM_ST2R_QUEUE_SHIFT (0) 193 #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 194 195 REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 196 REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 197 198 #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 199 #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 200 #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 201 #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 202 203 /*****************************************/ 204 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 205 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 206 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 207 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 208 209 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 210 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 211 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 212 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 213 #define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ 214 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 215 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 216 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 217 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 218 #define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ 219 220 #define GEM_DMACFG_ADDR_64B (1U << 30) 221 #define GEM_DMACFG_TX_BD_EXT (1U << 29) 222 #define GEM_DMACFG_RX_BD_EXT (1U << 28) 223 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 224 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 225 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 226 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 227 228 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 229 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 230 231 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 232 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 233 234 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 235 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 236 #define GEM_INT_AMBA_ERR 0x00000040 237 #define GEM_INT_TXUSED 0x00000008 238 #define GEM_INT_RXUSED 0x00000004 239 #define GEM_INT_RXCMPL 0x00000002 240 241 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 242 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 243 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 244 #define GEM_PHYMNTNC_ADDR_SHFT 23 245 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 246 #define GEM_PHYMNTNC_REG_SHIFT 18 247 248 /* Marvell PHY definitions */ 249 #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 250 251 #define PHY_REG_CONTROL 0 252 #define PHY_REG_STATUS 1 253 #define PHY_REG_PHYID1 2 254 #define PHY_REG_PHYID2 3 255 #define PHY_REG_ANEGADV 4 256 #define PHY_REG_LINKPABIL 5 257 #define PHY_REG_ANEGEXP 6 258 #define PHY_REG_NEXTP 7 259 #define PHY_REG_LINKPNEXTP 8 260 #define PHY_REG_100BTCTRL 9 261 #define PHY_REG_1000BTSTAT 10 262 #define PHY_REG_EXTSTAT 15 263 #define PHY_REG_PHYSPCFC_CTL 16 264 #define PHY_REG_PHYSPCFC_ST 17 265 #define PHY_REG_INT_EN 18 266 #define PHY_REG_INT_ST 19 267 #define PHY_REG_EXT_PHYSPCFC_CTL 20 268 #define PHY_REG_RXERR 21 269 #define PHY_REG_EACD 22 270 #define PHY_REG_LED 24 271 #define PHY_REG_LED_OVRD 25 272 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 273 #define PHY_REG_EXT_PHYSPCFC_ST 27 274 #define PHY_REG_CABLE_DIAG 28 275 276 #define PHY_REG_CONTROL_RST 0x8000 277 #define PHY_REG_CONTROL_LOOP 0x4000 278 #define PHY_REG_CONTROL_ANEG 0x1000 279 #define PHY_REG_CONTROL_ANRESTART 0x0200 280 281 #define PHY_REG_STATUS_LINK 0x0004 282 #define PHY_REG_STATUS_ANEGCMPL 0x0020 283 284 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 285 #define PHY_REG_INT_ST_LINKC 0x0400 286 #define PHY_REG_INT_ST_ENERGY 0x0010 287 288 /***********************************************************************/ 289 #define GEM_RX_REJECT (-1) 290 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 291 #define GEM_RX_BROADCAST_ACCEPT (-3) 292 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 293 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 294 295 #define GEM_RX_SAR_ACCEPT 0 296 297 /***********************************************************************/ 298 299 #define DESC_1_USED 0x80000000 300 #define DESC_1_LENGTH 0x00001FFF 301 302 #define DESC_1_TX_WRAP 0x40000000 303 #define DESC_1_TX_LAST 0x00008000 304 305 #define DESC_0_RX_WRAP 0x00000002 306 #define DESC_0_RX_OWNERSHIP 0x00000001 307 308 #define R_DESC_1_RX_SAR_SHIFT 25 309 #define R_DESC_1_RX_SAR_LENGTH 2 310 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 311 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 312 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 313 #define R_DESC_1_RX_BROADCAST (1 << 31) 314 315 #define DESC_1_RX_SOF 0x00004000 316 #define DESC_1_RX_EOF 0x00008000 317 318 #define GEM_MODID_VALUE 0x00020118 319 320 static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 321 { 322 uint64_t ret = desc[0]; 323 324 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 325 ret |= (uint64_t)desc[2] << 32; 326 } 327 return ret; 328 } 329 330 static inline unsigned tx_desc_get_used(uint32_t *desc) 331 { 332 return (desc[1] & DESC_1_USED) ? 1 : 0; 333 } 334 335 static inline void tx_desc_set_used(uint32_t *desc) 336 { 337 desc[1] |= DESC_1_USED; 338 } 339 340 static inline unsigned tx_desc_get_wrap(uint32_t *desc) 341 { 342 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 343 } 344 345 static inline unsigned tx_desc_get_last(uint32_t *desc) 346 { 347 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 348 } 349 350 static inline unsigned tx_desc_get_length(uint32_t *desc) 351 { 352 return desc[1] & DESC_1_LENGTH; 353 } 354 355 static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 356 { 357 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 358 DB_PRINT("bufaddr: 0x%08x\n", *desc); 359 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 360 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 361 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 362 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 363 } 364 365 static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 366 { 367 uint64_t ret = desc[0] & ~0x3UL; 368 369 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 370 ret |= (uint64_t)desc[2] << 32; 371 } 372 return ret; 373 } 374 375 static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 376 { 377 int ret = 2; 378 379 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 380 ret += 2; 381 } 382 if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 383 : GEM_DMACFG_TX_BD_EXT)) { 384 ret += 2; 385 } 386 387 assert(ret <= DESC_MAX_NUM_WORDS); 388 return ret; 389 } 390 391 static inline unsigned rx_desc_get_wrap(uint32_t *desc) 392 { 393 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 394 } 395 396 static inline unsigned rx_desc_get_ownership(uint32_t *desc) 397 { 398 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 399 } 400 401 static inline void rx_desc_set_ownership(uint32_t *desc) 402 { 403 desc[0] |= DESC_0_RX_OWNERSHIP; 404 } 405 406 static inline void rx_desc_set_sof(uint32_t *desc) 407 { 408 desc[1] |= DESC_1_RX_SOF; 409 } 410 411 static inline void rx_desc_clear_control(uint32_t *desc) 412 { 413 desc[1] = 0; 414 } 415 416 static inline void rx_desc_set_eof(uint32_t *desc) 417 { 418 desc[1] |= DESC_1_RX_EOF; 419 } 420 421 static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 422 { 423 desc[1] &= ~DESC_1_LENGTH; 424 desc[1] |= len; 425 } 426 427 static inline void rx_desc_set_broadcast(uint32_t *desc) 428 { 429 desc[1] |= R_DESC_1_RX_BROADCAST; 430 } 431 432 static inline void rx_desc_set_unicast_hash(uint32_t *desc) 433 { 434 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 435 } 436 437 static inline void rx_desc_set_multicast_hash(uint32_t *desc) 438 { 439 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 440 } 441 442 static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 443 { 444 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 445 sar_idx); 446 desc[1] |= R_DESC_1_RX_SAR_MATCH; 447 } 448 449 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 450 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 451 452 static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 453 { 454 uint32_t size; 455 if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { 456 size = s->regs[R_JUMBO_MAX_LEN]; 457 if (size > s->jumbo_max_len) { 458 size = s->jumbo_max_len; 459 qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 460 " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 461 } 462 } else if (tx) { 463 size = 1518; 464 } else { 465 size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; 466 } 467 return size; 468 } 469 470 static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 471 { 472 if (q == 0) { 473 s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 474 } else { 475 s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 476 ~(s->regs[R_INT_Q1_MASK + q - 1]); 477 } 478 } 479 480 /* 481 * gem_init_register_masks: 482 * One time initialization. 483 * Set masks to identify which register bits have magical clear properties 484 */ 485 static void gem_init_register_masks(CadenceGEMState *s) 486 { 487 unsigned int i; 488 /* Mask of register bits which are read only */ 489 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 490 s->regs_ro[R_NWCTRL] = 0xFFF80000; 491 s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 492 s->regs_ro[R_DMACFG] = 0x8E00F000; 493 s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 494 s->regs_ro[R_RXQBASE] = 0x00000003; 495 s->regs_ro[R_TXQBASE] = 0x00000003; 496 s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 497 s->regs_ro[R_ISR] = 0xFFFFFFFF; 498 s->regs_ro[R_IMR] = 0xFFFFFFFF; 499 s->regs_ro[R_MODID] = 0xFFFFFFFF; 500 for (i = 0; i < s->num_priority_queues; i++) { 501 s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 502 s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 503 s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 504 s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 505 } 506 507 /* Mask of register bits which are clear on read */ 508 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 509 s->regs_rtc[R_ISR] = 0xFFFFFFFF; 510 for (i = 0; i < s->num_priority_queues; i++) { 511 s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 512 } 513 514 /* Mask of register bits which are write 1 to clear */ 515 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 516 s->regs_w1c[R_TXSTATUS] = 0x000001F7; 517 s->regs_w1c[R_RXSTATUS] = 0x0000000F; 518 519 /* Mask of register bits which are write only */ 520 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 521 s->regs_wo[R_NWCTRL] = 0x00073E60; 522 s->regs_wo[R_IER] = 0x07FFFFFF; 523 s->regs_wo[R_IDR] = 0x07FFFFFF; 524 for (i = 0; i < s->num_priority_queues; i++) { 525 s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 526 s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 527 } 528 } 529 530 /* 531 * phy_update_link: 532 * Make the emulated PHY link state match the QEMU "interface" state. 533 */ 534 static void phy_update_link(CadenceGEMState *s) 535 { 536 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 537 538 /* Autonegotiation status mirrors link status. */ 539 if (qemu_get_queue(s->nic)->link_down) { 540 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 541 PHY_REG_STATUS_LINK); 542 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 543 } else { 544 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 545 PHY_REG_STATUS_LINK); 546 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 547 PHY_REG_INT_ST_ANEGCMPL | 548 PHY_REG_INT_ST_ENERGY); 549 } 550 } 551 552 static bool gem_can_receive(NetClientState *nc) 553 { 554 CadenceGEMState *s; 555 int i; 556 557 s = qemu_get_nic_opaque(nc); 558 559 /* Do nothing if receive is not enabled. */ 560 if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) { 561 if (s->can_rx_state != 1) { 562 s->can_rx_state = 1; 563 DB_PRINT("can't receive - no enable\n"); 564 } 565 return false; 566 } 567 568 for (i = 0; i < s->num_priority_queues; i++) { 569 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 570 break; 571 } 572 }; 573 574 if (i == s->num_priority_queues) { 575 if (s->can_rx_state != 2) { 576 s->can_rx_state = 2; 577 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 578 } 579 return false; 580 } 581 582 if (s->can_rx_state != 0) { 583 s->can_rx_state = 0; 584 DB_PRINT("can receive\n"); 585 } 586 return true; 587 } 588 589 /* 590 * gem_update_int_status: 591 * Raise or lower interrupt based on current status. 592 */ 593 static void gem_update_int_status(CadenceGEMState *s) 594 { 595 int i; 596 597 qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 598 599 for (i = 1; i < s->num_priority_queues; ++i) { 600 qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 601 } 602 } 603 604 /* 605 * gem_receive_updatestats: 606 * Increment receive statistics. 607 */ 608 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 609 unsigned bytes) 610 { 611 uint64_t octets; 612 613 /* Total octets (bytes) received */ 614 octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 615 s->regs[R_OCTRXHI]; 616 octets += bytes; 617 s->regs[R_OCTRXLO] = octets >> 32; 618 s->regs[R_OCTRXHI] = octets; 619 620 /* Error-free Frames received */ 621 s->regs[R_RXCNT]++; 622 623 /* Error-free Broadcast Frames counter */ 624 if (!memcmp(packet, broadcast_addr, 6)) { 625 s->regs[R_RXBROADCNT]++; 626 } 627 628 /* Error-free Multicast Frames counter */ 629 if (packet[0] == 0x01) { 630 s->regs[R_RXMULTICNT]++; 631 } 632 633 if (bytes <= 64) { 634 s->regs[R_RX64CNT]++; 635 } else if (bytes <= 127) { 636 s->regs[R_RX65CNT]++; 637 } else if (bytes <= 255) { 638 s->regs[R_RX128CNT]++; 639 } else if (bytes <= 511) { 640 s->regs[R_RX256CNT]++; 641 } else if (bytes <= 1023) { 642 s->regs[R_RX512CNT]++; 643 } else if (bytes <= 1518) { 644 s->regs[R_RX1024CNT]++; 645 } else { 646 s->regs[R_RX1519CNT]++; 647 } 648 } 649 650 /* 651 * Get the MAC Address bit from the specified position 652 */ 653 static unsigned get_bit(const uint8_t *mac, unsigned bit) 654 { 655 unsigned byte; 656 657 byte = mac[bit / 8]; 658 byte >>= (bit & 0x7); 659 byte &= 1; 660 661 return byte; 662 } 663 664 /* 665 * Calculate a GEM MAC Address hash index 666 */ 667 static unsigned calc_mac_hash(const uint8_t *mac) 668 { 669 int index_bit, mac_bit; 670 unsigned hash_index; 671 672 hash_index = 0; 673 mac_bit = 5; 674 for (index_bit = 5; index_bit >= 0; index_bit--) { 675 hash_index |= (get_bit(mac, mac_bit) ^ 676 get_bit(mac, mac_bit + 6) ^ 677 get_bit(mac, mac_bit + 12) ^ 678 get_bit(mac, mac_bit + 18) ^ 679 get_bit(mac, mac_bit + 24) ^ 680 get_bit(mac, mac_bit + 30) ^ 681 get_bit(mac, mac_bit + 36) ^ 682 get_bit(mac, mac_bit + 42)) << index_bit; 683 mac_bit--; 684 } 685 686 return hash_index; 687 } 688 689 /* 690 * gem_mac_address_filter: 691 * Accept or reject this destination address? 692 * Returns: 693 * GEM_RX_REJECT: reject 694 * >= 0: Specific address accept (which matched SAR is returned) 695 * others for various other modes of accept: 696 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 697 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 698 */ 699 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 700 { 701 uint8_t *gem_spaddr; 702 int i, is_mc; 703 704 /* Promiscuous mode? */ 705 if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { 706 return GEM_RX_PROMISCUOUS_ACCEPT; 707 } 708 709 if (!memcmp(packet, broadcast_addr, 6)) { 710 /* Reject broadcast packets? */ 711 if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { 712 return GEM_RX_REJECT; 713 } 714 return GEM_RX_BROADCAST_ACCEPT; 715 } 716 717 /* Accept packets -w- hash match? */ 718 is_mc = is_multicast_ether_addr(packet); 719 if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 720 (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 721 uint64_t buckets; 722 unsigned hash_index; 723 724 hash_index = calc_mac_hash(packet); 725 buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 726 if ((buckets >> hash_index) & 1) { 727 return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 728 : GEM_RX_UNICAST_HASH_ACCEPT; 729 } 730 } 731 732 /* Check all 4 specific addresses */ 733 gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 734 for (i = 3; i >= 0; i--) { 735 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 736 return GEM_RX_SAR_ACCEPT + i; 737 } 738 } 739 740 /* No address match; reject the packet */ 741 return GEM_RX_REJECT; 742 } 743 744 /* Figure out which queue the received data should be sent to */ 745 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 746 unsigned rxbufsize) 747 { 748 uint32_t reg; 749 bool matched, mismatched; 750 int i, j; 751 752 for (i = 0; i < s->num_type1_screeners; i++) { 753 reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 754 matched = false; 755 mismatched = false; 756 757 /* Screening is based on UDP Port */ 758 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 759 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 760 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 761 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 762 matched = true; 763 } else { 764 mismatched = true; 765 } 766 } 767 768 /* Screening is based on DS/TC */ 769 if (reg & GEM_ST1R_DSTC_ENABLE) { 770 uint8_t dscp = rxbuf_ptr[14 + 1]; 771 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 772 GEM_ST1R_DSTC_MATCH_WIDTH)) { 773 matched = true; 774 } else { 775 mismatched = true; 776 } 777 } 778 779 if (matched && !mismatched) { 780 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 781 } 782 } 783 784 for (i = 0; i < s->num_type2_screeners; i++) { 785 reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 786 matched = false; 787 mismatched = false; 788 789 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 790 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 791 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 792 GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 793 794 if (et_idx > s->num_type2_screeners) { 795 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 796 "register index: %d\n", et_idx); 797 } 798 if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 799 et_idx]) { 800 matched = true; 801 } else { 802 mismatched = true; 803 } 804 } 805 806 /* Compare A, B, C */ 807 for (j = 0; j < 3; j++) { 808 uint32_t cr0, cr1, mask; 809 uint16_t rx_cmp; 810 int offset; 811 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 812 GEM_ST2R_COMPARE_WIDTH); 813 814 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 815 continue; 816 } 817 if (cr_idx > s->num_type2_screeners) { 818 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 819 "register index: %d\n", cr_idx); 820 } 821 822 cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 823 cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 824 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 825 GEM_T2CW1_OFFSET_VALUE_WIDTH); 826 827 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 828 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 829 case 3: /* Skip UDP header */ 830 qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 831 "unimplemented - assuming UDP\n"); 832 offset += 8; 833 /* Fallthrough */ 834 case 2: /* skip the IP header */ 835 offset += 20; 836 /* Fallthrough */ 837 case 1: /* Count from after the ethertype */ 838 offset += 14; 839 break; 840 case 0: 841 /* Offset from start of frame */ 842 break; 843 } 844 845 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 846 mask = extract32(cr0, 0, 16); 847 848 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 849 matched = true; 850 } else { 851 mismatched = true; 852 } 853 } 854 855 if (matched && !mismatched) { 856 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 857 } 858 } 859 860 /* We made it here, assume it's queue 0 */ 861 return 0; 862 } 863 864 static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 865 { 866 uint32_t base_addr = 0; 867 868 switch (q) { 869 case 0: 870 base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 871 break; 872 case 1 ... (MAX_PRIORITY_QUEUES - 1): 873 base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 874 R_RECEIVE_Q1_PTR) + q - 1]; 875 break; 876 default: 877 g_assert_not_reached(); 878 }; 879 880 return base_addr; 881 } 882 883 static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 884 { 885 return gem_get_queue_base_addr(s, true, q); 886 } 887 888 static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 889 { 890 return gem_get_queue_base_addr(s, false, q); 891 } 892 893 static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 894 { 895 hwaddr desc_addr = 0; 896 897 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 898 desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 899 } 900 desc_addr <<= 32; 901 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 902 return desc_addr; 903 } 904 905 static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 906 { 907 return gem_get_desc_addr(s, true, q); 908 } 909 910 static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 911 { 912 return gem_get_desc_addr(s, false, q); 913 } 914 915 static void gem_get_rx_desc(CadenceGEMState *s, int q) 916 { 917 hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 918 919 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 920 921 /* read current descriptor */ 922 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 923 s->rx_desc[q], 924 sizeof(uint32_t) * gem_get_desc_len(s, true)); 925 926 /* Descriptor owned by software ? */ 927 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 928 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 929 s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 930 gem_set_isr(s, q, GEM_INT_RXUSED); 931 /* Handle interrupt consequences */ 932 gem_update_int_status(s); 933 } 934 } 935 936 /* 937 * gem_receive: 938 * Fit a packet handed to us by QEMU into the receive descriptor ring. 939 */ 940 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 941 { 942 CadenceGEMState *s = qemu_get_nic_opaque(nc); 943 unsigned rxbufsize, bytes_to_copy; 944 unsigned rxbuf_offset; 945 uint8_t *rxbuf_ptr; 946 bool first_desc = true; 947 int maf; 948 int q = 0; 949 950 /* Is this destination MAC address "for us" ? */ 951 maf = gem_mac_address_filter(s, buf); 952 if (maf == GEM_RX_REJECT) { 953 return size; /* no, drop silently b/c it's not an error */ 954 } 955 956 /* Discard packets with receive length error enabled ? */ 957 if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { 958 unsigned type_len; 959 960 /* Fish the ethertype / length field out of the RX packet */ 961 type_len = buf[12] << 8 | buf[13]; 962 /* It is a length field, not an ethertype */ 963 if (type_len < 0x600) { 964 if (size < type_len) { 965 /* discard */ 966 return -1; 967 } 968 } 969 } 970 971 /* 972 * Determine configured receive buffer offset (probably 0) 973 */ 974 rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 975 GEM_NWCFG_BUFF_OFST_S; 976 977 /* The configure size of each receive buffer. Determines how many 978 * buffers needed to hold this packet. 979 */ 980 rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 981 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 982 bytes_to_copy = size; 983 984 /* Hardware allows a zero value here but warns against it. To avoid QEMU 985 * indefinite loops we enforce a minimum value here 986 */ 987 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 988 rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 989 } 990 991 /* Pad to minimum length. Assume FCS field is stripped, logic 992 * below will increment it to the real minimum of 64 when 993 * not FCS stripping 994 */ 995 if (size < 60) { 996 size = 60; 997 } 998 999 /* Strip of FCS field ? (usually yes) */ 1000 if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { 1001 rxbuf_ptr = (void *)buf; 1002 } else { 1003 unsigned crc_val; 1004 1005 if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 1006 size = MAX_FRAME_SIZE - sizeof(crc_val); 1007 } 1008 bytes_to_copy = size; 1009 /* The application wants the FCS field, which QEMU does not provide. 1010 * We must try and calculate one. 1011 */ 1012 1013 memcpy(s->rx_packet, buf, size); 1014 memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 1015 rxbuf_ptr = s->rx_packet; 1016 crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 1017 memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 1018 1019 bytes_to_copy += 4; 1020 size += 4; 1021 } 1022 1023 DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 1024 1025 /* Find which queue we are targeting */ 1026 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1027 1028 if (size > gem_get_max_buf_len(s, false)) { 1029 qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 1030 gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1031 return -1; 1032 } 1033 1034 while (bytes_to_copy) { 1035 hwaddr desc_addr; 1036 1037 /* Do nothing if receive is not enabled. */ 1038 if (!gem_can_receive(nc)) { 1039 return -1; 1040 } 1041 1042 DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1043 MIN(bytes_to_copy, rxbufsize), 1044 rx_desc_get_buffer(s, s->rx_desc[q])); 1045 1046 /* Copy packet data to emulated DMA buffer */ 1047 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 1048 rxbuf_offset, 1049 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1050 MIN(bytes_to_copy, rxbufsize)); 1051 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 1052 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 1053 1054 rx_desc_clear_control(s->rx_desc[q]); 1055 1056 /* Update the descriptor. */ 1057 if (first_desc) { 1058 rx_desc_set_sof(s->rx_desc[q]); 1059 first_desc = false; 1060 } 1061 if (bytes_to_copy == 0) { 1062 rx_desc_set_eof(s->rx_desc[q]); 1063 rx_desc_set_length(s->rx_desc[q], size); 1064 } 1065 rx_desc_set_ownership(s->rx_desc[q]); 1066 1067 switch (maf) { 1068 case GEM_RX_PROMISCUOUS_ACCEPT: 1069 break; 1070 case GEM_RX_BROADCAST_ACCEPT: 1071 rx_desc_set_broadcast(s->rx_desc[q]); 1072 break; 1073 case GEM_RX_UNICAST_HASH_ACCEPT: 1074 rx_desc_set_unicast_hash(s->rx_desc[q]); 1075 break; 1076 case GEM_RX_MULTICAST_HASH_ACCEPT: 1077 rx_desc_set_multicast_hash(s->rx_desc[q]); 1078 break; 1079 case GEM_RX_REJECT: 1080 abort(); 1081 default: /* SAR */ 1082 rx_desc_set_sar(s->rx_desc[q], maf); 1083 } 1084 1085 /* Descriptor write-back. */ 1086 desc_addr = gem_get_rx_desc_addr(s, q); 1087 address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1088 s->rx_desc[q], 1089 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1090 1091 /* Next descriptor */ 1092 if (rx_desc_get_wrap(s->rx_desc[q])) { 1093 DB_PRINT("wrapping RX descriptor list\n"); 1094 s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 1095 } else { 1096 DB_PRINT("incrementing RX descriptor list\n"); 1097 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 1098 } 1099 1100 gem_get_rx_desc(s, q); 1101 } 1102 1103 /* Count it */ 1104 gem_receive_updatestats(s, buf, size); 1105 1106 s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 1107 gem_set_isr(s, q, GEM_INT_RXCMPL); 1108 1109 /* Handle interrupt consequences */ 1110 gem_update_int_status(s); 1111 1112 return size; 1113 } 1114 1115 /* 1116 * gem_transmit_updatestats: 1117 * Increment transmit statistics. 1118 */ 1119 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 1120 unsigned bytes) 1121 { 1122 uint64_t octets; 1123 1124 /* Total octets (bytes) transmitted */ 1125 octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1126 s->regs[R_OCTTXHI]; 1127 octets += bytes; 1128 s->regs[R_OCTTXLO] = octets >> 32; 1129 s->regs[R_OCTTXHI] = octets; 1130 1131 /* Error-free Frames transmitted */ 1132 s->regs[R_TXCNT]++; 1133 1134 /* Error-free Broadcast Frames counter */ 1135 if (!memcmp(packet, broadcast_addr, 6)) { 1136 s->regs[R_TXBCNT]++; 1137 } 1138 1139 /* Error-free Multicast Frames counter */ 1140 if (packet[0] == 0x01) { 1141 s->regs[R_TXMCNT]++; 1142 } 1143 1144 if (bytes <= 64) { 1145 s->regs[R_TX64CNT]++; 1146 } else if (bytes <= 127) { 1147 s->regs[R_TX65CNT]++; 1148 } else if (bytes <= 255) { 1149 s->regs[R_TX128CNT]++; 1150 } else if (bytes <= 511) { 1151 s->regs[R_TX256CNT]++; 1152 } else if (bytes <= 1023) { 1153 s->regs[R_TX512CNT]++; 1154 } else if (bytes <= 1518) { 1155 s->regs[R_TX1024CNT]++; 1156 } else { 1157 s->regs[R_TX1519CNT]++; 1158 } 1159 } 1160 1161 /* 1162 * gem_transmit: 1163 * Fish packets out of the descriptor ring and feed them to QEMU 1164 */ 1165 static void gem_transmit(CadenceGEMState *s) 1166 { 1167 uint32_t desc[DESC_MAX_NUM_WORDS]; 1168 hwaddr packet_desc_addr; 1169 uint8_t *p; 1170 unsigned total_bytes; 1171 int q = 0; 1172 1173 /* Do nothing if transmit is not enabled. */ 1174 if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { 1175 return; 1176 } 1177 1178 DB_PRINT("\n"); 1179 1180 /* The packet we will hand off to QEMU. 1181 * Packets scattered across multiple descriptors are gathered to this 1182 * one contiguous buffer first. 1183 */ 1184 p = s->tx_packet; 1185 total_bytes = 0; 1186 1187 for (q = s->num_priority_queues - 1; q >= 0; q--) { 1188 /* read current descriptor */ 1189 packet_desc_addr = gem_get_tx_desc_addr(s, q); 1190 1191 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1192 address_space_read(&s->dma_as, packet_desc_addr, 1193 MEMTXATTRS_UNSPECIFIED, desc, 1194 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1195 /* Handle all descriptors owned by hardware */ 1196 while (tx_desc_get_used(desc) == 0) { 1197 1198 /* Do nothing if transmit is not enabled. */ 1199 if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { 1200 return; 1201 } 1202 print_gem_tx_desc(desc, q); 1203 1204 /* The real hardware would eat this (and possibly crash). 1205 * For QEMU let's lend a helping hand. 1206 */ 1207 if ((tx_desc_get_buffer(s, desc) == 0) || 1208 (tx_desc_get_length(desc) == 0)) { 1209 DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 1210 packet_desc_addr); 1211 break; 1212 } 1213 1214 if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 1215 (p - s->tx_packet)) { 1216 qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 1217 HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1218 packet_desc_addr, tx_desc_get_length(desc), 1219 gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 1220 gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1221 break; 1222 } 1223 1224 /* Gather this fragment of the packet from "dma memory" to our 1225 * contig buffer. 1226 */ 1227 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 1228 MEMTXATTRS_UNSPECIFIED, 1229 p, tx_desc_get_length(desc)); 1230 p += tx_desc_get_length(desc); 1231 total_bytes += tx_desc_get_length(desc); 1232 1233 /* Last descriptor for this packet; hand the whole thing off */ 1234 if (tx_desc_get_last(desc)) { 1235 uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1236 hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 1237 1238 /* Modify the 1st descriptor of this packet to be owned by 1239 * the processor. 1240 */ 1241 address_space_read(&s->dma_as, desc_addr, 1242 MEMTXATTRS_UNSPECIFIED, desc_first, 1243 sizeof(desc_first)); 1244 tx_desc_set_used(desc_first); 1245 address_space_write(&s->dma_as, desc_addr, 1246 MEMTXATTRS_UNSPECIFIED, desc_first, 1247 sizeof(desc_first)); 1248 /* Advance the hardware current descriptor past this packet */ 1249 if (tx_desc_get_wrap(desc)) { 1250 s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 1251 } else { 1252 s->tx_desc_addr[q] = packet_desc_addr + 1253 4 * gem_get_desc_len(s, false); 1254 } 1255 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 1256 1257 s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 1258 gem_set_isr(s, q, GEM_INT_TXCMPL); 1259 1260 /* Handle interrupt consequences */ 1261 gem_update_int_status(s); 1262 1263 /* Is checksum offload enabled? */ 1264 if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1265 net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 1266 } 1267 1268 /* Update MAC statistics */ 1269 gem_transmit_updatestats(s, s->tx_packet, total_bytes); 1270 1271 /* Send the packet somewhere */ 1272 if (s->phy_loop || (s->regs[R_NWCTRL] & 1273 GEM_NWCTRL_LOCALLOOP)) { 1274 qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 1275 total_bytes); 1276 } else { 1277 qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 1278 total_bytes); 1279 } 1280 1281 /* Prepare for next packet */ 1282 p = s->tx_packet; 1283 total_bytes = 0; 1284 } 1285 1286 /* read next descriptor */ 1287 if (tx_desc_get_wrap(desc)) { 1288 if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 1289 packet_desc_addr = s->regs[R_TBQPH]; 1290 packet_desc_addr <<= 32; 1291 } else { 1292 packet_desc_addr = 0; 1293 } 1294 packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 1295 } else { 1296 packet_desc_addr += 4 * gem_get_desc_len(s, false); 1297 } 1298 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1299 address_space_read(&s->dma_as, packet_desc_addr, 1300 MEMTXATTRS_UNSPECIFIED, desc, 1301 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1302 } 1303 1304 if (tx_desc_get_used(desc)) { 1305 s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; 1306 /* IRQ TXUSED is defined only for queue 0 */ 1307 if (q == 0) { 1308 gem_set_isr(s, 0, GEM_INT_TXUSED); 1309 } 1310 gem_update_int_status(s); 1311 } 1312 } 1313 } 1314 1315 static void gem_phy_reset(CadenceGEMState *s) 1316 { 1317 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 1318 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 1319 s->phy_regs[PHY_REG_STATUS] = 0x7969; 1320 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 1321 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 1322 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 1323 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 1324 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 1325 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 1326 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 1327 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 1328 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 1329 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 1330 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 1331 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 1332 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 1333 s->phy_regs[PHY_REG_LED] = 0x4100; 1334 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 1335 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 1336 1337 phy_update_link(s); 1338 } 1339 1340 static void gem_reset(DeviceState *d) 1341 { 1342 int i; 1343 CadenceGEMState *s = CADENCE_GEM(d); 1344 const uint8_t *a; 1345 uint32_t queues_mask = 0; 1346 1347 DB_PRINT("\n"); 1348 1349 /* Set post reset register values */ 1350 memset(&s->regs[0], 0, sizeof(s->regs)); 1351 s->regs[R_NWCFG] = 0x00080000; 1352 s->regs[R_NWSTATUS] = 0x00000006; 1353 s->regs[R_DMACFG] = 0x00020784; 1354 s->regs[R_IMR] = 0x07ffffff; 1355 s->regs[R_TXPAUSE] = 0x0000ffff; 1356 s->regs[R_TXPARTIALSF] = 0x000003ff; 1357 s->regs[R_RXPARTIALSF] = 0x000003ff; 1358 s->regs[R_MODID] = s->revision; 1359 s->regs[R_DESCONF] = 0x02D00111; 1360 s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1361 s->regs[R_DESCONF5] = 0x002f2045; 1362 s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; 1363 s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1364 s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1365 1366 if (s->num_priority_queues > 1) { 1367 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1368 s->regs[R_DESCONF6] |= queues_mask; 1369 } 1370 1371 /* Set MAC address */ 1372 a = &s->conf.macaddr.a[0]; 1373 s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1374 s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1375 1376 for (i = 0; i < 4; i++) { 1377 s->sar_active[i] = false; 1378 } 1379 1380 gem_phy_reset(s); 1381 1382 gem_update_int_status(s); 1383 } 1384 1385 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1386 { 1387 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1388 return s->phy_regs[reg_num]; 1389 } 1390 1391 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1392 { 1393 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1394 1395 switch (reg_num) { 1396 case PHY_REG_CONTROL: 1397 if (val & PHY_REG_CONTROL_RST) { 1398 /* Phy reset */ 1399 gem_phy_reset(s); 1400 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1401 s->phy_loop = 0; 1402 } 1403 if (val & PHY_REG_CONTROL_ANEG) { 1404 /* Complete autonegotiation immediately */ 1405 val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 1406 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1407 } 1408 if (val & PHY_REG_CONTROL_LOOP) { 1409 DB_PRINT("PHY placed in loopback\n"); 1410 s->phy_loop = 1; 1411 } else { 1412 s->phy_loop = 0; 1413 } 1414 break; 1415 } 1416 s->phy_regs[reg_num] = val; 1417 } 1418 1419 /* 1420 * gem_read32: 1421 * Read a GEM register. 1422 */ 1423 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1424 { 1425 CadenceGEMState *s; 1426 uint32_t retval; 1427 s = opaque; 1428 1429 offset >>= 2; 1430 retval = s->regs[offset]; 1431 1432 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1433 1434 switch (offset) { 1435 case R_ISR: 1436 DB_PRINT("lowering irqs on ISR read\n"); 1437 /* The interrupts get updated at the end of the function. */ 1438 break; 1439 case R_PHYMNTNC: 1440 if (retval & GEM_PHYMNTNC_OP_R) { 1441 uint32_t phy_addr, reg_num; 1442 1443 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1444 if (phy_addr == s->phy_addr) { 1445 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1446 retval &= 0xFFFF0000; 1447 retval |= gem_phy_read(s, reg_num); 1448 } else { 1449 retval |= 0xFFFF; /* No device at this address */ 1450 } 1451 } 1452 break; 1453 } 1454 1455 /* Squash read to clear bits */ 1456 s->regs[offset] &= ~(s->regs_rtc[offset]); 1457 1458 /* Do not provide write only bits */ 1459 retval &= ~(s->regs_wo[offset]); 1460 1461 DB_PRINT("0x%08x\n", retval); 1462 gem_update_int_status(s); 1463 return retval; 1464 } 1465 1466 /* 1467 * gem_write32: 1468 * Write a GEM register. 1469 */ 1470 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1471 unsigned size) 1472 { 1473 CadenceGEMState *s = (CadenceGEMState *)opaque; 1474 uint32_t readonly; 1475 int i; 1476 1477 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1478 offset >>= 2; 1479 1480 /* Squash bits which are read only in write value */ 1481 val &= ~(s->regs_ro[offset]); 1482 /* Preserve (only) bits which are read only and wtc in register */ 1483 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1484 1485 /* Copy register write to backing store */ 1486 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1487 1488 /* do w1c */ 1489 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1490 1491 /* Handle register write side effects */ 1492 switch (offset) { 1493 case R_NWCTRL: 1494 if (val & GEM_NWCTRL_RXENA) { 1495 for (i = 0; i < s->num_priority_queues; ++i) { 1496 gem_get_rx_desc(s, i); 1497 } 1498 } 1499 if (val & GEM_NWCTRL_TXSTART) { 1500 gem_transmit(s); 1501 } 1502 if (!(val & GEM_NWCTRL_TXENA)) { 1503 /* Reset to start of Q when transmit disabled. */ 1504 for (i = 0; i < s->num_priority_queues; i++) { 1505 s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 1506 } 1507 } 1508 if (gem_can_receive(qemu_get_queue(s->nic))) { 1509 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1510 } 1511 break; 1512 1513 case R_TXSTATUS: 1514 gem_update_int_status(s); 1515 break; 1516 case R_RXQBASE: 1517 s->rx_desc_addr[0] = val; 1518 break; 1519 case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1520 s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 1521 break; 1522 case R_TXQBASE: 1523 s->tx_desc_addr[0] = val; 1524 break; 1525 case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1526 s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 1527 break; 1528 case R_RXSTATUS: 1529 gem_update_int_status(s); 1530 break; 1531 case R_IER: 1532 s->regs[R_IMR] &= ~val; 1533 gem_update_int_status(s); 1534 break; 1535 case R_JUMBO_MAX_LEN: 1536 s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 1537 break; 1538 case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1539 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 1540 gem_update_int_status(s); 1541 break; 1542 case R_IDR: 1543 s->regs[R_IMR] |= val; 1544 gem_update_int_status(s); 1545 break; 1546 case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1547 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 1548 gem_update_int_status(s); 1549 break; 1550 case R_SPADDR1LO: 1551 case R_SPADDR2LO: 1552 case R_SPADDR3LO: 1553 case R_SPADDR4LO: 1554 s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 1555 break; 1556 case R_SPADDR1HI: 1557 case R_SPADDR2HI: 1558 case R_SPADDR3HI: 1559 case R_SPADDR4HI: 1560 s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 1561 break; 1562 case R_PHYMNTNC: 1563 if (val & GEM_PHYMNTNC_OP_W) { 1564 uint32_t phy_addr, reg_num; 1565 1566 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1567 if (phy_addr == s->phy_addr) { 1568 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1569 gem_phy_write(s, reg_num, val); 1570 } 1571 } 1572 break; 1573 } 1574 1575 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1576 } 1577 1578 static const MemoryRegionOps gem_ops = { 1579 .read = gem_read, 1580 .write = gem_write, 1581 .endianness = DEVICE_LITTLE_ENDIAN, 1582 }; 1583 1584 static void gem_set_link(NetClientState *nc) 1585 { 1586 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1587 1588 DB_PRINT("\n"); 1589 phy_update_link(s); 1590 gem_update_int_status(s); 1591 } 1592 1593 static NetClientInfo net_gem_info = { 1594 .type = NET_CLIENT_DRIVER_NIC, 1595 .size = sizeof(NICState), 1596 .can_receive = gem_can_receive, 1597 .receive = gem_receive, 1598 .link_status_changed = gem_set_link, 1599 }; 1600 1601 static void gem_realize(DeviceState *dev, Error **errp) 1602 { 1603 CadenceGEMState *s = CADENCE_GEM(dev); 1604 int i; 1605 1606 address_space_init(&s->dma_as, 1607 s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 1608 1609 if (s->num_priority_queues == 0 || 1610 s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1611 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1612 s->num_priority_queues); 1613 return; 1614 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1615 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1616 s->num_type1_screeners); 1617 return; 1618 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1619 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1620 s->num_type2_screeners); 1621 return; 1622 } 1623 1624 for (i = 0; i < s->num_priority_queues; ++i) { 1625 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1626 } 1627 1628 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1629 1630 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1631 object_get_typename(OBJECT(dev)), dev->id, s); 1632 1633 if (s->jumbo_max_len > MAX_FRAME_SIZE) { 1634 error_setg(errp, "jumbo-max-len is greater than %d", 1635 MAX_FRAME_SIZE); 1636 return; 1637 } 1638 } 1639 1640 static void gem_init(Object *obj) 1641 { 1642 CadenceGEMState *s = CADENCE_GEM(obj); 1643 DeviceState *dev = DEVICE(obj); 1644 1645 DB_PRINT("\n"); 1646 1647 gem_init_register_masks(s); 1648 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1649 "enet", sizeof(s->regs)); 1650 1651 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1652 } 1653 1654 static const VMStateDescription vmstate_cadence_gem = { 1655 .name = "cadence_gem", 1656 .version_id = 4, 1657 .minimum_version_id = 4, 1658 .fields = (VMStateField[]) { 1659 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1660 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1661 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1662 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1663 MAX_PRIORITY_QUEUES), 1664 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1665 MAX_PRIORITY_QUEUES), 1666 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1667 VMSTATE_END_OF_LIST(), 1668 } 1669 }; 1670 1671 static Property gem_properties[] = { 1672 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1673 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1674 GEM_MODID_VALUE), 1675 DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 1676 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1677 num_priority_queues, 1), 1678 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1679 num_type1_screeners, 4), 1680 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1681 num_type2_screeners, 4), 1682 DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 1683 jumbo_max_len, 10240), 1684 DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 1685 TYPE_MEMORY_REGION, MemoryRegion *), 1686 DEFINE_PROP_END_OF_LIST(), 1687 }; 1688 1689 static void gem_class_init(ObjectClass *klass, void *data) 1690 { 1691 DeviceClass *dc = DEVICE_CLASS(klass); 1692 1693 dc->realize = gem_realize; 1694 device_class_set_props(dc, gem_properties); 1695 dc->vmsd = &vmstate_cadence_gem; 1696 dc->reset = gem_reset; 1697 } 1698 1699 static const TypeInfo gem_info = { 1700 .name = TYPE_CADENCE_GEM, 1701 .parent = TYPE_SYS_BUS_DEVICE, 1702 .instance_size = sizeof(CadenceGEMState), 1703 .instance_init = gem_init, 1704 .class_init = gem_class_init, 1705 }; 1706 1707 static void gem_register_types(void) 1708 { 1709 type_register_static(&gem_info); 1710 } 1711 1712 type_init(gem_register_types) 1713