1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/irq.h" 29 #include "hw/net/cadence_gem.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/registerfields.h" 32 #include "migration/vmstate.h" 33 #include "qapi/error.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "sysemu/dma.h" 37 #include "net/checksum.h" 38 #include "net/eth.h" 39 40 #define CADENCE_GEM_ERR_DEBUG 0 41 #define DB_PRINT(...) do {\ 42 if (CADENCE_GEM_ERR_DEBUG) { \ 43 qemu_log(": %s: ", __func__); \ 44 qemu_log(__VA_ARGS__); \ 45 } \ 46 } while (0) 47 48 REG32(NWCTRL, 0x0) /* Network Control reg */ 49 FIELD(NWCTRL, LOOPBACK , 0, 1) 50 FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) 51 FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) 52 FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) 53 FIELD(NWCTRL, MAN_PORT_EN , 4, 1) 54 FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) 55 FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) 56 FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) 57 FIELD(NWCTRL, BACK_PRESSURE, 8, 1) 58 FIELD(NWCTRL, TRANSMIT_START , 9, 1) 59 FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) 60 FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) 61 FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) 62 FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) 63 FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) 64 FIELD(NWCTRL, STORE_RX_TS, 15, 1) 65 FIELD(NWCTRL, PFC_ENABLE, 16, 1) 66 FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) 67 FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) 68 FIELD(NWCTRL, TX_LPI_EN, 19, 1) 69 FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) 70 FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) 71 FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) 72 FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) 73 FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) 74 FIELD(NWCTRL, PFC_CTRL , 25, 1) 75 FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) 76 FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) 77 FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) 78 FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) 79 FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) 80 81 REG32(NWCFG, 0x4) /* Network Config reg */ 82 FIELD(NWCFG, SPEED, 0, 1) 83 FIELD(NWCFG, FULL_DUPLEX, 1, 1) 84 FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) 85 FIELD(NWCFG, JUMBO_FRAMES, 3, 1) 86 FIELD(NWCFG, PROMISC, 4, 1) 87 FIELD(NWCFG, NO_BROADCAST, 5, 1) 88 FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) 89 FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) 90 FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) 91 FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) 92 FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) 93 FIELD(NWCFG, PCS_SELECT, 11, 1) 94 FIELD(NWCFG, RETRY_TEST, 12, 1) 95 FIELD(NWCFG, PAUSE_ENABLE, 13, 1) 96 FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) 97 FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) 98 FIELD(NWCFG, FCS_REMOVE, 17, 1) 99 FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) 100 FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) 101 FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) 102 FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) 103 FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) 104 FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) 105 FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) 106 FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) 107 FIELD(NWCFG, NSP_ACCEPT, 29, 1) 108 FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) 109 FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) 110 111 REG32(NWSTATUS, 0x8) /* Network Status reg */ 112 REG32(USERIO, 0xc) /* User IO reg */ 113 114 REG32(DMACFG, 0x10) /* DMA Control reg */ 115 FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1) 116 FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1) 117 FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1) 118 FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1) 119 FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1) 120 FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1) 121 FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1) 122 FIELD(DMACFG, RX_BUF_SIZE, 16, 8) 123 FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1) 124 FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1) 125 FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1) 126 FIELD(DMACFG, TX_PBUF_SIZE, 10, 1) 127 FIELD(DMACFG, RX_PBUF_SIZE, 8, 2) 128 FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1) 129 FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1) 130 FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1) 131 FIELD(DMACFG, AMBA_BURST_LEN , 0, 5) 132 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 133 134 REG32(TXSTATUS, 0x14) /* TX Status reg */ 135 FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1) 136 FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1) 137 FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1) 138 FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1) 139 FIELD(TXSTATUS, RESP_NOT_OK, 8, 1) 140 FIELD(TXSTATUS, LATE_COLLISION, 7, 1) 141 FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1) 142 FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1) 143 FIELD(TXSTATUS, AMBA_ERROR, 4, 1) 144 FIELD(TXSTATUS, TRANSMIT_GO, 3, 1) 145 FIELD(TXSTATUS, RETRY_LIMIT, 2, 1) 146 FIELD(TXSTATUS, COLLISION, 1, 1) 147 FIELD(TXSTATUS, USED_BIT_READ, 0, 1) 148 149 REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 150 REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 151 REG32(RXSTATUS, 0x20) /* RX Status reg */ 152 FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1) 153 FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1) 154 FIELD(RXSTATUS, RESP_NOT_OK, 3, 1) 155 FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1) 156 FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1) 157 FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1) 158 159 REG32(ISR, 0x24) /* Interrupt Status reg */ 160 FIELD(ISR, TX_LOCKUP, 31, 1) 161 FIELD(ISR, RX_LOCKUP, 30, 1) 162 FIELD(ISR, TSU_TIMER, 29, 1) 163 FIELD(ISR, WOL, 28, 1) 164 FIELD(ISR, RECV_LPI, 27, 1) 165 FIELD(ISR, TSU_SEC_INCR, 26, 1) 166 FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1) 167 FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1) 168 FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1) 169 FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1) 170 FIELD(ISR, PTP_SYNC_XMIT, 21, 1) 171 FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1) 172 FIELD(ISR, PTP_SYNC_RECV, 19, 1) 173 FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1) 174 FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1) 175 FIELD(ISR, PCS_AN_COMPLETE, 16, 1) 176 FIELD(ISR, EXT_IRQ, 15, 1) 177 FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1) 178 FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1) 179 FIELD(ISR, PAUSE_FRAME_RECV, 12, 1) 180 FIELD(ISR, RESP_NOT_OK, 11, 1) 181 FIELD(ISR, RECV_OVERRUN, 10, 1) 182 FIELD(ISR, LINK_CHANGE, 9, 1) 183 FIELD(ISR, USXGMII_INT, 8, 1) 184 FIELD(ISR, XMIT_COMPLETE, 7, 1) 185 FIELD(ISR, AMBA_ERROR, 6, 1) 186 FIELD(ISR, RETRY_EXCEEDED, 5, 1) 187 FIELD(ISR, XMIT_UNDER_RUN, 4, 1) 188 FIELD(ISR, TX_USED, 3, 1) 189 FIELD(ISR, RX_USED, 2, 1) 190 FIELD(ISR, RECV_COMPLETE, 1, 1) 191 FIELD(ISR, MGNT_FRAME_SENT, 0, 1) 192 REG32(IER, 0x28) /* Interrupt Enable reg */ 193 REG32(IDR, 0x2c) /* Interrupt Disable reg */ 194 REG32(IMR, 0x30) /* Interrupt Mask reg */ 195 196 REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 197 REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 198 REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 199 REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 200 REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 201 REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 202 REG32(HASHLO, 0x80) /* Hash Low address reg */ 203 REG32(HASHHI, 0x84) /* Hash High address reg */ 204 REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 205 REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 206 REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 207 REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 208 REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 209 REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 210 REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 211 REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 212 REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 213 REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 214 REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 215 REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 216 REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 217 REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 218 REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 219 REG32(MODID, 0xfc) /* Module ID reg */ 220 REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 221 REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 222 REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 223 REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 224 REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 225 REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 226 REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 227 REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 228 REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 229 REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 230 REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 231 REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 232 REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 233 REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 234 REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 235 REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 236 REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 237 REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 238 REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 239 REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 240 REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 241 REG32(OCTRXHI, 0x154) /* Octects Received register High */ 242 REG32(RXCNT, 0x158) /* Error-free Frames Received */ 243 REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 244 REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 245 REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 246 REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 247 REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 248 REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 249 REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 250 REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 251 REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 252 REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 253 REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 254 REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 255 REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 256 REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 257 REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 258 REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 259 REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 260 REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 261 REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 262 REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 263 REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 264 REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 265 266 REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 267 REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 268 REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 269 REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 270 REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 271 REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 272 REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 273 REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 274 REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 275 REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 276 REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 277 REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 278 279 /* Design Configuration Registers */ 280 REG32(DESCONF, 0x280) 281 REG32(DESCONF2, 0x284) 282 REG32(DESCONF3, 0x288) 283 REG32(DESCONF4, 0x28c) 284 REG32(DESCONF5, 0x290) 285 REG32(DESCONF6, 0x294) 286 FIELD(DESCONF6, DMA_ADDR_64B, 23, 1) 287 REG32(DESCONF7, 0x298) 288 289 REG32(INT_Q1_STATUS, 0x400) 290 REG32(INT_Q1_MASK, 0x640) 291 292 REG32(TRANSMIT_Q1_PTR, 0x440) 293 REG32(TRANSMIT_Q7_PTR, 0x458) 294 295 REG32(RECEIVE_Q1_PTR, 0x480) 296 REG32(RECEIVE_Q7_PTR, 0x498) 297 298 REG32(TBQPH, 0x4c8) 299 REG32(RBQPH, 0x4d4) 300 301 REG32(INT_Q1_ENABLE, 0x600) 302 REG32(INT_Q7_ENABLE, 0x618) 303 304 REG32(INT_Q1_DISABLE, 0x620) 305 REG32(INT_Q7_DISABLE, 0x638) 306 307 REG32(SCREENING_TYPE1_REG0, 0x500) 308 FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) 309 FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) 310 FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) 311 FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) 312 FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) 313 FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) 314 315 REG32(SCREENING_TYPE2_REG0, 0x540) 316 FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) 317 FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) 318 FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) 319 FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) 320 FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) 321 FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) 322 FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) 323 FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) 324 FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) 325 FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) 326 FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) 327 FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) 328 329 REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 330 331 REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 332 FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) 333 FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) 334 335 REG32(TYPE2_COMPARE_0_WORD_1, 0x704) 336 FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) 337 FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) 338 FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) 339 FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) 340 341 /*****************************************/ 342 343 344 345 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 346 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 347 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 348 #define GEM_PHYMNTNC_ADDR_SHFT 23 349 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 350 #define GEM_PHYMNTNC_REG_SHIFT 18 351 352 /* Marvell PHY definitions */ 353 #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 354 355 #define PHY_REG_CONTROL 0 356 #define PHY_REG_STATUS 1 357 #define PHY_REG_PHYID1 2 358 #define PHY_REG_PHYID2 3 359 #define PHY_REG_ANEGADV 4 360 #define PHY_REG_LINKPABIL 5 361 #define PHY_REG_ANEGEXP 6 362 #define PHY_REG_NEXTP 7 363 #define PHY_REG_LINKPNEXTP 8 364 #define PHY_REG_100BTCTRL 9 365 #define PHY_REG_1000BTSTAT 10 366 #define PHY_REG_EXTSTAT 15 367 #define PHY_REG_PHYSPCFC_CTL 16 368 #define PHY_REG_PHYSPCFC_ST 17 369 #define PHY_REG_INT_EN 18 370 #define PHY_REG_INT_ST 19 371 #define PHY_REG_EXT_PHYSPCFC_CTL 20 372 #define PHY_REG_RXERR 21 373 #define PHY_REG_EACD 22 374 #define PHY_REG_LED 24 375 #define PHY_REG_LED_OVRD 25 376 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 377 #define PHY_REG_EXT_PHYSPCFC_ST 27 378 #define PHY_REG_CABLE_DIAG 28 379 380 #define PHY_REG_CONTROL_RST 0x8000 381 #define PHY_REG_CONTROL_LOOP 0x4000 382 #define PHY_REG_CONTROL_ANEG 0x1000 383 #define PHY_REG_CONTROL_ANRESTART 0x0200 384 385 #define PHY_REG_STATUS_LINK 0x0004 386 #define PHY_REG_STATUS_ANEGCMPL 0x0020 387 388 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 389 #define PHY_REG_INT_ST_LINKC 0x0400 390 #define PHY_REG_INT_ST_ENERGY 0x0010 391 392 /***********************************************************************/ 393 #define GEM_RX_REJECT (-1) 394 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 395 #define GEM_RX_BROADCAST_ACCEPT (-3) 396 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 397 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 398 399 #define GEM_RX_SAR_ACCEPT 0 400 401 /***********************************************************************/ 402 403 #define DESC_1_USED 0x80000000 404 #define DESC_1_LENGTH 0x00001FFF 405 406 #define DESC_1_TX_WRAP 0x40000000 407 #define DESC_1_TX_LAST 0x00008000 408 409 #define DESC_0_RX_WRAP 0x00000002 410 #define DESC_0_RX_OWNERSHIP 0x00000001 411 412 #define R_DESC_1_RX_SAR_SHIFT 25 413 #define R_DESC_1_RX_SAR_LENGTH 2 414 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 415 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 416 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 417 #define R_DESC_1_RX_BROADCAST (1 << 31) 418 419 #define DESC_1_RX_SOF 0x00004000 420 #define DESC_1_RX_EOF 0x00008000 421 422 #define GEM_MODID_VALUE 0x00020118 423 424 static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 425 { 426 uint64_t ret = desc[0]; 427 428 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 429 ret |= (uint64_t)desc[2] << 32; 430 } 431 return ret; 432 } 433 434 static inline unsigned tx_desc_get_used(uint32_t *desc) 435 { 436 return (desc[1] & DESC_1_USED) ? 1 : 0; 437 } 438 439 static inline void tx_desc_set_used(uint32_t *desc) 440 { 441 desc[1] |= DESC_1_USED; 442 } 443 444 static inline unsigned tx_desc_get_wrap(uint32_t *desc) 445 { 446 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 447 } 448 449 static inline unsigned tx_desc_get_last(uint32_t *desc) 450 { 451 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 452 } 453 454 static inline unsigned tx_desc_get_length(uint32_t *desc) 455 { 456 return desc[1] & DESC_1_LENGTH; 457 } 458 459 static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 460 { 461 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 462 DB_PRINT("bufaddr: 0x%08x\n", *desc); 463 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 464 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 465 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 466 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 467 } 468 469 static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 470 { 471 uint64_t ret = desc[0] & ~0x3UL; 472 473 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 474 ret |= (uint64_t)desc[2] << 32; 475 } 476 return ret; 477 } 478 479 static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 480 { 481 int ret = 2; 482 483 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 484 ret += 2; 485 } 486 if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK 487 : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) { 488 ret += 2; 489 } 490 491 assert(ret <= DESC_MAX_NUM_WORDS); 492 return ret; 493 } 494 495 static inline unsigned rx_desc_get_wrap(uint32_t *desc) 496 { 497 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 498 } 499 500 static inline unsigned rx_desc_get_ownership(uint32_t *desc) 501 { 502 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 503 } 504 505 static inline void rx_desc_set_ownership(uint32_t *desc) 506 { 507 desc[0] |= DESC_0_RX_OWNERSHIP; 508 } 509 510 static inline void rx_desc_set_sof(uint32_t *desc) 511 { 512 desc[1] |= DESC_1_RX_SOF; 513 } 514 515 static inline void rx_desc_clear_control(uint32_t *desc) 516 { 517 desc[1] = 0; 518 } 519 520 static inline void rx_desc_set_eof(uint32_t *desc) 521 { 522 desc[1] |= DESC_1_RX_EOF; 523 } 524 525 static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 526 { 527 desc[1] &= ~DESC_1_LENGTH; 528 desc[1] |= len; 529 } 530 531 static inline void rx_desc_set_broadcast(uint32_t *desc) 532 { 533 desc[1] |= R_DESC_1_RX_BROADCAST; 534 } 535 536 static inline void rx_desc_set_unicast_hash(uint32_t *desc) 537 { 538 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 539 } 540 541 static inline void rx_desc_set_multicast_hash(uint32_t *desc) 542 { 543 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 544 } 545 546 static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 547 { 548 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 549 sar_idx); 550 desc[1] |= R_DESC_1_RX_SAR_MATCH; 551 } 552 553 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 554 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 555 556 static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 557 { 558 uint32_t size; 559 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { 560 size = s->regs[R_JUMBO_MAX_LEN]; 561 if (size > s->jumbo_max_len) { 562 size = s->jumbo_max_len; 563 qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 564 " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 565 } 566 } else if (tx) { 567 size = 1518; 568 } else { 569 size = FIELD_EX32(s->regs[R_NWCFG], 570 NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; 571 } 572 return size; 573 } 574 575 static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 576 { 577 if (q == 0) { 578 s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 579 } else { 580 s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 581 ~(s->regs[R_INT_Q1_MASK + q - 1]); 582 } 583 } 584 585 /* 586 * gem_init_register_masks: 587 * One time initialization. 588 * Set masks to identify which register bits have magical clear properties 589 */ 590 static void gem_init_register_masks(CadenceGEMState *s) 591 { 592 unsigned int i; 593 /* Mask of register bits which are read only */ 594 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 595 s->regs_ro[R_NWCTRL] = 0xFFF80000; 596 s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 597 s->regs_ro[R_DMACFG] = 0x8E00F000; 598 s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 599 s->regs_ro[R_RXQBASE] = 0x00000003; 600 s->regs_ro[R_TXQBASE] = 0x00000003; 601 s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 602 s->regs_ro[R_ISR] = 0xFFFFFFFF; 603 s->regs_ro[R_IMR] = 0xFFFFFFFF; 604 s->regs_ro[R_MODID] = 0xFFFFFFFF; 605 for (i = 0; i < s->num_priority_queues; i++) { 606 s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 607 s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 608 s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 609 s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 610 } 611 612 /* Mask of register bits which are clear on read */ 613 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 614 s->regs_rtc[R_ISR] = 0xFFFFFFFF; 615 for (i = 0; i < s->num_priority_queues; i++) { 616 s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 617 } 618 619 /* Mask of register bits which are write 1 to clear */ 620 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 621 s->regs_w1c[R_TXSTATUS] = 0x000001F7; 622 s->regs_w1c[R_RXSTATUS] = 0x0000000F; 623 624 /* Mask of register bits which are write only */ 625 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 626 s->regs_wo[R_NWCTRL] = 0x00073E60; 627 s->regs_wo[R_IER] = 0x07FFFFFF; 628 s->regs_wo[R_IDR] = 0x07FFFFFF; 629 for (i = 0; i < s->num_priority_queues; i++) { 630 s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 631 s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 632 } 633 } 634 635 /* 636 * phy_update_link: 637 * Make the emulated PHY link state match the QEMU "interface" state. 638 */ 639 static void phy_update_link(CadenceGEMState *s) 640 { 641 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 642 643 /* Autonegotiation status mirrors link status. */ 644 if (qemu_get_queue(s->nic)->link_down) { 645 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 646 PHY_REG_STATUS_LINK); 647 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 648 } else { 649 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 650 PHY_REG_STATUS_LINK); 651 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 652 PHY_REG_INT_ST_ANEGCMPL | 653 PHY_REG_INT_ST_ENERGY); 654 } 655 } 656 657 static bool gem_can_receive(NetClientState *nc) 658 { 659 CadenceGEMState *s; 660 int i; 661 662 s = qemu_get_nic_opaque(nc); 663 664 /* Do nothing if receive is not enabled. */ 665 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { 666 if (s->can_rx_state != 1) { 667 s->can_rx_state = 1; 668 DB_PRINT("can't receive - no enable\n"); 669 } 670 return false; 671 } 672 673 for (i = 0; i < s->num_priority_queues; i++) { 674 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 675 break; 676 } 677 }; 678 679 if (i == s->num_priority_queues) { 680 if (s->can_rx_state != 2) { 681 s->can_rx_state = 2; 682 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 683 } 684 return false; 685 } 686 687 if (s->can_rx_state != 0) { 688 s->can_rx_state = 0; 689 DB_PRINT("can receive\n"); 690 } 691 return true; 692 } 693 694 /* 695 * gem_update_int_status: 696 * Raise or lower interrupt based on current status. 697 */ 698 static void gem_update_int_status(CadenceGEMState *s) 699 { 700 int i; 701 702 qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 703 704 for (i = 1; i < s->num_priority_queues; ++i) { 705 qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 706 } 707 } 708 709 /* 710 * gem_receive_updatestats: 711 * Increment receive statistics. 712 */ 713 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 714 unsigned bytes) 715 { 716 uint64_t octets; 717 718 /* Total octets (bytes) received */ 719 octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 720 s->regs[R_OCTRXHI]; 721 octets += bytes; 722 s->regs[R_OCTRXLO] = octets >> 32; 723 s->regs[R_OCTRXHI] = octets; 724 725 /* Error-free Frames received */ 726 s->regs[R_RXCNT]++; 727 728 /* Error-free Broadcast Frames counter */ 729 if (!memcmp(packet, broadcast_addr, 6)) { 730 s->regs[R_RXBROADCNT]++; 731 } 732 733 /* Error-free Multicast Frames counter */ 734 if (packet[0] == 0x01) { 735 s->regs[R_RXMULTICNT]++; 736 } 737 738 if (bytes <= 64) { 739 s->regs[R_RX64CNT]++; 740 } else if (bytes <= 127) { 741 s->regs[R_RX65CNT]++; 742 } else if (bytes <= 255) { 743 s->regs[R_RX128CNT]++; 744 } else if (bytes <= 511) { 745 s->regs[R_RX256CNT]++; 746 } else if (bytes <= 1023) { 747 s->regs[R_RX512CNT]++; 748 } else if (bytes <= 1518) { 749 s->regs[R_RX1024CNT]++; 750 } else { 751 s->regs[R_RX1519CNT]++; 752 } 753 } 754 755 /* 756 * Get the MAC Address bit from the specified position 757 */ 758 static unsigned get_bit(const uint8_t *mac, unsigned bit) 759 { 760 unsigned byte; 761 762 byte = mac[bit / 8]; 763 byte >>= (bit & 0x7); 764 byte &= 1; 765 766 return byte; 767 } 768 769 /* 770 * Calculate a GEM MAC Address hash index 771 */ 772 static unsigned calc_mac_hash(const uint8_t *mac) 773 { 774 int index_bit, mac_bit; 775 unsigned hash_index; 776 777 hash_index = 0; 778 mac_bit = 5; 779 for (index_bit = 5; index_bit >= 0; index_bit--) { 780 hash_index |= (get_bit(mac, mac_bit) ^ 781 get_bit(mac, mac_bit + 6) ^ 782 get_bit(mac, mac_bit + 12) ^ 783 get_bit(mac, mac_bit + 18) ^ 784 get_bit(mac, mac_bit + 24) ^ 785 get_bit(mac, mac_bit + 30) ^ 786 get_bit(mac, mac_bit + 36) ^ 787 get_bit(mac, mac_bit + 42)) << index_bit; 788 mac_bit--; 789 } 790 791 return hash_index; 792 } 793 794 /* 795 * gem_mac_address_filter: 796 * Accept or reject this destination address? 797 * Returns: 798 * GEM_RX_REJECT: reject 799 * >= 0: Specific address accept (which matched SAR is returned) 800 * others for various other modes of accept: 801 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 802 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 803 */ 804 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 805 { 806 uint8_t *gem_spaddr; 807 int i, is_mc; 808 809 /* Promiscuous mode? */ 810 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { 811 return GEM_RX_PROMISCUOUS_ACCEPT; 812 } 813 814 if (!memcmp(packet, broadcast_addr, 6)) { 815 /* Reject broadcast packets? */ 816 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { 817 return GEM_RX_REJECT; 818 } 819 return GEM_RX_BROADCAST_ACCEPT; 820 } 821 822 /* Accept packets -w- hash match? */ 823 is_mc = is_multicast_ether_addr(packet); 824 if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || 825 (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { 826 uint64_t buckets; 827 unsigned hash_index; 828 829 hash_index = calc_mac_hash(packet); 830 buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 831 if ((buckets >> hash_index) & 1) { 832 return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 833 : GEM_RX_UNICAST_HASH_ACCEPT; 834 } 835 } 836 837 /* Check all 4 specific addresses */ 838 gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 839 for (i = 3; i >= 0; i--) { 840 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 841 return GEM_RX_SAR_ACCEPT + i; 842 } 843 } 844 845 /* No address match; reject the packet */ 846 return GEM_RX_REJECT; 847 } 848 849 /* Figure out which queue the received data should be sent to */ 850 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 851 unsigned rxbufsize) 852 { 853 uint32_t reg; 854 bool matched, mismatched; 855 int i, j; 856 857 for (i = 0; i < s->num_type1_screeners; i++) { 858 reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 859 matched = false; 860 mismatched = false; 861 862 /* Screening is based on UDP Port */ 863 if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { 864 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 865 if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { 866 matched = true; 867 } else { 868 mismatched = true; 869 } 870 } 871 872 /* Screening is based on DS/TC */ 873 if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { 874 uint8_t dscp = rxbuf_ptr[14 + 1]; 875 if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { 876 matched = true; 877 } else { 878 mismatched = true; 879 } 880 } 881 882 if (matched && !mismatched) { 883 return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); 884 } 885 } 886 887 for (i = 0; i < s->num_type2_screeners; i++) { 888 reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 889 matched = false; 890 mismatched = false; 891 892 if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { 893 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 894 int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, 895 ETHERTYPE_REG_INDEX); 896 897 if (et_idx > s->num_type2_screeners) { 898 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 899 "register index: %d\n", et_idx); 900 } 901 if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 902 et_idx]) { 903 matched = true; 904 } else { 905 mismatched = true; 906 } 907 } 908 909 /* Compare A, B, C */ 910 for (j = 0; j < 3; j++) { 911 uint32_t cr0, cr1, mask, compare; 912 uint16_t rx_cmp; 913 int offset; 914 int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, 915 R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); 916 917 if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, 918 R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { 919 continue; 920 } 921 922 if (cr_idx > s->num_type2_screeners) { 923 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 924 "register index: %d\n", cr_idx); 925 } 926 927 cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 928 cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; 929 offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); 930 931 switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { 932 case 3: /* Skip UDP header */ 933 qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 934 "unimplemented - assuming UDP\n"); 935 offset += 8; 936 /* Fallthrough */ 937 case 2: /* skip the IP header */ 938 offset += 20; 939 /* Fallthrough */ 940 case 1: /* Count from after the ethertype */ 941 offset += 14; 942 break; 943 case 0: 944 /* Offset from start of frame */ 945 break; 946 } 947 948 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 949 mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); 950 compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); 951 952 if ((rx_cmp & mask) == (compare & mask)) { 953 matched = true; 954 } else { 955 mismatched = true; 956 } 957 } 958 959 if (matched && !mismatched) { 960 return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); 961 } 962 } 963 964 /* We made it here, assume it's queue 0 */ 965 return 0; 966 } 967 968 static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 969 { 970 uint32_t base_addr = 0; 971 972 switch (q) { 973 case 0: 974 base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 975 break; 976 case 1 ... (MAX_PRIORITY_QUEUES - 1): 977 base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 978 R_RECEIVE_Q1_PTR) + q - 1]; 979 break; 980 default: 981 g_assert_not_reached(); 982 }; 983 984 return base_addr; 985 } 986 987 static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 988 { 989 return gem_get_queue_base_addr(s, true, q); 990 } 991 992 static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 993 { 994 return gem_get_queue_base_addr(s, false, q); 995 } 996 997 static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 998 { 999 hwaddr desc_addr = 0; 1000 1001 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 1002 desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 1003 } 1004 desc_addr <<= 32; 1005 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 1006 return desc_addr; 1007 } 1008 1009 static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 1010 { 1011 return gem_get_desc_addr(s, true, q); 1012 } 1013 1014 static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 1015 { 1016 return gem_get_desc_addr(s, false, q); 1017 } 1018 1019 static void gem_get_rx_desc(CadenceGEMState *s, int q) 1020 { 1021 hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 1022 1023 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 1024 1025 /* read current descriptor */ 1026 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1027 s->rx_desc[q], 1028 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1029 1030 /* Descriptor owned by software ? */ 1031 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 1032 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 1033 s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK; 1034 gem_set_isr(s, q, R_ISR_RX_USED_MASK); 1035 /* Handle interrupt consequences */ 1036 gem_update_int_status(s); 1037 } 1038 } 1039 1040 /* 1041 * gem_receive: 1042 * Fit a packet handed to us by QEMU into the receive descriptor ring. 1043 */ 1044 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1045 { 1046 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1047 unsigned rxbufsize, bytes_to_copy; 1048 unsigned rxbuf_offset; 1049 uint8_t *rxbuf_ptr; 1050 bool first_desc = true; 1051 int maf; 1052 int q = 0; 1053 1054 /* Is this destination MAC address "for us" ? */ 1055 maf = gem_mac_address_filter(s, buf); 1056 if (maf == GEM_RX_REJECT) { 1057 return size; /* no, drop silently b/c it's not an error */ 1058 } 1059 1060 /* Discard packets with receive length error enabled ? */ 1061 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { 1062 unsigned type_len; 1063 1064 /* Fish the ethertype / length field out of the RX packet */ 1065 type_len = buf[12] << 8 | buf[13]; 1066 /* It is a length field, not an ethertype */ 1067 if (type_len < 0x600) { 1068 if (size < type_len) { 1069 /* discard */ 1070 return -1; 1071 } 1072 } 1073 } 1074 1075 /* 1076 * Determine configured receive buffer offset (probably 0) 1077 */ 1078 rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); 1079 1080 /* The configure size of each receive buffer. Determines how many 1081 * buffers needed to hold this packet. 1082 */ 1083 rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); 1084 rxbufsize *= GEM_DMACFG_RBUFSZ_MUL; 1085 1086 bytes_to_copy = size; 1087 1088 /* Hardware allows a zero value here but warns against it. To avoid QEMU 1089 * indefinite loops we enforce a minimum value here 1090 */ 1091 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1092 rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1093 } 1094 1095 /* Pad to minimum length. Assume FCS field is stripped, logic 1096 * below will increment it to the real minimum of 64 when 1097 * not FCS stripping 1098 */ 1099 if (size < 60) { 1100 size = 60; 1101 } 1102 1103 /* Strip of FCS field ? (usually yes) */ 1104 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { 1105 rxbuf_ptr = (void *)buf; 1106 } else { 1107 unsigned crc_val; 1108 1109 if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 1110 size = MAX_FRAME_SIZE - sizeof(crc_val); 1111 } 1112 bytes_to_copy = size; 1113 /* The application wants the FCS field, which QEMU does not provide. 1114 * We must try and calculate one. 1115 */ 1116 1117 memcpy(s->rx_packet, buf, size); 1118 memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 1119 rxbuf_ptr = s->rx_packet; 1120 crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 1121 memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 1122 1123 bytes_to_copy += 4; 1124 size += 4; 1125 } 1126 1127 DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 1128 1129 /* Find which queue we are targeting */ 1130 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1131 1132 if (size > gem_get_max_buf_len(s, false)) { 1133 qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 1134 gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK); 1135 return -1; 1136 } 1137 1138 while (bytes_to_copy) { 1139 hwaddr desc_addr; 1140 1141 /* Do nothing if receive is not enabled. */ 1142 if (!gem_can_receive(nc)) { 1143 return -1; 1144 } 1145 1146 DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1147 MIN(bytes_to_copy, rxbufsize), 1148 rx_desc_get_buffer(s, s->rx_desc[q])); 1149 1150 /* Copy packet data to emulated DMA buffer */ 1151 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 1152 rxbuf_offset, 1153 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1154 MIN(bytes_to_copy, rxbufsize)); 1155 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 1156 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 1157 1158 rx_desc_clear_control(s->rx_desc[q]); 1159 1160 /* Update the descriptor. */ 1161 if (first_desc) { 1162 rx_desc_set_sof(s->rx_desc[q]); 1163 first_desc = false; 1164 } 1165 if (bytes_to_copy == 0) { 1166 rx_desc_set_eof(s->rx_desc[q]); 1167 rx_desc_set_length(s->rx_desc[q], size); 1168 } 1169 rx_desc_set_ownership(s->rx_desc[q]); 1170 1171 switch (maf) { 1172 case GEM_RX_PROMISCUOUS_ACCEPT: 1173 break; 1174 case GEM_RX_BROADCAST_ACCEPT: 1175 rx_desc_set_broadcast(s->rx_desc[q]); 1176 break; 1177 case GEM_RX_UNICAST_HASH_ACCEPT: 1178 rx_desc_set_unicast_hash(s->rx_desc[q]); 1179 break; 1180 case GEM_RX_MULTICAST_HASH_ACCEPT: 1181 rx_desc_set_multicast_hash(s->rx_desc[q]); 1182 break; 1183 case GEM_RX_REJECT: 1184 abort(); 1185 default: /* SAR */ 1186 rx_desc_set_sar(s->rx_desc[q], maf); 1187 } 1188 1189 /* Descriptor write-back. */ 1190 desc_addr = gem_get_rx_desc_addr(s, q); 1191 address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1192 s->rx_desc[q], 1193 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1194 1195 /* Next descriptor */ 1196 if (rx_desc_get_wrap(s->rx_desc[q])) { 1197 DB_PRINT("wrapping RX descriptor list\n"); 1198 s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 1199 } else { 1200 DB_PRINT("incrementing RX descriptor list\n"); 1201 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 1202 } 1203 1204 gem_get_rx_desc(s, q); 1205 } 1206 1207 /* Count it */ 1208 gem_receive_updatestats(s, buf, size); 1209 1210 s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK; 1211 gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK); 1212 1213 /* Handle interrupt consequences */ 1214 gem_update_int_status(s); 1215 1216 return size; 1217 } 1218 1219 /* 1220 * gem_transmit_updatestats: 1221 * Increment transmit statistics. 1222 */ 1223 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 1224 unsigned bytes) 1225 { 1226 uint64_t octets; 1227 1228 /* Total octets (bytes) transmitted */ 1229 octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1230 s->regs[R_OCTTXHI]; 1231 octets += bytes; 1232 s->regs[R_OCTTXLO] = octets >> 32; 1233 s->regs[R_OCTTXHI] = octets; 1234 1235 /* Error-free Frames transmitted */ 1236 s->regs[R_TXCNT]++; 1237 1238 /* Error-free Broadcast Frames counter */ 1239 if (!memcmp(packet, broadcast_addr, 6)) { 1240 s->regs[R_TXBCNT]++; 1241 } 1242 1243 /* Error-free Multicast Frames counter */ 1244 if (packet[0] == 0x01) { 1245 s->regs[R_TXMCNT]++; 1246 } 1247 1248 if (bytes <= 64) { 1249 s->regs[R_TX64CNT]++; 1250 } else if (bytes <= 127) { 1251 s->regs[R_TX65CNT]++; 1252 } else if (bytes <= 255) { 1253 s->regs[R_TX128CNT]++; 1254 } else if (bytes <= 511) { 1255 s->regs[R_TX256CNT]++; 1256 } else if (bytes <= 1023) { 1257 s->regs[R_TX512CNT]++; 1258 } else if (bytes <= 1518) { 1259 s->regs[R_TX1024CNT]++; 1260 } else { 1261 s->regs[R_TX1519CNT]++; 1262 } 1263 } 1264 1265 /* 1266 * gem_transmit: 1267 * Fish packets out of the descriptor ring and feed them to QEMU 1268 */ 1269 static void gem_transmit(CadenceGEMState *s) 1270 { 1271 uint32_t desc[DESC_MAX_NUM_WORDS]; 1272 hwaddr packet_desc_addr; 1273 uint8_t *p; 1274 unsigned total_bytes; 1275 int q = 0; 1276 1277 /* Do nothing if transmit is not enabled. */ 1278 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 1279 return; 1280 } 1281 1282 DB_PRINT("\n"); 1283 1284 /* The packet we will hand off to QEMU. 1285 * Packets scattered across multiple descriptors are gathered to this 1286 * one contiguous buffer first. 1287 */ 1288 p = s->tx_packet; 1289 total_bytes = 0; 1290 1291 for (q = s->num_priority_queues - 1; q >= 0; q--) { 1292 /* read current descriptor */ 1293 packet_desc_addr = gem_get_tx_desc_addr(s, q); 1294 1295 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1296 address_space_read(&s->dma_as, packet_desc_addr, 1297 MEMTXATTRS_UNSPECIFIED, desc, 1298 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1299 /* Handle all descriptors owned by hardware */ 1300 while (tx_desc_get_used(desc) == 0) { 1301 1302 /* Do nothing if transmit is not enabled. */ 1303 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 1304 return; 1305 } 1306 print_gem_tx_desc(desc, q); 1307 1308 /* The real hardware would eat this (and possibly crash). 1309 * For QEMU let's lend a helping hand. 1310 */ 1311 if ((tx_desc_get_buffer(s, desc) == 0) || 1312 (tx_desc_get_length(desc) == 0)) { 1313 DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 1314 packet_desc_addr); 1315 break; 1316 } 1317 1318 if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 1319 (p - s->tx_packet)) { 1320 qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 1321 HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1322 packet_desc_addr, tx_desc_get_length(desc), 1323 gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 1324 gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK); 1325 break; 1326 } 1327 1328 /* Gather this fragment of the packet from "dma memory" to our 1329 * contig buffer. 1330 */ 1331 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 1332 MEMTXATTRS_UNSPECIFIED, 1333 p, tx_desc_get_length(desc)); 1334 p += tx_desc_get_length(desc); 1335 total_bytes += tx_desc_get_length(desc); 1336 1337 /* Last descriptor for this packet; hand the whole thing off */ 1338 if (tx_desc_get_last(desc)) { 1339 uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1340 hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 1341 1342 /* Modify the 1st descriptor of this packet to be owned by 1343 * the processor. 1344 */ 1345 address_space_read(&s->dma_as, desc_addr, 1346 MEMTXATTRS_UNSPECIFIED, desc_first, 1347 sizeof(desc_first)); 1348 tx_desc_set_used(desc_first); 1349 address_space_write(&s->dma_as, desc_addr, 1350 MEMTXATTRS_UNSPECIFIED, desc_first, 1351 sizeof(desc_first)); 1352 /* Advance the hardware current descriptor past this packet */ 1353 if (tx_desc_get_wrap(desc)) { 1354 s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 1355 } else { 1356 s->tx_desc_addr[q] = packet_desc_addr + 1357 4 * gem_get_desc_len(s, false); 1358 } 1359 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 1360 1361 s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK; 1362 gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK); 1363 1364 /* Handle interrupt consequences */ 1365 gem_update_int_status(s); 1366 1367 /* Is checksum offload enabled? */ 1368 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) { 1369 net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 1370 } 1371 1372 /* Update MAC statistics */ 1373 gem_transmit_updatestats(s, s->tx_packet, total_bytes); 1374 1375 /* Send the packet somewhere */ 1376 if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, 1377 LOOPBACK_LOCAL)) { 1378 qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 1379 total_bytes); 1380 } else { 1381 qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 1382 total_bytes); 1383 } 1384 1385 /* Prepare for next packet */ 1386 p = s->tx_packet; 1387 total_bytes = 0; 1388 } 1389 1390 /* read next descriptor */ 1391 if (tx_desc_get_wrap(desc)) { 1392 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 1393 packet_desc_addr = s->regs[R_TBQPH]; 1394 packet_desc_addr <<= 32; 1395 } else { 1396 packet_desc_addr = 0; 1397 } 1398 packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 1399 } else { 1400 packet_desc_addr += 4 * gem_get_desc_len(s, false); 1401 } 1402 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1403 address_space_read(&s->dma_as, packet_desc_addr, 1404 MEMTXATTRS_UNSPECIFIED, desc, 1405 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1406 } 1407 1408 if (tx_desc_get_used(desc)) { 1409 s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK; 1410 /* IRQ TXUSED is defined only for queue 0 */ 1411 if (q == 0) { 1412 gem_set_isr(s, 0, R_ISR_TX_USED_MASK); 1413 } 1414 gem_update_int_status(s); 1415 } 1416 } 1417 } 1418 1419 static void gem_phy_reset(CadenceGEMState *s) 1420 { 1421 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 1422 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 1423 s->phy_regs[PHY_REG_STATUS] = 0x7969; 1424 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 1425 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 1426 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 1427 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 1428 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 1429 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 1430 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 1431 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 1432 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 1433 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 1434 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 1435 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 1436 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 1437 s->phy_regs[PHY_REG_LED] = 0x4100; 1438 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 1439 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 1440 1441 phy_update_link(s); 1442 } 1443 1444 static void gem_reset(DeviceState *d) 1445 { 1446 int i; 1447 CadenceGEMState *s = CADENCE_GEM(d); 1448 const uint8_t *a; 1449 uint32_t queues_mask = 0; 1450 1451 DB_PRINT("\n"); 1452 1453 /* Set post reset register values */ 1454 memset(&s->regs[0], 0, sizeof(s->regs)); 1455 s->regs[R_NWCFG] = 0x00080000; 1456 s->regs[R_NWSTATUS] = 0x00000006; 1457 s->regs[R_DMACFG] = 0x00020784; 1458 s->regs[R_IMR] = 0x07ffffff; 1459 s->regs[R_TXPAUSE] = 0x0000ffff; 1460 s->regs[R_TXPARTIALSF] = 0x000003ff; 1461 s->regs[R_RXPARTIALSF] = 0x000003ff; 1462 s->regs[R_MODID] = s->revision; 1463 s->regs[R_DESCONF] = 0x02D00111; 1464 s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1465 s->regs[R_DESCONF5] = 0x002f2045; 1466 s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK; 1467 s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1468 s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1469 1470 if (s->num_priority_queues > 1) { 1471 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1472 s->regs[R_DESCONF6] |= queues_mask; 1473 } 1474 1475 /* Set MAC address */ 1476 a = &s->conf.macaddr.a[0]; 1477 s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1478 s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1479 1480 for (i = 0; i < 4; i++) { 1481 s->sar_active[i] = false; 1482 } 1483 1484 gem_phy_reset(s); 1485 1486 gem_update_int_status(s); 1487 } 1488 1489 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1490 { 1491 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1492 return s->phy_regs[reg_num]; 1493 } 1494 1495 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1496 { 1497 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1498 1499 switch (reg_num) { 1500 case PHY_REG_CONTROL: 1501 if (val & PHY_REG_CONTROL_RST) { 1502 /* Phy reset */ 1503 gem_phy_reset(s); 1504 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1505 s->phy_loop = 0; 1506 } 1507 if (val & PHY_REG_CONTROL_ANEG) { 1508 /* Complete autonegotiation immediately */ 1509 val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 1510 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1511 } 1512 if (val & PHY_REG_CONTROL_LOOP) { 1513 DB_PRINT("PHY placed in loopback\n"); 1514 s->phy_loop = 1; 1515 } else { 1516 s->phy_loop = 0; 1517 } 1518 break; 1519 } 1520 s->phy_regs[reg_num] = val; 1521 } 1522 1523 /* 1524 * gem_read32: 1525 * Read a GEM register. 1526 */ 1527 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1528 { 1529 CadenceGEMState *s; 1530 uint32_t retval; 1531 s = opaque; 1532 1533 offset >>= 2; 1534 retval = s->regs[offset]; 1535 1536 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1537 1538 switch (offset) { 1539 case R_ISR: 1540 DB_PRINT("lowering irqs on ISR read\n"); 1541 /* The interrupts get updated at the end of the function. */ 1542 break; 1543 case R_PHYMNTNC: 1544 if (retval & GEM_PHYMNTNC_OP_R) { 1545 uint32_t phy_addr, reg_num; 1546 1547 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1548 if (phy_addr == s->phy_addr) { 1549 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1550 retval &= 0xFFFF0000; 1551 retval |= gem_phy_read(s, reg_num); 1552 } else { 1553 retval |= 0xFFFF; /* No device at this address */ 1554 } 1555 } 1556 break; 1557 } 1558 1559 /* Squash read to clear bits */ 1560 s->regs[offset] &= ~(s->regs_rtc[offset]); 1561 1562 /* Do not provide write only bits */ 1563 retval &= ~(s->regs_wo[offset]); 1564 1565 DB_PRINT("0x%08x\n", retval); 1566 gem_update_int_status(s); 1567 return retval; 1568 } 1569 1570 /* 1571 * gem_write32: 1572 * Write a GEM register. 1573 */ 1574 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1575 unsigned size) 1576 { 1577 CadenceGEMState *s = (CadenceGEMState *)opaque; 1578 uint32_t readonly; 1579 int i; 1580 1581 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1582 offset >>= 2; 1583 1584 /* Squash bits which are read only in write value */ 1585 val &= ~(s->regs_ro[offset]); 1586 /* Preserve (only) bits which are read only and wtc in register */ 1587 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1588 1589 /* Copy register write to backing store */ 1590 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1591 1592 /* do w1c */ 1593 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1594 1595 /* Handle register write side effects */ 1596 switch (offset) { 1597 case R_NWCTRL: 1598 if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { 1599 for (i = 0; i < s->num_priority_queues; ++i) { 1600 gem_get_rx_desc(s, i); 1601 } 1602 } 1603 if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { 1604 gem_transmit(s); 1605 } 1606 if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { 1607 /* Reset to start of Q when transmit disabled. */ 1608 for (i = 0; i < s->num_priority_queues; i++) { 1609 s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 1610 } 1611 } 1612 if (gem_can_receive(qemu_get_queue(s->nic))) { 1613 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1614 } 1615 break; 1616 1617 case R_TXSTATUS: 1618 gem_update_int_status(s); 1619 break; 1620 case R_RXQBASE: 1621 s->rx_desc_addr[0] = val; 1622 break; 1623 case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1624 s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 1625 break; 1626 case R_TXQBASE: 1627 s->tx_desc_addr[0] = val; 1628 break; 1629 case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1630 s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 1631 break; 1632 case R_RXSTATUS: 1633 gem_update_int_status(s); 1634 break; 1635 case R_IER: 1636 s->regs[R_IMR] &= ~val; 1637 gem_update_int_status(s); 1638 break; 1639 case R_JUMBO_MAX_LEN: 1640 s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 1641 break; 1642 case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1643 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 1644 gem_update_int_status(s); 1645 break; 1646 case R_IDR: 1647 s->regs[R_IMR] |= val; 1648 gem_update_int_status(s); 1649 break; 1650 case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1651 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 1652 gem_update_int_status(s); 1653 break; 1654 case R_SPADDR1LO: 1655 case R_SPADDR2LO: 1656 case R_SPADDR3LO: 1657 case R_SPADDR4LO: 1658 s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 1659 break; 1660 case R_SPADDR1HI: 1661 case R_SPADDR2HI: 1662 case R_SPADDR3HI: 1663 case R_SPADDR4HI: 1664 s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 1665 break; 1666 case R_PHYMNTNC: 1667 if (val & GEM_PHYMNTNC_OP_W) { 1668 uint32_t phy_addr, reg_num; 1669 1670 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1671 if (phy_addr == s->phy_addr) { 1672 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1673 gem_phy_write(s, reg_num, val); 1674 } 1675 } 1676 break; 1677 } 1678 1679 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1680 } 1681 1682 static const MemoryRegionOps gem_ops = { 1683 .read = gem_read, 1684 .write = gem_write, 1685 .endianness = DEVICE_LITTLE_ENDIAN, 1686 }; 1687 1688 static void gem_set_link(NetClientState *nc) 1689 { 1690 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1691 1692 DB_PRINT("\n"); 1693 phy_update_link(s); 1694 gem_update_int_status(s); 1695 } 1696 1697 static NetClientInfo net_gem_info = { 1698 .type = NET_CLIENT_DRIVER_NIC, 1699 .size = sizeof(NICState), 1700 .can_receive = gem_can_receive, 1701 .receive = gem_receive, 1702 .link_status_changed = gem_set_link, 1703 }; 1704 1705 static void gem_realize(DeviceState *dev, Error **errp) 1706 { 1707 CadenceGEMState *s = CADENCE_GEM(dev); 1708 int i; 1709 1710 address_space_init(&s->dma_as, 1711 s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 1712 1713 if (s->num_priority_queues == 0 || 1714 s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1715 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1716 s->num_priority_queues); 1717 return; 1718 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1719 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1720 s->num_type1_screeners); 1721 return; 1722 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1723 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1724 s->num_type2_screeners); 1725 return; 1726 } 1727 1728 for (i = 0; i < s->num_priority_queues; ++i) { 1729 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1730 } 1731 1732 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1733 1734 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1735 object_get_typename(OBJECT(dev)), dev->id, s); 1736 1737 if (s->jumbo_max_len > MAX_FRAME_SIZE) { 1738 error_setg(errp, "jumbo-max-len is greater than %d", 1739 MAX_FRAME_SIZE); 1740 return; 1741 } 1742 } 1743 1744 static void gem_init(Object *obj) 1745 { 1746 CadenceGEMState *s = CADENCE_GEM(obj); 1747 DeviceState *dev = DEVICE(obj); 1748 1749 DB_PRINT("\n"); 1750 1751 gem_init_register_masks(s); 1752 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1753 "enet", sizeof(s->regs)); 1754 1755 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1756 } 1757 1758 static const VMStateDescription vmstate_cadence_gem = { 1759 .name = "cadence_gem", 1760 .version_id = 4, 1761 .minimum_version_id = 4, 1762 .fields = (VMStateField[]) { 1763 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1764 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1765 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1766 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1767 MAX_PRIORITY_QUEUES), 1768 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1769 MAX_PRIORITY_QUEUES), 1770 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1771 VMSTATE_END_OF_LIST(), 1772 } 1773 }; 1774 1775 static Property gem_properties[] = { 1776 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1777 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1778 GEM_MODID_VALUE), 1779 DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 1780 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1781 num_priority_queues, 1), 1782 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1783 num_type1_screeners, 4), 1784 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1785 num_type2_screeners, 4), 1786 DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 1787 jumbo_max_len, 10240), 1788 DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 1789 TYPE_MEMORY_REGION, MemoryRegion *), 1790 DEFINE_PROP_END_OF_LIST(), 1791 }; 1792 1793 static void gem_class_init(ObjectClass *klass, void *data) 1794 { 1795 DeviceClass *dc = DEVICE_CLASS(klass); 1796 1797 dc->realize = gem_realize; 1798 device_class_set_props(dc, gem_properties); 1799 dc->vmsd = &vmstate_cadence_gem; 1800 dc->reset = gem_reset; 1801 } 1802 1803 static const TypeInfo gem_info = { 1804 .name = TYPE_CADENCE_GEM, 1805 .parent = TYPE_SYS_BUS_DEVICE, 1806 .instance_size = sizeof(CadenceGEMState), 1807 .instance_init = gem_init, 1808 .class_init = gem_class_init, 1809 }; 1810 1811 static void gem_register_types(void) 1812 { 1813 type_register_static(&gem_info); 1814 } 1815 1816 type_init(gem_register_types) 1817