1 /* 2 * QEMU Cadence GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include <zlib.h> /* For crc32 */ 27 28 #include "hw/irq.h" 29 #include "hw/net/cadence_gem.h" 30 #include "hw/qdev-properties.h" 31 #include "hw/registerfields.h" 32 #include "migration/vmstate.h" 33 #include "qapi/error.h" 34 #include "qemu/log.h" 35 #include "qemu/module.h" 36 #include "sysemu/dma.h" 37 #include "net/checksum.h" 38 #include "net/eth.h" 39 40 #define CADENCE_GEM_ERR_DEBUG 0 41 #define DB_PRINT(...) do {\ 42 if (CADENCE_GEM_ERR_DEBUG) { \ 43 qemu_log(": %s: ", __func__); \ 44 qemu_log(__VA_ARGS__); \ 45 } \ 46 } while (0) 47 48 REG32(NWCTRL, 0x0) /* Network Control reg */ 49 FIELD(NWCTRL, LOOPBACK , 0, 1) 50 FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) 51 FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) 52 FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) 53 FIELD(NWCTRL, MAN_PORT_EN , 4, 1) 54 FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) 55 FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) 56 FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) 57 FIELD(NWCTRL, BACK_PRESSURE, 8, 1) 58 FIELD(NWCTRL, TRANSMIT_START , 9, 1) 59 FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) 60 FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) 61 FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) 62 FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) 63 FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) 64 FIELD(NWCTRL, STORE_RX_TS, 15, 1) 65 FIELD(NWCTRL, PFC_ENABLE, 16, 1) 66 FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) 67 FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) 68 FIELD(NWCTRL, TX_LPI_EN, 19, 1) 69 FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) 70 FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) 71 FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) 72 FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) 73 FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) 74 FIELD(NWCTRL, PFC_CTRL , 25, 1) 75 FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) 76 FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) 77 FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) 78 FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) 79 FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) 80 81 REG32(NWCFG, 0x4) /* Network Config reg */ 82 FIELD(NWCFG, SPEED, 0, 1) 83 FIELD(NWCFG, FULL_DUPLEX, 1, 1) 84 FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) 85 FIELD(NWCFG, JUMBO_FRAMES, 3, 1) 86 FIELD(NWCFG, PROMISC, 4, 1) 87 FIELD(NWCFG, NO_BROADCAST, 5, 1) 88 FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) 89 FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) 90 FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) 91 FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) 92 FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) 93 FIELD(NWCFG, PCS_SELECT, 11, 1) 94 FIELD(NWCFG, RETRY_TEST, 12, 1) 95 FIELD(NWCFG, PAUSE_ENABLE, 13, 1) 96 FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) 97 FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) 98 FIELD(NWCFG, FCS_REMOVE, 17, 1) 99 FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) 100 FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) 101 FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) 102 FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) 103 FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) 104 FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) 105 FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) 106 FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) 107 FIELD(NWCFG, NSP_ACCEPT, 29, 1) 108 FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) 109 FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) 110 111 REG32(NWSTATUS, 0x8) /* Network Status reg */ 112 REG32(USERIO, 0xc) /* User IO reg */ 113 114 REG32(DMACFG, 0x10) /* DMA Control reg */ 115 FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1) 116 FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1) 117 FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1) 118 FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1) 119 FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1) 120 FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1) 121 FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1) 122 FIELD(DMACFG, RX_BUF_SIZE, 16, 8) 123 FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1) 124 FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1) 125 FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1) 126 FIELD(DMACFG, TX_PBUF_SIZE, 10, 1) 127 FIELD(DMACFG, RX_PBUF_SIZE, 8, 2) 128 FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1) 129 FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1) 130 FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1) 131 FIELD(DMACFG, AMBA_BURST_LEN , 0, 5) 132 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 133 134 REG32(TXSTATUS, 0x14) /* TX Status reg */ 135 REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 136 REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 137 REG32(RXSTATUS, 0x20) /* RX Status reg */ 138 REG32(ISR, 0x24) /* Interrupt Status reg */ 139 REG32(IER, 0x28) /* Interrupt Enable reg */ 140 REG32(IDR, 0x2c) /* Interrupt Disable reg */ 141 REG32(IMR, 0x30) /* Interrupt Mask reg */ 142 REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 143 REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 144 REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 145 REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 146 REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 147 REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 148 REG32(HASHLO, 0x80) /* Hash Low address reg */ 149 REG32(HASHHI, 0x84) /* Hash High address reg */ 150 REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 151 REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 152 REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 153 REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 154 REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 155 REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 156 REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 157 REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 158 REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 159 REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 160 REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 161 REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 162 REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 163 REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 164 REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 165 REG32(MODID, 0xfc) /* Module ID reg */ 166 REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 167 REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 168 REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 169 REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 170 REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 171 REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 172 REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 173 REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 174 REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 175 REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 176 REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 177 REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 178 REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 179 REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 180 REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 181 REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 182 REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 183 REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 184 REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 185 REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 186 REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 187 REG32(OCTRXHI, 0x154) /* Octects Received register High */ 188 REG32(RXCNT, 0x158) /* Error-free Frames Received */ 189 REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 190 REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 191 REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 192 REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 193 REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 194 REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 195 REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 196 REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 197 REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 198 REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 199 REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 200 REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 201 REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 202 REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 203 REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 204 REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 205 REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 206 REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 207 REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 208 REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 209 REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 210 REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 211 212 REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 213 REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 214 REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 215 REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 216 REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 217 REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 218 REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 219 REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 220 REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 221 REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 222 REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 223 REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 224 225 /* Design Configuration Registers */ 226 REG32(DESCONF, 0x280) 227 REG32(DESCONF2, 0x284) 228 REG32(DESCONF3, 0x288) 229 REG32(DESCONF4, 0x28c) 230 REG32(DESCONF5, 0x290) 231 REG32(DESCONF6, 0x294) 232 #define GEM_DESCONF6_64B_MASK (1U << 23) 233 REG32(DESCONF7, 0x298) 234 235 REG32(INT_Q1_STATUS, 0x400) 236 REG32(INT_Q1_MASK, 0x640) 237 238 REG32(TRANSMIT_Q1_PTR, 0x440) 239 REG32(TRANSMIT_Q7_PTR, 0x458) 240 241 REG32(RECEIVE_Q1_PTR, 0x480) 242 REG32(RECEIVE_Q7_PTR, 0x498) 243 244 REG32(TBQPH, 0x4c8) 245 REG32(RBQPH, 0x4d4) 246 247 REG32(INT_Q1_ENABLE, 0x600) 248 REG32(INT_Q7_ENABLE, 0x618) 249 250 REG32(INT_Q1_DISABLE, 0x620) 251 REG32(INT_Q7_DISABLE, 0x638) 252 253 REG32(SCREENING_TYPE1_REG0, 0x500) 254 FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) 255 FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) 256 FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) 257 FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) 258 FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) 259 FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) 260 261 REG32(SCREENING_TYPE2_REG0, 0x540) 262 FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) 263 FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) 264 FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) 265 FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) 266 FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) 267 FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) 268 FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) 269 FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) 270 FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) 271 FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) 272 FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) 273 FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) 274 275 REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 276 277 REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 278 FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) 279 FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) 280 281 REG32(TYPE2_COMPARE_0_WORD_1, 0x704) 282 FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) 283 FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) 284 FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) 285 FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) 286 287 /*****************************************/ 288 289 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 290 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 291 292 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 293 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 294 295 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 296 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 297 #define GEM_INT_AMBA_ERR 0x00000040 298 #define GEM_INT_TXUSED 0x00000008 299 #define GEM_INT_RXUSED 0x00000004 300 #define GEM_INT_RXCMPL 0x00000002 301 302 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 303 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 304 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 305 #define GEM_PHYMNTNC_ADDR_SHFT 23 306 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 307 #define GEM_PHYMNTNC_REG_SHIFT 18 308 309 /* Marvell PHY definitions */ 310 #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 311 312 #define PHY_REG_CONTROL 0 313 #define PHY_REG_STATUS 1 314 #define PHY_REG_PHYID1 2 315 #define PHY_REG_PHYID2 3 316 #define PHY_REG_ANEGADV 4 317 #define PHY_REG_LINKPABIL 5 318 #define PHY_REG_ANEGEXP 6 319 #define PHY_REG_NEXTP 7 320 #define PHY_REG_LINKPNEXTP 8 321 #define PHY_REG_100BTCTRL 9 322 #define PHY_REG_1000BTSTAT 10 323 #define PHY_REG_EXTSTAT 15 324 #define PHY_REG_PHYSPCFC_CTL 16 325 #define PHY_REG_PHYSPCFC_ST 17 326 #define PHY_REG_INT_EN 18 327 #define PHY_REG_INT_ST 19 328 #define PHY_REG_EXT_PHYSPCFC_CTL 20 329 #define PHY_REG_RXERR 21 330 #define PHY_REG_EACD 22 331 #define PHY_REG_LED 24 332 #define PHY_REG_LED_OVRD 25 333 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 334 #define PHY_REG_EXT_PHYSPCFC_ST 27 335 #define PHY_REG_CABLE_DIAG 28 336 337 #define PHY_REG_CONTROL_RST 0x8000 338 #define PHY_REG_CONTROL_LOOP 0x4000 339 #define PHY_REG_CONTROL_ANEG 0x1000 340 #define PHY_REG_CONTROL_ANRESTART 0x0200 341 342 #define PHY_REG_STATUS_LINK 0x0004 343 #define PHY_REG_STATUS_ANEGCMPL 0x0020 344 345 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 346 #define PHY_REG_INT_ST_LINKC 0x0400 347 #define PHY_REG_INT_ST_ENERGY 0x0010 348 349 /***********************************************************************/ 350 #define GEM_RX_REJECT (-1) 351 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 352 #define GEM_RX_BROADCAST_ACCEPT (-3) 353 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 354 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 355 356 #define GEM_RX_SAR_ACCEPT 0 357 358 /***********************************************************************/ 359 360 #define DESC_1_USED 0x80000000 361 #define DESC_1_LENGTH 0x00001FFF 362 363 #define DESC_1_TX_WRAP 0x40000000 364 #define DESC_1_TX_LAST 0x00008000 365 366 #define DESC_0_RX_WRAP 0x00000002 367 #define DESC_0_RX_OWNERSHIP 0x00000001 368 369 #define R_DESC_1_RX_SAR_SHIFT 25 370 #define R_DESC_1_RX_SAR_LENGTH 2 371 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 372 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 373 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 374 #define R_DESC_1_RX_BROADCAST (1 << 31) 375 376 #define DESC_1_RX_SOF 0x00004000 377 #define DESC_1_RX_EOF 0x00008000 378 379 #define GEM_MODID_VALUE 0x00020118 380 381 static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 382 { 383 uint64_t ret = desc[0]; 384 385 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 386 ret |= (uint64_t)desc[2] << 32; 387 } 388 return ret; 389 } 390 391 static inline unsigned tx_desc_get_used(uint32_t *desc) 392 { 393 return (desc[1] & DESC_1_USED) ? 1 : 0; 394 } 395 396 static inline void tx_desc_set_used(uint32_t *desc) 397 { 398 desc[1] |= DESC_1_USED; 399 } 400 401 static inline unsigned tx_desc_get_wrap(uint32_t *desc) 402 { 403 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 404 } 405 406 static inline unsigned tx_desc_get_last(uint32_t *desc) 407 { 408 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 409 } 410 411 static inline unsigned tx_desc_get_length(uint32_t *desc) 412 { 413 return desc[1] & DESC_1_LENGTH; 414 } 415 416 static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 417 { 418 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 419 DB_PRINT("bufaddr: 0x%08x\n", *desc); 420 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 421 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 422 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 423 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 424 } 425 426 static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 427 { 428 uint64_t ret = desc[0] & ~0x3UL; 429 430 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 431 ret |= (uint64_t)desc[2] << 32; 432 } 433 return ret; 434 } 435 436 static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 437 { 438 int ret = 2; 439 440 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 441 ret += 2; 442 } 443 if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK 444 : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) { 445 ret += 2; 446 } 447 448 assert(ret <= DESC_MAX_NUM_WORDS); 449 return ret; 450 } 451 452 static inline unsigned rx_desc_get_wrap(uint32_t *desc) 453 { 454 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 455 } 456 457 static inline unsigned rx_desc_get_ownership(uint32_t *desc) 458 { 459 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 460 } 461 462 static inline void rx_desc_set_ownership(uint32_t *desc) 463 { 464 desc[0] |= DESC_0_RX_OWNERSHIP; 465 } 466 467 static inline void rx_desc_set_sof(uint32_t *desc) 468 { 469 desc[1] |= DESC_1_RX_SOF; 470 } 471 472 static inline void rx_desc_clear_control(uint32_t *desc) 473 { 474 desc[1] = 0; 475 } 476 477 static inline void rx_desc_set_eof(uint32_t *desc) 478 { 479 desc[1] |= DESC_1_RX_EOF; 480 } 481 482 static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 483 { 484 desc[1] &= ~DESC_1_LENGTH; 485 desc[1] |= len; 486 } 487 488 static inline void rx_desc_set_broadcast(uint32_t *desc) 489 { 490 desc[1] |= R_DESC_1_RX_BROADCAST; 491 } 492 493 static inline void rx_desc_set_unicast_hash(uint32_t *desc) 494 { 495 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 496 } 497 498 static inline void rx_desc_set_multicast_hash(uint32_t *desc) 499 { 500 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 501 } 502 503 static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 504 { 505 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 506 sar_idx); 507 desc[1] |= R_DESC_1_RX_SAR_MATCH; 508 } 509 510 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 511 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 512 513 static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 514 { 515 uint32_t size; 516 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { 517 size = s->regs[R_JUMBO_MAX_LEN]; 518 if (size > s->jumbo_max_len) { 519 size = s->jumbo_max_len; 520 qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 521 " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 522 } 523 } else if (tx) { 524 size = 1518; 525 } else { 526 size = FIELD_EX32(s->regs[R_NWCFG], 527 NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; 528 } 529 return size; 530 } 531 532 static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 533 { 534 if (q == 0) { 535 s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 536 } else { 537 s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 538 ~(s->regs[R_INT_Q1_MASK + q - 1]); 539 } 540 } 541 542 /* 543 * gem_init_register_masks: 544 * One time initialization. 545 * Set masks to identify which register bits have magical clear properties 546 */ 547 static void gem_init_register_masks(CadenceGEMState *s) 548 { 549 unsigned int i; 550 /* Mask of register bits which are read only */ 551 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 552 s->regs_ro[R_NWCTRL] = 0xFFF80000; 553 s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 554 s->regs_ro[R_DMACFG] = 0x8E00F000; 555 s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 556 s->regs_ro[R_RXQBASE] = 0x00000003; 557 s->regs_ro[R_TXQBASE] = 0x00000003; 558 s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 559 s->regs_ro[R_ISR] = 0xFFFFFFFF; 560 s->regs_ro[R_IMR] = 0xFFFFFFFF; 561 s->regs_ro[R_MODID] = 0xFFFFFFFF; 562 for (i = 0; i < s->num_priority_queues; i++) { 563 s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 564 s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 565 s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 566 s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 567 } 568 569 /* Mask of register bits which are clear on read */ 570 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 571 s->regs_rtc[R_ISR] = 0xFFFFFFFF; 572 for (i = 0; i < s->num_priority_queues; i++) { 573 s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 574 } 575 576 /* Mask of register bits which are write 1 to clear */ 577 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 578 s->regs_w1c[R_TXSTATUS] = 0x000001F7; 579 s->regs_w1c[R_RXSTATUS] = 0x0000000F; 580 581 /* Mask of register bits which are write only */ 582 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 583 s->regs_wo[R_NWCTRL] = 0x00073E60; 584 s->regs_wo[R_IER] = 0x07FFFFFF; 585 s->regs_wo[R_IDR] = 0x07FFFFFF; 586 for (i = 0; i < s->num_priority_queues; i++) { 587 s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 588 s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 589 } 590 } 591 592 /* 593 * phy_update_link: 594 * Make the emulated PHY link state match the QEMU "interface" state. 595 */ 596 static void phy_update_link(CadenceGEMState *s) 597 { 598 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 599 600 /* Autonegotiation status mirrors link status. */ 601 if (qemu_get_queue(s->nic)->link_down) { 602 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 603 PHY_REG_STATUS_LINK); 604 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 605 } else { 606 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 607 PHY_REG_STATUS_LINK); 608 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 609 PHY_REG_INT_ST_ANEGCMPL | 610 PHY_REG_INT_ST_ENERGY); 611 } 612 } 613 614 static bool gem_can_receive(NetClientState *nc) 615 { 616 CadenceGEMState *s; 617 int i; 618 619 s = qemu_get_nic_opaque(nc); 620 621 /* Do nothing if receive is not enabled. */ 622 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { 623 if (s->can_rx_state != 1) { 624 s->can_rx_state = 1; 625 DB_PRINT("can't receive - no enable\n"); 626 } 627 return false; 628 } 629 630 for (i = 0; i < s->num_priority_queues; i++) { 631 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 632 break; 633 } 634 }; 635 636 if (i == s->num_priority_queues) { 637 if (s->can_rx_state != 2) { 638 s->can_rx_state = 2; 639 DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 640 } 641 return false; 642 } 643 644 if (s->can_rx_state != 0) { 645 s->can_rx_state = 0; 646 DB_PRINT("can receive\n"); 647 } 648 return true; 649 } 650 651 /* 652 * gem_update_int_status: 653 * Raise or lower interrupt based on current status. 654 */ 655 static void gem_update_int_status(CadenceGEMState *s) 656 { 657 int i; 658 659 qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 660 661 for (i = 1; i < s->num_priority_queues; ++i) { 662 qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 663 } 664 } 665 666 /* 667 * gem_receive_updatestats: 668 * Increment receive statistics. 669 */ 670 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 671 unsigned bytes) 672 { 673 uint64_t octets; 674 675 /* Total octets (bytes) received */ 676 octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 677 s->regs[R_OCTRXHI]; 678 octets += bytes; 679 s->regs[R_OCTRXLO] = octets >> 32; 680 s->regs[R_OCTRXHI] = octets; 681 682 /* Error-free Frames received */ 683 s->regs[R_RXCNT]++; 684 685 /* Error-free Broadcast Frames counter */ 686 if (!memcmp(packet, broadcast_addr, 6)) { 687 s->regs[R_RXBROADCNT]++; 688 } 689 690 /* Error-free Multicast Frames counter */ 691 if (packet[0] == 0x01) { 692 s->regs[R_RXMULTICNT]++; 693 } 694 695 if (bytes <= 64) { 696 s->regs[R_RX64CNT]++; 697 } else if (bytes <= 127) { 698 s->regs[R_RX65CNT]++; 699 } else if (bytes <= 255) { 700 s->regs[R_RX128CNT]++; 701 } else if (bytes <= 511) { 702 s->regs[R_RX256CNT]++; 703 } else if (bytes <= 1023) { 704 s->regs[R_RX512CNT]++; 705 } else if (bytes <= 1518) { 706 s->regs[R_RX1024CNT]++; 707 } else { 708 s->regs[R_RX1519CNT]++; 709 } 710 } 711 712 /* 713 * Get the MAC Address bit from the specified position 714 */ 715 static unsigned get_bit(const uint8_t *mac, unsigned bit) 716 { 717 unsigned byte; 718 719 byte = mac[bit / 8]; 720 byte >>= (bit & 0x7); 721 byte &= 1; 722 723 return byte; 724 } 725 726 /* 727 * Calculate a GEM MAC Address hash index 728 */ 729 static unsigned calc_mac_hash(const uint8_t *mac) 730 { 731 int index_bit, mac_bit; 732 unsigned hash_index; 733 734 hash_index = 0; 735 mac_bit = 5; 736 for (index_bit = 5; index_bit >= 0; index_bit--) { 737 hash_index |= (get_bit(mac, mac_bit) ^ 738 get_bit(mac, mac_bit + 6) ^ 739 get_bit(mac, mac_bit + 12) ^ 740 get_bit(mac, mac_bit + 18) ^ 741 get_bit(mac, mac_bit + 24) ^ 742 get_bit(mac, mac_bit + 30) ^ 743 get_bit(mac, mac_bit + 36) ^ 744 get_bit(mac, mac_bit + 42)) << index_bit; 745 mac_bit--; 746 } 747 748 return hash_index; 749 } 750 751 /* 752 * gem_mac_address_filter: 753 * Accept or reject this destination address? 754 * Returns: 755 * GEM_RX_REJECT: reject 756 * >= 0: Specific address accept (which matched SAR is returned) 757 * others for various other modes of accept: 758 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 759 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 760 */ 761 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 762 { 763 uint8_t *gem_spaddr; 764 int i, is_mc; 765 766 /* Promiscuous mode? */ 767 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { 768 return GEM_RX_PROMISCUOUS_ACCEPT; 769 } 770 771 if (!memcmp(packet, broadcast_addr, 6)) { 772 /* Reject broadcast packets? */ 773 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { 774 return GEM_RX_REJECT; 775 } 776 return GEM_RX_BROADCAST_ACCEPT; 777 } 778 779 /* Accept packets -w- hash match? */ 780 is_mc = is_multicast_ether_addr(packet); 781 if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || 782 (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { 783 uint64_t buckets; 784 unsigned hash_index; 785 786 hash_index = calc_mac_hash(packet); 787 buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 788 if ((buckets >> hash_index) & 1) { 789 return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 790 : GEM_RX_UNICAST_HASH_ACCEPT; 791 } 792 } 793 794 /* Check all 4 specific addresses */ 795 gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 796 for (i = 3; i >= 0; i--) { 797 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 798 return GEM_RX_SAR_ACCEPT + i; 799 } 800 } 801 802 /* No address match; reject the packet */ 803 return GEM_RX_REJECT; 804 } 805 806 /* Figure out which queue the received data should be sent to */ 807 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 808 unsigned rxbufsize) 809 { 810 uint32_t reg; 811 bool matched, mismatched; 812 int i, j; 813 814 for (i = 0; i < s->num_type1_screeners; i++) { 815 reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 816 matched = false; 817 mismatched = false; 818 819 /* Screening is based on UDP Port */ 820 if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { 821 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 822 if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { 823 matched = true; 824 } else { 825 mismatched = true; 826 } 827 } 828 829 /* Screening is based on DS/TC */ 830 if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { 831 uint8_t dscp = rxbuf_ptr[14 + 1]; 832 if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { 833 matched = true; 834 } else { 835 mismatched = true; 836 } 837 } 838 839 if (matched && !mismatched) { 840 return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); 841 } 842 } 843 844 for (i = 0; i < s->num_type2_screeners; i++) { 845 reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 846 matched = false; 847 mismatched = false; 848 849 if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { 850 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 851 int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, 852 ETHERTYPE_REG_INDEX); 853 854 if (et_idx > s->num_type2_screeners) { 855 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 856 "register index: %d\n", et_idx); 857 } 858 if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 859 et_idx]) { 860 matched = true; 861 } else { 862 mismatched = true; 863 } 864 } 865 866 /* Compare A, B, C */ 867 for (j = 0; j < 3; j++) { 868 uint32_t cr0, cr1, mask, compare; 869 uint16_t rx_cmp; 870 int offset; 871 int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, 872 R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); 873 874 if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, 875 R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { 876 continue; 877 } 878 879 if (cr_idx > s->num_type2_screeners) { 880 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 881 "register index: %d\n", cr_idx); 882 } 883 884 cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 885 cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; 886 offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); 887 888 switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { 889 case 3: /* Skip UDP header */ 890 qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 891 "unimplemented - assuming UDP\n"); 892 offset += 8; 893 /* Fallthrough */ 894 case 2: /* skip the IP header */ 895 offset += 20; 896 /* Fallthrough */ 897 case 1: /* Count from after the ethertype */ 898 offset += 14; 899 break; 900 case 0: 901 /* Offset from start of frame */ 902 break; 903 } 904 905 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 906 mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); 907 compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); 908 909 if ((rx_cmp & mask) == (compare & mask)) { 910 matched = true; 911 } else { 912 mismatched = true; 913 } 914 } 915 916 if (matched && !mismatched) { 917 return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); 918 } 919 } 920 921 /* We made it here, assume it's queue 0 */ 922 return 0; 923 } 924 925 static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 926 { 927 uint32_t base_addr = 0; 928 929 switch (q) { 930 case 0: 931 base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 932 break; 933 case 1 ... (MAX_PRIORITY_QUEUES - 1): 934 base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 935 R_RECEIVE_Q1_PTR) + q - 1]; 936 break; 937 default: 938 g_assert_not_reached(); 939 }; 940 941 return base_addr; 942 } 943 944 static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 945 { 946 return gem_get_queue_base_addr(s, true, q); 947 } 948 949 static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 950 { 951 return gem_get_queue_base_addr(s, false, q); 952 } 953 954 static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 955 { 956 hwaddr desc_addr = 0; 957 958 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 959 desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 960 } 961 desc_addr <<= 32; 962 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 963 return desc_addr; 964 } 965 966 static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 967 { 968 return gem_get_desc_addr(s, true, q); 969 } 970 971 static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 972 { 973 return gem_get_desc_addr(s, false, q); 974 } 975 976 static void gem_get_rx_desc(CadenceGEMState *s, int q) 977 { 978 hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 979 980 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 981 982 /* read current descriptor */ 983 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 984 s->rx_desc[q], 985 sizeof(uint32_t) * gem_get_desc_len(s, true)); 986 987 /* Descriptor owned by software ? */ 988 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 989 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 990 s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 991 gem_set_isr(s, q, GEM_INT_RXUSED); 992 /* Handle interrupt consequences */ 993 gem_update_int_status(s); 994 } 995 } 996 997 /* 998 * gem_receive: 999 * Fit a packet handed to us by QEMU into the receive descriptor ring. 1000 */ 1001 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1002 { 1003 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1004 unsigned rxbufsize, bytes_to_copy; 1005 unsigned rxbuf_offset; 1006 uint8_t *rxbuf_ptr; 1007 bool first_desc = true; 1008 int maf; 1009 int q = 0; 1010 1011 /* Is this destination MAC address "for us" ? */ 1012 maf = gem_mac_address_filter(s, buf); 1013 if (maf == GEM_RX_REJECT) { 1014 return size; /* no, drop silently b/c it's not an error */ 1015 } 1016 1017 /* Discard packets with receive length error enabled ? */ 1018 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { 1019 unsigned type_len; 1020 1021 /* Fish the ethertype / length field out of the RX packet */ 1022 type_len = buf[12] << 8 | buf[13]; 1023 /* It is a length field, not an ethertype */ 1024 if (type_len < 0x600) { 1025 if (size < type_len) { 1026 /* discard */ 1027 return -1; 1028 } 1029 } 1030 } 1031 1032 /* 1033 * Determine configured receive buffer offset (probably 0) 1034 */ 1035 rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); 1036 1037 /* The configure size of each receive buffer. Determines how many 1038 * buffers needed to hold this packet. 1039 */ 1040 rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); 1041 rxbufsize *= GEM_DMACFG_RBUFSZ_MUL; 1042 1043 bytes_to_copy = size; 1044 1045 /* Hardware allows a zero value here but warns against it. To avoid QEMU 1046 * indefinite loops we enforce a minimum value here 1047 */ 1048 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1049 rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1050 } 1051 1052 /* Pad to minimum length. Assume FCS field is stripped, logic 1053 * below will increment it to the real minimum of 64 when 1054 * not FCS stripping 1055 */ 1056 if (size < 60) { 1057 size = 60; 1058 } 1059 1060 /* Strip of FCS field ? (usually yes) */ 1061 if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { 1062 rxbuf_ptr = (void *)buf; 1063 } else { 1064 unsigned crc_val; 1065 1066 if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 1067 size = MAX_FRAME_SIZE - sizeof(crc_val); 1068 } 1069 bytes_to_copy = size; 1070 /* The application wants the FCS field, which QEMU does not provide. 1071 * We must try and calculate one. 1072 */ 1073 1074 memcpy(s->rx_packet, buf, size); 1075 memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 1076 rxbuf_ptr = s->rx_packet; 1077 crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 1078 memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 1079 1080 bytes_to_copy += 4; 1081 size += 4; 1082 } 1083 1084 DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 1085 1086 /* Find which queue we are targeting */ 1087 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1088 1089 if (size > gem_get_max_buf_len(s, false)) { 1090 qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 1091 gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1092 return -1; 1093 } 1094 1095 while (bytes_to_copy) { 1096 hwaddr desc_addr; 1097 1098 /* Do nothing if receive is not enabled. */ 1099 if (!gem_can_receive(nc)) { 1100 return -1; 1101 } 1102 1103 DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1104 MIN(bytes_to_copy, rxbufsize), 1105 rx_desc_get_buffer(s, s->rx_desc[q])); 1106 1107 /* Copy packet data to emulated DMA buffer */ 1108 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 1109 rxbuf_offset, 1110 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1111 MIN(bytes_to_copy, rxbufsize)); 1112 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 1113 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 1114 1115 rx_desc_clear_control(s->rx_desc[q]); 1116 1117 /* Update the descriptor. */ 1118 if (first_desc) { 1119 rx_desc_set_sof(s->rx_desc[q]); 1120 first_desc = false; 1121 } 1122 if (bytes_to_copy == 0) { 1123 rx_desc_set_eof(s->rx_desc[q]); 1124 rx_desc_set_length(s->rx_desc[q], size); 1125 } 1126 rx_desc_set_ownership(s->rx_desc[q]); 1127 1128 switch (maf) { 1129 case GEM_RX_PROMISCUOUS_ACCEPT: 1130 break; 1131 case GEM_RX_BROADCAST_ACCEPT: 1132 rx_desc_set_broadcast(s->rx_desc[q]); 1133 break; 1134 case GEM_RX_UNICAST_HASH_ACCEPT: 1135 rx_desc_set_unicast_hash(s->rx_desc[q]); 1136 break; 1137 case GEM_RX_MULTICAST_HASH_ACCEPT: 1138 rx_desc_set_multicast_hash(s->rx_desc[q]); 1139 break; 1140 case GEM_RX_REJECT: 1141 abort(); 1142 default: /* SAR */ 1143 rx_desc_set_sar(s->rx_desc[q], maf); 1144 } 1145 1146 /* Descriptor write-back. */ 1147 desc_addr = gem_get_rx_desc_addr(s, q); 1148 address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1149 s->rx_desc[q], 1150 sizeof(uint32_t) * gem_get_desc_len(s, true)); 1151 1152 /* Next descriptor */ 1153 if (rx_desc_get_wrap(s->rx_desc[q])) { 1154 DB_PRINT("wrapping RX descriptor list\n"); 1155 s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 1156 } else { 1157 DB_PRINT("incrementing RX descriptor list\n"); 1158 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 1159 } 1160 1161 gem_get_rx_desc(s, q); 1162 } 1163 1164 /* Count it */ 1165 gem_receive_updatestats(s, buf, size); 1166 1167 s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 1168 gem_set_isr(s, q, GEM_INT_RXCMPL); 1169 1170 /* Handle interrupt consequences */ 1171 gem_update_int_status(s); 1172 1173 return size; 1174 } 1175 1176 /* 1177 * gem_transmit_updatestats: 1178 * Increment transmit statistics. 1179 */ 1180 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 1181 unsigned bytes) 1182 { 1183 uint64_t octets; 1184 1185 /* Total octets (bytes) transmitted */ 1186 octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1187 s->regs[R_OCTTXHI]; 1188 octets += bytes; 1189 s->regs[R_OCTTXLO] = octets >> 32; 1190 s->regs[R_OCTTXHI] = octets; 1191 1192 /* Error-free Frames transmitted */ 1193 s->regs[R_TXCNT]++; 1194 1195 /* Error-free Broadcast Frames counter */ 1196 if (!memcmp(packet, broadcast_addr, 6)) { 1197 s->regs[R_TXBCNT]++; 1198 } 1199 1200 /* Error-free Multicast Frames counter */ 1201 if (packet[0] == 0x01) { 1202 s->regs[R_TXMCNT]++; 1203 } 1204 1205 if (bytes <= 64) { 1206 s->regs[R_TX64CNT]++; 1207 } else if (bytes <= 127) { 1208 s->regs[R_TX65CNT]++; 1209 } else if (bytes <= 255) { 1210 s->regs[R_TX128CNT]++; 1211 } else if (bytes <= 511) { 1212 s->regs[R_TX256CNT]++; 1213 } else if (bytes <= 1023) { 1214 s->regs[R_TX512CNT]++; 1215 } else if (bytes <= 1518) { 1216 s->regs[R_TX1024CNT]++; 1217 } else { 1218 s->regs[R_TX1519CNT]++; 1219 } 1220 } 1221 1222 /* 1223 * gem_transmit: 1224 * Fish packets out of the descriptor ring and feed them to QEMU 1225 */ 1226 static void gem_transmit(CadenceGEMState *s) 1227 { 1228 uint32_t desc[DESC_MAX_NUM_WORDS]; 1229 hwaddr packet_desc_addr; 1230 uint8_t *p; 1231 unsigned total_bytes; 1232 int q = 0; 1233 1234 /* Do nothing if transmit is not enabled. */ 1235 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 1236 return; 1237 } 1238 1239 DB_PRINT("\n"); 1240 1241 /* The packet we will hand off to QEMU. 1242 * Packets scattered across multiple descriptors are gathered to this 1243 * one contiguous buffer first. 1244 */ 1245 p = s->tx_packet; 1246 total_bytes = 0; 1247 1248 for (q = s->num_priority_queues - 1; q >= 0; q--) { 1249 /* read current descriptor */ 1250 packet_desc_addr = gem_get_tx_desc_addr(s, q); 1251 1252 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1253 address_space_read(&s->dma_as, packet_desc_addr, 1254 MEMTXATTRS_UNSPECIFIED, desc, 1255 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1256 /* Handle all descriptors owned by hardware */ 1257 while (tx_desc_get_used(desc) == 0) { 1258 1259 /* Do nothing if transmit is not enabled. */ 1260 if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 1261 return; 1262 } 1263 print_gem_tx_desc(desc, q); 1264 1265 /* The real hardware would eat this (and possibly crash). 1266 * For QEMU let's lend a helping hand. 1267 */ 1268 if ((tx_desc_get_buffer(s, desc) == 0) || 1269 (tx_desc_get_length(desc) == 0)) { 1270 DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 1271 packet_desc_addr); 1272 break; 1273 } 1274 1275 if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 1276 (p - s->tx_packet)) { 1277 qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 1278 HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1279 packet_desc_addr, tx_desc_get_length(desc), 1280 gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 1281 gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1282 break; 1283 } 1284 1285 /* Gather this fragment of the packet from "dma memory" to our 1286 * contig buffer. 1287 */ 1288 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 1289 MEMTXATTRS_UNSPECIFIED, 1290 p, tx_desc_get_length(desc)); 1291 p += tx_desc_get_length(desc); 1292 total_bytes += tx_desc_get_length(desc); 1293 1294 /* Last descriptor for this packet; hand the whole thing off */ 1295 if (tx_desc_get_last(desc)) { 1296 uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1297 hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 1298 1299 /* Modify the 1st descriptor of this packet to be owned by 1300 * the processor. 1301 */ 1302 address_space_read(&s->dma_as, desc_addr, 1303 MEMTXATTRS_UNSPECIFIED, desc_first, 1304 sizeof(desc_first)); 1305 tx_desc_set_used(desc_first); 1306 address_space_write(&s->dma_as, desc_addr, 1307 MEMTXATTRS_UNSPECIFIED, desc_first, 1308 sizeof(desc_first)); 1309 /* Advance the hardware current descriptor past this packet */ 1310 if (tx_desc_get_wrap(desc)) { 1311 s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 1312 } else { 1313 s->tx_desc_addr[q] = packet_desc_addr + 1314 4 * gem_get_desc_len(s, false); 1315 } 1316 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 1317 1318 s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 1319 gem_set_isr(s, q, GEM_INT_TXCMPL); 1320 1321 /* Handle interrupt consequences */ 1322 gem_update_int_status(s); 1323 1324 /* Is checksum offload enabled? */ 1325 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) { 1326 net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 1327 } 1328 1329 /* Update MAC statistics */ 1330 gem_transmit_updatestats(s, s->tx_packet, total_bytes); 1331 1332 /* Send the packet somewhere */ 1333 if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, 1334 LOOPBACK_LOCAL)) { 1335 qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 1336 total_bytes); 1337 } else { 1338 qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 1339 total_bytes); 1340 } 1341 1342 /* Prepare for next packet */ 1343 p = s->tx_packet; 1344 total_bytes = 0; 1345 } 1346 1347 /* read next descriptor */ 1348 if (tx_desc_get_wrap(desc)) { 1349 if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 1350 packet_desc_addr = s->regs[R_TBQPH]; 1351 packet_desc_addr <<= 32; 1352 } else { 1353 packet_desc_addr = 0; 1354 } 1355 packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 1356 } else { 1357 packet_desc_addr += 4 * gem_get_desc_len(s, false); 1358 } 1359 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1360 address_space_read(&s->dma_as, packet_desc_addr, 1361 MEMTXATTRS_UNSPECIFIED, desc, 1362 sizeof(uint32_t) * gem_get_desc_len(s, false)); 1363 } 1364 1365 if (tx_desc_get_used(desc)) { 1366 s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; 1367 /* IRQ TXUSED is defined only for queue 0 */ 1368 if (q == 0) { 1369 gem_set_isr(s, 0, GEM_INT_TXUSED); 1370 } 1371 gem_update_int_status(s); 1372 } 1373 } 1374 } 1375 1376 static void gem_phy_reset(CadenceGEMState *s) 1377 { 1378 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 1379 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 1380 s->phy_regs[PHY_REG_STATUS] = 0x7969; 1381 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 1382 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 1383 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 1384 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 1385 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 1386 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 1387 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 1388 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 1389 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 1390 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 1391 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 1392 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 1393 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 1394 s->phy_regs[PHY_REG_LED] = 0x4100; 1395 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 1396 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 1397 1398 phy_update_link(s); 1399 } 1400 1401 static void gem_reset(DeviceState *d) 1402 { 1403 int i; 1404 CadenceGEMState *s = CADENCE_GEM(d); 1405 const uint8_t *a; 1406 uint32_t queues_mask = 0; 1407 1408 DB_PRINT("\n"); 1409 1410 /* Set post reset register values */ 1411 memset(&s->regs[0], 0, sizeof(s->regs)); 1412 s->regs[R_NWCFG] = 0x00080000; 1413 s->regs[R_NWSTATUS] = 0x00000006; 1414 s->regs[R_DMACFG] = 0x00020784; 1415 s->regs[R_IMR] = 0x07ffffff; 1416 s->regs[R_TXPAUSE] = 0x0000ffff; 1417 s->regs[R_TXPARTIALSF] = 0x000003ff; 1418 s->regs[R_RXPARTIALSF] = 0x000003ff; 1419 s->regs[R_MODID] = s->revision; 1420 s->regs[R_DESCONF] = 0x02D00111; 1421 s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1422 s->regs[R_DESCONF5] = 0x002f2045; 1423 s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; 1424 s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1425 s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1426 1427 if (s->num_priority_queues > 1) { 1428 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1429 s->regs[R_DESCONF6] |= queues_mask; 1430 } 1431 1432 /* Set MAC address */ 1433 a = &s->conf.macaddr.a[0]; 1434 s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1435 s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1436 1437 for (i = 0; i < 4; i++) { 1438 s->sar_active[i] = false; 1439 } 1440 1441 gem_phy_reset(s); 1442 1443 gem_update_int_status(s); 1444 } 1445 1446 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 1447 { 1448 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1449 return s->phy_regs[reg_num]; 1450 } 1451 1452 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 1453 { 1454 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1455 1456 switch (reg_num) { 1457 case PHY_REG_CONTROL: 1458 if (val & PHY_REG_CONTROL_RST) { 1459 /* Phy reset */ 1460 gem_phy_reset(s); 1461 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1462 s->phy_loop = 0; 1463 } 1464 if (val & PHY_REG_CONTROL_ANEG) { 1465 /* Complete autonegotiation immediately */ 1466 val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 1467 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1468 } 1469 if (val & PHY_REG_CONTROL_LOOP) { 1470 DB_PRINT("PHY placed in loopback\n"); 1471 s->phy_loop = 1; 1472 } else { 1473 s->phy_loop = 0; 1474 } 1475 break; 1476 } 1477 s->phy_regs[reg_num] = val; 1478 } 1479 1480 /* 1481 * gem_read32: 1482 * Read a GEM register. 1483 */ 1484 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1485 { 1486 CadenceGEMState *s; 1487 uint32_t retval; 1488 s = opaque; 1489 1490 offset >>= 2; 1491 retval = s->regs[offset]; 1492 1493 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1494 1495 switch (offset) { 1496 case R_ISR: 1497 DB_PRINT("lowering irqs on ISR read\n"); 1498 /* The interrupts get updated at the end of the function. */ 1499 break; 1500 case R_PHYMNTNC: 1501 if (retval & GEM_PHYMNTNC_OP_R) { 1502 uint32_t phy_addr, reg_num; 1503 1504 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1505 if (phy_addr == s->phy_addr) { 1506 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1507 retval &= 0xFFFF0000; 1508 retval |= gem_phy_read(s, reg_num); 1509 } else { 1510 retval |= 0xFFFF; /* No device at this address */ 1511 } 1512 } 1513 break; 1514 } 1515 1516 /* Squash read to clear bits */ 1517 s->regs[offset] &= ~(s->regs_rtc[offset]); 1518 1519 /* Do not provide write only bits */ 1520 retval &= ~(s->regs_wo[offset]); 1521 1522 DB_PRINT("0x%08x\n", retval); 1523 gem_update_int_status(s); 1524 return retval; 1525 } 1526 1527 /* 1528 * gem_write32: 1529 * Write a GEM register. 1530 */ 1531 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1532 unsigned size) 1533 { 1534 CadenceGEMState *s = (CadenceGEMState *)opaque; 1535 uint32_t readonly; 1536 int i; 1537 1538 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1539 offset >>= 2; 1540 1541 /* Squash bits which are read only in write value */ 1542 val &= ~(s->regs_ro[offset]); 1543 /* Preserve (only) bits which are read only and wtc in register */ 1544 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1545 1546 /* Copy register write to backing store */ 1547 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1548 1549 /* do w1c */ 1550 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1551 1552 /* Handle register write side effects */ 1553 switch (offset) { 1554 case R_NWCTRL: 1555 if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { 1556 for (i = 0; i < s->num_priority_queues; ++i) { 1557 gem_get_rx_desc(s, i); 1558 } 1559 } 1560 if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { 1561 gem_transmit(s); 1562 } 1563 if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { 1564 /* Reset to start of Q when transmit disabled. */ 1565 for (i = 0; i < s->num_priority_queues; i++) { 1566 s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 1567 } 1568 } 1569 if (gem_can_receive(qemu_get_queue(s->nic))) { 1570 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1571 } 1572 break; 1573 1574 case R_TXSTATUS: 1575 gem_update_int_status(s); 1576 break; 1577 case R_RXQBASE: 1578 s->rx_desc_addr[0] = val; 1579 break; 1580 case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1581 s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 1582 break; 1583 case R_TXQBASE: 1584 s->tx_desc_addr[0] = val; 1585 break; 1586 case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1587 s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 1588 break; 1589 case R_RXSTATUS: 1590 gem_update_int_status(s); 1591 break; 1592 case R_IER: 1593 s->regs[R_IMR] &= ~val; 1594 gem_update_int_status(s); 1595 break; 1596 case R_JUMBO_MAX_LEN: 1597 s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 1598 break; 1599 case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1600 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 1601 gem_update_int_status(s); 1602 break; 1603 case R_IDR: 1604 s->regs[R_IMR] |= val; 1605 gem_update_int_status(s); 1606 break; 1607 case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1608 s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 1609 gem_update_int_status(s); 1610 break; 1611 case R_SPADDR1LO: 1612 case R_SPADDR2LO: 1613 case R_SPADDR3LO: 1614 case R_SPADDR4LO: 1615 s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 1616 break; 1617 case R_SPADDR1HI: 1618 case R_SPADDR2HI: 1619 case R_SPADDR3HI: 1620 case R_SPADDR4HI: 1621 s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 1622 break; 1623 case R_PHYMNTNC: 1624 if (val & GEM_PHYMNTNC_OP_W) { 1625 uint32_t phy_addr, reg_num; 1626 1627 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1628 if (phy_addr == s->phy_addr) { 1629 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1630 gem_phy_write(s, reg_num, val); 1631 } 1632 } 1633 break; 1634 } 1635 1636 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1637 } 1638 1639 static const MemoryRegionOps gem_ops = { 1640 .read = gem_read, 1641 .write = gem_write, 1642 .endianness = DEVICE_LITTLE_ENDIAN, 1643 }; 1644 1645 static void gem_set_link(NetClientState *nc) 1646 { 1647 CadenceGEMState *s = qemu_get_nic_opaque(nc); 1648 1649 DB_PRINT("\n"); 1650 phy_update_link(s); 1651 gem_update_int_status(s); 1652 } 1653 1654 static NetClientInfo net_gem_info = { 1655 .type = NET_CLIENT_DRIVER_NIC, 1656 .size = sizeof(NICState), 1657 .can_receive = gem_can_receive, 1658 .receive = gem_receive, 1659 .link_status_changed = gem_set_link, 1660 }; 1661 1662 static void gem_realize(DeviceState *dev, Error **errp) 1663 { 1664 CadenceGEMState *s = CADENCE_GEM(dev); 1665 int i; 1666 1667 address_space_init(&s->dma_as, 1668 s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 1669 1670 if (s->num_priority_queues == 0 || 1671 s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1672 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1673 s->num_priority_queues); 1674 return; 1675 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1676 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1677 s->num_type1_screeners); 1678 return; 1679 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1680 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1681 s->num_type2_screeners); 1682 return; 1683 } 1684 1685 for (i = 0; i < s->num_priority_queues; ++i) { 1686 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1687 } 1688 1689 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1690 1691 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1692 object_get_typename(OBJECT(dev)), dev->id, s); 1693 1694 if (s->jumbo_max_len > MAX_FRAME_SIZE) { 1695 error_setg(errp, "jumbo-max-len is greater than %d", 1696 MAX_FRAME_SIZE); 1697 return; 1698 } 1699 } 1700 1701 static void gem_init(Object *obj) 1702 { 1703 CadenceGEMState *s = CADENCE_GEM(obj); 1704 DeviceState *dev = DEVICE(obj); 1705 1706 DB_PRINT("\n"); 1707 1708 gem_init_register_masks(s); 1709 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1710 "enet", sizeof(s->regs)); 1711 1712 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1713 } 1714 1715 static const VMStateDescription vmstate_cadence_gem = { 1716 .name = "cadence_gem", 1717 .version_id = 4, 1718 .minimum_version_id = 4, 1719 .fields = (VMStateField[]) { 1720 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1721 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1722 VMSTATE_UINT8(phy_loop, CadenceGEMState), 1723 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1724 MAX_PRIORITY_QUEUES), 1725 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1726 MAX_PRIORITY_QUEUES), 1727 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 1728 VMSTATE_END_OF_LIST(), 1729 } 1730 }; 1731 1732 static Property gem_properties[] = { 1733 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1734 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1735 GEM_MODID_VALUE), 1736 DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 1737 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1738 num_priority_queues, 1), 1739 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1740 num_type1_screeners, 4), 1741 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1742 num_type2_screeners, 4), 1743 DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 1744 jumbo_max_len, 10240), 1745 DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 1746 TYPE_MEMORY_REGION, MemoryRegion *), 1747 DEFINE_PROP_END_OF_LIST(), 1748 }; 1749 1750 static void gem_class_init(ObjectClass *klass, void *data) 1751 { 1752 DeviceClass *dc = DEVICE_CLASS(klass); 1753 1754 dc->realize = gem_realize; 1755 device_class_set_props(dc, gem_properties); 1756 dc->vmsd = &vmstate_cadence_gem; 1757 dc->reset = gem_reset; 1758 } 1759 1760 static const TypeInfo gem_info = { 1761 .name = TYPE_CADENCE_GEM, 1762 .parent = TYPE_SYS_BUS_DEVICE, 1763 .instance_size = sizeof(CadenceGEMState), 1764 .instance_init = gem_init, 1765 .class_init = gem_class_init, 1766 }; 1767 1768 static void gem_register_types(void) 1769 { 1770 type_register_static(&gem_info); 1771 } 1772 1773 type_init(gem_register_types) 1774