149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 28f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 29*2bf57f73SAlistair Francis #include "qapi/error.h" 3049ab747fSPaolo Bonzini #include "net/checksum.h" 3149ab747fSPaolo Bonzini 3249ab747fSPaolo Bonzini #ifdef CADENCE_GEM_ERR_DEBUG 3349ab747fSPaolo Bonzini #define DB_PRINT(...) do { \ 3449ab747fSPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 3549ab747fSPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 3649ab747fSPaolo Bonzini } while (0); 3749ab747fSPaolo Bonzini #else 3849ab747fSPaolo Bonzini #define DB_PRINT(...) 3949ab747fSPaolo Bonzini #endif 4049ab747fSPaolo Bonzini 4149ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 4249ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 4349ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 4449ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 4549ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 4649ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 4749ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 4849ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 4949ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 5049ab747fSPaolo Bonzini #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 5149ab747fSPaolo Bonzini #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 5249ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 5349ab747fSPaolo Bonzini #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 543048ed6aSPeter Crosthwaite #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 5549ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 5649ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 5749ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 5849ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 5949ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 6049ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 6149ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 6249ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 6349ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 6449ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 6549ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 6649ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 6749ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 6849ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 6949ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 7049ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 7149ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 7249ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 7349ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 7449ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 7549ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 7649ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 7749ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 7849ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 7949ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 8049ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 8149ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 8249ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 8349ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 8449ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 8549ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 8649ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 8749ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 8849ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 8949ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 9049ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 9149ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 9249ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 9349ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 9449ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 9549ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 9649ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 9749ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 9849ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 9949ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 10049ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 10149ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 10249ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 10349ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 10449ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 10549ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 10649ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 10749ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 10849ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 10949ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 11049ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 11149ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 11249ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 11349ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 11449ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 11549ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 11649ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 11749ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 11849ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 11949ab747fSPaolo Bonzini #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 12149ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 12249ab747fSPaolo Bonzini 12349ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 12449ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 12549ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 12649ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 12749ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 12849ab747fSPaolo Bonzini #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 12949ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 13049ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 13149ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 13249ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 13349ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 13449ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 13549ab747fSPaolo Bonzini 13649ab747fSPaolo Bonzini /* Design Configuration Registers */ 13749ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280/4) 13849ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284/4) 13949ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288/4) 14049ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C/4) 14149ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290/4) 14249ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294/4) 14349ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298/4) 14449ab747fSPaolo Bonzini 14549ab747fSPaolo Bonzini /*****************************************/ 14649ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 14749ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 14849ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 14949ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 15049ab747fSPaolo Bonzini 15149ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 1523048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 15349ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 15449ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 15549ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 15649ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 15749ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 15849ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 15949ab747fSPaolo Bonzini 1602801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 16149ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 16249ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 16349ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 16449ab747fSPaolo Bonzini 16549ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 16649ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 16749ab747fSPaolo Bonzini 16849ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 16949ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 17049ab747fSPaolo Bonzini 17149ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 17249ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 17349ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 17449ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 17549ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 17649ab747fSPaolo Bonzini 17749ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 17849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 17949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 18049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 18149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 18249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 18349ab747fSPaolo Bonzini 18449ab747fSPaolo Bonzini /* Marvell PHY definitions */ 18549ab747fSPaolo Bonzini #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 18649ab747fSPaolo Bonzini 18749ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 18849ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 18949ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 19049ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 19149ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 19249ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 19349ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 19449ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 19549ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 19649ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 19749ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 19849ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 19949ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 20049ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 20149ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 20249ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 20349ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 20449ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 20549ab747fSPaolo Bonzini #define PHY_REG_EACD 22 20649ab747fSPaolo Bonzini #define PHY_REG_LED 24 20749ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 20849ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 20949ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 21049ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 21149ab747fSPaolo Bonzini 21249ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 21349ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 21449ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 21549ab747fSPaolo Bonzini 21649ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 21749ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 21849ab747fSPaolo Bonzini 21949ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 22049ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 22149ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 22249ab747fSPaolo Bonzini 22349ab747fSPaolo Bonzini /***********************************************************************/ 22463af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 22563af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 22663af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 22763af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 22863af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 22963af1e0cSPeter Crosthwaite 23063af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 23149ab747fSPaolo Bonzini 23249ab747fSPaolo Bonzini /***********************************************************************/ 23349ab747fSPaolo Bonzini 23449ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 23549ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 23649ab747fSPaolo Bonzini 23749ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 23849ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 23949ab747fSPaolo Bonzini 24049ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 24149ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 24249ab747fSPaolo Bonzini 24363af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 24463af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 245a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 24663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 24763af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 24863af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 24963af1e0cSPeter Crosthwaite 25049ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 25149ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 25249ab747fSPaolo Bonzini 25349ab747fSPaolo Bonzini static inline unsigned tx_desc_get_buffer(unsigned *desc) 25449ab747fSPaolo Bonzini { 25549ab747fSPaolo Bonzini return desc[0]; 25649ab747fSPaolo Bonzini } 25749ab747fSPaolo Bonzini 25849ab747fSPaolo Bonzini static inline unsigned tx_desc_get_used(unsigned *desc) 25949ab747fSPaolo Bonzini { 26049ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 26149ab747fSPaolo Bonzini } 26249ab747fSPaolo Bonzini 26349ab747fSPaolo Bonzini static inline void tx_desc_set_used(unsigned *desc) 26449ab747fSPaolo Bonzini { 26549ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 26649ab747fSPaolo Bonzini } 26749ab747fSPaolo Bonzini 26849ab747fSPaolo Bonzini static inline unsigned tx_desc_get_wrap(unsigned *desc) 26949ab747fSPaolo Bonzini { 27049ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 27149ab747fSPaolo Bonzini } 27249ab747fSPaolo Bonzini 27349ab747fSPaolo Bonzini static inline unsigned tx_desc_get_last(unsigned *desc) 27449ab747fSPaolo Bonzini { 27549ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 27649ab747fSPaolo Bonzini } 27749ab747fSPaolo Bonzini 278cbdab58dSAlistair Francis static inline void tx_desc_set_last(unsigned *desc) 279cbdab58dSAlistair Francis { 280cbdab58dSAlistair Francis desc[1] |= DESC_1_TX_LAST; 281cbdab58dSAlistair Francis } 282cbdab58dSAlistair Francis 28349ab747fSPaolo Bonzini static inline unsigned tx_desc_get_length(unsigned *desc) 28449ab747fSPaolo Bonzini { 28549ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 28649ab747fSPaolo Bonzini } 28749ab747fSPaolo Bonzini 28849ab747fSPaolo Bonzini static inline void print_gem_tx_desc(unsigned *desc) 28949ab747fSPaolo Bonzini { 29049ab747fSPaolo Bonzini DB_PRINT("TXDESC:\n"); 29149ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 29249ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 29349ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 29449ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 29549ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 29649ab747fSPaolo Bonzini } 29749ab747fSPaolo Bonzini 29849ab747fSPaolo Bonzini static inline unsigned rx_desc_get_buffer(unsigned *desc) 29949ab747fSPaolo Bonzini { 30049ab747fSPaolo Bonzini return desc[0] & ~0x3UL; 30149ab747fSPaolo Bonzini } 30249ab747fSPaolo Bonzini 30349ab747fSPaolo Bonzini static inline unsigned rx_desc_get_wrap(unsigned *desc) 30449ab747fSPaolo Bonzini { 30549ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 30649ab747fSPaolo Bonzini } 30749ab747fSPaolo Bonzini 30849ab747fSPaolo Bonzini static inline unsigned rx_desc_get_ownership(unsigned *desc) 30949ab747fSPaolo Bonzini { 31049ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 31149ab747fSPaolo Bonzini } 31249ab747fSPaolo Bonzini 31349ab747fSPaolo Bonzini static inline void rx_desc_set_ownership(unsigned *desc) 31449ab747fSPaolo Bonzini { 31549ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 31649ab747fSPaolo Bonzini } 31749ab747fSPaolo Bonzini 31849ab747fSPaolo Bonzini static inline void rx_desc_set_sof(unsigned *desc) 31949ab747fSPaolo Bonzini { 32049ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 32149ab747fSPaolo Bonzini } 32249ab747fSPaolo Bonzini 32349ab747fSPaolo Bonzini static inline void rx_desc_set_eof(unsigned *desc) 32449ab747fSPaolo Bonzini { 32549ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 32649ab747fSPaolo Bonzini } 32749ab747fSPaolo Bonzini 32849ab747fSPaolo Bonzini static inline void rx_desc_set_length(unsigned *desc, unsigned len) 32949ab747fSPaolo Bonzini { 33049ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 33149ab747fSPaolo Bonzini desc[1] |= len; 33249ab747fSPaolo Bonzini } 33349ab747fSPaolo Bonzini 33463af1e0cSPeter Crosthwaite static inline void rx_desc_set_broadcast(unsigned *desc) 33563af1e0cSPeter Crosthwaite { 33663af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 33763af1e0cSPeter Crosthwaite } 33863af1e0cSPeter Crosthwaite 33963af1e0cSPeter Crosthwaite static inline void rx_desc_set_unicast_hash(unsigned *desc) 34063af1e0cSPeter Crosthwaite { 34163af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 34263af1e0cSPeter Crosthwaite } 34363af1e0cSPeter Crosthwaite 34463af1e0cSPeter Crosthwaite static inline void rx_desc_set_multicast_hash(unsigned *desc) 34563af1e0cSPeter Crosthwaite { 34663af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 34763af1e0cSPeter Crosthwaite } 34863af1e0cSPeter Crosthwaite 34963af1e0cSPeter Crosthwaite static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) 35063af1e0cSPeter Crosthwaite { 35163af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 35263af1e0cSPeter Crosthwaite sar_idx); 353a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 35463af1e0cSPeter Crosthwaite } 35563af1e0cSPeter Crosthwaite 35649ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 3576a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 35849ab747fSPaolo Bonzini 35949ab747fSPaolo Bonzini /* 36049ab747fSPaolo Bonzini * gem_init_register_masks: 36149ab747fSPaolo Bonzini * One time initialization. 36249ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 36349ab747fSPaolo Bonzini */ 364448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 36549ab747fSPaolo Bonzini { 36649ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 36749ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 36849ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 36949ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 37049ab747fSPaolo Bonzini s->regs_ro[GEM_DMACFG] = 0xFE00F000; 37149ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 37249ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 37349ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 37449ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 37549ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 37649ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 37749ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 37849ab747fSPaolo Bonzini 37949ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 38049ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 38149ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 38249ab747fSPaolo Bonzini 38349ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 38449ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 38549ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 38649ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 38749ab747fSPaolo Bonzini 38849ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 38949ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 39049ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 39149ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 39249ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 39349ab747fSPaolo Bonzini } 39449ab747fSPaolo Bonzini 39549ab747fSPaolo Bonzini /* 39649ab747fSPaolo Bonzini * phy_update_link: 39749ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 39849ab747fSPaolo Bonzini */ 399448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 40049ab747fSPaolo Bonzini { 40149ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 40249ab747fSPaolo Bonzini 40349ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 40449ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 40549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 40649ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 40749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 40849ab747fSPaolo Bonzini } else { 40949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 41049ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 41149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 41249ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 41349ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 41449ab747fSPaolo Bonzini } 41549ab747fSPaolo Bonzini } 41649ab747fSPaolo Bonzini 41749ab747fSPaolo Bonzini static int gem_can_receive(NetClientState *nc) 41849ab747fSPaolo Bonzini { 419448f19e2SPeter Crosthwaite CadenceGEMState *s; 42049ab747fSPaolo Bonzini 42149ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 42249ab747fSPaolo Bonzini 42349ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 42449ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 4253ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 4263ae5725fSPeter Crosthwaite s->can_rx_state = 1; 4273ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 4283ae5725fSPeter Crosthwaite } 42949ab747fSPaolo Bonzini return 0; 43049ab747fSPaolo Bonzini } 43149ab747fSPaolo Bonzini 432*2bf57f73SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[0]) == 1) { 4338202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 4348202aa53SPeter Crosthwaite s->can_rx_state = 2; 4358202aa53SPeter Crosthwaite DB_PRINT("can't receive - busy buffer descriptor 0x%x\n", 436*2bf57f73SAlistair Francis s->rx_desc_addr[0]); 4378202aa53SPeter Crosthwaite } 4388202aa53SPeter Crosthwaite return 0; 4398202aa53SPeter Crosthwaite } 4408202aa53SPeter Crosthwaite 4413ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 4423ae5725fSPeter Crosthwaite s->can_rx_state = 0; 443*2bf57f73SAlistair Francis DB_PRINT("can receive 0x%x\n", s->rx_desc_addr[0]); 4443ae5725fSPeter Crosthwaite } 44549ab747fSPaolo Bonzini return 1; 44649ab747fSPaolo Bonzini } 44749ab747fSPaolo Bonzini 44849ab747fSPaolo Bonzini /* 44949ab747fSPaolo Bonzini * gem_update_int_status: 45049ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 45149ab747fSPaolo Bonzini */ 452448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 45349ab747fSPaolo Bonzini { 45449ab747fSPaolo Bonzini if (s->regs[GEM_ISR]) { 45549ab747fSPaolo Bonzini DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]); 456*2bf57f73SAlistair Francis qemu_set_irq(s->irq[0], 1); 45749ab747fSPaolo Bonzini } 45849ab747fSPaolo Bonzini } 45949ab747fSPaolo Bonzini 46049ab747fSPaolo Bonzini /* 46149ab747fSPaolo Bonzini * gem_receive_updatestats: 46249ab747fSPaolo Bonzini * Increment receive statistics. 46349ab747fSPaolo Bonzini */ 464448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 46549ab747fSPaolo Bonzini unsigned bytes) 46649ab747fSPaolo Bonzini { 46749ab747fSPaolo Bonzini uint64_t octets; 46849ab747fSPaolo Bonzini 46949ab747fSPaolo Bonzini /* Total octets (bytes) received */ 47049ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 47149ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 47249ab747fSPaolo Bonzini octets += bytes; 47349ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 47449ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 47549ab747fSPaolo Bonzini 47649ab747fSPaolo Bonzini /* Error-free Frames received */ 47749ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 47849ab747fSPaolo Bonzini 47949ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 48049ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 48149ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 48249ab747fSPaolo Bonzini } 48349ab747fSPaolo Bonzini 48449ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 48549ab747fSPaolo Bonzini if (packet[0] == 0x01) { 48649ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 48749ab747fSPaolo Bonzini } 48849ab747fSPaolo Bonzini 48949ab747fSPaolo Bonzini if (bytes <= 64) { 49049ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 49149ab747fSPaolo Bonzini } else if (bytes <= 127) { 49249ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 49349ab747fSPaolo Bonzini } else if (bytes <= 255) { 49449ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 49549ab747fSPaolo Bonzini } else if (bytes <= 511) { 49649ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 49749ab747fSPaolo Bonzini } else if (bytes <= 1023) { 49849ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 49949ab747fSPaolo Bonzini } else if (bytes <= 1518) { 50049ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 50149ab747fSPaolo Bonzini } else { 50249ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 50349ab747fSPaolo Bonzini } 50449ab747fSPaolo Bonzini } 50549ab747fSPaolo Bonzini 50649ab747fSPaolo Bonzini /* 50749ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 50849ab747fSPaolo Bonzini */ 50949ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 51049ab747fSPaolo Bonzini { 51149ab747fSPaolo Bonzini unsigned byte; 51249ab747fSPaolo Bonzini 51349ab747fSPaolo Bonzini byte = mac[bit / 8]; 51449ab747fSPaolo Bonzini byte >>= (bit & 0x7); 51549ab747fSPaolo Bonzini byte &= 1; 51649ab747fSPaolo Bonzini 51749ab747fSPaolo Bonzini return byte; 51849ab747fSPaolo Bonzini } 51949ab747fSPaolo Bonzini 52049ab747fSPaolo Bonzini /* 52149ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 52249ab747fSPaolo Bonzini */ 52349ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 52449ab747fSPaolo Bonzini { 52549ab747fSPaolo Bonzini int index_bit, mac_bit; 52649ab747fSPaolo Bonzini unsigned hash_index; 52749ab747fSPaolo Bonzini 52849ab747fSPaolo Bonzini hash_index = 0; 52949ab747fSPaolo Bonzini mac_bit = 5; 53049ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 53149ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 53249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 53349ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 53449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 53549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 53649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 53749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 53849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 53949ab747fSPaolo Bonzini mac_bit--; 54049ab747fSPaolo Bonzini } 54149ab747fSPaolo Bonzini 54249ab747fSPaolo Bonzini return hash_index; 54349ab747fSPaolo Bonzini } 54449ab747fSPaolo Bonzini 54549ab747fSPaolo Bonzini /* 54649ab747fSPaolo Bonzini * gem_mac_address_filter: 54749ab747fSPaolo Bonzini * Accept or reject this destination address? 54849ab747fSPaolo Bonzini * Returns: 54949ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 55063af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 55163af1e0cSPeter Crosthwaite * others for various other modes of accept: 55263af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 55363af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 55449ab747fSPaolo Bonzini */ 555448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 55649ab747fSPaolo Bonzini { 55749ab747fSPaolo Bonzini uint8_t *gem_spaddr; 55849ab747fSPaolo Bonzini int i; 55949ab747fSPaolo Bonzini 56049ab747fSPaolo Bonzini /* Promiscuous mode? */ 56149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 56263af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 56349ab747fSPaolo Bonzini } 56449ab747fSPaolo Bonzini 56549ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 56649ab747fSPaolo Bonzini /* Reject broadcast packets? */ 56749ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 56849ab747fSPaolo Bonzini return GEM_RX_REJECT; 56949ab747fSPaolo Bonzini } 57063af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 57149ab747fSPaolo Bonzini } 57249ab747fSPaolo Bonzini 57349ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 57449ab747fSPaolo Bonzini if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 57549ab747fSPaolo Bonzini (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 57649ab747fSPaolo Bonzini unsigned hash_index; 57749ab747fSPaolo Bonzini 57849ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 57949ab747fSPaolo Bonzini if (hash_index < 32) { 58049ab747fSPaolo Bonzini if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 58163af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 58263af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 58349ab747fSPaolo Bonzini } 58449ab747fSPaolo Bonzini } else { 58549ab747fSPaolo Bonzini hash_index -= 32; 58649ab747fSPaolo Bonzini if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 58763af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 58863af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 58949ab747fSPaolo Bonzini } 59049ab747fSPaolo Bonzini } 59149ab747fSPaolo Bonzini } 59249ab747fSPaolo Bonzini 59349ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 59449ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 59563af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 59664eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 59763af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 59849ab747fSPaolo Bonzini } 59949ab747fSPaolo Bonzini } 60049ab747fSPaolo Bonzini 60149ab747fSPaolo Bonzini /* No address match; reject the packet */ 60249ab747fSPaolo Bonzini return GEM_RX_REJECT; 60349ab747fSPaolo Bonzini } 60449ab747fSPaolo Bonzini 605448f19e2SPeter Crosthwaite static void gem_get_rx_desc(CadenceGEMState *s) 60606c2fe95SPeter Crosthwaite { 607*2bf57f73SAlistair Francis DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[0]); 60806c2fe95SPeter Crosthwaite /* read current descriptor */ 609*2bf57f73SAlistair Francis cpu_physical_memory_read(s->rx_desc_addr[0], 610*2bf57f73SAlistair Francis (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0])); 61106c2fe95SPeter Crosthwaite 61206c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 613*2bf57f73SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[0]) == 1) { 61406c2fe95SPeter Crosthwaite DB_PRINT("descriptor 0x%x owned by sw.\n", 615*2bf57f73SAlistair Francis (unsigned)s->rx_desc_addr[0]); 61606c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 61706c2fe95SPeter Crosthwaite s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 61806c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 61906c2fe95SPeter Crosthwaite gem_update_int_status(s); 62006c2fe95SPeter Crosthwaite } 62106c2fe95SPeter Crosthwaite } 62206c2fe95SPeter Crosthwaite 62349ab747fSPaolo Bonzini /* 62449ab747fSPaolo Bonzini * gem_receive: 62549ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 62649ab747fSPaolo Bonzini */ 62749ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 62849ab747fSPaolo Bonzini { 629448f19e2SPeter Crosthwaite CadenceGEMState *s; 63049ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 63149ab747fSPaolo Bonzini unsigned rxbuf_offset; 63249ab747fSPaolo Bonzini uint8_t rxbuf[2048]; 63349ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 6343b2c97f9SEdgar E. Iglesias bool first_desc = true; 63563af1e0cSPeter Crosthwaite int maf; 636*2bf57f73SAlistair Francis int q = 0; 63749ab747fSPaolo Bonzini 63849ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 63949ab747fSPaolo Bonzini 64049ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 64163af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 64263af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 64349ab747fSPaolo Bonzini return -1; 64449ab747fSPaolo Bonzini } 64549ab747fSPaolo Bonzini 64649ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 64749ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 64849ab747fSPaolo Bonzini unsigned type_len; 64949ab747fSPaolo Bonzini 65049ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 65149ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 65249ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 65349ab747fSPaolo Bonzini if (type_len < 0x600) { 65449ab747fSPaolo Bonzini if (size < type_len) { 65549ab747fSPaolo Bonzini /* discard */ 65649ab747fSPaolo Bonzini return -1; 65749ab747fSPaolo Bonzini } 65849ab747fSPaolo Bonzini } 65949ab747fSPaolo Bonzini } 66049ab747fSPaolo Bonzini 66149ab747fSPaolo Bonzini /* 66249ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 66349ab747fSPaolo Bonzini */ 66449ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 66549ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 66649ab747fSPaolo Bonzini 66749ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 66849ab747fSPaolo Bonzini * buffers needed to hold this packet. 66949ab747fSPaolo Bonzini */ 67049ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 67149ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 67249ab747fSPaolo Bonzini bytes_to_copy = size; 67349ab747fSPaolo Bonzini 674f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 675f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 676f265ae8cSAlistair Francis */ 677f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 678f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 679f265ae8cSAlistair Francis } 680f265ae8cSAlistair Francis 681191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 682191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 683191946c5SPeter Crosthwaite * not FCS stripping 684191946c5SPeter Crosthwaite */ 685191946c5SPeter Crosthwaite if (size < 60) { 686191946c5SPeter Crosthwaite size = 60; 687191946c5SPeter Crosthwaite } 688191946c5SPeter Crosthwaite 68949ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 69049ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 69149ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 69249ab747fSPaolo Bonzini } else { 69349ab747fSPaolo Bonzini unsigned crc_val; 69449ab747fSPaolo Bonzini 695244381ecSPrasad J Pandit if (size > sizeof(rxbuf) - sizeof(crc_val)) { 696244381ecSPrasad J Pandit size = sizeof(rxbuf) - sizeof(crc_val); 697244381ecSPrasad J Pandit } 698244381ecSPrasad J Pandit bytes_to_copy = size; 69949ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 7003048ed6aSPeter Crosthwaite * We must try and calculate one. 70149ab747fSPaolo Bonzini */ 70249ab747fSPaolo Bonzini 70349ab747fSPaolo Bonzini memcpy(rxbuf, buf, size); 70449ab747fSPaolo Bonzini memset(rxbuf + size, 0, sizeof(rxbuf) - size); 70549ab747fSPaolo Bonzini rxbuf_ptr = rxbuf; 70649ab747fSPaolo Bonzini crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 707c94239feSPeter Maydell memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 70849ab747fSPaolo Bonzini 70949ab747fSPaolo Bonzini bytes_to_copy += 4; 71049ab747fSPaolo Bonzini size += 4; 71149ab747fSPaolo Bonzini } 71249ab747fSPaolo Bonzini 71349ab747fSPaolo Bonzini DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 71449ab747fSPaolo Bonzini 7157cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 71606c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 71706c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 71806c2fe95SPeter Crosthwaite assert(!first_desc); 71949ab747fSPaolo Bonzini return -1; 72049ab747fSPaolo Bonzini } 72149ab747fSPaolo Bonzini 72249ab747fSPaolo Bonzini DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 723*2bf57f73SAlistair Francis rx_desc_get_buffer(s->rx_desc[q])); 72449ab747fSPaolo Bonzini 72549ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 726*2bf57f73SAlistair Francis cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) + 727*2bf57f73SAlistair Francis rxbuf_offset, 72849ab747fSPaolo Bonzini rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 72949ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 73030570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 7313b2c97f9SEdgar E. Iglesias 7323b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 7333b2c97f9SEdgar E. Iglesias if (first_desc) { 734*2bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 7353b2c97f9SEdgar E. Iglesias first_desc = false; 7363b2c97f9SEdgar E. Iglesias } 7373b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 738*2bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 739*2bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 7403b2c97f9SEdgar E. Iglesias } 741*2bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 74263af1e0cSPeter Crosthwaite 74363af1e0cSPeter Crosthwaite switch (maf) { 74463af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 74563af1e0cSPeter Crosthwaite break; 74663af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 747*2bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 74863af1e0cSPeter Crosthwaite break; 74963af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 750*2bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 75163af1e0cSPeter Crosthwaite break; 75263af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 753*2bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 75463af1e0cSPeter Crosthwaite break; 75563af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 75663af1e0cSPeter Crosthwaite abort(); 75763af1e0cSPeter Crosthwaite default: /* SAR */ 758*2bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 75963af1e0cSPeter Crosthwaite } 76063af1e0cSPeter Crosthwaite 7613b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 762*2bf57f73SAlistair Francis cpu_physical_memory_write(s->rx_desc_addr[q], 763*2bf57f73SAlistair Francis (uint8_t *)s->rx_desc[q], 764*2bf57f73SAlistair Francis sizeof(s->rx_desc[q])); 7653b2c97f9SEdgar E. Iglesias 76649ab747fSPaolo Bonzini /* Next descriptor */ 767*2bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 76849ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 769*2bf57f73SAlistair Francis s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; 77049ab747fSPaolo Bonzini } else { 77149ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 772*2bf57f73SAlistair Francis s->rx_desc_addr[q] += 8; 77349ab747fSPaolo Bonzini } 77406c2fe95SPeter Crosthwaite gem_get_rx_desc(s); 7757cfd65e4SPeter Crosthwaite } 77649ab747fSPaolo Bonzini 77749ab747fSPaolo Bonzini /* Count it */ 77849ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 77949ab747fSPaolo Bonzini 78049ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 78149ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 78249ab747fSPaolo Bonzini 78349ab747fSPaolo Bonzini /* Handle interrupt consequences */ 78449ab747fSPaolo Bonzini gem_update_int_status(s); 78549ab747fSPaolo Bonzini 78649ab747fSPaolo Bonzini return size; 78749ab747fSPaolo Bonzini } 78849ab747fSPaolo Bonzini 78949ab747fSPaolo Bonzini /* 79049ab747fSPaolo Bonzini * gem_transmit_updatestats: 79149ab747fSPaolo Bonzini * Increment transmit statistics. 79249ab747fSPaolo Bonzini */ 793448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 79449ab747fSPaolo Bonzini unsigned bytes) 79549ab747fSPaolo Bonzini { 79649ab747fSPaolo Bonzini uint64_t octets; 79749ab747fSPaolo Bonzini 79849ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 79949ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 80049ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 80149ab747fSPaolo Bonzini octets += bytes; 80249ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 80349ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 80449ab747fSPaolo Bonzini 80549ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 80649ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 80749ab747fSPaolo Bonzini 80849ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 80949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 81049ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 81149ab747fSPaolo Bonzini } 81249ab747fSPaolo Bonzini 81349ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 81449ab747fSPaolo Bonzini if (packet[0] == 0x01) { 81549ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 81649ab747fSPaolo Bonzini } 81749ab747fSPaolo Bonzini 81849ab747fSPaolo Bonzini if (bytes <= 64) { 81949ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 82049ab747fSPaolo Bonzini } else if (bytes <= 127) { 82149ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 82249ab747fSPaolo Bonzini } else if (bytes <= 255) { 82349ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 82449ab747fSPaolo Bonzini } else if (bytes <= 511) { 82549ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 82649ab747fSPaolo Bonzini } else if (bytes <= 1023) { 82749ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 82849ab747fSPaolo Bonzini } else if (bytes <= 1518) { 82949ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 83049ab747fSPaolo Bonzini } else { 83149ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 83249ab747fSPaolo Bonzini } 83349ab747fSPaolo Bonzini } 83449ab747fSPaolo Bonzini 83549ab747fSPaolo Bonzini /* 83649ab747fSPaolo Bonzini * gem_transmit: 83749ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 83849ab747fSPaolo Bonzini */ 839448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 84049ab747fSPaolo Bonzini { 84149ab747fSPaolo Bonzini unsigned desc[2]; 84249ab747fSPaolo Bonzini hwaddr packet_desc_addr; 84349ab747fSPaolo Bonzini uint8_t tx_packet[2048]; 84449ab747fSPaolo Bonzini uint8_t *p; 84549ab747fSPaolo Bonzini unsigned total_bytes; 846*2bf57f73SAlistair Francis int q = 0; 84749ab747fSPaolo Bonzini 84849ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 84949ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 85049ab747fSPaolo Bonzini return; 85149ab747fSPaolo Bonzini } 85249ab747fSPaolo Bonzini 85349ab747fSPaolo Bonzini DB_PRINT("\n"); 85449ab747fSPaolo Bonzini 8553048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 85649ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 85749ab747fSPaolo Bonzini * one contiguous buffer first. 85849ab747fSPaolo Bonzini */ 85949ab747fSPaolo Bonzini p = tx_packet; 86049ab747fSPaolo Bonzini total_bytes = 0; 86149ab747fSPaolo Bonzini 86249ab747fSPaolo Bonzini /* read current descriptor */ 863*2bf57f73SAlistair Francis packet_desc_addr = s->tx_desc_addr[q]; 864fa15286aSPeter Crosthwaite 865fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 86649ab747fSPaolo Bonzini cpu_physical_memory_read(packet_desc_addr, 867ef18c2f5SPeter Crosthwaite (uint8_t *)desc, sizeof(desc)); 86849ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 86949ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 87049ab747fSPaolo Bonzini 87149ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 87249ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 87349ab747fSPaolo Bonzini return; 87449ab747fSPaolo Bonzini } 87549ab747fSPaolo Bonzini print_gem_tx_desc(desc); 87649ab747fSPaolo Bonzini 87749ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 87849ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 87949ab747fSPaolo Bonzini */ 88049ab747fSPaolo Bonzini if ((tx_desc_get_buffer(desc) == 0) || 88149ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 88249ab747fSPaolo Bonzini DB_PRINT("Invalid TX descriptor @ 0x%x\n", 88349ab747fSPaolo Bonzini (unsigned)packet_desc_addr); 88449ab747fSPaolo Bonzini break; 88549ab747fSPaolo Bonzini } 88649ab747fSPaolo Bonzini 887d7f05365SMichael S. Tsirkin if (tx_desc_get_length(desc) > sizeof(tx_packet) - (p - tx_packet)) { 888d7f05365SMichael S. Tsirkin DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space 0x%x\n", 889d7f05365SMichael S. Tsirkin (unsigned)packet_desc_addr, 890d7f05365SMichael S. Tsirkin (unsigned)tx_desc_get_length(desc), 891d7f05365SMichael S. Tsirkin sizeof(tx_packet) - (p - tx_packet)); 892d7f05365SMichael S. Tsirkin break; 893d7f05365SMichael S. Tsirkin } 894d7f05365SMichael S. Tsirkin 89549ab747fSPaolo Bonzini /* Gather this fragment of the packet from "dma memory" to our contig. 89649ab747fSPaolo Bonzini * buffer. 89749ab747fSPaolo Bonzini */ 89849ab747fSPaolo Bonzini cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 89949ab747fSPaolo Bonzini tx_desc_get_length(desc)); 90049ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 90149ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 90249ab747fSPaolo Bonzini 90349ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 90449ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 9056ab57a6bSPeter Crosthwaite unsigned desc_first[2]; 9066ab57a6bSPeter Crosthwaite 90749ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 90849ab747fSPaolo Bonzini * the processor. 90949ab747fSPaolo Bonzini */ 910*2bf57f73SAlistair Francis cpu_physical_memory_read(s->tx_desc_addr[q], (uint8_t *)desc_first, 9116ab57a6bSPeter Crosthwaite sizeof(desc_first)); 9126ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 913*2bf57f73SAlistair Francis cpu_physical_memory_write(s->tx_desc_addr[q], (uint8_t *)desc_first, 9146ab57a6bSPeter Crosthwaite sizeof(desc_first)); 9153048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 91649ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 917*2bf57f73SAlistair Francis s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; 91849ab747fSPaolo Bonzini } else { 919*2bf57f73SAlistair Francis s->tx_desc_addr[q] = packet_desc_addr + 8; 92049ab747fSPaolo Bonzini } 921*2bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 92249ab747fSPaolo Bonzini 92349ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 92449ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 92549ab747fSPaolo Bonzini 92649ab747fSPaolo Bonzini /* Handle interrupt consequences */ 92749ab747fSPaolo Bonzini gem_update_int_status(s); 92849ab747fSPaolo Bonzini 92949ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 93049ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 93149ab747fSPaolo Bonzini net_checksum_calculate(tx_packet, total_bytes); 93249ab747fSPaolo Bonzini } 93349ab747fSPaolo Bonzini 93449ab747fSPaolo Bonzini /* Update MAC statistics */ 93549ab747fSPaolo Bonzini gem_transmit_updatestats(s, tx_packet, total_bytes); 93649ab747fSPaolo Bonzini 93749ab747fSPaolo Bonzini /* Send the packet somewhere */ 93824e822eaSPeter Crosthwaite if (s->phy_loop || (s->regs[GEM_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) { 93949ab747fSPaolo Bonzini gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes); 94049ab747fSPaolo Bonzini } else { 94149ab747fSPaolo Bonzini qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 94249ab747fSPaolo Bonzini total_bytes); 94349ab747fSPaolo Bonzini } 94449ab747fSPaolo Bonzini 94549ab747fSPaolo Bonzini /* Prepare for next packet */ 94649ab747fSPaolo Bonzini p = tx_packet; 94749ab747fSPaolo Bonzini total_bytes = 0; 94849ab747fSPaolo Bonzini } 94949ab747fSPaolo Bonzini 95049ab747fSPaolo Bonzini /* read next descriptor */ 95149ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 952cbdab58dSAlistair Francis tx_desc_set_last(desc); 95349ab747fSPaolo Bonzini packet_desc_addr = s->regs[GEM_TXQBASE]; 95449ab747fSPaolo Bonzini } else { 95549ab747fSPaolo Bonzini packet_desc_addr += 8; 95649ab747fSPaolo Bonzini } 957fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 95849ab747fSPaolo Bonzini cpu_physical_memory_read(packet_desc_addr, 959ef18c2f5SPeter Crosthwaite (uint8_t *)desc, sizeof(desc)); 96049ab747fSPaolo Bonzini } 96149ab747fSPaolo Bonzini 96249ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 96349ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 96449ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 96549ab747fSPaolo Bonzini gem_update_int_status(s); 96649ab747fSPaolo Bonzini } 96749ab747fSPaolo Bonzini } 96849ab747fSPaolo Bonzini 969448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 97049ab747fSPaolo Bonzini { 97149ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 97249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 97349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 97449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 97549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 97649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 97749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 97849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 97949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 98049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 98149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 98249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 98349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 98449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 9857777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 98649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 98749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 98849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 98949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 99049ab747fSPaolo Bonzini 99149ab747fSPaolo Bonzini phy_update_link(s); 99249ab747fSPaolo Bonzini } 99349ab747fSPaolo Bonzini 99449ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 99549ab747fSPaolo Bonzini { 99664eb9301SPeter Crosthwaite int i; 997448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 998afb4c51fSSebastian Huber const uint8_t *a; 99949ab747fSPaolo Bonzini 100049ab747fSPaolo Bonzini DB_PRINT("\n"); 100149ab747fSPaolo Bonzini 100249ab747fSPaolo Bonzini /* Set post reset register values */ 100349ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 100449ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 100549ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 100649ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 100749ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 100849ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 100949ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 101049ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 101149ab747fSPaolo Bonzini s->regs[GEM_MODID] = 0x00020118; 101249ab747fSPaolo Bonzini s->regs[GEM_DESCONF] = 0x02500111; 101349ab747fSPaolo Bonzini s->regs[GEM_DESCONF2] = 0x2ab13fff; 101449ab747fSPaolo Bonzini s->regs[GEM_DESCONF5] = 0x002f2145; 101549ab747fSPaolo Bonzini s->regs[GEM_DESCONF6] = 0x00000200; 101649ab747fSPaolo Bonzini 1017afb4c51fSSebastian Huber /* Set MAC address */ 1018afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1019afb4c51fSSebastian Huber s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1020afb4c51fSSebastian Huber s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1021afb4c51fSSebastian Huber 102264eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 102364eb9301SPeter Crosthwaite s->sar_active[i] = false; 102464eb9301SPeter Crosthwaite } 102564eb9301SPeter Crosthwaite 102649ab747fSPaolo Bonzini gem_phy_reset(s); 102749ab747fSPaolo Bonzini 102849ab747fSPaolo Bonzini gem_update_int_status(s); 102949ab747fSPaolo Bonzini } 103049ab747fSPaolo Bonzini 1031448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 103249ab747fSPaolo Bonzini { 103349ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 103449ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 103549ab747fSPaolo Bonzini } 103649ab747fSPaolo Bonzini 1037448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 103849ab747fSPaolo Bonzini { 103949ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 104049ab747fSPaolo Bonzini 104149ab747fSPaolo Bonzini switch (reg_num) { 104249ab747fSPaolo Bonzini case PHY_REG_CONTROL: 104349ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 104449ab747fSPaolo Bonzini /* Phy reset */ 104549ab747fSPaolo Bonzini gem_phy_reset(s); 104649ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 104749ab747fSPaolo Bonzini s->phy_loop = 0; 104849ab747fSPaolo Bonzini } 104949ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 105049ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 105149ab747fSPaolo Bonzini val &= ~PHY_REG_CONTROL_ANEG; 105249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 105349ab747fSPaolo Bonzini } 105449ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 105549ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 105649ab747fSPaolo Bonzini s->phy_loop = 1; 105749ab747fSPaolo Bonzini } else { 105849ab747fSPaolo Bonzini s->phy_loop = 0; 105949ab747fSPaolo Bonzini } 106049ab747fSPaolo Bonzini break; 106149ab747fSPaolo Bonzini } 106249ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 106349ab747fSPaolo Bonzini } 106449ab747fSPaolo Bonzini 106549ab747fSPaolo Bonzini /* 106649ab747fSPaolo Bonzini * gem_read32: 106749ab747fSPaolo Bonzini * Read a GEM register. 106849ab747fSPaolo Bonzini */ 106949ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 107049ab747fSPaolo Bonzini { 1071448f19e2SPeter Crosthwaite CadenceGEMState *s; 107249ab747fSPaolo Bonzini uint32_t retval; 107349ab747fSPaolo Bonzini 1074448f19e2SPeter Crosthwaite s = (CadenceGEMState *)opaque; 107549ab747fSPaolo Bonzini 107649ab747fSPaolo Bonzini offset >>= 2; 107749ab747fSPaolo Bonzini retval = s->regs[offset]; 107849ab747fSPaolo Bonzini 107949ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 108049ab747fSPaolo Bonzini 108149ab747fSPaolo Bonzini switch (offset) { 108249ab747fSPaolo Bonzini case GEM_ISR: 108349ab747fSPaolo Bonzini DB_PRINT("lowering irq on ISR read\n"); 1084*2bf57f73SAlistair Francis qemu_set_irq(s->irq[0], 0); 108549ab747fSPaolo Bonzini break; 108649ab747fSPaolo Bonzini case GEM_PHYMNTNC: 108749ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 108849ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 108949ab747fSPaolo Bonzini 109049ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 109155389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 109249ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 109349ab747fSPaolo Bonzini retval &= 0xFFFF0000; 109449ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 109549ab747fSPaolo Bonzini } else { 109649ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 109749ab747fSPaolo Bonzini } 109849ab747fSPaolo Bonzini } 109949ab747fSPaolo Bonzini break; 110049ab747fSPaolo Bonzini } 110149ab747fSPaolo Bonzini 110249ab747fSPaolo Bonzini /* Squash read to clear bits */ 110349ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 110449ab747fSPaolo Bonzini 110549ab747fSPaolo Bonzini /* Do not provide write only bits */ 110649ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 110749ab747fSPaolo Bonzini 110849ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 110949ab747fSPaolo Bonzini return retval; 111049ab747fSPaolo Bonzini } 111149ab747fSPaolo Bonzini 111249ab747fSPaolo Bonzini /* 111349ab747fSPaolo Bonzini * gem_write32: 111449ab747fSPaolo Bonzini * Write a GEM register. 111549ab747fSPaolo Bonzini */ 111649ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 111749ab747fSPaolo Bonzini unsigned size) 111849ab747fSPaolo Bonzini { 1119448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 112049ab747fSPaolo Bonzini uint32_t readonly; 112149ab747fSPaolo Bonzini 112249ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 112349ab747fSPaolo Bonzini offset >>= 2; 112449ab747fSPaolo Bonzini 112549ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 112649ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1127e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1128e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 112949ab747fSPaolo Bonzini 113049ab747fSPaolo Bonzini /* Copy register write to backing store */ 1131e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1132e2314fdaSPeter Crosthwaite 1133e2314fdaSPeter Crosthwaite /* do w1c */ 1134e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 113549ab747fSPaolo Bonzini 113649ab747fSPaolo Bonzini /* Handle register write side effects */ 113749ab747fSPaolo Bonzini switch (offset) { 113849ab747fSPaolo Bonzini case GEM_NWCTRL: 113906c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 114006c2fe95SPeter Crosthwaite gem_get_rx_desc(s); 114106c2fe95SPeter Crosthwaite } 114249ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 114349ab747fSPaolo Bonzini gem_transmit(s); 114449ab747fSPaolo Bonzini } 114549ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 114649ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 1147*2bf57f73SAlistair Francis s->tx_desc_addr[0] = s->regs[GEM_TXQBASE]; 114849ab747fSPaolo Bonzini } 11498202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 115049ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 115149ab747fSPaolo Bonzini } 115249ab747fSPaolo Bonzini break; 115349ab747fSPaolo Bonzini 115449ab747fSPaolo Bonzini case GEM_TXSTATUS: 115549ab747fSPaolo Bonzini gem_update_int_status(s); 115649ab747fSPaolo Bonzini break; 115749ab747fSPaolo Bonzini case GEM_RXQBASE: 1158*2bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 115949ab747fSPaolo Bonzini break; 116049ab747fSPaolo Bonzini case GEM_TXQBASE: 1161*2bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 116249ab747fSPaolo Bonzini break; 116349ab747fSPaolo Bonzini case GEM_RXSTATUS: 116449ab747fSPaolo Bonzini gem_update_int_status(s); 116549ab747fSPaolo Bonzini break; 116649ab747fSPaolo Bonzini case GEM_IER: 116749ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 116849ab747fSPaolo Bonzini gem_update_int_status(s); 116949ab747fSPaolo Bonzini break; 117049ab747fSPaolo Bonzini case GEM_IDR: 117149ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 117249ab747fSPaolo Bonzini gem_update_int_status(s); 117349ab747fSPaolo Bonzini break; 117464eb9301SPeter Crosthwaite case GEM_SPADDR1LO: 117564eb9301SPeter Crosthwaite case GEM_SPADDR2LO: 117664eb9301SPeter Crosthwaite case GEM_SPADDR3LO: 117764eb9301SPeter Crosthwaite case GEM_SPADDR4LO: 117864eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 117964eb9301SPeter Crosthwaite break; 118064eb9301SPeter Crosthwaite case GEM_SPADDR1HI: 118164eb9301SPeter Crosthwaite case GEM_SPADDR2HI: 118264eb9301SPeter Crosthwaite case GEM_SPADDR3HI: 118364eb9301SPeter Crosthwaite case GEM_SPADDR4HI: 118464eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 118564eb9301SPeter Crosthwaite break; 118649ab747fSPaolo Bonzini case GEM_PHYMNTNC: 118749ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 118849ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 118949ab747fSPaolo Bonzini 119049ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 119155389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 119249ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 119349ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 119449ab747fSPaolo Bonzini } 119549ab747fSPaolo Bonzini } 119649ab747fSPaolo Bonzini break; 119749ab747fSPaolo Bonzini } 119849ab747fSPaolo Bonzini 119949ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 120049ab747fSPaolo Bonzini } 120149ab747fSPaolo Bonzini 120249ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 120349ab747fSPaolo Bonzini .read = gem_read, 120449ab747fSPaolo Bonzini .write = gem_write, 120549ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 120649ab747fSPaolo Bonzini }; 120749ab747fSPaolo Bonzini 120849ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 120949ab747fSPaolo Bonzini { 121049ab747fSPaolo Bonzini DB_PRINT("\n"); 121149ab747fSPaolo Bonzini phy_update_link(qemu_get_nic_opaque(nc)); 121249ab747fSPaolo Bonzini } 121349ab747fSPaolo Bonzini 121449ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1215f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 121649ab747fSPaolo Bonzini .size = sizeof(NICState), 121749ab747fSPaolo Bonzini .can_receive = gem_can_receive, 121849ab747fSPaolo Bonzini .receive = gem_receive, 121949ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 122049ab747fSPaolo Bonzini }; 122149ab747fSPaolo Bonzini 1222bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 122349ab747fSPaolo Bonzini { 1224448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 122549ab747fSPaolo Bonzini 1226*2bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 1227*2bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 1228*2bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 1229*2bf57f73SAlistair Francis s->num_priority_queues); 1230*2bf57f73SAlistair Francis return; 1231*2bf57f73SAlistair Francis } 1232*2bf57f73SAlistair Francis 1233*2bf57f73SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[0]); 1234bcb39a65SAlistair Francis 1235bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1236bcb39a65SAlistair Francis 1237bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1238bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 1239bcb39a65SAlistair Francis } 1240bcb39a65SAlistair Francis 1241bcb39a65SAlistair Francis static void gem_init(Object *obj) 1242bcb39a65SAlistair Francis { 1243bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1244bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1245bcb39a65SAlistair Francis 124649ab747fSPaolo Bonzini DB_PRINT("\n"); 124749ab747fSPaolo Bonzini 124849ab747fSPaolo Bonzini gem_init_register_masks(s); 1249eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1250eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 125149ab747fSPaolo Bonzini 1252bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 125349ab747fSPaolo Bonzini } 125449ab747fSPaolo Bonzini 125549ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 125649ab747fSPaolo Bonzini .name = "cadence_gem", 1257*2bf57f73SAlistair Francis .version_id = 3, 1258*2bf57f73SAlistair Francis .minimum_version_id = 3, 125949ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1260448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1261448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1262448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 1263*2bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 1264*2bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1265*2bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 1266*2bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1267448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 126817cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 126949ab747fSPaolo Bonzini } 127049ab747fSPaolo Bonzini }; 127149ab747fSPaolo Bonzini 127249ab747fSPaolo Bonzini static Property gem_properties[] = { 1273448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1274*2bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 1275*2bf57f73SAlistair Francis num_priority_queues, 1), 127649ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 127749ab747fSPaolo Bonzini }; 127849ab747fSPaolo Bonzini 127949ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 128049ab747fSPaolo Bonzini { 128149ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 128249ab747fSPaolo Bonzini 1283bcb39a65SAlistair Francis dc->realize = gem_realize; 128449ab747fSPaolo Bonzini dc->props = gem_properties; 128549ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 128649ab747fSPaolo Bonzini dc->reset = gem_reset; 128749ab747fSPaolo Bonzini } 128849ab747fSPaolo Bonzini 128949ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1290318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 129149ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1292448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1293bcb39a65SAlistair Francis .instance_init = gem_init, 1294318643beSAndreas Färber .class_init = gem_class_init, 129549ab747fSPaolo Bonzini }; 129649ab747fSPaolo Bonzini 129749ab747fSPaolo Bonzini static void gem_register_types(void) 129849ab747fSPaolo Bonzini { 129949ab747fSPaolo Bonzini type_register_static(&gem_info); 130049ab747fSPaolo Bonzini } 130149ab747fSPaolo Bonzini 130249ab747fSPaolo Bonzini type_init(gem_register_types) 1303