149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31c755c943SLuc Michel #include "hw/registerfields.h" 32d6454270SMarkus Armbruster #include "migration/vmstate.h" 332bf57f73SAlistair Francis #include "qapi/error.h" 34e8e49943SAlistair Francis #include "qemu/log.h" 350b8fa32fSMarkus Armbruster #include "qemu/module.h" 3684aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3749ab747fSPaolo Bonzini #include "net/checksum.h" 38fbc14a09STong Ho #include "net/eth.h" 3949ab747fSPaolo Bonzini 406fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 4149ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 426fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 436fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 446fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 456fe7661dSSai Pavan Boddu } \ 462562755eSEric Blake } while (0) 4749ab747fSPaolo Bonzini 48c755c943SLuc Michel REG32(NWCTRL, 0x0) /* Network Control reg */ 49bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK , 0, 1) 50bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) 51bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) 52bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) 53bd8a922dSLuc Michel FIELD(NWCTRL, MAN_PORT_EN , 4, 1) 54bd8a922dSLuc Michel FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) 55bd8a922dSLuc Michel FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) 56bd8a922dSLuc Michel FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) 57bd8a922dSLuc Michel FIELD(NWCTRL, BACK_PRESSURE, 8, 1) 58bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_START , 9, 1) 59bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) 60bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) 61bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) 62bd8a922dSLuc Michel FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) 63bd8a922dSLuc Michel FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) 64bd8a922dSLuc Michel FIELD(NWCTRL, STORE_RX_TS, 15, 1) 65bd8a922dSLuc Michel FIELD(NWCTRL, PFC_ENABLE, 16, 1) 66bd8a922dSLuc Michel FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) 67bd8a922dSLuc Michel FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) 68bd8a922dSLuc Michel FIELD(NWCTRL, TX_LPI_EN, 19, 1) 69bd8a922dSLuc Michel FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) 70bd8a922dSLuc Michel FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) 71bd8a922dSLuc Michel FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) 72bd8a922dSLuc Michel FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) 73bd8a922dSLuc Michel FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) 74bd8a922dSLuc Michel FIELD(NWCTRL, PFC_CTRL , 25, 1) 75bd8a922dSLuc Michel FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) 76bd8a922dSLuc Michel FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) 77bd8a922dSLuc Michel FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) 78bd8a922dSLuc Michel FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) 79bd8a922dSLuc Michel FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) 80bd8a922dSLuc Michel 81c755c943SLuc Michel REG32(NWCFG, 0x4) /* Network Config reg */ 8287a49c3fSLuc Michel FIELD(NWCFG, SPEED, 0, 1) 8387a49c3fSLuc Michel FIELD(NWCFG, FULL_DUPLEX, 1, 1) 8487a49c3fSLuc Michel FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) 8587a49c3fSLuc Michel FIELD(NWCFG, JUMBO_FRAMES, 3, 1) 8687a49c3fSLuc Michel FIELD(NWCFG, PROMISC, 4, 1) 8787a49c3fSLuc Michel FIELD(NWCFG, NO_BROADCAST, 5, 1) 8887a49c3fSLuc Michel FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) 8987a49c3fSLuc Michel FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) 9087a49c3fSLuc Michel FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) 9187a49c3fSLuc Michel FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) 9287a49c3fSLuc Michel FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) 9387a49c3fSLuc Michel FIELD(NWCFG, PCS_SELECT, 11, 1) 9487a49c3fSLuc Michel FIELD(NWCFG, RETRY_TEST, 12, 1) 9587a49c3fSLuc Michel FIELD(NWCFG, PAUSE_ENABLE, 13, 1) 9687a49c3fSLuc Michel FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) 9787a49c3fSLuc Michel FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) 9887a49c3fSLuc Michel FIELD(NWCFG, FCS_REMOVE, 17, 1) 9987a49c3fSLuc Michel FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) 10087a49c3fSLuc Michel FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) 10187a49c3fSLuc Michel FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) 10287a49c3fSLuc Michel FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) 10387a49c3fSLuc Michel FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) 10487a49c3fSLuc Michel FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) 10587a49c3fSLuc Michel FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) 10687a49c3fSLuc Michel FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) 10787a49c3fSLuc Michel FIELD(NWCFG, NSP_ACCEPT, 29, 1) 10887a49c3fSLuc Michel FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) 10987a49c3fSLuc Michel FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) 11087a49c3fSLuc Michel 111c755c943SLuc Michel REG32(NWSTATUS, 0x8) /* Network Status reg */ 112c755c943SLuc Michel REG32(USERIO, 0xc) /* User IO reg */ 11301f9175dSLuc Michel 114c755c943SLuc Michel REG32(DMACFG, 0x10) /* DMA Control reg */ 11501f9175dSLuc Michel FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1) 11601f9175dSLuc Michel FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1) 11701f9175dSLuc Michel FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1) 11801f9175dSLuc Michel FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1) 11901f9175dSLuc Michel FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1) 12001f9175dSLuc Michel FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1) 12101f9175dSLuc Michel FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1) 12201f9175dSLuc Michel FIELD(DMACFG, RX_BUF_SIZE, 16, 8) 12301f9175dSLuc Michel FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1) 12401f9175dSLuc Michel FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1) 12501f9175dSLuc Michel FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1) 12601f9175dSLuc Michel FIELD(DMACFG, TX_PBUF_SIZE, 10, 1) 12701f9175dSLuc Michel FIELD(DMACFG, RX_PBUF_SIZE, 8, 2) 12801f9175dSLuc Michel FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1) 12901f9175dSLuc Michel FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1) 13001f9175dSLuc Michel FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1) 13101f9175dSLuc Michel FIELD(DMACFG, AMBA_BURST_LEN , 0, 5) 13201f9175dSLuc Michel #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 13301f9175dSLuc Michel 134c755c943SLuc Michel REG32(TXSTATUS, 0x14) /* TX Status reg */ 135466da857SLuc Michel FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1) 136466da857SLuc Michel FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1) 137466da857SLuc Michel FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1) 138466da857SLuc Michel FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1) 139466da857SLuc Michel FIELD(TXSTATUS, RESP_NOT_OK, 8, 1) 140466da857SLuc Michel FIELD(TXSTATUS, LATE_COLLISION, 7, 1) 141466da857SLuc Michel FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1) 142466da857SLuc Michel FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1) 143466da857SLuc Michel FIELD(TXSTATUS, AMBA_ERROR, 4, 1) 144466da857SLuc Michel FIELD(TXSTATUS, TRANSMIT_GO, 3, 1) 145466da857SLuc Michel FIELD(TXSTATUS, RETRY_LIMIT, 2, 1) 146466da857SLuc Michel FIELD(TXSTATUS, COLLISION, 1, 1) 147466da857SLuc Michel FIELD(TXSTATUS, USED_BIT_READ, 0, 1) 148466da857SLuc Michel 149c755c943SLuc Michel REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 150c755c943SLuc Michel REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 151c755c943SLuc Michel REG32(RXSTATUS, 0x20) /* RX Status reg */ 152466da857SLuc Michel FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1) 153466da857SLuc Michel FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1) 154466da857SLuc Michel FIELD(RXSTATUS, RESP_NOT_OK, 3, 1) 155466da857SLuc Michel FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1) 156466da857SLuc Michel FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1) 157466da857SLuc Michel FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1) 158466da857SLuc Michel 159c755c943SLuc Michel REG32(ISR, 0x24) /* Interrupt Status reg */ 160c755c943SLuc Michel REG32(IER, 0x28) /* Interrupt Enable reg */ 161c755c943SLuc Michel REG32(IDR, 0x2c) /* Interrupt Disable reg */ 162c755c943SLuc Michel REG32(IMR, 0x30) /* Interrupt Mask reg */ 163c755c943SLuc Michel REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 164c755c943SLuc Michel REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 165c755c943SLuc Michel REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 166c755c943SLuc Michel REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 167c755c943SLuc Michel REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 168c755c943SLuc Michel REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 169c755c943SLuc Michel REG32(HASHLO, 0x80) /* Hash Low address reg */ 170c755c943SLuc Michel REG32(HASHHI, 0x84) /* Hash High address reg */ 171c755c943SLuc Michel REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 172c755c943SLuc Michel REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 173c755c943SLuc Michel REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 174c755c943SLuc Michel REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 175c755c943SLuc Michel REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 176c755c943SLuc Michel REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 177c755c943SLuc Michel REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 178c755c943SLuc Michel REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 179c755c943SLuc Michel REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 180c755c943SLuc Michel REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 181c755c943SLuc Michel REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 182c755c943SLuc Michel REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 183c755c943SLuc Michel REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 184c755c943SLuc Michel REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 185c755c943SLuc Michel REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 186c755c943SLuc Michel REG32(MODID, 0xfc) /* Module ID reg */ 187c755c943SLuc Michel REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 188c755c943SLuc Michel REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 189c755c943SLuc Michel REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 190c755c943SLuc Michel REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 191c755c943SLuc Michel REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 192c755c943SLuc Michel REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 193c755c943SLuc Michel REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 194c755c943SLuc Michel REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 195c755c943SLuc Michel REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 196c755c943SLuc Michel REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 197c755c943SLuc Michel REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 198c755c943SLuc Michel REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 199c755c943SLuc Michel REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 200c755c943SLuc Michel REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 201c755c943SLuc Michel REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 202c755c943SLuc Michel REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 203c755c943SLuc Michel REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 204c755c943SLuc Michel REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 205c755c943SLuc Michel REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 206c755c943SLuc Michel REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 207c755c943SLuc Michel REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 208c755c943SLuc Michel REG32(OCTRXHI, 0x154) /* Octects Received register High */ 209c755c943SLuc Michel REG32(RXCNT, 0x158) /* Error-free Frames Received */ 210c755c943SLuc Michel REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 211c755c943SLuc Michel REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 212c755c943SLuc Michel REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 213c755c943SLuc Michel REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 214c755c943SLuc Michel REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 215c755c943SLuc Michel REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 216c755c943SLuc Michel REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 217c755c943SLuc Michel REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 218c755c943SLuc Michel REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 219c755c943SLuc Michel REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 220c755c943SLuc Michel REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 221c755c943SLuc Michel REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 222c755c943SLuc Michel REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 223c755c943SLuc Michel REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 224c755c943SLuc Michel REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 225c755c943SLuc Michel REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 226c755c943SLuc Michel REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 227c755c943SLuc Michel REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 228c755c943SLuc Michel REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 229c755c943SLuc Michel REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 230c755c943SLuc Michel REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 231c755c943SLuc Michel REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 23249ab747fSPaolo Bonzini 233c755c943SLuc Michel REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 234c755c943SLuc Michel REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 235c755c943SLuc Michel REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 236c755c943SLuc Michel REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 237c755c943SLuc Michel REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 238c755c943SLuc Michel REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 239c755c943SLuc Michel REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 240c755c943SLuc Michel REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 241c755c943SLuc Michel REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 242c755c943SLuc Michel REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 243c755c943SLuc Michel REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 244c755c943SLuc Michel REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 24549ab747fSPaolo Bonzini 24649ab747fSPaolo Bonzini /* Design Configuration Registers */ 247c755c943SLuc Michel REG32(DESCONF, 0x280) 248c755c943SLuc Michel REG32(DESCONF2, 0x284) 249c755c943SLuc Michel REG32(DESCONF3, 0x288) 250c755c943SLuc Michel REG32(DESCONF4, 0x28c) 251c755c943SLuc Michel REG32(DESCONF5, 0x290) 252c755c943SLuc Michel REG32(DESCONF6, 0x294) 253e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 254c755c943SLuc Michel REG32(DESCONF7, 0x298) 25549ab747fSPaolo Bonzini 256c755c943SLuc Michel REG32(INT_Q1_STATUS, 0x400) 257c755c943SLuc Michel REG32(INT_Q1_MASK, 0x640) 25867101725SAlistair Francis 259c755c943SLuc Michel REG32(TRANSMIT_Q1_PTR, 0x440) 260c755c943SLuc Michel REG32(TRANSMIT_Q7_PTR, 0x458) 26167101725SAlistair Francis 262c755c943SLuc Michel REG32(RECEIVE_Q1_PTR, 0x480) 263c755c943SLuc Michel REG32(RECEIVE_Q7_PTR, 0x498) 26467101725SAlistair Francis 265c755c943SLuc Michel REG32(TBQPH, 0x4c8) 266c755c943SLuc Michel REG32(RBQPH, 0x4d4) 267357aa013SEdgar E. Iglesias 268c755c943SLuc Michel REG32(INT_Q1_ENABLE, 0x600) 269c755c943SLuc Michel REG32(INT_Q7_ENABLE, 0x618) 27067101725SAlistair Francis 271c755c943SLuc Michel REG32(INT_Q1_DISABLE, 0x620) 272c755c943SLuc Michel REG32(INT_Q7_DISABLE, 0x638) 27367101725SAlistair Francis 274c755c943SLuc Michel REG32(SCREENING_TYPE1_REG0, 0x500) 275b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) 276b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) 277b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) 278b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) 279b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) 280b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) 281e8e49943SAlistair Francis 282c755c943SLuc Michel REG32(SCREENING_TYPE2_REG0, 0x540) 283b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) 284b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) 285b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) 286b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) 287b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) 288b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) 289b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) 290b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) 291b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) 292b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) 293b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) 294b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) 295e8e49943SAlistair Francis 296c755c943SLuc Michel REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 297e8e49943SAlistair Francis 298b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 299b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) 300b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) 301b46b526cSLuc Michel 302b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_1, 0x704) 303b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) 304b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) 305b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) 306b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) 307e8e49943SAlistair Francis 30849ab747fSPaolo Bonzini /*****************************************/ 30949ab747fSPaolo Bonzini 31049ab747fSPaolo Bonzini 31149ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 31249ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 3137ca151c3SSai Pavan Boddu #define GEM_INT_AMBA_ERR 0x00000040 31449ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 31549ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 31649ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 31749ab747fSPaolo Bonzini 31849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 31949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 32049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 32149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 32249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 32349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 32449ab747fSPaolo Bonzini 32549ab747fSPaolo Bonzini /* Marvell PHY definitions */ 326dfc38879SBin Meng #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 32749ab747fSPaolo Bonzini 32849ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 32949ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 33049ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 33149ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 33249ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 33349ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 33449ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 33549ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 33649ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 33749ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 33849ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 33949ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 34049ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 34149ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 34249ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 34349ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 34449ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 34549ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 34649ab747fSPaolo Bonzini #define PHY_REG_EACD 22 34749ab747fSPaolo Bonzini #define PHY_REG_LED 24 34849ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 34949ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 35049ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 35149ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 35249ab747fSPaolo Bonzini 35349ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 35449ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 35549ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 3566623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 35749ab747fSPaolo Bonzini 35849ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 35949ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 36049ab747fSPaolo Bonzini 36149ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 36249ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 36349ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 36449ab747fSPaolo Bonzini 36549ab747fSPaolo Bonzini /***********************************************************************/ 36663af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 36763af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 36863af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 36963af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 37063af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 37163af1e0cSPeter Crosthwaite 37263af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 37349ab747fSPaolo Bonzini 37449ab747fSPaolo Bonzini /***********************************************************************/ 37549ab747fSPaolo Bonzini 37649ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 37749ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 37849ab747fSPaolo Bonzini 37949ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 38049ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 38149ab747fSPaolo Bonzini 38249ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 38349ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 38449ab747fSPaolo Bonzini 38563af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 38663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 387a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 38863af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 38963af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 39063af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 39163af1e0cSPeter Crosthwaite 39249ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 39349ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 39449ab747fSPaolo Bonzini 395a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 396a5517666SAlistair Francis 397e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 39849ab747fSPaolo Bonzini { 399e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 400e48fdd9dSEdgar E. Iglesias 40101f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 402e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 403e48fdd9dSEdgar E. Iglesias } 404e48fdd9dSEdgar E. Iglesias return ret; 40549ab747fSPaolo Bonzini } 40649ab747fSPaolo Bonzini 407f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 40849ab747fSPaolo Bonzini { 40949ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 41049ab747fSPaolo Bonzini } 41149ab747fSPaolo Bonzini 412f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 41349ab747fSPaolo Bonzini { 41449ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 41549ab747fSPaolo Bonzini } 41649ab747fSPaolo Bonzini 417f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 41849ab747fSPaolo Bonzini { 41949ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 42049ab747fSPaolo Bonzini } 42149ab747fSPaolo Bonzini 422f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 42349ab747fSPaolo Bonzini { 42449ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 42549ab747fSPaolo Bonzini } 42649ab747fSPaolo Bonzini 427f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 42849ab747fSPaolo Bonzini { 42949ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 43049ab747fSPaolo Bonzini } 43149ab747fSPaolo Bonzini 432f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 43349ab747fSPaolo Bonzini { 43467101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 43549ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 43649ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 43749ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 43849ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 43949ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 44049ab747fSPaolo Bonzini } 44149ab747fSPaolo Bonzini 442e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 44349ab747fSPaolo Bonzini { 444e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 445e48fdd9dSEdgar E. Iglesias 44601f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 447e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 448e48fdd9dSEdgar E. Iglesias } 449e48fdd9dSEdgar E. Iglesias return ret; 450e48fdd9dSEdgar E. Iglesias } 451e48fdd9dSEdgar E. Iglesias 452e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 453e48fdd9dSEdgar E. Iglesias { 454e48fdd9dSEdgar E. Iglesias int ret = 2; 455e48fdd9dSEdgar E. Iglesias 45601f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 457e48fdd9dSEdgar E. Iglesias ret += 2; 458e48fdd9dSEdgar E. Iglesias } 45901f9175dSLuc Michel if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK 46001f9175dSLuc Michel : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) { 461e48fdd9dSEdgar E. Iglesias ret += 2; 462e48fdd9dSEdgar E. Iglesias } 463e48fdd9dSEdgar E. Iglesias 464e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 465e48fdd9dSEdgar E. Iglesias return ret; 46649ab747fSPaolo Bonzini } 46749ab747fSPaolo Bonzini 468f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 46949ab747fSPaolo Bonzini { 47049ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 47149ab747fSPaolo Bonzini } 47249ab747fSPaolo Bonzini 473f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 47449ab747fSPaolo Bonzini { 47549ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 47649ab747fSPaolo Bonzini } 47749ab747fSPaolo Bonzini 478f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 47949ab747fSPaolo Bonzini { 48049ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 48149ab747fSPaolo Bonzini } 48249ab747fSPaolo Bonzini 483f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 48449ab747fSPaolo Bonzini { 48549ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 48649ab747fSPaolo Bonzini } 48749ab747fSPaolo Bonzini 48859ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 48959ab136aSRamon Fried { 49059ab136aSRamon Fried desc[1] = 0; 49159ab136aSRamon Fried } 49259ab136aSRamon Fried 493f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 49449ab747fSPaolo Bonzini { 49549ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 49649ab747fSPaolo Bonzini } 49749ab747fSPaolo Bonzini 498f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 49949ab747fSPaolo Bonzini { 50049ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 50149ab747fSPaolo Bonzini desc[1] |= len; 50249ab747fSPaolo Bonzini } 50349ab747fSPaolo Bonzini 504f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 50563af1e0cSPeter Crosthwaite { 50663af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 50763af1e0cSPeter Crosthwaite } 50863af1e0cSPeter Crosthwaite 509f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 51063af1e0cSPeter Crosthwaite { 51163af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 51263af1e0cSPeter Crosthwaite } 51363af1e0cSPeter Crosthwaite 514f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 51563af1e0cSPeter Crosthwaite { 51663af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 51763af1e0cSPeter Crosthwaite } 51863af1e0cSPeter Crosthwaite 519f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 52063af1e0cSPeter Crosthwaite { 52163af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 52263af1e0cSPeter Crosthwaite sar_idx); 523a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 52463af1e0cSPeter Crosthwaite } 52563af1e0cSPeter Crosthwaite 52649ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 5276a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 52849ab747fSPaolo Bonzini 5297ca151c3SSai Pavan Boddu static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 5307ca151c3SSai Pavan Boddu { 5317ca151c3SSai Pavan Boddu uint32_t size; 53287a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { 533c755c943SLuc Michel size = s->regs[R_JUMBO_MAX_LEN]; 5347ca151c3SSai Pavan Boddu if (size > s->jumbo_max_len) { 5357ca151c3SSai Pavan Boddu size = s->jumbo_max_len; 5367ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 5377ca151c3SSai Pavan Boddu " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 5387ca151c3SSai Pavan Boddu } 5397ca151c3SSai Pavan Boddu } else if (tx) { 5407ca151c3SSai Pavan Boddu size = 1518; 5417ca151c3SSai Pavan Boddu } else { 54287a49c3fSLuc Michel size = FIELD_EX32(s->regs[R_NWCFG], 54387a49c3fSLuc Michel NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; 5447ca151c3SSai Pavan Boddu } 5457ca151c3SSai Pavan Boddu return size; 5467ca151c3SSai Pavan Boddu } 5477ca151c3SSai Pavan Boddu 54868dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 54968dbee3bSSai Pavan Boddu { 55068dbee3bSSai Pavan Boddu if (q == 0) { 551c755c943SLuc Michel s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 55268dbee3bSSai Pavan Boddu } else { 553c755c943SLuc Michel s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 554c755c943SLuc Michel ~(s->regs[R_INT_Q1_MASK + q - 1]); 55568dbee3bSSai Pavan Boddu } 55668dbee3bSSai Pavan Boddu } 55768dbee3bSSai Pavan Boddu 55849ab747fSPaolo Bonzini /* 55949ab747fSPaolo Bonzini * gem_init_register_masks: 56049ab747fSPaolo Bonzini * One time initialization. 56149ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 56249ab747fSPaolo Bonzini */ 563448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 56449ab747fSPaolo Bonzini { 5654c70e32fSSai Pavan Boddu unsigned int i; 56649ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 56749ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 568c755c943SLuc Michel s->regs_ro[R_NWCTRL] = 0xFFF80000; 569c755c943SLuc Michel s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 570c755c943SLuc Michel s->regs_ro[R_DMACFG] = 0x8E00F000; 571c755c943SLuc Michel s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 572c755c943SLuc Michel s->regs_ro[R_RXQBASE] = 0x00000003; 573c755c943SLuc Michel s->regs_ro[R_TXQBASE] = 0x00000003; 574c755c943SLuc Michel s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 575c755c943SLuc Michel s->regs_ro[R_ISR] = 0xFFFFFFFF; 576c755c943SLuc Michel s->regs_ro[R_IMR] = 0xFFFFFFFF; 577c755c943SLuc Michel s->regs_ro[R_MODID] = 0xFFFFFFFF; 5784c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 579c755c943SLuc Michel s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 580c755c943SLuc Michel s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 581c755c943SLuc Michel s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 582c755c943SLuc Michel s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 5834c70e32fSSai Pavan Boddu } 58449ab747fSPaolo Bonzini 58549ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 58649ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 587c755c943SLuc Michel s->regs_rtc[R_ISR] = 0xFFFFFFFF; 5884c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 589c755c943SLuc Michel s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 5904c70e32fSSai Pavan Boddu } 59149ab747fSPaolo Bonzini 59249ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 59349ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 594c755c943SLuc Michel s->regs_w1c[R_TXSTATUS] = 0x000001F7; 595c755c943SLuc Michel s->regs_w1c[R_RXSTATUS] = 0x0000000F; 59649ab747fSPaolo Bonzini 59749ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 59849ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 599c755c943SLuc Michel s->regs_wo[R_NWCTRL] = 0x00073E60; 600c755c943SLuc Michel s->regs_wo[R_IER] = 0x07FFFFFF; 601c755c943SLuc Michel s->regs_wo[R_IDR] = 0x07FFFFFF; 6024c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 603c755c943SLuc Michel s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 604c755c943SLuc Michel s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 6054c70e32fSSai Pavan Boddu } 60649ab747fSPaolo Bonzini } 60749ab747fSPaolo Bonzini 60849ab747fSPaolo Bonzini /* 60949ab747fSPaolo Bonzini * phy_update_link: 61049ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 61149ab747fSPaolo Bonzini */ 612448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 61349ab747fSPaolo Bonzini { 61449ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 61549ab747fSPaolo Bonzini 61649ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 61749ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 61849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 61949ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 62049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 62149ab747fSPaolo Bonzini } else { 62249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 62349ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 62449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 62549ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 62649ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 62749ab747fSPaolo Bonzini } 62849ab747fSPaolo Bonzini } 62949ab747fSPaolo Bonzini 630b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 63149ab747fSPaolo Bonzini { 632448f19e2SPeter Crosthwaite CadenceGEMState *s; 63367101725SAlistair Francis int i; 63449ab747fSPaolo Bonzini 63549ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 63649ab747fSPaolo Bonzini 63749ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 638bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { 6393ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 6403ae5725fSPeter Crosthwaite s->can_rx_state = 1; 6413ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 6423ae5725fSPeter Crosthwaite } 643b8c4b67eSPhilippe Mathieu-Daudé return false; 64449ab747fSPaolo Bonzini } 64549ab747fSPaolo Bonzini 64667101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 647dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 648dacc0566SAlistair Francis break; 649dacc0566SAlistair Francis } 650dacc0566SAlistair Francis }; 651dacc0566SAlistair Francis 652dacc0566SAlistair Francis if (i == s->num_priority_queues) { 6538202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 6548202aa53SPeter Crosthwaite s->can_rx_state = 2; 655dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 6568202aa53SPeter Crosthwaite } 657b8c4b67eSPhilippe Mathieu-Daudé return false; 6588202aa53SPeter Crosthwaite } 6598202aa53SPeter Crosthwaite 6603ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 6613ae5725fSPeter Crosthwaite s->can_rx_state = 0; 66267101725SAlistair Francis DB_PRINT("can receive\n"); 6633ae5725fSPeter Crosthwaite } 664b8c4b67eSPhilippe Mathieu-Daudé return true; 66549ab747fSPaolo Bonzini } 66649ab747fSPaolo Bonzini 66749ab747fSPaolo Bonzini /* 66849ab747fSPaolo Bonzini * gem_update_int_status: 66949ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 67049ab747fSPaolo Bonzini */ 671448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 67249ab747fSPaolo Bonzini { 67367101725SAlistair Francis int i; 67467101725SAlistair Francis 675c755c943SLuc Michel qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 676596b6f51SAlistair Francis 67786a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 678c755c943SLuc Michel qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 67949ab747fSPaolo Bonzini } 68049ab747fSPaolo Bonzini } 68149ab747fSPaolo Bonzini 68249ab747fSPaolo Bonzini /* 68349ab747fSPaolo Bonzini * gem_receive_updatestats: 68449ab747fSPaolo Bonzini * Increment receive statistics. 68549ab747fSPaolo Bonzini */ 686448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 68749ab747fSPaolo Bonzini unsigned bytes) 68849ab747fSPaolo Bonzini { 68949ab747fSPaolo Bonzini uint64_t octets; 69049ab747fSPaolo Bonzini 69149ab747fSPaolo Bonzini /* Total octets (bytes) received */ 692c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 693c755c943SLuc Michel s->regs[R_OCTRXHI]; 69449ab747fSPaolo Bonzini octets += bytes; 695c755c943SLuc Michel s->regs[R_OCTRXLO] = octets >> 32; 696c755c943SLuc Michel s->regs[R_OCTRXHI] = octets; 69749ab747fSPaolo Bonzini 69849ab747fSPaolo Bonzini /* Error-free Frames received */ 699c755c943SLuc Michel s->regs[R_RXCNT]++; 70049ab747fSPaolo Bonzini 70149ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 70249ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 703c755c943SLuc Michel s->regs[R_RXBROADCNT]++; 70449ab747fSPaolo Bonzini } 70549ab747fSPaolo Bonzini 70649ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 70749ab747fSPaolo Bonzini if (packet[0] == 0x01) { 708c755c943SLuc Michel s->regs[R_RXMULTICNT]++; 70949ab747fSPaolo Bonzini } 71049ab747fSPaolo Bonzini 71149ab747fSPaolo Bonzini if (bytes <= 64) { 712c755c943SLuc Michel s->regs[R_RX64CNT]++; 71349ab747fSPaolo Bonzini } else if (bytes <= 127) { 714c755c943SLuc Michel s->regs[R_RX65CNT]++; 71549ab747fSPaolo Bonzini } else if (bytes <= 255) { 716c755c943SLuc Michel s->regs[R_RX128CNT]++; 71749ab747fSPaolo Bonzini } else if (bytes <= 511) { 718c755c943SLuc Michel s->regs[R_RX256CNT]++; 71949ab747fSPaolo Bonzini } else if (bytes <= 1023) { 720c755c943SLuc Michel s->regs[R_RX512CNT]++; 72149ab747fSPaolo Bonzini } else if (bytes <= 1518) { 722c755c943SLuc Michel s->regs[R_RX1024CNT]++; 72349ab747fSPaolo Bonzini } else { 724c755c943SLuc Michel s->regs[R_RX1519CNT]++; 72549ab747fSPaolo Bonzini } 72649ab747fSPaolo Bonzini } 72749ab747fSPaolo Bonzini 72849ab747fSPaolo Bonzini /* 72949ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 73049ab747fSPaolo Bonzini */ 73149ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 73249ab747fSPaolo Bonzini { 73349ab747fSPaolo Bonzini unsigned byte; 73449ab747fSPaolo Bonzini 73549ab747fSPaolo Bonzini byte = mac[bit / 8]; 73649ab747fSPaolo Bonzini byte >>= (bit & 0x7); 73749ab747fSPaolo Bonzini byte &= 1; 73849ab747fSPaolo Bonzini 73949ab747fSPaolo Bonzini return byte; 74049ab747fSPaolo Bonzini } 74149ab747fSPaolo Bonzini 74249ab747fSPaolo Bonzini /* 74349ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 74449ab747fSPaolo Bonzini */ 74549ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 74649ab747fSPaolo Bonzini { 74749ab747fSPaolo Bonzini int index_bit, mac_bit; 74849ab747fSPaolo Bonzini unsigned hash_index; 74949ab747fSPaolo Bonzini 75049ab747fSPaolo Bonzini hash_index = 0; 75149ab747fSPaolo Bonzini mac_bit = 5; 75249ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 75349ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 75449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 75549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 75649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 75749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 75849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 75949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 76049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 76149ab747fSPaolo Bonzini mac_bit--; 76249ab747fSPaolo Bonzini } 76349ab747fSPaolo Bonzini 76449ab747fSPaolo Bonzini return hash_index; 76549ab747fSPaolo Bonzini } 76649ab747fSPaolo Bonzini 76749ab747fSPaolo Bonzini /* 76849ab747fSPaolo Bonzini * gem_mac_address_filter: 76949ab747fSPaolo Bonzini * Accept or reject this destination address? 77049ab747fSPaolo Bonzini * Returns: 77149ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 77263af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 77363af1e0cSPeter Crosthwaite * others for various other modes of accept: 77463af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 77563af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 77649ab747fSPaolo Bonzini */ 777448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 77849ab747fSPaolo Bonzini { 77949ab747fSPaolo Bonzini uint8_t *gem_spaddr; 780fbc14a09STong Ho int i, is_mc; 78149ab747fSPaolo Bonzini 78249ab747fSPaolo Bonzini /* Promiscuous mode? */ 78387a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { 78463af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 78549ab747fSPaolo Bonzini } 78649ab747fSPaolo Bonzini 78749ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 78849ab747fSPaolo Bonzini /* Reject broadcast packets? */ 78987a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { 79049ab747fSPaolo Bonzini return GEM_RX_REJECT; 79149ab747fSPaolo Bonzini } 79263af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 79349ab747fSPaolo Bonzini } 79449ab747fSPaolo Bonzini 79549ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 796fbc14a09STong Ho is_mc = is_multicast_ether_addr(packet); 79787a49c3fSLuc Michel if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || 79887a49c3fSLuc Michel (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { 799fbc14a09STong Ho uint64_t buckets; 80049ab747fSPaolo Bonzini unsigned hash_index; 80149ab747fSPaolo Bonzini 80249ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 803c755c943SLuc Michel buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 804fbc14a09STong Ho if ((buckets >> hash_index) & 1) { 805fbc14a09STong Ho return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 806fbc14a09STong Ho : GEM_RX_UNICAST_HASH_ACCEPT; 80749ab747fSPaolo Bonzini } 80849ab747fSPaolo Bonzini } 80949ab747fSPaolo Bonzini 81049ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 811c755c943SLuc Michel gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 81263af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 81364eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 81463af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 81549ab747fSPaolo Bonzini } 81649ab747fSPaolo Bonzini } 81749ab747fSPaolo Bonzini 81849ab747fSPaolo Bonzini /* No address match; reject the packet */ 81949ab747fSPaolo Bonzini return GEM_RX_REJECT; 82049ab747fSPaolo Bonzini } 82149ab747fSPaolo Bonzini 822e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 823e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 824e8e49943SAlistair Francis unsigned rxbufsize) 825e8e49943SAlistair Francis { 826e8e49943SAlistair Francis uint32_t reg; 827e8e49943SAlistair Francis bool matched, mismatched; 828e8e49943SAlistair Francis int i, j; 829e8e49943SAlistair Francis 830e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 831c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 832e8e49943SAlistair Francis matched = false; 833e8e49943SAlistair Francis mismatched = false; 834e8e49943SAlistair Francis 835e8e49943SAlistair Francis /* Screening is based on UDP Port */ 836b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { 837e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 838b46b526cSLuc Michel if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { 839e8e49943SAlistair Francis matched = true; 840e8e49943SAlistair Francis } else { 841e8e49943SAlistair Francis mismatched = true; 842e8e49943SAlistair Francis } 843e8e49943SAlistair Francis } 844e8e49943SAlistair Francis 845e8e49943SAlistair Francis /* Screening is based on DS/TC */ 846b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { 847e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 848b46b526cSLuc Michel if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { 849e8e49943SAlistair Francis matched = true; 850e8e49943SAlistair Francis } else { 851e8e49943SAlistair Francis mismatched = true; 852e8e49943SAlistair Francis } 853e8e49943SAlistair Francis } 854e8e49943SAlistair Francis 855e8e49943SAlistair Francis if (matched && !mismatched) { 856b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); 857e8e49943SAlistair Francis } 858e8e49943SAlistair Francis } 859e8e49943SAlistair Francis 860e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 861c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 862e8e49943SAlistair Francis matched = false; 863e8e49943SAlistair Francis mismatched = false; 864e8e49943SAlistair Francis 865b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { 866e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 867b46b526cSLuc Michel int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, 868b46b526cSLuc Michel ETHERTYPE_REG_INDEX); 869e8e49943SAlistair Francis 870e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 871e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 872e8e49943SAlistair Francis "register index: %d\n", et_idx); 873e8e49943SAlistair Francis } 874c755c943SLuc Michel if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 875e8e49943SAlistair Francis et_idx]) { 876e8e49943SAlistair Francis matched = true; 877e8e49943SAlistair Francis } else { 878e8e49943SAlistair Francis mismatched = true; 879e8e49943SAlistair Francis } 880e8e49943SAlistair Francis } 881e8e49943SAlistair Francis 882e8e49943SAlistair Francis /* Compare A, B, C */ 883e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 884b46b526cSLuc Michel uint32_t cr0, cr1, mask, compare; 885e8e49943SAlistair Francis uint16_t rx_cmp; 886e8e49943SAlistair Francis int offset; 887b46b526cSLuc Michel int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, 888b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); 889e8e49943SAlistair Francis 890b46b526cSLuc Michel if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, 891b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { 892e8e49943SAlistair Francis continue; 893e8e49943SAlistair Francis } 894b46b526cSLuc Michel 895e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 896e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 897e8e49943SAlistair Francis "register index: %d\n", cr_idx); 898e8e49943SAlistair Francis } 899e8e49943SAlistair Francis 900c755c943SLuc Michel cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 901b46b526cSLuc Michel cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; 902b46b526cSLuc Michel offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); 903e8e49943SAlistair Francis 904b46b526cSLuc Michel switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { 905e8e49943SAlistair Francis case 3: /* Skip UDP header */ 906e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 907e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 908e8e49943SAlistair Francis offset += 8; 909e8e49943SAlistair Francis /* Fallthrough */ 910e8e49943SAlistair Francis case 2: /* skip the IP header */ 911e8e49943SAlistair Francis offset += 20; 912e8e49943SAlistair Francis /* Fallthrough */ 913e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 914e8e49943SAlistair Francis offset += 14; 915e8e49943SAlistair Francis break; 916e8e49943SAlistair Francis case 0: 917e8e49943SAlistair Francis /* Offset from start of frame */ 918e8e49943SAlistair Francis break; 919e8e49943SAlistair Francis } 920e8e49943SAlistair Francis 921e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 922b46b526cSLuc Michel mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); 923b46b526cSLuc Michel compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); 924e8e49943SAlistair Francis 925b46b526cSLuc Michel if ((rx_cmp & mask) == (compare & mask)) { 926e8e49943SAlistair Francis matched = true; 927e8e49943SAlistair Francis } else { 928e8e49943SAlistair Francis mismatched = true; 929e8e49943SAlistair Francis } 930e8e49943SAlistair Francis } 931e8e49943SAlistair Francis 932e8e49943SAlistair Francis if (matched && !mismatched) { 933b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); 934e8e49943SAlistair Francis } 935e8e49943SAlistair Francis } 936e8e49943SAlistair Francis 937e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 938e8e49943SAlistair Francis return 0; 939e8e49943SAlistair Francis } 940e8e49943SAlistair Francis 94196ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 94296ea126aSSai Pavan Boddu { 94396ea126aSSai Pavan Boddu uint32_t base_addr = 0; 94496ea126aSSai Pavan Boddu 94596ea126aSSai Pavan Boddu switch (q) { 94696ea126aSSai Pavan Boddu case 0: 947c755c943SLuc Michel base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 94896ea126aSSai Pavan Boddu break; 94996ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 950c755c943SLuc Michel base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 951c755c943SLuc Michel R_RECEIVE_Q1_PTR) + q - 1]; 95296ea126aSSai Pavan Boddu break; 95396ea126aSSai Pavan Boddu default: 95496ea126aSSai Pavan Boddu g_assert_not_reached(); 95596ea126aSSai Pavan Boddu }; 95696ea126aSSai Pavan Boddu 95796ea126aSSai Pavan Boddu return base_addr; 95896ea126aSSai Pavan Boddu } 95996ea126aSSai Pavan Boddu 96096ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 96196ea126aSSai Pavan Boddu { 96296ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 96396ea126aSSai Pavan Boddu } 96496ea126aSSai Pavan Boddu 96596ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 96696ea126aSSai Pavan Boddu { 96796ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 96896ea126aSSai Pavan Boddu } 96996ea126aSSai Pavan Boddu 970357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 971357aa013SEdgar E. Iglesias { 972357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 973357aa013SEdgar E. Iglesias 97401f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 975c755c943SLuc Michel desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 976357aa013SEdgar E. Iglesias } 977357aa013SEdgar E. Iglesias desc_addr <<= 32; 978357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 979357aa013SEdgar E. Iglesias return desc_addr; 980357aa013SEdgar E. Iglesias } 981357aa013SEdgar E. Iglesias 982357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 983357aa013SEdgar E. Iglesias { 984357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 985357aa013SEdgar E. Iglesias } 986357aa013SEdgar E. Iglesias 987357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 988357aa013SEdgar E. Iglesias { 989357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 990357aa013SEdgar E. Iglesias } 991357aa013SEdgar E. Iglesias 99267101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 99306c2fe95SPeter Crosthwaite { 994357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 995357aa013SEdgar E. Iglesias 996357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 997357aa013SEdgar E. Iglesias 99806c2fe95SPeter Crosthwaite /* read current descriptor */ 999357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1000b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1001e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 100206c2fe95SPeter Crosthwaite 100306c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 100467101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 1005357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 1006466da857SLuc Michel s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK; 100768dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXUSED); 100806c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 100906c2fe95SPeter Crosthwaite gem_update_int_status(s); 101006c2fe95SPeter Crosthwaite } 101106c2fe95SPeter Crosthwaite } 101206c2fe95SPeter Crosthwaite 101349ab747fSPaolo Bonzini /* 101449ab747fSPaolo Bonzini * gem_receive: 101549ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 101649ab747fSPaolo Bonzini */ 101749ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 101849ab747fSPaolo Bonzini { 101924d62fd5SSai Pavan Boddu CadenceGEMState *s = qemu_get_nic_opaque(nc); 102049ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 102149ab747fSPaolo Bonzini unsigned rxbuf_offset; 102249ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 10233b2c97f9SEdgar E. Iglesias bool first_desc = true; 102463af1e0cSPeter Crosthwaite int maf; 10252bf57f73SAlistair Francis int q = 0; 102649ab747fSPaolo Bonzini 102749ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 102863af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 102963af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 10302431f4f1SMichael Tokarev return size; /* no, drop silently b/c it's not an error */ 103149ab747fSPaolo Bonzini } 103249ab747fSPaolo Bonzini 103349ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 103487a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { 103549ab747fSPaolo Bonzini unsigned type_len; 103649ab747fSPaolo Bonzini 103749ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 103849ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 103949ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 104049ab747fSPaolo Bonzini if (type_len < 0x600) { 104149ab747fSPaolo Bonzini if (size < type_len) { 104249ab747fSPaolo Bonzini /* discard */ 104349ab747fSPaolo Bonzini return -1; 104449ab747fSPaolo Bonzini } 104549ab747fSPaolo Bonzini } 104649ab747fSPaolo Bonzini } 104749ab747fSPaolo Bonzini 104849ab747fSPaolo Bonzini /* 104949ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 105049ab747fSPaolo Bonzini */ 105187a49c3fSLuc Michel rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); 105249ab747fSPaolo Bonzini 105349ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 105449ab747fSPaolo Bonzini * buffers needed to hold this packet. 105549ab747fSPaolo Bonzini */ 105601f9175dSLuc Michel rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); 105701f9175dSLuc Michel rxbufsize *= GEM_DMACFG_RBUFSZ_MUL; 105801f9175dSLuc Michel 105949ab747fSPaolo Bonzini bytes_to_copy = size; 106049ab747fSPaolo Bonzini 1061f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 1062f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 1063f265ae8cSAlistair Francis */ 1064f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1065f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1066f265ae8cSAlistair Francis } 1067f265ae8cSAlistair Francis 1068191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 1069191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 1070191946c5SPeter Crosthwaite * not FCS stripping 1071191946c5SPeter Crosthwaite */ 1072191946c5SPeter Crosthwaite if (size < 60) { 1073191946c5SPeter Crosthwaite size = 60; 1074191946c5SPeter Crosthwaite } 1075191946c5SPeter Crosthwaite 107649ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 107787a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { 107849ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 107949ab747fSPaolo Bonzini } else { 108049ab747fSPaolo Bonzini unsigned crc_val; 108149ab747fSPaolo Bonzini 108224d62fd5SSai Pavan Boddu if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 108324d62fd5SSai Pavan Boddu size = MAX_FRAME_SIZE - sizeof(crc_val); 1084244381ecSPrasad J Pandit } 1085244381ecSPrasad J Pandit bytes_to_copy = size; 108649ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 10873048ed6aSPeter Crosthwaite * We must try and calculate one. 108849ab747fSPaolo Bonzini */ 108949ab747fSPaolo Bonzini 109024d62fd5SSai Pavan Boddu memcpy(s->rx_packet, buf, size); 109124d62fd5SSai Pavan Boddu memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 109224d62fd5SSai Pavan Boddu rxbuf_ptr = s->rx_packet; 109324d62fd5SSai Pavan Boddu crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 109424d62fd5SSai Pavan Boddu memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 109549ab747fSPaolo Bonzini 109649ab747fSPaolo Bonzini bytes_to_copy += 4; 109749ab747fSPaolo Bonzini size += 4; 109849ab747fSPaolo Bonzini } 109949ab747fSPaolo Bonzini 11006fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 110149ab747fSPaolo Bonzini 1102b12227afSStefan Weil /* Find which queue we are targeting */ 1103e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1104e8e49943SAlistair Francis 11057ca151c3SSai Pavan Boddu if (size > gem_get_max_buf_len(s, false)) { 11067ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 11077ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 11087ca151c3SSai Pavan Boddu return -1; 11097ca151c3SSai Pavan Boddu } 11107ca151c3SSai Pavan Boddu 11117cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1112357aa013SEdgar E. Iglesias hwaddr desc_addr; 1113357aa013SEdgar E. Iglesias 111406c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 111506c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 111649ab747fSPaolo Bonzini return -1; 111749ab747fSPaolo Bonzini } 111849ab747fSPaolo Bonzini 11196fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1120dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1121dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 112249ab747fSPaolo Bonzini 112349ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 112484aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 11252bf57f73SAlistair Francis rxbuf_offset, 112684aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1127e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 112849ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 112930570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 11303b2c97f9SEdgar E. Iglesias 113159ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 113259ab136aSRamon Fried 11333b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 11343b2c97f9SEdgar E. Iglesias if (first_desc) { 11352bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 11363b2c97f9SEdgar E. Iglesias first_desc = false; 11373b2c97f9SEdgar E. Iglesias } 11383b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 11392bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 11402bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 11413b2c97f9SEdgar E. Iglesias } 11422bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 114363af1e0cSPeter Crosthwaite 114463af1e0cSPeter Crosthwaite switch (maf) { 114563af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 114663af1e0cSPeter Crosthwaite break; 114763af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 11482bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 114963af1e0cSPeter Crosthwaite break; 115063af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 11512bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 115263af1e0cSPeter Crosthwaite break; 115363af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 11542bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 115563af1e0cSPeter Crosthwaite break; 115663af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 115763af1e0cSPeter Crosthwaite abort(); 115863af1e0cSPeter Crosthwaite default: /* SAR */ 11592bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 116063af1e0cSPeter Crosthwaite } 116163af1e0cSPeter Crosthwaite 11623b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1163357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1164b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1165b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1166e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 11673b2c97f9SEdgar E. Iglesias 116849ab747fSPaolo Bonzini /* Next descriptor */ 11692bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 117049ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 117196ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 117249ab747fSPaolo Bonzini } else { 117349ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1174e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 117549ab747fSPaolo Bonzini } 117667101725SAlistair Francis 117767101725SAlistair Francis gem_get_rx_desc(s, q); 11787cfd65e4SPeter Crosthwaite } 117949ab747fSPaolo Bonzini 118049ab747fSPaolo Bonzini /* Count it */ 118149ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 118249ab747fSPaolo Bonzini 1183466da857SLuc Michel s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK; 118468dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXCMPL); 118549ab747fSPaolo Bonzini 118649ab747fSPaolo Bonzini /* Handle interrupt consequences */ 118749ab747fSPaolo Bonzini gem_update_int_status(s); 118849ab747fSPaolo Bonzini 118949ab747fSPaolo Bonzini return size; 119049ab747fSPaolo Bonzini } 119149ab747fSPaolo Bonzini 119249ab747fSPaolo Bonzini /* 119349ab747fSPaolo Bonzini * gem_transmit_updatestats: 119449ab747fSPaolo Bonzini * Increment transmit statistics. 119549ab747fSPaolo Bonzini */ 1196448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 119749ab747fSPaolo Bonzini unsigned bytes) 119849ab747fSPaolo Bonzini { 119949ab747fSPaolo Bonzini uint64_t octets; 120049ab747fSPaolo Bonzini 120149ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 1202c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1203c755c943SLuc Michel s->regs[R_OCTTXHI]; 120449ab747fSPaolo Bonzini octets += bytes; 1205c755c943SLuc Michel s->regs[R_OCTTXLO] = octets >> 32; 1206c755c943SLuc Michel s->regs[R_OCTTXHI] = octets; 120749ab747fSPaolo Bonzini 120849ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 1209c755c943SLuc Michel s->regs[R_TXCNT]++; 121049ab747fSPaolo Bonzini 121149ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 121249ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 1213c755c943SLuc Michel s->regs[R_TXBCNT]++; 121449ab747fSPaolo Bonzini } 121549ab747fSPaolo Bonzini 121649ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 121749ab747fSPaolo Bonzini if (packet[0] == 0x01) { 1218c755c943SLuc Michel s->regs[R_TXMCNT]++; 121949ab747fSPaolo Bonzini } 122049ab747fSPaolo Bonzini 122149ab747fSPaolo Bonzini if (bytes <= 64) { 1222c755c943SLuc Michel s->regs[R_TX64CNT]++; 122349ab747fSPaolo Bonzini } else if (bytes <= 127) { 1224c755c943SLuc Michel s->regs[R_TX65CNT]++; 122549ab747fSPaolo Bonzini } else if (bytes <= 255) { 1226c755c943SLuc Michel s->regs[R_TX128CNT]++; 122749ab747fSPaolo Bonzini } else if (bytes <= 511) { 1228c755c943SLuc Michel s->regs[R_TX256CNT]++; 122949ab747fSPaolo Bonzini } else if (bytes <= 1023) { 1230c755c943SLuc Michel s->regs[R_TX512CNT]++; 123149ab747fSPaolo Bonzini } else if (bytes <= 1518) { 1232c755c943SLuc Michel s->regs[R_TX1024CNT]++; 123349ab747fSPaolo Bonzini } else { 1234c755c943SLuc Michel s->regs[R_TX1519CNT]++; 123549ab747fSPaolo Bonzini } 123649ab747fSPaolo Bonzini } 123749ab747fSPaolo Bonzini 123849ab747fSPaolo Bonzini /* 123949ab747fSPaolo Bonzini * gem_transmit: 124049ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 124149ab747fSPaolo Bonzini */ 1242448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 124349ab747fSPaolo Bonzini { 12448568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 124549ab747fSPaolo Bonzini hwaddr packet_desc_addr; 124649ab747fSPaolo Bonzini uint8_t *p; 124749ab747fSPaolo Bonzini unsigned total_bytes; 12482bf57f73SAlistair Francis int q = 0; 124949ab747fSPaolo Bonzini 125049ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1251bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 125249ab747fSPaolo Bonzini return; 125349ab747fSPaolo Bonzini } 125449ab747fSPaolo Bonzini 125549ab747fSPaolo Bonzini DB_PRINT("\n"); 125649ab747fSPaolo Bonzini 12573048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 125849ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 125949ab747fSPaolo Bonzini * one contiguous buffer first. 126049ab747fSPaolo Bonzini */ 126124d62fd5SSai Pavan Boddu p = s->tx_packet; 126249ab747fSPaolo Bonzini total_bytes = 0; 126349ab747fSPaolo Bonzini 126467101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 126549ab747fSPaolo Bonzini /* read current descriptor */ 1266357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1267fa15286aSPeter Crosthwaite 1268fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 126984aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1270b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1271e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 127249ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 127349ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 127449ab747fSPaolo Bonzini 127549ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1276bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 127749ab747fSPaolo Bonzini return; 127849ab747fSPaolo Bonzini } 127967101725SAlistair Francis print_gem_tx_desc(desc, q); 128049ab747fSPaolo Bonzini 128149ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 128249ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 128349ab747fSPaolo Bonzini */ 1284e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 128549ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 12866fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 12876fe7661dSSai Pavan Boddu packet_desc_addr); 128849ab747fSPaolo Bonzini break; 128949ab747fSPaolo Bonzini } 129049ab747fSPaolo Bonzini 12917ca151c3SSai Pavan Boddu if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 129224d62fd5SSai Pavan Boddu (p - s->tx_packet)) { 12937ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 12947ca151c3SSai Pavan Boddu HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1295dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 12967ca151c3SSai Pavan Boddu gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 12977ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1298d7f05365SMichael S. Tsirkin break; 1299d7f05365SMichael S. Tsirkin } 1300d7f05365SMichael S. Tsirkin 130177524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 130277524d11SAlistair Francis * contig buffer. 130349ab747fSPaolo Bonzini */ 130484aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 130584aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 130684aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 130749ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 130849ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 130949ab747fSPaolo Bonzini 131049ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 131149ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 13128568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1313357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 13146ab57a6bSPeter Crosthwaite 131549ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 131649ab747fSPaolo Bonzini * the processor. 131749ab747fSPaolo Bonzini */ 1318357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1319b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 13206ab57a6bSPeter Crosthwaite sizeof(desc_first)); 13216ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1322357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1323b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 13246ab57a6bSPeter Crosthwaite sizeof(desc_first)); 13253048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 132649ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 132796ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 132849ab747fSPaolo Bonzini } else { 1329e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1330e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 133149ab747fSPaolo Bonzini } 13322bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 133349ab747fSPaolo Bonzini 1334466da857SLuc Michel s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK; 133568dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_TXCMPL); 133667101725SAlistair Francis 133749ab747fSPaolo Bonzini /* Handle interrupt consequences */ 133849ab747fSPaolo Bonzini gem_update_int_status(s); 133949ab747fSPaolo Bonzini 134049ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 134101f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) { 1342f5746335SBin Meng net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 134349ab747fSPaolo Bonzini } 134449ab747fSPaolo Bonzini 134549ab747fSPaolo Bonzini /* Update MAC statistics */ 134624d62fd5SSai Pavan Boddu gem_transmit_updatestats(s, s->tx_packet, total_bytes); 134749ab747fSPaolo Bonzini 134849ab747fSPaolo Bonzini /* Send the packet somewhere */ 1349bd8a922dSLuc Michel if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, 1350bd8a922dSLuc Michel LOOPBACK_LOCAL)) { 1351e73adfbeSAlexander Bulekov qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 135277524d11SAlistair Francis total_bytes); 135349ab747fSPaolo Bonzini } else { 135424d62fd5SSai Pavan Boddu qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 135549ab747fSPaolo Bonzini total_bytes); 135649ab747fSPaolo Bonzini } 135749ab747fSPaolo Bonzini 135849ab747fSPaolo Bonzini /* Prepare for next packet */ 135924d62fd5SSai Pavan Boddu p = s->tx_packet; 136049ab747fSPaolo Bonzini total_bytes = 0; 136149ab747fSPaolo Bonzini } 136249ab747fSPaolo Bonzini 136349ab747fSPaolo Bonzini /* read next descriptor */ 136449ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 136501f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 1366c755c943SLuc Michel packet_desc_addr = s->regs[R_TBQPH]; 1367f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1368f1e7cb13SRamon Fried } else { 1369f1e7cb13SRamon Fried packet_desc_addr = 0; 1370f1e7cb13SRamon Fried } 137196ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 137249ab747fSPaolo Bonzini } else { 1373e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 137449ab747fSPaolo Bonzini } 1375fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 137684aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1377b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1378e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 137949ab747fSPaolo Bonzini } 138049ab747fSPaolo Bonzini 138149ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 1382466da857SLuc Michel s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK; 138368dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 138468dbee3bSSai Pavan Boddu if (q == 0) { 138568dbee3bSSai Pavan Boddu gem_set_isr(s, 0, GEM_INT_TXUSED); 138668dbee3bSSai Pavan Boddu } 138749ab747fSPaolo Bonzini gem_update_int_status(s); 138849ab747fSPaolo Bonzini } 138949ab747fSPaolo Bonzini } 139067101725SAlistair Francis } 139149ab747fSPaolo Bonzini 1392448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 139349ab747fSPaolo Bonzini { 139449ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 139549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 139649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 139749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 139849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 139949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 140049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 140149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 140249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 140349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 140449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 140549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 140649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 140749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 14087777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 140949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 141049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 141149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 141249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 141349ab747fSPaolo Bonzini 141449ab747fSPaolo Bonzini phy_update_link(s); 141549ab747fSPaolo Bonzini } 141649ab747fSPaolo Bonzini 141749ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 141849ab747fSPaolo Bonzini { 141964eb9301SPeter Crosthwaite int i; 1420448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1421afb4c51fSSebastian Huber const uint8_t *a; 1422726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 142349ab747fSPaolo Bonzini 142449ab747fSPaolo Bonzini DB_PRINT("\n"); 142549ab747fSPaolo Bonzini 142649ab747fSPaolo Bonzini /* Set post reset register values */ 142749ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 1428c755c943SLuc Michel s->regs[R_NWCFG] = 0x00080000; 1429c755c943SLuc Michel s->regs[R_NWSTATUS] = 0x00000006; 1430c755c943SLuc Michel s->regs[R_DMACFG] = 0x00020784; 1431c755c943SLuc Michel s->regs[R_IMR] = 0x07ffffff; 1432c755c943SLuc Michel s->regs[R_TXPAUSE] = 0x0000ffff; 1433c755c943SLuc Michel s->regs[R_TXPARTIALSF] = 0x000003ff; 1434c755c943SLuc Michel s->regs[R_RXPARTIALSF] = 0x000003ff; 1435c755c943SLuc Michel s->regs[R_MODID] = s->revision; 1436c755c943SLuc Michel s->regs[R_DESCONF] = 0x02D00111; 1437c755c943SLuc Michel s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1438c755c943SLuc Michel s->regs[R_DESCONF5] = 0x002f2045; 1439c755c943SLuc Michel s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; 1440c755c943SLuc Michel s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1441c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1442726a2a95SEdgar E. Iglesias 1443726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1444726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1445c755c943SLuc Michel s->regs[R_DESCONF6] |= queues_mask; 1446726a2a95SEdgar E. Iglesias } 144749ab747fSPaolo Bonzini 1448afb4c51fSSebastian Huber /* Set MAC address */ 1449afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1450c755c943SLuc Michel s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1451c755c943SLuc Michel s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1452afb4c51fSSebastian Huber 145364eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 145464eb9301SPeter Crosthwaite s->sar_active[i] = false; 145564eb9301SPeter Crosthwaite } 145664eb9301SPeter Crosthwaite 145749ab747fSPaolo Bonzini gem_phy_reset(s); 145849ab747fSPaolo Bonzini 145949ab747fSPaolo Bonzini gem_update_int_status(s); 146049ab747fSPaolo Bonzini } 146149ab747fSPaolo Bonzini 1462448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 146349ab747fSPaolo Bonzini { 146449ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 146549ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 146649ab747fSPaolo Bonzini } 146749ab747fSPaolo Bonzini 1468448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 146949ab747fSPaolo Bonzini { 147049ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 147149ab747fSPaolo Bonzini 147249ab747fSPaolo Bonzini switch (reg_num) { 147349ab747fSPaolo Bonzini case PHY_REG_CONTROL: 147449ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 147549ab747fSPaolo Bonzini /* Phy reset */ 147649ab747fSPaolo Bonzini gem_phy_reset(s); 147749ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 147849ab747fSPaolo Bonzini s->phy_loop = 0; 147949ab747fSPaolo Bonzini } 148049ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 148149ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 14826623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 148349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 148449ab747fSPaolo Bonzini } 148549ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 148649ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 148749ab747fSPaolo Bonzini s->phy_loop = 1; 148849ab747fSPaolo Bonzini } else { 148949ab747fSPaolo Bonzini s->phy_loop = 0; 149049ab747fSPaolo Bonzini } 149149ab747fSPaolo Bonzini break; 149249ab747fSPaolo Bonzini } 149349ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 149449ab747fSPaolo Bonzini } 149549ab747fSPaolo Bonzini 149649ab747fSPaolo Bonzini /* 149749ab747fSPaolo Bonzini * gem_read32: 149849ab747fSPaolo Bonzini * Read a GEM register. 149949ab747fSPaolo Bonzini */ 150049ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 150149ab747fSPaolo Bonzini { 1502448f19e2SPeter Crosthwaite CadenceGEMState *s; 150349ab747fSPaolo Bonzini uint32_t retval; 15043d558330SMarkus Armbruster s = opaque; 150549ab747fSPaolo Bonzini 150649ab747fSPaolo Bonzini offset >>= 2; 150749ab747fSPaolo Bonzini retval = s->regs[offset]; 150849ab747fSPaolo Bonzini 150949ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 151049ab747fSPaolo Bonzini 151149ab747fSPaolo Bonzini switch (offset) { 1512c755c943SLuc Michel case R_ISR: 151367101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1514596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 151549ab747fSPaolo Bonzini break; 1516c755c943SLuc Michel case R_PHYMNTNC: 151749ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 151849ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 151949ab747fSPaolo Bonzini 152049ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1521dfc38879SBin Meng if (phy_addr == s->phy_addr) { 152249ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 152349ab747fSPaolo Bonzini retval &= 0xFFFF0000; 152449ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 152549ab747fSPaolo Bonzini } else { 152649ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 152749ab747fSPaolo Bonzini } 152849ab747fSPaolo Bonzini } 152949ab747fSPaolo Bonzini break; 153049ab747fSPaolo Bonzini } 153149ab747fSPaolo Bonzini 153249ab747fSPaolo Bonzini /* Squash read to clear bits */ 153349ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 153449ab747fSPaolo Bonzini 153549ab747fSPaolo Bonzini /* Do not provide write only bits */ 153649ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 153749ab747fSPaolo Bonzini 153849ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 153967101725SAlistair Francis gem_update_int_status(s); 154049ab747fSPaolo Bonzini return retval; 154149ab747fSPaolo Bonzini } 154249ab747fSPaolo Bonzini 154349ab747fSPaolo Bonzini /* 154449ab747fSPaolo Bonzini * gem_write32: 154549ab747fSPaolo Bonzini * Write a GEM register. 154649ab747fSPaolo Bonzini */ 154749ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 154849ab747fSPaolo Bonzini unsigned size) 154949ab747fSPaolo Bonzini { 1550448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 155149ab747fSPaolo Bonzini uint32_t readonly; 155267101725SAlistair Francis int i; 155349ab747fSPaolo Bonzini 155449ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 155549ab747fSPaolo Bonzini offset >>= 2; 155649ab747fSPaolo Bonzini 155749ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 155849ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1559e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1560e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 156149ab747fSPaolo Bonzini 156249ab747fSPaolo Bonzini /* Copy register write to backing store */ 1563e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1564e2314fdaSPeter Crosthwaite 1565e2314fdaSPeter Crosthwaite /* do w1c */ 1566e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 156749ab747fSPaolo Bonzini 156849ab747fSPaolo Bonzini /* Handle register write side effects */ 156949ab747fSPaolo Bonzini switch (offset) { 1570c755c943SLuc Michel case R_NWCTRL: 1571bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { 157267101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 157367101725SAlistair Francis gem_get_rx_desc(s, i); 157467101725SAlistair Francis } 157506c2fe95SPeter Crosthwaite } 1576bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { 157749ab747fSPaolo Bonzini gem_transmit(s); 157849ab747fSPaolo Bonzini } 1579bd8a922dSLuc Michel if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { 158049ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 158167101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 158296ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 158367101725SAlistair Francis } 158449ab747fSPaolo Bonzini } 15858202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 158649ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 158749ab747fSPaolo Bonzini } 158849ab747fSPaolo Bonzini break; 158949ab747fSPaolo Bonzini 1590c755c943SLuc Michel case R_TXSTATUS: 159149ab747fSPaolo Bonzini gem_update_int_status(s); 159249ab747fSPaolo Bonzini break; 1593c755c943SLuc Michel case R_RXQBASE: 15942bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 159549ab747fSPaolo Bonzini break; 1596c755c943SLuc Michel case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1597c755c943SLuc Michel s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 159867101725SAlistair Francis break; 1599c755c943SLuc Michel case R_TXQBASE: 16002bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 160149ab747fSPaolo Bonzini break; 1602c755c943SLuc Michel case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1603c755c943SLuc Michel s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 160467101725SAlistair Francis break; 1605c755c943SLuc Michel case R_RXSTATUS: 160649ab747fSPaolo Bonzini gem_update_int_status(s); 160749ab747fSPaolo Bonzini break; 1608c755c943SLuc Michel case R_IER: 1609c755c943SLuc Michel s->regs[R_IMR] &= ~val; 161049ab747fSPaolo Bonzini gem_update_int_status(s); 161149ab747fSPaolo Bonzini break; 1612c755c943SLuc Michel case R_JUMBO_MAX_LEN: 1613c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 16147ca151c3SSai Pavan Boddu break; 1615c755c943SLuc Michel case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1616c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 161767101725SAlistair Francis gem_update_int_status(s); 161867101725SAlistair Francis break; 1619c755c943SLuc Michel case R_IDR: 1620c755c943SLuc Michel s->regs[R_IMR] |= val; 162149ab747fSPaolo Bonzini gem_update_int_status(s); 162249ab747fSPaolo Bonzini break; 1623c755c943SLuc Michel case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1624c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 162567101725SAlistair Francis gem_update_int_status(s); 162667101725SAlistair Francis break; 1627c755c943SLuc Michel case R_SPADDR1LO: 1628c755c943SLuc Michel case R_SPADDR2LO: 1629c755c943SLuc Michel case R_SPADDR3LO: 1630c755c943SLuc Michel case R_SPADDR4LO: 1631c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 163264eb9301SPeter Crosthwaite break; 1633c755c943SLuc Michel case R_SPADDR1HI: 1634c755c943SLuc Michel case R_SPADDR2HI: 1635c755c943SLuc Michel case R_SPADDR3HI: 1636c755c943SLuc Michel case R_SPADDR4HI: 1637c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 163864eb9301SPeter Crosthwaite break; 1639c755c943SLuc Michel case R_PHYMNTNC: 164049ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 164149ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 164249ab747fSPaolo Bonzini 164349ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1644dfc38879SBin Meng if (phy_addr == s->phy_addr) { 164549ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 164649ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 164749ab747fSPaolo Bonzini } 164849ab747fSPaolo Bonzini } 164949ab747fSPaolo Bonzini break; 165049ab747fSPaolo Bonzini } 165149ab747fSPaolo Bonzini 165249ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 165349ab747fSPaolo Bonzini } 165449ab747fSPaolo Bonzini 165549ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 165649ab747fSPaolo Bonzini .read = gem_read, 165749ab747fSPaolo Bonzini .write = gem_write, 165849ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 165949ab747fSPaolo Bonzini }; 166049ab747fSPaolo Bonzini 166149ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 166249ab747fSPaolo Bonzini { 166367101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 166467101725SAlistair Francis 166549ab747fSPaolo Bonzini DB_PRINT("\n"); 166667101725SAlistair Francis phy_update_link(s); 166767101725SAlistair Francis gem_update_int_status(s); 166849ab747fSPaolo Bonzini } 166949ab747fSPaolo Bonzini 167049ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1671f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 167249ab747fSPaolo Bonzini .size = sizeof(NICState), 167349ab747fSPaolo Bonzini .can_receive = gem_can_receive, 167449ab747fSPaolo Bonzini .receive = gem_receive, 167549ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 167649ab747fSPaolo Bonzini }; 167749ab747fSPaolo Bonzini 1678bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 167949ab747fSPaolo Bonzini { 1680448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 168167101725SAlistair Francis int i; 168249ab747fSPaolo Bonzini 168384aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 168484aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 168584aec8efSEdgar E. Iglesias 16862bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 16872bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 16882bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 16892bf57f73SAlistair Francis s->num_priority_queues); 16902bf57f73SAlistair Francis return; 1691e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1692e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1693e8e49943SAlistair Francis s->num_type1_screeners); 1694e8e49943SAlistair Francis return; 1695e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1696e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1697e8e49943SAlistair Francis s->num_type2_screeners); 1698e8e49943SAlistair Francis return; 16992bf57f73SAlistair Francis } 17002bf57f73SAlistair Francis 170167101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 170267101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 170367101725SAlistair Francis } 1704bcb39a65SAlistair Francis 1705bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1706bcb39a65SAlistair Francis 1707bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1708bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 17097ca151c3SSai Pavan Boddu 17107ca151c3SSai Pavan Boddu if (s->jumbo_max_len > MAX_FRAME_SIZE) { 17117ca151c3SSai Pavan Boddu error_setg(errp, "jumbo-max-len is greater than %d", 17127ca151c3SSai Pavan Boddu MAX_FRAME_SIZE); 17137ca151c3SSai Pavan Boddu return; 17147ca151c3SSai Pavan Boddu } 1715bcb39a65SAlistair Francis } 1716bcb39a65SAlistair Francis 1717bcb39a65SAlistair Francis static void gem_init(Object *obj) 1718bcb39a65SAlistair Francis { 1719bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1720bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1721bcb39a65SAlistair Francis 172249ab747fSPaolo Bonzini DB_PRINT("\n"); 172349ab747fSPaolo Bonzini 172449ab747fSPaolo Bonzini gem_init_register_masks(s); 1725eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1726eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 172749ab747fSPaolo Bonzini 1728bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 172949ab747fSPaolo Bonzini } 173049ab747fSPaolo Bonzini 173149ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 173249ab747fSPaolo Bonzini .name = "cadence_gem", 1733e8e49943SAlistair Francis .version_id = 4, 1734e8e49943SAlistair Francis .minimum_version_id = 4, 173549ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1736448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1737448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1738448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 17392bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 17402bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 17412bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 17422bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1743448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 174417cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 174549ab747fSPaolo Bonzini } 174649ab747fSPaolo Bonzini }; 174749ab747fSPaolo Bonzini 174849ab747fSPaolo Bonzini static Property gem_properties[] = { 1749448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1750a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1751a5517666SAlistair Francis GEM_MODID_VALUE), 175264ac1363SBin Meng DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 17532bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 17542bf57f73SAlistair Francis num_priority_queues, 1), 1755e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1756e8e49943SAlistair Francis num_type1_screeners, 4), 1757e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1758e8e49943SAlistair Francis num_type2_screeners, 4), 17597ca151c3SSai Pavan Boddu DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 17607ca151c3SSai Pavan Boddu jumbo_max_len, 10240), 176108d45942SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 176208d45942SPhilippe Mathieu-Daudé TYPE_MEMORY_REGION, MemoryRegion *), 176349ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 176449ab747fSPaolo Bonzini }; 176549ab747fSPaolo Bonzini 176649ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 176749ab747fSPaolo Bonzini { 176849ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 176949ab747fSPaolo Bonzini 1770bcb39a65SAlistair Francis dc->realize = gem_realize; 17714f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 177249ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 177349ab747fSPaolo Bonzini dc->reset = gem_reset; 177449ab747fSPaolo Bonzini } 177549ab747fSPaolo Bonzini 177649ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1777318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 177849ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1779448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1780bcb39a65SAlistair Francis .instance_init = gem_init, 1781318643beSAndreas Färber .class_init = gem_class_init, 178249ab747fSPaolo Bonzini }; 178349ab747fSPaolo Bonzini 178449ab747fSPaolo Bonzini static void gem_register_types(void) 178549ab747fSPaolo Bonzini { 178649ab747fSPaolo Bonzini type_register_static(&gem_info); 178749ab747fSPaolo Bonzini } 178849ab747fSPaolo Bonzini 178949ab747fSPaolo Bonzini type_init(gem_register_types) 1790