149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31d6454270SMarkus Armbruster #include "migration/vmstate.h" 322bf57f73SAlistair Francis #include "qapi/error.h" 33e8e49943SAlistair Francis #include "qemu/log.h" 340b8fa32fSMarkus Armbruster #include "qemu/module.h" 3584aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3649ab747fSPaolo Bonzini #include "net/checksum.h" 3749ab747fSPaolo Bonzini 3849ab747fSPaolo Bonzini #ifdef CADENCE_GEM_ERR_DEBUG 3949ab747fSPaolo Bonzini #define DB_PRINT(...) do { \ 4049ab747fSPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 4149ab747fSPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 422562755eSEric Blake } while (0) 4349ab747fSPaolo Bonzini #else 4449ab747fSPaolo Bonzini #define DB_PRINT(...) 4549ab747fSPaolo Bonzini #endif 4649ab747fSPaolo Bonzini 4749ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 4849ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 4949ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 5049ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 5149ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 5249ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 5349ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 5449ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 5549ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 5649ab747fSPaolo Bonzini #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 5749ab747fSPaolo Bonzini #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 5849ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 5949ab747fSPaolo Bonzini #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 603048ed6aSPeter Crosthwaite #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 6149ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 6249ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 6349ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 6449ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 6549ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 6649ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 6749ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 6849ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 6949ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 7049ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 7149ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 7249ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 7349ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 7449ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 7549ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 7649ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 7749ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 7849ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 7949ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 8049ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 8149ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 8249ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 8349ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 8449ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 8549ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 8649ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 8749ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 8849ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 8949ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 9049ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 9149ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 9249ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 9349ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 9449ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 9549ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 9649ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 9749ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 9849ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 9949ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 10049ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 10149ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 10249ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 10349ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 10449ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 10549ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 10649ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 10749ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 10849ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 10949ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 11049ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 11149ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 11249ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 11349ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 11449ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 11549ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 11649ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 11749ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 11849ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 11949ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 12149ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 12249ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 12349ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 12449ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 12549ab747fSPaolo Bonzini #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 12649ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 12749ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 12849ab747fSPaolo Bonzini 12949ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 13049ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 13149ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 13249ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 13349ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 13449ab747fSPaolo Bonzini #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 13549ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 13649ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 13749ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 13849ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 13949ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 14049ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 14149ab747fSPaolo Bonzini 14249ab747fSPaolo Bonzini /* Design Configuration Registers */ 14349ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280/4) 14449ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284/4) 14549ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288/4) 14649ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C/4) 14749ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290/4) 14849ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294/4) 149e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 15049ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298/4) 15149ab747fSPaolo Bonzini 15267101725SAlistair Francis #define GEM_INT_Q1_STATUS (0x00000400 / 4) 15367101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 15467101725SAlistair Francis 15567101725SAlistair Francis #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 15679b2ac8fSAlistair Francis #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 15767101725SAlistair Francis 15867101725SAlistair Francis #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 15979b2ac8fSAlistair Francis #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 16067101725SAlistair Francis 161357aa013SEdgar E. Iglesias #define GEM_TBQPH (0x000004C8 / 4) 162357aa013SEdgar E. Iglesias #define GEM_RBQPH (0x000004D4 / 4) 163357aa013SEdgar E. Iglesias 16467101725SAlistair Francis #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 16567101725SAlistair Francis #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 16667101725SAlistair Francis 16767101725SAlistair Francis #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 16867101725SAlistair Francis #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 16967101725SAlistair Francis 17067101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 17167101725SAlistair Francis #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 17267101725SAlistair Francis 173e8e49943SAlistair Francis #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 174e8e49943SAlistair Francis 175e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 176e8e49943SAlistair Francis #define GEM_ST1R_DSTC_ENABLE (1 << 28) 177e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 178e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 179e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 180e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 181e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_SHIFT (0) 182e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 183e8e49943SAlistair Francis 184e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 185e8e49943SAlistair Francis 186e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 187e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_SHIFT (13) 188e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 189e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 190e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 191e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 192e8e49943SAlistair Francis + 1) 193e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_SHIFT (0) 194e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 195e8e49943SAlistair Francis 196e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 197e8e49943SAlistair Francis #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 198e8e49943SAlistair Francis 199e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 200e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 201e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 202e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 203e8e49943SAlistair Francis 20449ab747fSPaolo Bonzini /*****************************************/ 20549ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 20649ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 20749ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 20849ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 20949ab747fSPaolo Bonzini 21049ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2113048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 21249ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 21349ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 21449ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 21549ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 21649ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 21749ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 21849ab747fSPaolo Bonzini 219e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 220e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 221e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2222801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 22349ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 22449ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 22549ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 22649ab747fSPaolo Bonzini 22749ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 22849ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 22949ab747fSPaolo Bonzini 23049ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 23149ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 23249ab747fSPaolo Bonzini 23349ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 23449ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 23549ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 23649ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 23749ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 23849ab747fSPaolo Bonzini 23949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 24049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 24149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 24249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 24349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 24449ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 24549ab747fSPaolo Bonzini 24649ab747fSPaolo Bonzini /* Marvell PHY definitions */ 24749ab747fSPaolo Bonzini #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 24849ab747fSPaolo Bonzini 24949ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 25049ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 25149ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 25249ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 25349ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 25449ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 25549ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 25649ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 25749ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 25849ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 25949ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 26049ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 26149ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 26249ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 26349ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 26449ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 26549ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 26649ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 26749ab747fSPaolo Bonzini #define PHY_REG_EACD 22 26849ab747fSPaolo Bonzini #define PHY_REG_LED 24 26949ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 27049ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 27149ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 27249ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 27349ab747fSPaolo Bonzini 27449ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 27549ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 27649ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 2776623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 27849ab747fSPaolo Bonzini 27949ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 28049ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 28149ab747fSPaolo Bonzini 28249ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 28349ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 28449ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 28549ab747fSPaolo Bonzini 28649ab747fSPaolo Bonzini /***********************************************************************/ 28763af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 28863af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 28963af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 29063af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 29163af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 29263af1e0cSPeter Crosthwaite 29363af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 29449ab747fSPaolo Bonzini 29549ab747fSPaolo Bonzini /***********************************************************************/ 29649ab747fSPaolo Bonzini 29749ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 29849ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 29949ab747fSPaolo Bonzini 30049ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 30149ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 30249ab747fSPaolo Bonzini 30349ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 30449ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 30549ab747fSPaolo Bonzini 30663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 30763af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 308a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 30963af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 31063af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 31163af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 31263af1e0cSPeter Crosthwaite 31349ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 31449ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 31549ab747fSPaolo Bonzini 316a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 317a5517666SAlistair Francis 318e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 31949ab747fSPaolo Bonzini { 320e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 321e48fdd9dSEdgar E. Iglesias 322e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 323e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 324e48fdd9dSEdgar E. Iglesias } 325e48fdd9dSEdgar E. Iglesias return ret; 32649ab747fSPaolo Bonzini } 32749ab747fSPaolo Bonzini 328f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 32949ab747fSPaolo Bonzini { 33049ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 33149ab747fSPaolo Bonzini } 33249ab747fSPaolo Bonzini 333f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 33449ab747fSPaolo Bonzini { 33549ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 33649ab747fSPaolo Bonzini } 33749ab747fSPaolo Bonzini 338f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 33949ab747fSPaolo Bonzini { 34049ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 34149ab747fSPaolo Bonzini } 34249ab747fSPaolo Bonzini 343f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 34449ab747fSPaolo Bonzini { 34549ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 34649ab747fSPaolo Bonzini } 34749ab747fSPaolo Bonzini 348f0236182SEdgar E. Iglesias static inline void tx_desc_set_last(uint32_t *desc) 349cbdab58dSAlistair Francis { 350cbdab58dSAlistair Francis desc[1] |= DESC_1_TX_LAST; 351cbdab58dSAlistair Francis } 352cbdab58dSAlistair Francis 353f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 35449ab747fSPaolo Bonzini { 35549ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 35649ab747fSPaolo Bonzini } 35749ab747fSPaolo Bonzini 358f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 35949ab747fSPaolo Bonzini { 36067101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 36149ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 36249ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 36349ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 36449ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 36549ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 36649ab747fSPaolo Bonzini } 36749ab747fSPaolo Bonzini 368e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 36949ab747fSPaolo Bonzini { 370e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 371e48fdd9dSEdgar E. Iglesias 372e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 373e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 374e48fdd9dSEdgar E. Iglesias } 375e48fdd9dSEdgar E. Iglesias return ret; 376e48fdd9dSEdgar E. Iglesias } 377e48fdd9dSEdgar E. Iglesias 378e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 379e48fdd9dSEdgar E. Iglesias { 380e48fdd9dSEdgar E. Iglesias int ret = 2; 381e48fdd9dSEdgar E. Iglesias 382e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 383e48fdd9dSEdgar E. Iglesias ret += 2; 384e48fdd9dSEdgar E. Iglesias } 385e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 386e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 387e48fdd9dSEdgar E. Iglesias ret += 2; 388e48fdd9dSEdgar E. Iglesias } 389e48fdd9dSEdgar E. Iglesias 390e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 391e48fdd9dSEdgar E. Iglesias return ret; 39249ab747fSPaolo Bonzini } 39349ab747fSPaolo Bonzini 394f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 39549ab747fSPaolo Bonzini { 39649ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 39749ab747fSPaolo Bonzini } 39849ab747fSPaolo Bonzini 399f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 40049ab747fSPaolo Bonzini { 40149ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 40249ab747fSPaolo Bonzini } 40349ab747fSPaolo Bonzini 404f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 40549ab747fSPaolo Bonzini { 40649ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 40749ab747fSPaolo Bonzini } 40849ab747fSPaolo Bonzini 409f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 41049ab747fSPaolo Bonzini { 41149ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 41249ab747fSPaolo Bonzini } 41349ab747fSPaolo Bonzini 414*59ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 415*59ab136aSRamon Fried { 416*59ab136aSRamon Fried desc[1] = 0; 417*59ab136aSRamon Fried } 418*59ab136aSRamon Fried 419f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 42049ab747fSPaolo Bonzini { 42149ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 42249ab747fSPaolo Bonzini } 42349ab747fSPaolo Bonzini 424f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 42549ab747fSPaolo Bonzini { 42649ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 42749ab747fSPaolo Bonzini desc[1] |= len; 42849ab747fSPaolo Bonzini } 42949ab747fSPaolo Bonzini 430f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 43163af1e0cSPeter Crosthwaite { 43263af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 43363af1e0cSPeter Crosthwaite } 43463af1e0cSPeter Crosthwaite 435f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 43663af1e0cSPeter Crosthwaite { 43763af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 43863af1e0cSPeter Crosthwaite } 43963af1e0cSPeter Crosthwaite 440f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 44163af1e0cSPeter Crosthwaite { 44263af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 44363af1e0cSPeter Crosthwaite } 44463af1e0cSPeter Crosthwaite 445f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 44663af1e0cSPeter Crosthwaite { 44763af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 44863af1e0cSPeter Crosthwaite sar_idx); 449a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 45063af1e0cSPeter Crosthwaite } 45163af1e0cSPeter Crosthwaite 45249ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4536a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 45449ab747fSPaolo Bonzini 45549ab747fSPaolo Bonzini /* 45649ab747fSPaolo Bonzini * gem_init_register_masks: 45749ab747fSPaolo Bonzini * One time initialization. 45849ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 45949ab747fSPaolo Bonzini */ 460448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 46149ab747fSPaolo Bonzini { 46249ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 46349ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 46449ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 46549ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 466e48fdd9dSEdgar E. Iglesias s->regs_ro[GEM_DMACFG] = 0x8E00F000; 46749ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 46849ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 46949ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 47049ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 47149ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 47249ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 47349ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 47449ab747fSPaolo Bonzini 47549ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 47649ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 47749ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 47849ab747fSPaolo Bonzini 47949ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 48049ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 48149ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 48249ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 48349ab747fSPaolo Bonzini 48449ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 48549ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 48649ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 48749ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 48849ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 48949ab747fSPaolo Bonzini } 49049ab747fSPaolo Bonzini 49149ab747fSPaolo Bonzini /* 49249ab747fSPaolo Bonzini * phy_update_link: 49349ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 49449ab747fSPaolo Bonzini */ 495448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 49649ab747fSPaolo Bonzini { 49749ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 49849ab747fSPaolo Bonzini 49949ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 50049ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 50149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 50249ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 50349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 50449ab747fSPaolo Bonzini } else { 50549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 50649ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 50749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 50849ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 50949ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 51049ab747fSPaolo Bonzini } 51149ab747fSPaolo Bonzini } 51249ab747fSPaolo Bonzini 513b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 51449ab747fSPaolo Bonzini { 515448f19e2SPeter Crosthwaite CadenceGEMState *s; 51667101725SAlistair Francis int i; 51749ab747fSPaolo Bonzini 51849ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 51949ab747fSPaolo Bonzini 52049ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 52149ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 5223ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 5233ae5725fSPeter Crosthwaite s->can_rx_state = 1; 5243ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 5253ae5725fSPeter Crosthwaite } 526b8c4b67eSPhilippe Mathieu-Daudé return false; 52749ab747fSPaolo Bonzini } 52849ab747fSPaolo Bonzini 52967101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 530dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 531dacc0566SAlistair Francis break; 532dacc0566SAlistair Francis } 533dacc0566SAlistair Francis }; 534dacc0566SAlistair Francis 535dacc0566SAlistair Francis if (i == s->num_priority_queues) { 5368202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 5378202aa53SPeter Crosthwaite s->can_rx_state = 2; 538dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 5398202aa53SPeter Crosthwaite } 540b8c4b67eSPhilippe Mathieu-Daudé return false; 5418202aa53SPeter Crosthwaite } 5428202aa53SPeter Crosthwaite 5433ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 5443ae5725fSPeter Crosthwaite s->can_rx_state = 0; 54567101725SAlistair Francis DB_PRINT("can receive\n"); 5463ae5725fSPeter Crosthwaite } 547b8c4b67eSPhilippe Mathieu-Daudé return true; 54849ab747fSPaolo Bonzini } 54949ab747fSPaolo Bonzini 55049ab747fSPaolo Bonzini /* 55149ab747fSPaolo Bonzini * gem_update_int_status: 55249ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 55349ab747fSPaolo Bonzini */ 554448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 55549ab747fSPaolo Bonzini { 55667101725SAlistair Francis int i; 55767101725SAlistair Francis 558596b6f51SAlistair Francis if (!s->regs[GEM_ISR]) { 559596b6f51SAlistair Francis /* ISR isn't set, clear all the interrupts */ 560596b6f51SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 561596b6f51SAlistair Francis qemu_set_irq(s->irq[i], 0); 562596b6f51SAlistair Francis } 563596b6f51SAlistair Francis return; 564596b6f51SAlistair Francis } 565596b6f51SAlistair Francis 566596b6f51SAlistair Francis /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to 567596b6f51SAlistair Francis * check it again. 568596b6f51SAlistair Francis */ 569596b6f51SAlistair Francis if (s->num_priority_queues == 1) { 57067101725SAlistair Francis /* No priority queues, just trigger the interrupt */ 5718ea1d056SFam Zheng DB_PRINT("asserting int.\n"); 5722bf57f73SAlistair Francis qemu_set_irq(s->irq[0], 1); 57367101725SAlistair Francis return; 57467101725SAlistair Francis } 57567101725SAlistair Francis 57667101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 57767101725SAlistair Francis if (s->regs[GEM_INT_Q1_STATUS + i]) { 57867101725SAlistair Francis DB_PRINT("asserting int. (q=%d)\n", i); 57967101725SAlistair Francis qemu_set_irq(s->irq[i], 1); 58067101725SAlistair Francis } 58149ab747fSPaolo Bonzini } 58249ab747fSPaolo Bonzini } 58349ab747fSPaolo Bonzini 58449ab747fSPaolo Bonzini /* 58549ab747fSPaolo Bonzini * gem_receive_updatestats: 58649ab747fSPaolo Bonzini * Increment receive statistics. 58749ab747fSPaolo Bonzini */ 588448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 58949ab747fSPaolo Bonzini unsigned bytes) 59049ab747fSPaolo Bonzini { 59149ab747fSPaolo Bonzini uint64_t octets; 59249ab747fSPaolo Bonzini 59349ab747fSPaolo Bonzini /* Total octets (bytes) received */ 59449ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 59549ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 59649ab747fSPaolo Bonzini octets += bytes; 59749ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 59849ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 59949ab747fSPaolo Bonzini 60049ab747fSPaolo Bonzini /* Error-free Frames received */ 60149ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 60249ab747fSPaolo Bonzini 60349ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 60449ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 60549ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 60649ab747fSPaolo Bonzini } 60749ab747fSPaolo Bonzini 60849ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 60949ab747fSPaolo Bonzini if (packet[0] == 0x01) { 61049ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 61149ab747fSPaolo Bonzini } 61249ab747fSPaolo Bonzini 61349ab747fSPaolo Bonzini if (bytes <= 64) { 61449ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 61549ab747fSPaolo Bonzini } else if (bytes <= 127) { 61649ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 61749ab747fSPaolo Bonzini } else if (bytes <= 255) { 61849ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 61949ab747fSPaolo Bonzini } else if (bytes <= 511) { 62049ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 62149ab747fSPaolo Bonzini } else if (bytes <= 1023) { 62249ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 62349ab747fSPaolo Bonzini } else if (bytes <= 1518) { 62449ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 62549ab747fSPaolo Bonzini } else { 62649ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 62749ab747fSPaolo Bonzini } 62849ab747fSPaolo Bonzini } 62949ab747fSPaolo Bonzini 63049ab747fSPaolo Bonzini /* 63149ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 63249ab747fSPaolo Bonzini */ 63349ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 63449ab747fSPaolo Bonzini { 63549ab747fSPaolo Bonzini unsigned byte; 63649ab747fSPaolo Bonzini 63749ab747fSPaolo Bonzini byte = mac[bit / 8]; 63849ab747fSPaolo Bonzini byte >>= (bit & 0x7); 63949ab747fSPaolo Bonzini byte &= 1; 64049ab747fSPaolo Bonzini 64149ab747fSPaolo Bonzini return byte; 64249ab747fSPaolo Bonzini } 64349ab747fSPaolo Bonzini 64449ab747fSPaolo Bonzini /* 64549ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 64649ab747fSPaolo Bonzini */ 64749ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 64849ab747fSPaolo Bonzini { 64949ab747fSPaolo Bonzini int index_bit, mac_bit; 65049ab747fSPaolo Bonzini unsigned hash_index; 65149ab747fSPaolo Bonzini 65249ab747fSPaolo Bonzini hash_index = 0; 65349ab747fSPaolo Bonzini mac_bit = 5; 65449ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 65549ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 65649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 65749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 65849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 65949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 66049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 66149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 66249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 66349ab747fSPaolo Bonzini mac_bit--; 66449ab747fSPaolo Bonzini } 66549ab747fSPaolo Bonzini 66649ab747fSPaolo Bonzini return hash_index; 66749ab747fSPaolo Bonzini } 66849ab747fSPaolo Bonzini 66949ab747fSPaolo Bonzini /* 67049ab747fSPaolo Bonzini * gem_mac_address_filter: 67149ab747fSPaolo Bonzini * Accept or reject this destination address? 67249ab747fSPaolo Bonzini * Returns: 67349ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 67463af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 67563af1e0cSPeter Crosthwaite * others for various other modes of accept: 67663af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 67763af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 67849ab747fSPaolo Bonzini */ 679448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 68049ab747fSPaolo Bonzini { 68149ab747fSPaolo Bonzini uint8_t *gem_spaddr; 68249ab747fSPaolo Bonzini int i; 68349ab747fSPaolo Bonzini 68449ab747fSPaolo Bonzini /* Promiscuous mode? */ 68549ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 68663af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 68749ab747fSPaolo Bonzini } 68849ab747fSPaolo Bonzini 68949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 69049ab747fSPaolo Bonzini /* Reject broadcast packets? */ 69149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 69249ab747fSPaolo Bonzini return GEM_RX_REJECT; 69349ab747fSPaolo Bonzini } 69463af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 69549ab747fSPaolo Bonzini } 69649ab747fSPaolo Bonzini 69749ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 69849ab747fSPaolo Bonzini if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 69949ab747fSPaolo Bonzini (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 70049ab747fSPaolo Bonzini unsigned hash_index; 70149ab747fSPaolo Bonzini 70249ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 70349ab747fSPaolo Bonzini if (hash_index < 32) { 70449ab747fSPaolo Bonzini if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 70563af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 70663af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 70749ab747fSPaolo Bonzini } 70849ab747fSPaolo Bonzini } else { 70949ab747fSPaolo Bonzini hash_index -= 32; 71049ab747fSPaolo Bonzini if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 71163af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 71263af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 71349ab747fSPaolo Bonzini } 71449ab747fSPaolo Bonzini } 71549ab747fSPaolo Bonzini } 71649ab747fSPaolo Bonzini 71749ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 71849ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 71963af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 72064eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 72163af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 72249ab747fSPaolo Bonzini } 72349ab747fSPaolo Bonzini } 72449ab747fSPaolo Bonzini 72549ab747fSPaolo Bonzini /* No address match; reject the packet */ 72649ab747fSPaolo Bonzini return GEM_RX_REJECT; 72749ab747fSPaolo Bonzini } 72849ab747fSPaolo Bonzini 729e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 730e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 731e8e49943SAlistair Francis unsigned rxbufsize) 732e8e49943SAlistair Francis { 733e8e49943SAlistair Francis uint32_t reg; 734e8e49943SAlistair Francis bool matched, mismatched; 735e8e49943SAlistair Francis int i, j; 736e8e49943SAlistair Francis 737e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 738e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 739e8e49943SAlistair Francis matched = false; 740e8e49943SAlistair Francis mismatched = false; 741e8e49943SAlistair Francis 742e8e49943SAlistair Francis /* Screening is based on UDP Port */ 743e8e49943SAlistair Francis if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 744e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 745e8e49943SAlistair Francis if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 746e8e49943SAlistair Francis GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 747e8e49943SAlistair Francis matched = true; 748e8e49943SAlistair Francis } else { 749e8e49943SAlistair Francis mismatched = true; 750e8e49943SAlistair Francis } 751e8e49943SAlistair Francis } 752e8e49943SAlistair Francis 753e8e49943SAlistair Francis /* Screening is based on DS/TC */ 754e8e49943SAlistair Francis if (reg & GEM_ST1R_DSTC_ENABLE) { 755e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 756e8e49943SAlistair Francis if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 757e8e49943SAlistair Francis GEM_ST1R_DSTC_MATCH_WIDTH)) { 758e8e49943SAlistair Francis matched = true; 759e8e49943SAlistair Francis } else { 760e8e49943SAlistair Francis mismatched = true; 761e8e49943SAlistair Francis } 762e8e49943SAlistair Francis } 763e8e49943SAlistair Francis 764e8e49943SAlistair Francis if (matched && !mismatched) { 765e8e49943SAlistair Francis return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 766e8e49943SAlistair Francis } 767e8e49943SAlistair Francis } 768e8e49943SAlistair Francis 769e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 770e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 771e8e49943SAlistair Francis matched = false; 772e8e49943SAlistair Francis mismatched = false; 773e8e49943SAlistair Francis 774e8e49943SAlistair Francis if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 775e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 776e8e49943SAlistair Francis int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 777e8e49943SAlistair Francis GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 778e8e49943SAlistair Francis 779e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 780e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 781e8e49943SAlistair Francis "register index: %d\n", et_idx); 782e8e49943SAlistair Francis } 783e8e49943SAlistair Francis if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 784e8e49943SAlistair Francis et_idx]) { 785e8e49943SAlistair Francis matched = true; 786e8e49943SAlistair Francis } else { 787e8e49943SAlistair Francis mismatched = true; 788e8e49943SAlistair Francis } 789e8e49943SAlistair Francis } 790e8e49943SAlistair Francis 791e8e49943SAlistair Francis /* Compare A, B, C */ 792e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 793e8e49943SAlistair Francis uint32_t cr0, cr1, mask; 794e8e49943SAlistair Francis uint16_t rx_cmp; 795e8e49943SAlistair Francis int offset; 796e8e49943SAlistair Francis int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 797e8e49943SAlistair Francis GEM_ST2R_COMPARE_WIDTH); 798e8e49943SAlistair Francis 799e8e49943SAlistair Francis if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 800e8e49943SAlistair Francis continue; 801e8e49943SAlistair Francis } 802e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 803e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 804e8e49943SAlistair Francis "register index: %d\n", cr_idx); 805e8e49943SAlistair Francis } 806e8e49943SAlistair Francis 807e8e49943SAlistair Francis cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 808e8e49943SAlistair Francis cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 809e8e49943SAlistair Francis offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 810e8e49943SAlistair Francis GEM_T2CW1_OFFSET_VALUE_WIDTH); 811e8e49943SAlistair Francis 812e8e49943SAlistair Francis switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 813e8e49943SAlistair Francis GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 814e8e49943SAlistair Francis case 3: /* Skip UDP header */ 815e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 816e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 817e8e49943SAlistair Francis offset += 8; 818e8e49943SAlistair Francis /* Fallthrough */ 819e8e49943SAlistair Francis case 2: /* skip the IP header */ 820e8e49943SAlistair Francis offset += 20; 821e8e49943SAlistair Francis /* Fallthrough */ 822e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 823e8e49943SAlistair Francis offset += 14; 824e8e49943SAlistair Francis break; 825e8e49943SAlistair Francis case 0: 826e8e49943SAlistair Francis /* Offset from start of frame */ 827e8e49943SAlistair Francis break; 828e8e49943SAlistair Francis } 829e8e49943SAlistair Francis 830e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 831e8e49943SAlistair Francis mask = extract32(cr0, 0, 16); 832e8e49943SAlistair Francis 833e8e49943SAlistair Francis if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 834e8e49943SAlistair Francis matched = true; 835e8e49943SAlistair Francis } else { 836e8e49943SAlistair Francis mismatched = true; 837e8e49943SAlistair Francis } 838e8e49943SAlistair Francis } 839e8e49943SAlistair Francis 840e8e49943SAlistair Francis if (matched && !mismatched) { 841e8e49943SAlistair Francis return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 842e8e49943SAlistair Francis } 843e8e49943SAlistair Francis } 844e8e49943SAlistair Francis 845e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 846e8e49943SAlistair Francis return 0; 847e8e49943SAlistair Francis } 848e8e49943SAlistair Francis 849357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 850357aa013SEdgar E. Iglesias { 851357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 852357aa013SEdgar E. Iglesias 853357aa013SEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 854357aa013SEdgar E. Iglesias desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; 855357aa013SEdgar E. Iglesias } 856357aa013SEdgar E. Iglesias desc_addr <<= 32; 857357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 858357aa013SEdgar E. Iglesias return desc_addr; 859357aa013SEdgar E. Iglesias } 860357aa013SEdgar E. Iglesias 861357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 862357aa013SEdgar E. Iglesias { 863357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 864357aa013SEdgar E. Iglesias } 865357aa013SEdgar E. Iglesias 866357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 867357aa013SEdgar E. Iglesias { 868357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 869357aa013SEdgar E. Iglesias } 870357aa013SEdgar E. Iglesias 87167101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 87206c2fe95SPeter Crosthwaite { 873357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 874357aa013SEdgar E. Iglesias 875357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 876357aa013SEdgar E. Iglesias 87706c2fe95SPeter Crosthwaite /* read current descriptor */ 878357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 879b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 880e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 88106c2fe95SPeter Crosthwaite 88206c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 88367101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 884357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 88506c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 88606c2fe95SPeter Crosthwaite s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 88706c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 88806c2fe95SPeter Crosthwaite gem_update_int_status(s); 88906c2fe95SPeter Crosthwaite } 89006c2fe95SPeter Crosthwaite } 89106c2fe95SPeter Crosthwaite 89249ab747fSPaolo Bonzini /* 89349ab747fSPaolo Bonzini * gem_receive: 89449ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 89549ab747fSPaolo Bonzini */ 89649ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 89749ab747fSPaolo Bonzini { 898448f19e2SPeter Crosthwaite CadenceGEMState *s; 89949ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 90049ab747fSPaolo Bonzini unsigned rxbuf_offset; 90149ab747fSPaolo Bonzini uint8_t rxbuf[2048]; 90249ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 9033b2c97f9SEdgar E. Iglesias bool first_desc = true; 90463af1e0cSPeter Crosthwaite int maf; 9052bf57f73SAlistair Francis int q = 0; 90649ab747fSPaolo Bonzini 90749ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 90849ab747fSPaolo Bonzini 90949ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 91063af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 91163af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 91249ab747fSPaolo Bonzini return -1; 91349ab747fSPaolo Bonzini } 91449ab747fSPaolo Bonzini 91549ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 91649ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 91749ab747fSPaolo Bonzini unsigned type_len; 91849ab747fSPaolo Bonzini 91949ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 92049ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 92149ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 92249ab747fSPaolo Bonzini if (type_len < 0x600) { 92349ab747fSPaolo Bonzini if (size < type_len) { 92449ab747fSPaolo Bonzini /* discard */ 92549ab747fSPaolo Bonzini return -1; 92649ab747fSPaolo Bonzini } 92749ab747fSPaolo Bonzini } 92849ab747fSPaolo Bonzini } 92949ab747fSPaolo Bonzini 93049ab747fSPaolo Bonzini /* 93149ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 93249ab747fSPaolo Bonzini */ 93349ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 93449ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 93549ab747fSPaolo Bonzini 93649ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 93749ab747fSPaolo Bonzini * buffers needed to hold this packet. 93849ab747fSPaolo Bonzini */ 93949ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 94049ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 94149ab747fSPaolo Bonzini bytes_to_copy = size; 94249ab747fSPaolo Bonzini 943f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 944f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 945f265ae8cSAlistair Francis */ 946f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 947f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 948f265ae8cSAlistair Francis } 949f265ae8cSAlistair Francis 950191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 951191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 952191946c5SPeter Crosthwaite * not FCS stripping 953191946c5SPeter Crosthwaite */ 954191946c5SPeter Crosthwaite if (size < 60) { 955191946c5SPeter Crosthwaite size = 60; 956191946c5SPeter Crosthwaite } 957191946c5SPeter Crosthwaite 95849ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 95949ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 96049ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 96149ab747fSPaolo Bonzini } else { 96249ab747fSPaolo Bonzini unsigned crc_val; 96349ab747fSPaolo Bonzini 964244381ecSPrasad J Pandit if (size > sizeof(rxbuf) - sizeof(crc_val)) { 965244381ecSPrasad J Pandit size = sizeof(rxbuf) - sizeof(crc_val); 966244381ecSPrasad J Pandit } 967244381ecSPrasad J Pandit bytes_to_copy = size; 96849ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 9693048ed6aSPeter Crosthwaite * We must try and calculate one. 97049ab747fSPaolo Bonzini */ 97149ab747fSPaolo Bonzini 97249ab747fSPaolo Bonzini memcpy(rxbuf, buf, size); 97349ab747fSPaolo Bonzini memset(rxbuf + size, 0, sizeof(rxbuf) - size); 97449ab747fSPaolo Bonzini rxbuf_ptr = rxbuf; 97549ab747fSPaolo Bonzini crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 976c94239feSPeter Maydell memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 97749ab747fSPaolo Bonzini 97849ab747fSPaolo Bonzini bytes_to_copy += 4; 97949ab747fSPaolo Bonzini size += 4; 98049ab747fSPaolo Bonzini } 98149ab747fSPaolo Bonzini 98249ab747fSPaolo Bonzini DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 98349ab747fSPaolo Bonzini 984b12227afSStefan Weil /* Find which queue we are targeting */ 985e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 986e8e49943SAlistair Francis 9877cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 988357aa013SEdgar E. Iglesias hwaddr desc_addr; 989357aa013SEdgar E. Iglesias 99006c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 99106c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 99249ab747fSPaolo Bonzini return -1; 99349ab747fSPaolo Bonzini } 99449ab747fSPaolo Bonzini 995dda8f185SBin Meng DB_PRINT("copy %u bytes to 0x%" PRIx64 "\n", 996dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 997dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 99849ab747fSPaolo Bonzini 99949ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 100084aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 10012bf57f73SAlistair Francis rxbuf_offset, 100284aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1003e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 100449ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 100530570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 10063b2c97f9SEdgar E. Iglesias 1007*59ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 1008*59ab136aSRamon Fried 10093b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 10103b2c97f9SEdgar E. Iglesias if (first_desc) { 10112bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 10123b2c97f9SEdgar E. Iglesias first_desc = false; 10133b2c97f9SEdgar E. Iglesias } 10143b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 10152bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 10162bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 10173b2c97f9SEdgar E. Iglesias } 10182bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 101963af1e0cSPeter Crosthwaite 102063af1e0cSPeter Crosthwaite switch (maf) { 102163af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 102263af1e0cSPeter Crosthwaite break; 102363af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 10242bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 102563af1e0cSPeter Crosthwaite break; 102663af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 10272bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 102863af1e0cSPeter Crosthwaite break; 102963af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 10302bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 103163af1e0cSPeter Crosthwaite break; 103263af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 103363af1e0cSPeter Crosthwaite abort(); 103463af1e0cSPeter Crosthwaite default: /* SAR */ 10352bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 103663af1e0cSPeter Crosthwaite } 103763af1e0cSPeter Crosthwaite 10383b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1039357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1040b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1041b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1042e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 10433b2c97f9SEdgar E. Iglesias 104449ab747fSPaolo Bonzini /* Next descriptor */ 10452bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 104649ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 10472bf57f73SAlistair Francis s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; 104849ab747fSPaolo Bonzini } else { 104949ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1050e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 105149ab747fSPaolo Bonzini } 105267101725SAlistair Francis 105367101725SAlistair Francis gem_get_rx_desc(s, q); 10547cfd65e4SPeter Crosthwaite } 105549ab747fSPaolo Bonzini 105649ab747fSPaolo Bonzini /* Count it */ 105749ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 105849ab747fSPaolo Bonzini 105949ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 106049ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 106149ab747fSPaolo Bonzini 106249ab747fSPaolo Bonzini /* Handle interrupt consequences */ 106349ab747fSPaolo Bonzini gem_update_int_status(s); 106449ab747fSPaolo Bonzini 106549ab747fSPaolo Bonzini return size; 106649ab747fSPaolo Bonzini } 106749ab747fSPaolo Bonzini 106849ab747fSPaolo Bonzini /* 106949ab747fSPaolo Bonzini * gem_transmit_updatestats: 107049ab747fSPaolo Bonzini * Increment transmit statistics. 107149ab747fSPaolo Bonzini */ 1072448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 107349ab747fSPaolo Bonzini unsigned bytes) 107449ab747fSPaolo Bonzini { 107549ab747fSPaolo Bonzini uint64_t octets; 107649ab747fSPaolo Bonzini 107749ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 107849ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 107949ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 108049ab747fSPaolo Bonzini octets += bytes; 108149ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 108249ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 108349ab747fSPaolo Bonzini 108449ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 108549ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 108649ab747fSPaolo Bonzini 108749ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 108849ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 108949ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 109049ab747fSPaolo Bonzini } 109149ab747fSPaolo Bonzini 109249ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 109349ab747fSPaolo Bonzini if (packet[0] == 0x01) { 109449ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 109549ab747fSPaolo Bonzini } 109649ab747fSPaolo Bonzini 109749ab747fSPaolo Bonzini if (bytes <= 64) { 109849ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 109949ab747fSPaolo Bonzini } else if (bytes <= 127) { 110049ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 110149ab747fSPaolo Bonzini } else if (bytes <= 255) { 110249ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 110349ab747fSPaolo Bonzini } else if (bytes <= 511) { 110449ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 110549ab747fSPaolo Bonzini } else if (bytes <= 1023) { 110649ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 110749ab747fSPaolo Bonzini } else if (bytes <= 1518) { 110849ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 110949ab747fSPaolo Bonzini } else { 111049ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 111149ab747fSPaolo Bonzini } 111249ab747fSPaolo Bonzini } 111349ab747fSPaolo Bonzini 111449ab747fSPaolo Bonzini /* 111549ab747fSPaolo Bonzini * gem_transmit: 111649ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 111749ab747fSPaolo Bonzini */ 1118448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 111949ab747fSPaolo Bonzini { 11208568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 112149ab747fSPaolo Bonzini hwaddr packet_desc_addr; 112249ab747fSPaolo Bonzini uint8_t tx_packet[2048]; 112349ab747fSPaolo Bonzini uint8_t *p; 112449ab747fSPaolo Bonzini unsigned total_bytes; 11252bf57f73SAlistair Francis int q = 0; 112649ab747fSPaolo Bonzini 112749ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 112849ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 112949ab747fSPaolo Bonzini return; 113049ab747fSPaolo Bonzini } 113149ab747fSPaolo Bonzini 113249ab747fSPaolo Bonzini DB_PRINT("\n"); 113349ab747fSPaolo Bonzini 11343048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 113549ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 113649ab747fSPaolo Bonzini * one contiguous buffer first. 113749ab747fSPaolo Bonzini */ 113849ab747fSPaolo Bonzini p = tx_packet; 113949ab747fSPaolo Bonzini total_bytes = 0; 114049ab747fSPaolo Bonzini 114167101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 114249ab747fSPaolo Bonzini /* read current descriptor */ 1143357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1144fa15286aSPeter Crosthwaite 1145fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 114684aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1147b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1148e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 114949ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 115049ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 115149ab747fSPaolo Bonzini 115249ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 115349ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 115449ab747fSPaolo Bonzini return; 115549ab747fSPaolo Bonzini } 115667101725SAlistair Francis print_gem_tx_desc(desc, q); 115749ab747fSPaolo Bonzini 115849ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 115949ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 116049ab747fSPaolo Bonzini */ 1161e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 116249ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 116349ab747fSPaolo Bonzini DB_PRINT("Invalid TX descriptor @ 0x%x\n", 116449ab747fSPaolo Bonzini (unsigned)packet_desc_addr); 116549ab747fSPaolo Bonzini break; 116649ab747fSPaolo Bonzini } 116749ab747fSPaolo Bonzini 116877524d11SAlistair Francis if (tx_desc_get_length(desc) > sizeof(tx_packet) - 116977524d11SAlistair Francis (p - tx_packet)) { 1170dda8f185SBin Meng DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \ 1171dda8f185SBin Meng " too large: size 0x%x space 0x%zx\n", 1172dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 1173d7f05365SMichael S. Tsirkin sizeof(tx_packet) - (p - tx_packet)); 1174d7f05365SMichael S. Tsirkin break; 1175d7f05365SMichael S. Tsirkin } 1176d7f05365SMichael S. Tsirkin 117777524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 117877524d11SAlistair Francis * contig buffer. 117949ab747fSPaolo Bonzini */ 118084aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 118184aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 118284aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 118349ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 118449ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 118549ab747fSPaolo Bonzini 118649ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 118749ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 11888568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1189357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 11906ab57a6bSPeter Crosthwaite 119149ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 119249ab747fSPaolo Bonzini * the processor. 119349ab747fSPaolo Bonzini */ 1194357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1195b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 11966ab57a6bSPeter Crosthwaite sizeof(desc_first)); 11976ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1198357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1199b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12006ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12013048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 120249ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 12032bf57f73SAlistair Francis s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; 120449ab747fSPaolo Bonzini } else { 1205e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1206e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 120749ab747fSPaolo Bonzini } 12082bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 120949ab747fSPaolo Bonzini 121049ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 121149ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 121249ab747fSPaolo Bonzini 121367101725SAlistair Francis /* Update queue interrupt status */ 121467101725SAlistair Francis if (s->num_priority_queues > 1) { 121567101725SAlistair Francis s->regs[GEM_INT_Q1_STATUS + q] |= 121667101725SAlistair Francis GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]); 121767101725SAlistair Francis } 121867101725SAlistair Francis 121949ab747fSPaolo Bonzini /* Handle interrupt consequences */ 122049ab747fSPaolo Bonzini gem_update_int_status(s); 122149ab747fSPaolo Bonzini 122249ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 122349ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 122449ab747fSPaolo Bonzini net_checksum_calculate(tx_packet, total_bytes); 122549ab747fSPaolo Bonzini } 122649ab747fSPaolo Bonzini 122749ab747fSPaolo Bonzini /* Update MAC statistics */ 122849ab747fSPaolo Bonzini gem_transmit_updatestats(s, tx_packet, total_bytes); 122949ab747fSPaolo Bonzini 123049ab747fSPaolo Bonzini /* Send the packet somewhere */ 123177524d11SAlistair Francis if (s->phy_loop || (s->regs[GEM_NWCTRL] & 123277524d11SAlistair Francis GEM_NWCTRL_LOCALLOOP)) { 123377524d11SAlistair Francis gem_receive(qemu_get_queue(s->nic), tx_packet, 123477524d11SAlistair Francis total_bytes); 123549ab747fSPaolo Bonzini } else { 123649ab747fSPaolo Bonzini qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 123749ab747fSPaolo Bonzini total_bytes); 123849ab747fSPaolo Bonzini } 123949ab747fSPaolo Bonzini 124049ab747fSPaolo Bonzini /* Prepare for next packet */ 124149ab747fSPaolo Bonzini p = tx_packet; 124249ab747fSPaolo Bonzini total_bytes = 0; 124349ab747fSPaolo Bonzini } 124449ab747fSPaolo Bonzini 124549ab747fSPaolo Bonzini /* read next descriptor */ 124649ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1247cbdab58dSAlistair Francis tx_desc_set_last(desc); 1248f1e7cb13SRamon Fried 1249f1e7cb13SRamon Fried if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 1250f1e7cb13SRamon Fried packet_desc_addr = s->regs[GEM_TBQPH]; 1251f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1252f1e7cb13SRamon Fried } else { 1253f1e7cb13SRamon Fried packet_desc_addr = 0; 1254f1e7cb13SRamon Fried } 1255f1e7cb13SRamon Fried packet_desc_addr |= s->regs[GEM_TXQBASE]; 125649ab747fSPaolo Bonzini } else { 1257e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 125849ab747fSPaolo Bonzini } 1259fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 126084aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1261b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1262e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 126349ab747fSPaolo Bonzini } 126449ab747fSPaolo Bonzini 126549ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 126649ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 126749ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 126849ab747fSPaolo Bonzini gem_update_int_status(s); 126949ab747fSPaolo Bonzini } 127049ab747fSPaolo Bonzini } 127167101725SAlistair Francis } 127249ab747fSPaolo Bonzini 1273448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 127449ab747fSPaolo Bonzini { 127549ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 127649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 127749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 127849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 127949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 128049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 128149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 128249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 128349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 128449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 128549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 128649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 128749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 128849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 12897777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 129049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 129149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 129249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 129349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 129449ab747fSPaolo Bonzini 129549ab747fSPaolo Bonzini phy_update_link(s); 129649ab747fSPaolo Bonzini } 129749ab747fSPaolo Bonzini 129849ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 129949ab747fSPaolo Bonzini { 130064eb9301SPeter Crosthwaite int i; 1301448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1302afb4c51fSSebastian Huber const uint8_t *a; 1303726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 130449ab747fSPaolo Bonzini 130549ab747fSPaolo Bonzini DB_PRINT("\n"); 130649ab747fSPaolo Bonzini 130749ab747fSPaolo Bonzini /* Set post reset register values */ 130849ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 130949ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 131049ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 131149ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 131249ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 131349ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 131449ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 131549ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1316a5517666SAlistair Francis s->regs[GEM_MODID] = s->revision; 131749ab747fSPaolo Bonzini s->regs[GEM_DESCONF] = 0x02500111; 131849ab747fSPaolo Bonzini s->regs[GEM_DESCONF2] = 0x2ab13fff; 1319b2d43091SEdgar E. Iglesias s->regs[GEM_DESCONF5] = 0x002f2045; 1320e2c0c4eeSEdgar E. Iglesias s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; 1321726a2a95SEdgar E. Iglesias 1322726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1323726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1324726a2a95SEdgar E. Iglesias s->regs[GEM_DESCONF6] |= queues_mask; 1325726a2a95SEdgar E. Iglesias } 132649ab747fSPaolo Bonzini 1327afb4c51fSSebastian Huber /* Set MAC address */ 1328afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1329afb4c51fSSebastian Huber s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1330afb4c51fSSebastian Huber s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1331afb4c51fSSebastian Huber 133264eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 133364eb9301SPeter Crosthwaite s->sar_active[i] = false; 133464eb9301SPeter Crosthwaite } 133564eb9301SPeter Crosthwaite 133649ab747fSPaolo Bonzini gem_phy_reset(s); 133749ab747fSPaolo Bonzini 133849ab747fSPaolo Bonzini gem_update_int_status(s); 133949ab747fSPaolo Bonzini } 134049ab747fSPaolo Bonzini 1341448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 134249ab747fSPaolo Bonzini { 134349ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 134449ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 134549ab747fSPaolo Bonzini } 134649ab747fSPaolo Bonzini 1347448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 134849ab747fSPaolo Bonzini { 134949ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 135049ab747fSPaolo Bonzini 135149ab747fSPaolo Bonzini switch (reg_num) { 135249ab747fSPaolo Bonzini case PHY_REG_CONTROL: 135349ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 135449ab747fSPaolo Bonzini /* Phy reset */ 135549ab747fSPaolo Bonzini gem_phy_reset(s); 135649ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 135749ab747fSPaolo Bonzini s->phy_loop = 0; 135849ab747fSPaolo Bonzini } 135949ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 136049ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 13616623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 136249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 136349ab747fSPaolo Bonzini } 136449ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 136549ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 136649ab747fSPaolo Bonzini s->phy_loop = 1; 136749ab747fSPaolo Bonzini } else { 136849ab747fSPaolo Bonzini s->phy_loop = 0; 136949ab747fSPaolo Bonzini } 137049ab747fSPaolo Bonzini break; 137149ab747fSPaolo Bonzini } 137249ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 137349ab747fSPaolo Bonzini } 137449ab747fSPaolo Bonzini 137549ab747fSPaolo Bonzini /* 137649ab747fSPaolo Bonzini * gem_read32: 137749ab747fSPaolo Bonzini * Read a GEM register. 137849ab747fSPaolo Bonzini */ 137949ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 138049ab747fSPaolo Bonzini { 1381448f19e2SPeter Crosthwaite CadenceGEMState *s; 138249ab747fSPaolo Bonzini uint32_t retval; 1383448f19e2SPeter Crosthwaite s = (CadenceGEMState *)opaque; 138449ab747fSPaolo Bonzini 138549ab747fSPaolo Bonzini offset >>= 2; 138649ab747fSPaolo Bonzini retval = s->regs[offset]; 138749ab747fSPaolo Bonzini 138849ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 138949ab747fSPaolo Bonzini 139049ab747fSPaolo Bonzini switch (offset) { 139149ab747fSPaolo Bonzini case GEM_ISR: 139267101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1393596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 139449ab747fSPaolo Bonzini break; 139549ab747fSPaolo Bonzini case GEM_PHYMNTNC: 139649ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 139749ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 139849ab747fSPaolo Bonzini 139949ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 140055389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 140149ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 140249ab747fSPaolo Bonzini retval &= 0xFFFF0000; 140349ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 140449ab747fSPaolo Bonzini } else { 140549ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 140649ab747fSPaolo Bonzini } 140749ab747fSPaolo Bonzini } 140849ab747fSPaolo Bonzini break; 140949ab747fSPaolo Bonzini } 141049ab747fSPaolo Bonzini 141149ab747fSPaolo Bonzini /* Squash read to clear bits */ 141249ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 141349ab747fSPaolo Bonzini 141449ab747fSPaolo Bonzini /* Do not provide write only bits */ 141549ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 141649ab747fSPaolo Bonzini 141749ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 141867101725SAlistair Francis gem_update_int_status(s); 141949ab747fSPaolo Bonzini return retval; 142049ab747fSPaolo Bonzini } 142149ab747fSPaolo Bonzini 142249ab747fSPaolo Bonzini /* 142349ab747fSPaolo Bonzini * gem_write32: 142449ab747fSPaolo Bonzini * Write a GEM register. 142549ab747fSPaolo Bonzini */ 142649ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 142749ab747fSPaolo Bonzini unsigned size) 142849ab747fSPaolo Bonzini { 1429448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 143049ab747fSPaolo Bonzini uint32_t readonly; 143167101725SAlistair Francis int i; 143249ab747fSPaolo Bonzini 143349ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 143449ab747fSPaolo Bonzini offset >>= 2; 143549ab747fSPaolo Bonzini 143649ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 143749ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1438e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1439e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 144049ab747fSPaolo Bonzini 144149ab747fSPaolo Bonzini /* Copy register write to backing store */ 1442e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1443e2314fdaSPeter Crosthwaite 1444e2314fdaSPeter Crosthwaite /* do w1c */ 1445e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 144649ab747fSPaolo Bonzini 144749ab747fSPaolo Bonzini /* Handle register write side effects */ 144849ab747fSPaolo Bonzini switch (offset) { 144949ab747fSPaolo Bonzini case GEM_NWCTRL: 145006c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 145167101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 145267101725SAlistair Francis gem_get_rx_desc(s, i); 145367101725SAlistair Francis } 145406c2fe95SPeter Crosthwaite } 145549ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 145649ab747fSPaolo Bonzini gem_transmit(s); 145749ab747fSPaolo Bonzini } 145849ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 145949ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 146067101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 146167101725SAlistair Francis s->tx_desc_addr[i] = s->regs[GEM_TXQBASE]; 146267101725SAlistair Francis } 146349ab747fSPaolo Bonzini } 14648202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 146549ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 146649ab747fSPaolo Bonzini } 146749ab747fSPaolo Bonzini break; 146849ab747fSPaolo Bonzini 146949ab747fSPaolo Bonzini case GEM_TXSTATUS: 147049ab747fSPaolo Bonzini gem_update_int_status(s); 147149ab747fSPaolo Bonzini break; 147249ab747fSPaolo Bonzini case GEM_RXQBASE: 14732bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 147449ab747fSPaolo Bonzini break; 147579b2ac8fSAlistair Francis case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 147667101725SAlistair Francis s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 147767101725SAlistair Francis break; 147849ab747fSPaolo Bonzini case GEM_TXQBASE: 14792bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 148049ab747fSPaolo Bonzini break; 148179b2ac8fSAlistair Francis case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 148267101725SAlistair Francis s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 148367101725SAlistair Francis break; 148449ab747fSPaolo Bonzini case GEM_RXSTATUS: 148549ab747fSPaolo Bonzini gem_update_int_status(s); 148649ab747fSPaolo Bonzini break; 148749ab747fSPaolo Bonzini case GEM_IER: 148849ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 148949ab747fSPaolo Bonzini gem_update_int_status(s); 149049ab747fSPaolo Bonzini break; 149167101725SAlistair Francis case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 149267101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 149367101725SAlistair Francis gem_update_int_status(s); 149467101725SAlistair Francis break; 149549ab747fSPaolo Bonzini case GEM_IDR: 149649ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 149749ab747fSPaolo Bonzini gem_update_int_status(s); 149849ab747fSPaolo Bonzini break; 149967101725SAlistair Francis case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 150067101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 150167101725SAlistair Francis gem_update_int_status(s); 150267101725SAlistair Francis break; 150364eb9301SPeter Crosthwaite case GEM_SPADDR1LO: 150464eb9301SPeter Crosthwaite case GEM_SPADDR2LO: 150564eb9301SPeter Crosthwaite case GEM_SPADDR3LO: 150664eb9301SPeter Crosthwaite case GEM_SPADDR4LO: 150764eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 150864eb9301SPeter Crosthwaite break; 150964eb9301SPeter Crosthwaite case GEM_SPADDR1HI: 151064eb9301SPeter Crosthwaite case GEM_SPADDR2HI: 151164eb9301SPeter Crosthwaite case GEM_SPADDR3HI: 151264eb9301SPeter Crosthwaite case GEM_SPADDR4HI: 151364eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 151464eb9301SPeter Crosthwaite break; 151549ab747fSPaolo Bonzini case GEM_PHYMNTNC: 151649ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 151749ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 151849ab747fSPaolo Bonzini 151949ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 152055389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 152149ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 152249ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 152349ab747fSPaolo Bonzini } 152449ab747fSPaolo Bonzini } 152549ab747fSPaolo Bonzini break; 152649ab747fSPaolo Bonzini } 152749ab747fSPaolo Bonzini 152849ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 152949ab747fSPaolo Bonzini } 153049ab747fSPaolo Bonzini 153149ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 153249ab747fSPaolo Bonzini .read = gem_read, 153349ab747fSPaolo Bonzini .write = gem_write, 153449ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 153549ab747fSPaolo Bonzini }; 153649ab747fSPaolo Bonzini 153749ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 153849ab747fSPaolo Bonzini { 153967101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 154067101725SAlistair Francis 154149ab747fSPaolo Bonzini DB_PRINT("\n"); 154267101725SAlistair Francis phy_update_link(s); 154367101725SAlistair Francis gem_update_int_status(s); 154449ab747fSPaolo Bonzini } 154549ab747fSPaolo Bonzini 154649ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1547f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 154849ab747fSPaolo Bonzini .size = sizeof(NICState), 154949ab747fSPaolo Bonzini .can_receive = gem_can_receive, 155049ab747fSPaolo Bonzini .receive = gem_receive, 155149ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 155249ab747fSPaolo Bonzini }; 155349ab747fSPaolo Bonzini 1554bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 155549ab747fSPaolo Bonzini { 1556448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 155767101725SAlistair Francis int i; 155849ab747fSPaolo Bonzini 155984aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 156084aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 156184aec8efSEdgar E. Iglesias 15622bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 15632bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 15642bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 15652bf57f73SAlistair Francis s->num_priority_queues); 15662bf57f73SAlistair Francis return; 1567e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1568e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1569e8e49943SAlistair Francis s->num_type1_screeners); 1570e8e49943SAlistair Francis return; 1571e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1572e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1573e8e49943SAlistair Francis s->num_type2_screeners); 1574e8e49943SAlistair Francis return; 15752bf57f73SAlistair Francis } 15762bf57f73SAlistair Francis 157767101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 157867101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 157967101725SAlistair Francis } 1580bcb39a65SAlistair Francis 1581bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1582bcb39a65SAlistair Francis 1583bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1584bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 1585bcb39a65SAlistair Francis } 1586bcb39a65SAlistair Francis 1587bcb39a65SAlistair Francis static void gem_init(Object *obj) 1588bcb39a65SAlistair Francis { 1589bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1590bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1591bcb39a65SAlistair Francis 159249ab747fSPaolo Bonzini DB_PRINT("\n"); 159349ab747fSPaolo Bonzini 159449ab747fSPaolo Bonzini gem_init_register_masks(s); 1595eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1596eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 159749ab747fSPaolo Bonzini 1598bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 159984aec8efSEdgar E. Iglesias 160084aec8efSEdgar E. Iglesias object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 160184aec8efSEdgar E. Iglesias (Object **)&s->dma_mr, 160284aec8efSEdgar E. Iglesias qdev_prop_allow_set_link_before_realize, 160384aec8efSEdgar E. Iglesias OBJ_PROP_LINK_STRONG, 160484aec8efSEdgar E. Iglesias &error_abort); 160549ab747fSPaolo Bonzini } 160649ab747fSPaolo Bonzini 160749ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 160849ab747fSPaolo Bonzini .name = "cadence_gem", 1609e8e49943SAlistair Francis .version_id = 4, 1610e8e49943SAlistair Francis .minimum_version_id = 4, 161149ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1612448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1613448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1614448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 16152bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 16162bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 16172bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 16182bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1619448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 162017cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 162149ab747fSPaolo Bonzini } 162249ab747fSPaolo Bonzini }; 162349ab747fSPaolo Bonzini 162449ab747fSPaolo Bonzini static Property gem_properties[] = { 1625448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1626a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1627a5517666SAlistair Francis GEM_MODID_VALUE), 16282bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 16292bf57f73SAlistair Francis num_priority_queues, 1), 1630e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1631e8e49943SAlistair Francis num_type1_screeners, 4), 1632e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1633e8e49943SAlistair Francis num_type2_screeners, 4), 163449ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 163549ab747fSPaolo Bonzini }; 163649ab747fSPaolo Bonzini 163749ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 163849ab747fSPaolo Bonzini { 163949ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 164049ab747fSPaolo Bonzini 1641bcb39a65SAlistair Francis dc->realize = gem_realize; 16424f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 164349ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 164449ab747fSPaolo Bonzini dc->reset = gem_reset; 164549ab747fSPaolo Bonzini } 164649ab747fSPaolo Bonzini 164749ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1648318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 164949ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1650448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1651bcb39a65SAlistair Francis .instance_init = gem_init, 1652318643beSAndreas Färber .class_init = gem_class_init, 165349ab747fSPaolo Bonzini }; 165449ab747fSPaolo Bonzini 165549ab747fSPaolo Bonzini static void gem_register_types(void) 165649ab747fSPaolo Bonzini { 165749ab747fSPaolo Bonzini type_register_static(&gem_info); 165849ab747fSPaolo Bonzini } 165949ab747fSPaolo Bonzini 166049ab747fSPaolo Bonzini type_init(gem_register_types) 1661