149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31d6454270SMarkus Armbruster #include "migration/vmstate.h" 322bf57f73SAlistair Francis #include "qapi/error.h" 33e8e49943SAlistair Francis #include "qemu/log.h" 340b8fa32fSMarkus Armbruster #include "qemu/module.h" 3584aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3649ab747fSPaolo Bonzini #include "net/checksum.h" 3749ab747fSPaolo Bonzini 386fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 3949ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 406fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 416fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 426fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 436fe7661dSSai Pavan Boddu } \ 442562755eSEric Blake } while (0) 4549ab747fSPaolo Bonzini 4649ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 4749ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 4849ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 4949ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 5049ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 5149ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 5249ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 5349ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 5449ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 5549ab747fSPaolo Bonzini #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 5649ab747fSPaolo Bonzini #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 5749ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 5849ab747fSPaolo Bonzini #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 593048ed6aSPeter Crosthwaite #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 6049ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 6149ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 6249ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 6349ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 6449ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 6549ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 6649ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 6749ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 6849ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 6949ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 7049ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 7149ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 7249ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 7349ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 7449ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 7549ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 7649ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 7749ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 7849ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 7949ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 8049ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 8149ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 8249ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 8349ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 8449ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 8549ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 8649ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 8749ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 8849ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 8949ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 9049ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 9149ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 9249ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 9349ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 9449ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 9549ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 9649ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 9749ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 9849ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 9949ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 10049ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 10149ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 10249ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 10349ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 10449ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 10549ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 10649ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 10749ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 10849ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 10949ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 11049ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 11149ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 11249ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 11349ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 11449ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 11549ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 11649ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 11749ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 11849ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 11949ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 12149ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 12249ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 12349ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 12449ab747fSPaolo Bonzini #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 12549ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 12649ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 12749ab747fSPaolo Bonzini 12849ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 12949ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 13049ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 13149ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 13249ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 13349ab747fSPaolo Bonzini #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 13449ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 13549ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 13649ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 13749ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 13849ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 13949ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 14049ab747fSPaolo Bonzini 14149ab747fSPaolo Bonzini /* Design Configuration Registers */ 14249ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280/4) 14349ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284/4) 14449ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288/4) 14549ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C/4) 14649ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290/4) 14749ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294/4) 148e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 14949ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298/4) 15049ab747fSPaolo Bonzini 15167101725SAlistair Francis #define GEM_INT_Q1_STATUS (0x00000400 / 4) 15267101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 15367101725SAlistair Francis 15467101725SAlistair Francis #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 15579b2ac8fSAlistair Francis #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 15667101725SAlistair Francis 15767101725SAlistair Francis #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 15879b2ac8fSAlistair Francis #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 15967101725SAlistair Francis 160357aa013SEdgar E. Iglesias #define GEM_TBQPH (0x000004C8 / 4) 161357aa013SEdgar E. Iglesias #define GEM_RBQPH (0x000004D4 / 4) 162357aa013SEdgar E. Iglesias 16367101725SAlistair Francis #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 16467101725SAlistair Francis #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 16567101725SAlistair Francis 16667101725SAlistair Francis #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 16767101725SAlistair Francis #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 16867101725SAlistair Francis 16967101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 17067101725SAlistair Francis #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 17167101725SAlistair Francis 172e8e49943SAlistair Francis #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 173e8e49943SAlistair Francis 174e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 175e8e49943SAlistair Francis #define GEM_ST1R_DSTC_ENABLE (1 << 28) 176e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 177e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 178e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 179e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 180e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_SHIFT (0) 181e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 182e8e49943SAlistair Francis 183e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 184e8e49943SAlistair Francis 185e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 186e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_SHIFT (13) 187e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 188e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 189e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 190e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 191e8e49943SAlistair Francis + 1) 192e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_SHIFT (0) 193e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 194e8e49943SAlistair Francis 195e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 196e8e49943SAlistair Francis #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 197e8e49943SAlistair Francis 198e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 199e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 200e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 201e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 202e8e49943SAlistair Francis 20349ab747fSPaolo Bonzini /*****************************************/ 20449ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 20549ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 20649ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 20749ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 20849ab747fSPaolo Bonzini 20949ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2103048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 21149ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 21249ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 21349ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 21449ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 21549ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 21649ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 21749ab747fSPaolo Bonzini 218e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 219e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 220e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2212801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 22249ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 22349ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 22449ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 22549ab747fSPaolo Bonzini 22649ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 22749ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 22849ab747fSPaolo Bonzini 22949ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 23049ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 23149ab747fSPaolo Bonzini 23249ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 23349ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 23449ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 23549ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 23649ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 23749ab747fSPaolo Bonzini 23849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 23949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 24049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 24149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 24249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 24349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 24449ab747fSPaolo Bonzini 24549ab747fSPaolo Bonzini /* Marvell PHY definitions */ 24649ab747fSPaolo Bonzini #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 24749ab747fSPaolo Bonzini 24849ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 24949ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 25049ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 25149ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 25249ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 25349ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 25449ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 25549ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 25649ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 25749ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 25849ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 25949ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 26049ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 26149ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 26249ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 26349ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 26449ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 26549ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 26649ab747fSPaolo Bonzini #define PHY_REG_EACD 22 26749ab747fSPaolo Bonzini #define PHY_REG_LED 24 26849ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 26949ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 27049ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 27149ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 27249ab747fSPaolo Bonzini 27349ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 27449ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 27549ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 2766623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 27749ab747fSPaolo Bonzini 27849ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 27949ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 28049ab747fSPaolo Bonzini 28149ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 28249ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 28349ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 28449ab747fSPaolo Bonzini 28549ab747fSPaolo Bonzini /***********************************************************************/ 28663af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 28763af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 28863af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 28963af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 29063af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 29163af1e0cSPeter Crosthwaite 29263af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 29349ab747fSPaolo Bonzini 29449ab747fSPaolo Bonzini /***********************************************************************/ 29549ab747fSPaolo Bonzini 29649ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 29749ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 29849ab747fSPaolo Bonzini 29949ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 30049ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 30149ab747fSPaolo Bonzini 30249ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 30349ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 30449ab747fSPaolo Bonzini 30563af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 30663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 307a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 30863af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 30963af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 31063af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 31163af1e0cSPeter Crosthwaite 31249ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 31349ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 31449ab747fSPaolo Bonzini 315a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 316a5517666SAlistair Francis 317e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 31849ab747fSPaolo Bonzini { 319e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 320e48fdd9dSEdgar E. Iglesias 321e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 322e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 323e48fdd9dSEdgar E. Iglesias } 324e48fdd9dSEdgar E. Iglesias return ret; 32549ab747fSPaolo Bonzini } 32649ab747fSPaolo Bonzini 327f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 32849ab747fSPaolo Bonzini { 32949ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 33049ab747fSPaolo Bonzini } 33149ab747fSPaolo Bonzini 332f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 33349ab747fSPaolo Bonzini { 33449ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 33549ab747fSPaolo Bonzini } 33649ab747fSPaolo Bonzini 337f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 33849ab747fSPaolo Bonzini { 33949ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 34049ab747fSPaolo Bonzini } 34149ab747fSPaolo Bonzini 342f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 34349ab747fSPaolo Bonzini { 34449ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 34549ab747fSPaolo Bonzini } 34649ab747fSPaolo Bonzini 347f0236182SEdgar E. Iglesias static inline void tx_desc_set_last(uint32_t *desc) 348cbdab58dSAlistair Francis { 349cbdab58dSAlistair Francis desc[1] |= DESC_1_TX_LAST; 350cbdab58dSAlistair Francis } 351cbdab58dSAlistair Francis 352f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 35349ab747fSPaolo Bonzini { 35449ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 35549ab747fSPaolo Bonzini } 35649ab747fSPaolo Bonzini 357f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 35849ab747fSPaolo Bonzini { 35967101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 36049ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 36149ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 36249ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 36349ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 36449ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 36549ab747fSPaolo Bonzini } 36649ab747fSPaolo Bonzini 367e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 36849ab747fSPaolo Bonzini { 369e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 370e48fdd9dSEdgar E. Iglesias 371e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 372e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 373e48fdd9dSEdgar E. Iglesias } 374e48fdd9dSEdgar E. Iglesias return ret; 375e48fdd9dSEdgar E. Iglesias } 376e48fdd9dSEdgar E. Iglesias 377e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 378e48fdd9dSEdgar E. Iglesias { 379e48fdd9dSEdgar E. Iglesias int ret = 2; 380e48fdd9dSEdgar E. Iglesias 381e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 382e48fdd9dSEdgar E. Iglesias ret += 2; 383e48fdd9dSEdgar E. Iglesias } 384e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 385e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 386e48fdd9dSEdgar E. Iglesias ret += 2; 387e48fdd9dSEdgar E. Iglesias } 388e48fdd9dSEdgar E. Iglesias 389e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 390e48fdd9dSEdgar E. Iglesias return ret; 39149ab747fSPaolo Bonzini } 39249ab747fSPaolo Bonzini 393f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 39449ab747fSPaolo Bonzini { 39549ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 39649ab747fSPaolo Bonzini } 39749ab747fSPaolo Bonzini 398f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 39949ab747fSPaolo Bonzini { 40049ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 40149ab747fSPaolo Bonzini } 40249ab747fSPaolo Bonzini 403f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 40449ab747fSPaolo Bonzini { 40549ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 40649ab747fSPaolo Bonzini } 40749ab747fSPaolo Bonzini 408f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 40949ab747fSPaolo Bonzini { 41049ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 41149ab747fSPaolo Bonzini } 41249ab747fSPaolo Bonzini 41359ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 41459ab136aSRamon Fried { 41559ab136aSRamon Fried desc[1] = 0; 41659ab136aSRamon Fried } 41759ab136aSRamon Fried 418f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 41949ab747fSPaolo Bonzini { 42049ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 42149ab747fSPaolo Bonzini } 42249ab747fSPaolo Bonzini 423f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 42449ab747fSPaolo Bonzini { 42549ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 42649ab747fSPaolo Bonzini desc[1] |= len; 42749ab747fSPaolo Bonzini } 42849ab747fSPaolo Bonzini 429f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 43063af1e0cSPeter Crosthwaite { 43163af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 43263af1e0cSPeter Crosthwaite } 43363af1e0cSPeter Crosthwaite 434f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 43563af1e0cSPeter Crosthwaite { 43663af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 43763af1e0cSPeter Crosthwaite } 43863af1e0cSPeter Crosthwaite 439f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 44063af1e0cSPeter Crosthwaite { 44163af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 44263af1e0cSPeter Crosthwaite } 44363af1e0cSPeter Crosthwaite 444f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 44563af1e0cSPeter Crosthwaite { 44663af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 44763af1e0cSPeter Crosthwaite sar_idx); 448a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 44963af1e0cSPeter Crosthwaite } 45063af1e0cSPeter Crosthwaite 45149ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4526a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 45349ab747fSPaolo Bonzini 454*68dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 455*68dbee3bSSai Pavan Boddu { 456*68dbee3bSSai Pavan Boddu if (q == 0) { 457*68dbee3bSSai Pavan Boddu s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]); 458*68dbee3bSSai Pavan Boddu } else { 459*68dbee3bSSai Pavan Boddu s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag & 460*68dbee3bSSai Pavan Boddu ~(s->regs[GEM_INT_Q1_MASK + q - 1]); 461*68dbee3bSSai Pavan Boddu } 462*68dbee3bSSai Pavan Boddu } 463*68dbee3bSSai Pavan Boddu 46449ab747fSPaolo Bonzini /* 46549ab747fSPaolo Bonzini * gem_init_register_masks: 46649ab747fSPaolo Bonzini * One time initialization. 46749ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 46849ab747fSPaolo Bonzini */ 469448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 47049ab747fSPaolo Bonzini { 4714c70e32fSSai Pavan Boddu unsigned int i; 47249ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 47349ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 47449ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 47549ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 476e48fdd9dSEdgar E. Iglesias s->regs_ro[GEM_DMACFG] = 0x8E00F000; 47749ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 47849ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 47949ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 48049ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 48149ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 48249ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 48349ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 4844c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 4854c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF; 4864c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319; 4874c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319; 4884c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF; 4894c70e32fSSai Pavan Boddu } 49049ab747fSPaolo Bonzini 49149ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 49249ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 49349ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 4944c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 4954c70e32fSSai Pavan Boddu s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6; 4964c70e32fSSai Pavan Boddu } 49749ab747fSPaolo Bonzini 49849ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 49949ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 50049ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 50149ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 50249ab747fSPaolo Bonzini 50349ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 50449ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 50549ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 50649ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 50749ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 5084c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 5094c70e32fSSai Pavan Boddu s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6; 5104c70e32fSSai Pavan Boddu s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6; 5114c70e32fSSai Pavan Boddu } 51249ab747fSPaolo Bonzini } 51349ab747fSPaolo Bonzini 51449ab747fSPaolo Bonzini /* 51549ab747fSPaolo Bonzini * phy_update_link: 51649ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 51749ab747fSPaolo Bonzini */ 518448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 51949ab747fSPaolo Bonzini { 52049ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 52149ab747fSPaolo Bonzini 52249ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 52349ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 52449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 52549ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 52649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 52749ab747fSPaolo Bonzini } else { 52849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 52949ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 53049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 53149ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 53249ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 53349ab747fSPaolo Bonzini } 53449ab747fSPaolo Bonzini } 53549ab747fSPaolo Bonzini 536b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 53749ab747fSPaolo Bonzini { 538448f19e2SPeter Crosthwaite CadenceGEMState *s; 53967101725SAlistair Francis int i; 54049ab747fSPaolo Bonzini 54149ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 54249ab747fSPaolo Bonzini 54349ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 54449ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 5453ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 5463ae5725fSPeter Crosthwaite s->can_rx_state = 1; 5473ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 5483ae5725fSPeter Crosthwaite } 549b8c4b67eSPhilippe Mathieu-Daudé return false; 55049ab747fSPaolo Bonzini } 55149ab747fSPaolo Bonzini 55267101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 553dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 554dacc0566SAlistair Francis break; 555dacc0566SAlistair Francis } 556dacc0566SAlistair Francis }; 557dacc0566SAlistair Francis 558dacc0566SAlistair Francis if (i == s->num_priority_queues) { 5598202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 5608202aa53SPeter Crosthwaite s->can_rx_state = 2; 561dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 5628202aa53SPeter Crosthwaite } 563b8c4b67eSPhilippe Mathieu-Daudé return false; 5648202aa53SPeter Crosthwaite } 5658202aa53SPeter Crosthwaite 5663ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 5673ae5725fSPeter Crosthwaite s->can_rx_state = 0; 56867101725SAlistair Francis DB_PRINT("can receive\n"); 5693ae5725fSPeter Crosthwaite } 570b8c4b67eSPhilippe Mathieu-Daudé return true; 57149ab747fSPaolo Bonzini } 57249ab747fSPaolo Bonzini 57349ab747fSPaolo Bonzini /* 57449ab747fSPaolo Bonzini * gem_update_int_status: 57549ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 57649ab747fSPaolo Bonzini */ 577448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 57849ab747fSPaolo Bonzini { 57967101725SAlistair Francis int i; 58067101725SAlistair Francis 58186a29d4cSSai Pavan Boddu qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]); 582596b6f51SAlistair Francis 58386a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 58486a29d4cSSai Pavan Boddu qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]); 58549ab747fSPaolo Bonzini } 58649ab747fSPaolo Bonzini } 58749ab747fSPaolo Bonzini 58849ab747fSPaolo Bonzini /* 58949ab747fSPaolo Bonzini * gem_receive_updatestats: 59049ab747fSPaolo Bonzini * Increment receive statistics. 59149ab747fSPaolo Bonzini */ 592448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 59349ab747fSPaolo Bonzini unsigned bytes) 59449ab747fSPaolo Bonzini { 59549ab747fSPaolo Bonzini uint64_t octets; 59649ab747fSPaolo Bonzini 59749ab747fSPaolo Bonzini /* Total octets (bytes) received */ 59849ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 59949ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 60049ab747fSPaolo Bonzini octets += bytes; 60149ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 60249ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 60349ab747fSPaolo Bonzini 60449ab747fSPaolo Bonzini /* Error-free Frames received */ 60549ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 60649ab747fSPaolo Bonzini 60749ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 60849ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 60949ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 61049ab747fSPaolo Bonzini } 61149ab747fSPaolo Bonzini 61249ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 61349ab747fSPaolo Bonzini if (packet[0] == 0x01) { 61449ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 61549ab747fSPaolo Bonzini } 61649ab747fSPaolo Bonzini 61749ab747fSPaolo Bonzini if (bytes <= 64) { 61849ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 61949ab747fSPaolo Bonzini } else if (bytes <= 127) { 62049ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 62149ab747fSPaolo Bonzini } else if (bytes <= 255) { 62249ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 62349ab747fSPaolo Bonzini } else if (bytes <= 511) { 62449ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 62549ab747fSPaolo Bonzini } else if (bytes <= 1023) { 62649ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 62749ab747fSPaolo Bonzini } else if (bytes <= 1518) { 62849ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 62949ab747fSPaolo Bonzini } else { 63049ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 63149ab747fSPaolo Bonzini } 63249ab747fSPaolo Bonzini } 63349ab747fSPaolo Bonzini 63449ab747fSPaolo Bonzini /* 63549ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 63649ab747fSPaolo Bonzini */ 63749ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 63849ab747fSPaolo Bonzini { 63949ab747fSPaolo Bonzini unsigned byte; 64049ab747fSPaolo Bonzini 64149ab747fSPaolo Bonzini byte = mac[bit / 8]; 64249ab747fSPaolo Bonzini byte >>= (bit & 0x7); 64349ab747fSPaolo Bonzini byte &= 1; 64449ab747fSPaolo Bonzini 64549ab747fSPaolo Bonzini return byte; 64649ab747fSPaolo Bonzini } 64749ab747fSPaolo Bonzini 64849ab747fSPaolo Bonzini /* 64949ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 65049ab747fSPaolo Bonzini */ 65149ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 65249ab747fSPaolo Bonzini { 65349ab747fSPaolo Bonzini int index_bit, mac_bit; 65449ab747fSPaolo Bonzini unsigned hash_index; 65549ab747fSPaolo Bonzini 65649ab747fSPaolo Bonzini hash_index = 0; 65749ab747fSPaolo Bonzini mac_bit = 5; 65849ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 65949ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 66049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 66149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 66249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 66349ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 66449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 66549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 66649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 66749ab747fSPaolo Bonzini mac_bit--; 66849ab747fSPaolo Bonzini } 66949ab747fSPaolo Bonzini 67049ab747fSPaolo Bonzini return hash_index; 67149ab747fSPaolo Bonzini } 67249ab747fSPaolo Bonzini 67349ab747fSPaolo Bonzini /* 67449ab747fSPaolo Bonzini * gem_mac_address_filter: 67549ab747fSPaolo Bonzini * Accept or reject this destination address? 67649ab747fSPaolo Bonzini * Returns: 67749ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 67863af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 67963af1e0cSPeter Crosthwaite * others for various other modes of accept: 68063af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 68163af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 68249ab747fSPaolo Bonzini */ 683448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 68449ab747fSPaolo Bonzini { 68549ab747fSPaolo Bonzini uint8_t *gem_spaddr; 68649ab747fSPaolo Bonzini int i; 68749ab747fSPaolo Bonzini 68849ab747fSPaolo Bonzini /* Promiscuous mode? */ 68949ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 69063af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 69149ab747fSPaolo Bonzini } 69249ab747fSPaolo Bonzini 69349ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 69449ab747fSPaolo Bonzini /* Reject broadcast packets? */ 69549ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 69649ab747fSPaolo Bonzini return GEM_RX_REJECT; 69749ab747fSPaolo Bonzini } 69863af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 69949ab747fSPaolo Bonzini } 70049ab747fSPaolo Bonzini 70149ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 70249ab747fSPaolo Bonzini if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 70349ab747fSPaolo Bonzini (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 70449ab747fSPaolo Bonzini unsigned hash_index; 70549ab747fSPaolo Bonzini 70649ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 70749ab747fSPaolo Bonzini if (hash_index < 32) { 70849ab747fSPaolo Bonzini if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 70963af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 71063af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 71149ab747fSPaolo Bonzini } 71249ab747fSPaolo Bonzini } else { 71349ab747fSPaolo Bonzini hash_index -= 32; 71449ab747fSPaolo Bonzini if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 71563af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 71663af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 71749ab747fSPaolo Bonzini } 71849ab747fSPaolo Bonzini } 71949ab747fSPaolo Bonzini } 72049ab747fSPaolo Bonzini 72149ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 72249ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 72363af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 72464eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 72563af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 72649ab747fSPaolo Bonzini } 72749ab747fSPaolo Bonzini } 72849ab747fSPaolo Bonzini 72949ab747fSPaolo Bonzini /* No address match; reject the packet */ 73049ab747fSPaolo Bonzini return GEM_RX_REJECT; 73149ab747fSPaolo Bonzini } 73249ab747fSPaolo Bonzini 733e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 734e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 735e8e49943SAlistair Francis unsigned rxbufsize) 736e8e49943SAlistair Francis { 737e8e49943SAlistair Francis uint32_t reg; 738e8e49943SAlistair Francis bool matched, mismatched; 739e8e49943SAlistair Francis int i, j; 740e8e49943SAlistair Francis 741e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 742e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 743e8e49943SAlistair Francis matched = false; 744e8e49943SAlistair Francis mismatched = false; 745e8e49943SAlistair Francis 746e8e49943SAlistair Francis /* Screening is based on UDP Port */ 747e8e49943SAlistair Francis if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 748e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 749e8e49943SAlistair Francis if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 750e8e49943SAlistair Francis GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 751e8e49943SAlistair Francis matched = true; 752e8e49943SAlistair Francis } else { 753e8e49943SAlistair Francis mismatched = true; 754e8e49943SAlistair Francis } 755e8e49943SAlistair Francis } 756e8e49943SAlistair Francis 757e8e49943SAlistair Francis /* Screening is based on DS/TC */ 758e8e49943SAlistair Francis if (reg & GEM_ST1R_DSTC_ENABLE) { 759e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 760e8e49943SAlistair Francis if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 761e8e49943SAlistair Francis GEM_ST1R_DSTC_MATCH_WIDTH)) { 762e8e49943SAlistair Francis matched = true; 763e8e49943SAlistair Francis } else { 764e8e49943SAlistair Francis mismatched = true; 765e8e49943SAlistair Francis } 766e8e49943SAlistair Francis } 767e8e49943SAlistair Francis 768e8e49943SAlistair Francis if (matched && !mismatched) { 769e8e49943SAlistair Francis return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 770e8e49943SAlistair Francis } 771e8e49943SAlistair Francis } 772e8e49943SAlistair Francis 773e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 774e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 775e8e49943SAlistair Francis matched = false; 776e8e49943SAlistair Francis mismatched = false; 777e8e49943SAlistair Francis 778e8e49943SAlistair Francis if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 779e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 780e8e49943SAlistair Francis int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 781e8e49943SAlistair Francis GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 782e8e49943SAlistair Francis 783e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 784e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 785e8e49943SAlistair Francis "register index: %d\n", et_idx); 786e8e49943SAlistair Francis } 787e8e49943SAlistair Francis if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 788e8e49943SAlistair Francis et_idx]) { 789e8e49943SAlistair Francis matched = true; 790e8e49943SAlistair Francis } else { 791e8e49943SAlistair Francis mismatched = true; 792e8e49943SAlistair Francis } 793e8e49943SAlistair Francis } 794e8e49943SAlistair Francis 795e8e49943SAlistair Francis /* Compare A, B, C */ 796e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 797e8e49943SAlistair Francis uint32_t cr0, cr1, mask; 798e8e49943SAlistair Francis uint16_t rx_cmp; 799e8e49943SAlistair Francis int offset; 800e8e49943SAlistair Francis int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 801e8e49943SAlistair Francis GEM_ST2R_COMPARE_WIDTH); 802e8e49943SAlistair Francis 803e8e49943SAlistair Francis if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 804e8e49943SAlistair Francis continue; 805e8e49943SAlistair Francis } 806e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 807e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 808e8e49943SAlistair Francis "register index: %d\n", cr_idx); 809e8e49943SAlistair Francis } 810e8e49943SAlistair Francis 811e8e49943SAlistair Francis cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 812e8e49943SAlistair Francis cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 813e8e49943SAlistair Francis offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 814e8e49943SAlistair Francis GEM_T2CW1_OFFSET_VALUE_WIDTH); 815e8e49943SAlistair Francis 816e8e49943SAlistair Francis switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 817e8e49943SAlistair Francis GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 818e8e49943SAlistair Francis case 3: /* Skip UDP header */ 819e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 820e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 821e8e49943SAlistair Francis offset += 8; 822e8e49943SAlistair Francis /* Fallthrough */ 823e8e49943SAlistair Francis case 2: /* skip the IP header */ 824e8e49943SAlistair Francis offset += 20; 825e8e49943SAlistair Francis /* Fallthrough */ 826e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 827e8e49943SAlistair Francis offset += 14; 828e8e49943SAlistair Francis break; 829e8e49943SAlistair Francis case 0: 830e8e49943SAlistair Francis /* Offset from start of frame */ 831e8e49943SAlistair Francis break; 832e8e49943SAlistair Francis } 833e8e49943SAlistair Francis 834e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 835e8e49943SAlistair Francis mask = extract32(cr0, 0, 16); 836e8e49943SAlistair Francis 837e8e49943SAlistair Francis if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 838e8e49943SAlistair Francis matched = true; 839e8e49943SAlistair Francis } else { 840e8e49943SAlistair Francis mismatched = true; 841e8e49943SAlistair Francis } 842e8e49943SAlistair Francis } 843e8e49943SAlistair Francis 844e8e49943SAlistair Francis if (matched && !mismatched) { 845e8e49943SAlistair Francis return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 846e8e49943SAlistair Francis } 847e8e49943SAlistair Francis } 848e8e49943SAlistair Francis 849e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 850e8e49943SAlistair Francis return 0; 851e8e49943SAlistair Francis } 852e8e49943SAlistair Francis 85396ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 85496ea126aSSai Pavan Boddu { 85596ea126aSSai Pavan Boddu uint32_t base_addr = 0; 85696ea126aSSai Pavan Boddu 85796ea126aSSai Pavan Boddu switch (q) { 85896ea126aSSai Pavan Boddu case 0: 85996ea126aSSai Pavan Boddu base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE]; 86096ea126aSSai Pavan Boddu break; 86196ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 86296ea126aSSai Pavan Boddu base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR : 86396ea126aSSai Pavan Boddu GEM_RECEIVE_Q1_PTR) + q - 1]; 86496ea126aSSai Pavan Boddu break; 86596ea126aSSai Pavan Boddu default: 86696ea126aSSai Pavan Boddu g_assert_not_reached(); 86796ea126aSSai Pavan Boddu }; 86896ea126aSSai Pavan Boddu 86996ea126aSSai Pavan Boddu return base_addr; 87096ea126aSSai Pavan Boddu } 87196ea126aSSai Pavan Boddu 87296ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 87396ea126aSSai Pavan Boddu { 87496ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 87596ea126aSSai Pavan Boddu } 87696ea126aSSai Pavan Boddu 87796ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 87896ea126aSSai Pavan Boddu { 87996ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 88096ea126aSSai Pavan Boddu } 88196ea126aSSai Pavan Boddu 882357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 883357aa013SEdgar E. Iglesias { 884357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 885357aa013SEdgar E. Iglesias 886357aa013SEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 887357aa013SEdgar E. Iglesias desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; 888357aa013SEdgar E. Iglesias } 889357aa013SEdgar E. Iglesias desc_addr <<= 32; 890357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 891357aa013SEdgar E. Iglesias return desc_addr; 892357aa013SEdgar E. Iglesias } 893357aa013SEdgar E. Iglesias 894357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 895357aa013SEdgar E. Iglesias { 896357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 897357aa013SEdgar E. Iglesias } 898357aa013SEdgar E. Iglesias 899357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 900357aa013SEdgar E. Iglesias { 901357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 902357aa013SEdgar E. Iglesias } 903357aa013SEdgar E. Iglesias 90467101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 90506c2fe95SPeter Crosthwaite { 906357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 907357aa013SEdgar E. Iglesias 908357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 909357aa013SEdgar E. Iglesias 91006c2fe95SPeter Crosthwaite /* read current descriptor */ 911357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 912b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 913e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 91406c2fe95SPeter Crosthwaite 91506c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 91667101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 917357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 91806c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 919*68dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXUSED); 92006c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 92106c2fe95SPeter Crosthwaite gem_update_int_status(s); 92206c2fe95SPeter Crosthwaite } 92306c2fe95SPeter Crosthwaite } 92406c2fe95SPeter Crosthwaite 92549ab747fSPaolo Bonzini /* 92649ab747fSPaolo Bonzini * gem_receive: 92749ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 92849ab747fSPaolo Bonzini */ 92949ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 93049ab747fSPaolo Bonzini { 931448f19e2SPeter Crosthwaite CadenceGEMState *s; 93249ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 93349ab747fSPaolo Bonzini unsigned rxbuf_offset; 93449ab747fSPaolo Bonzini uint8_t rxbuf[2048]; 93549ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 9363b2c97f9SEdgar E. Iglesias bool first_desc = true; 93763af1e0cSPeter Crosthwaite int maf; 9382bf57f73SAlistair Francis int q = 0; 93949ab747fSPaolo Bonzini 94049ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 94149ab747fSPaolo Bonzini 94249ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 94363af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 94463af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 94549ab747fSPaolo Bonzini return -1; 94649ab747fSPaolo Bonzini } 94749ab747fSPaolo Bonzini 94849ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 94949ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 95049ab747fSPaolo Bonzini unsigned type_len; 95149ab747fSPaolo Bonzini 95249ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 95349ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 95449ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 95549ab747fSPaolo Bonzini if (type_len < 0x600) { 95649ab747fSPaolo Bonzini if (size < type_len) { 95749ab747fSPaolo Bonzini /* discard */ 95849ab747fSPaolo Bonzini return -1; 95949ab747fSPaolo Bonzini } 96049ab747fSPaolo Bonzini } 96149ab747fSPaolo Bonzini } 96249ab747fSPaolo Bonzini 96349ab747fSPaolo Bonzini /* 96449ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 96549ab747fSPaolo Bonzini */ 96649ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 96749ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 96849ab747fSPaolo Bonzini 96949ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 97049ab747fSPaolo Bonzini * buffers needed to hold this packet. 97149ab747fSPaolo Bonzini */ 97249ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 97349ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 97449ab747fSPaolo Bonzini bytes_to_copy = size; 97549ab747fSPaolo Bonzini 976f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 977f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 978f265ae8cSAlistair Francis */ 979f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 980f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 981f265ae8cSAlistair Francis } 982f265ae8cSAlistair Francis 983191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 984191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 985191946c5SPeter Crosthwaite * not FCS stripping 986191946c5SPeter Crosthwaite */ 987191946c5SPeter Crosthwaite if (size < 60) { 988191946c5SPeter Crosthwaite size = 60; 989191946c5SPeter Crosthwaite } 990191946c5SPeter Crosthwaite 99149ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 99249ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 99349ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 99449ab747fSPaolo Bonzini } else { 99549ab747fSPaolo Bonzini unsigned crc_val; 99649ab747fSPaolo Bonzini 997244381ecSPrasad J Pandit if (size > sizeof(rxbuf) - sizeof(crc_val)) { 998244381ecSPrasad J Pandit size = sizeof(rxbuf) - sizeof(crc_val); 999244381ecSPrasad J Pandit } 1000244381ecSPrasad J Pandit bytes_to_copy = size; 100149ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 10023048ed6aSPeter Crosthwaite * We must try and calculate one. 100349ab747fSPaolo Bonzini */ 100449ab747fSPaolo Bonzini 100549ab747fSPaolo Bonzini memcpy(rxbuf, buf, size); 100649ab747fSPaolo Bonzini memset(rxbuf + size, 0, sizeof(rxbuf) - size); 100749ab747fSPaolo Bonzini rxbuf_ptr = rxbuf; 100849ab747fSPaolo Bonzini crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 1009c94239feSPeter Maydell memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 101049ab747fSPaolo Bonzini 101149ab747fSPaolo Bonzini bytes_to_copy += 4; 101249ab747fSPaolo Bonzini size += 4; 101349ab747fSPaolo Bonzini } 101449ab747fSPaolo Bonzini 10156fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 101649ab747fSPaolo Bonzini 1017b12227afSStefan Weil /* Find which queue we are targeting */ 1018e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1019e8e49943SAlistair Francis 10207cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1021357aa013SEdgar E. Iglesias hwaddr desc_addr; 1022357aa013SEdgar E. Iglesias 102306c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 102406c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 102549ab747fSPaolo Bonzini return -1; 102649ab747fSPaolo Bonzini } 102749ab747fSPaolo Bonzini 10286fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1029dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1030dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 103149ab747fSPaolo Bonzini 103249ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 103384aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 10342bf57f73SAlistair Francis rxbuf_offset, 103584aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1036e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 103749ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 103830570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 10393b2c97f9SEdgar E. Iglesias 104059ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 104159ab136aSRamon Fried 10423b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 10433b2c97f9SEdgar E. Iglesias if (first_desc) { 10442bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 10453b2c97f9SEdgar E. Iglesias first_desc = false; 10463b2c97f9SEdgar E. Iglesias } 10473b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 10482bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 10492bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 10503b2c97f9SEdgar E. Iglesias } 10512bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 105263af1e0cSPeter Crosthwaite 105363af1e0cSPeter Crosthwaite switch (maf) { 105463af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 105563af1e0cSPeter Crosthwaite break; 105663af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 10572bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 105863af1e0cSPeter Crosthwaite break; 105963af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 10602bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 106163af1e0cSPeter Crosthwaite break; 106263af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 10632bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 106463af1e0cSPeter Crosthwaite break; 106563af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 106663af1e0cSPeter Crosthwaite abort(); 106763af1e0cSPeter Crosthwaite default: /* SAR */ 10682bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 106963af1e0cSPeter Crosthwaite } 107063af1e0cSPeter Crosthwaite 10713b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1072357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1073b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1074b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1075e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 10763b2c97f9SEdgar E. Iglesias 107749ab747fSPaolo Bonzini /* Next descriptor */ 10782bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 107949ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 108096ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 108149ab747fSPaolo Bonzini } else { 108249ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1083e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 108449ab747fSPaolo Bonzini } 108567101725SAlistair Francis 108667101725SAlistair Francis gem_get_rx_desc(s, q); 10877cfd65e4SPeter Crosthwaite } 108849ab747fSPaolo Bonzini 108949ab747fSPaolo Bonzini /* Count it */ 109049ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 109149ab747fSPaolo Bonzini 109249ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 1093*68dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXCMPL); 109449ab747fSPaolo Bonzini 109549ab747fSPaolo Bonzini /* Handle interrupt consequences */ 109649ab747fSPaolo Bonzini gem_update_int_status(s); 109749ab747fSPaolo Bonzini 109849ab747fSPaolo Bonzini return size; 109949ab747fSPaolo Bonzini } 110049ab747fSPaolo Bonzini 110149ab747fSPaolo Bonzini /* 110249ab747fSPaolo Bonzini * gem_transmit_updatestats: 110349ab747fSPaolo Bonzini * Increment transmit statistics. 110449ab747fSPaolo Bonzini */ 1105448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 110649ab747fSPaolo Bonzini unsigned bytes) 110749ab747fSPaolo Bonzini { 110849ab747fSPaolo Bonzini uint64_t octets; 110949ab747fSPaolo Bonzini 111049ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 111149ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 111249ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 111349ab747fSPaolo Bonzini octets += bytes; 111449ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 111549ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 111649ab747fSPaolo Bonzini 111749ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 111849ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 111949ab747fSPaolo Bonzini 112049ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 112149ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 112249ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 112349ab747fSPaolo Bonzini } 112449ab747fSPaolo Bonzini 112549ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 112649ab747fSPaolo Bonzini if (packet[0] == 0x01) { 112749ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 112849ab747fSPaolo Bonzini } 112949ab747fSPaolo Bonzini 113049ab747fSPaolo Bonzini if (bytes <= 64) { 113149ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 113249ab747fSPaolo Bonzini } else if (bytes <= 127) { 113349ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 113449ab747fSPaolo Bonzini } else if (bytes <= 255) { 113549ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 113649ab747fSPaolo Bonzini } else if (bytes <= 511) { 113749ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 113849ab747fSPaolo Bonzini } else if (bytes <= 1023) { 113949ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 114049ab747fSPaolo Bonzini } else if (bytes <= 1518) { 114149ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 114249ab747fSPaolo Bonzini } else { 114349ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 114449ab747fSPaolo Bonzini } 114549ab747fSPaolo Bonzini } 114649ab747fSPaolo Bonzini 114749ab747fSPaolo Bonzini /* 114849ab747fSPaolo Bonzini * gem_transmit: 114949ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 115049ab747fSPaolo Bonzini */ 1151448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 115249ab747fSPaolo Bonzini { 11538568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 115449ab747fSPaolo Bonzini hwaddr packet_desc_addr; 115549ab747fSPaolo Bonzini uint8_t tx_packet[2048]; 115649ab747fSPaolo Bonzini uint8_t *p; 115749ab747fSPaolo Bonzini unsigned total_bytes; 11582bf57f73SAlistair Francis int q = 0; 115949ab747fSPaolo Bonzini 116049ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 116149ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 116249ab747fSPaolo Bonzini return; 116349ab747fSPaolo Bonzini } 116449ab747fSPaolo Bonzini 116549ab747fSPaolo Bonzini DB_PRINT("\n"); 116649ab747fSPaolo Bonzini 11673048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 116849ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 116949ab747fSPaolo Bonzini * one contiguous buffer first. 117049ab747fSPaolo Bonzini */ 117149ab747fSPaolo Bonzini p = tx_packet; 117249ab747fSPaolo Bonzini total_bytes = 0; 117349ab747fSPaolo Bonzini 117467101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 117549ab747fSPaolo Bonzini /* read current descriptor */ 1176357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1177fa15286aSPeter Crosthwaite 1178fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 117984aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1180b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1181e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 118249ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 118349ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 118449ab747fSPaolo Bonzini 118549ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 118649ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 118749ab747fSPaolo Bonzini return; 118849ab747fSPaolo Bonzini } 118967101725SAlistair Francis print_gem_tx_desc(desc, q); 119049ab747fSPaolo Bonzini 119149ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 119249ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 119349ab747fSPaolo Bonzini */ 1194e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 119549ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 11966fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 11976fe7661dSSai Pavan Boddu packet_desc_addr); 119849ab747fSPaolo Bonzini break; 119949ab747fSPaolo Bonzini } 120049ab747fSPaolo Bonzini 120177524d11SAlistair Francis if (tx_desc_get_length(desc) > sizeof(tx_packet) - 120277524d11SAlistair Francis (p - tx_packet)) { 1203dda8f185SBin Meng DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \ 1204dda8f185SBin Meng " too large: size 0x%x space 0x%zx\n", 1205dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 1206d7f05365SMichael S. Tsirkin sizeof(tx_packet) - (p - tx_packet)); 1207d7f05365SMichael S. Tsirkin break; 1208d7f05365SMichael S. Tsirkin } 1209d7f05365SMichael S. Tsirkin 121077524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 121177524d11SAlistair Francis * contig buffer. 121249ab747fSPaolo Bonzini */ 121384aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 121484aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 121584aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 121649ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 121749ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 121849ab747fSPaolo Bonzini 121949ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 122049ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 12218568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1222357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 12236ab57a6bSPeter Crosthwaite 122449ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 122549ab747fSPaolo Bonzini * the processor. 122649ab747fSPaolo Bonzini */ 1227357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1228b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12296ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12306ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1231357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1232b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12336ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12343048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 123549ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 123696ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 123749ab747fSPaolo Bonzini } else { 1238e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1239e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 124049ab747fSPaolo Bonzini } 12412bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 124249ab747fSPaolo Bonzini 124349ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 1244*68dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_TXCMPL); 124567101725SAlistair Francis 124649ab747fSPaolo Bonzini /* Handle interrupt consequences */ 124749ab747fSPaolo Bonzini gem_update_int_status(s); 124849ab747fSPaolo Bonzini 124949ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 125049ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 125149ab747fSPaolo Bonzini net_checksum_calculate(tx_packet, total_bytes); 125249ab747fSPaolo Bonzini } 125349ab747fSPaolo Bonzini 125449ab747fSPaolo Bonzini /* Update MAC statistics */ 125549ab747fSPaolo Bonzini gem_transmit_updatestats(s, tx_packet, total_bytes); 125649ab747fSPaolo Bonzini 125749ab747fSPaolo Bonzini /* Send the packet somewhere */ 125877524d11SAlistair Francis if (s->phy_loop || (s->regs[GEM_NWCTRL] & 125977524d11SAlistair Francis GEM_NWCTRL_LOCALLOOP)) { 126077524d11SAlistair Francis gem_receive(qemu_get_queue(s->nic), tx_packet, 126177524d11SAlistair Francis total_bytes); 126249ab747fSPaolo Bonzini } else { 126349ab747fSPaolo Bonzini qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 126449ab747fSPaolo Bonzini total_bytes); 126549ab747fSPaolo Bonzini } 126649ab747fSPaolo Bonzini 126749ab747fSPaolo Bonzini /* Prepare for next packet */ 126849ab747fSPaolo Bonzini p = tx_packet; 126949ab747fSPaolo Bonzini total_bytes = 0; 127049ab747fSPaolo Bonzini } 127149ab747fSPaolo Bonzini 127249ab747fSPaolo Bonzini /* read next descriptor */ 127349ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1274cbdab58dSAlistair Francis tx_desc_set_last(desc); 1275f1e7cb13SRamon Fried 1276f1e7cb13SRamon Fried if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 1277f1e7cb13SRamon Fried packet_desc_addr = s->regs[GEM_TBQPH]; 1278f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1279f1e7cb13SRamon Fried } else { 1280f1e7cb13SRamon Fried packet_desc_addr = 0; 1281f1e7cb13SRamon Fried } 128296ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 128349ab747fSPaolo Bonzini } else { 1284e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 128549ab747fSPaolo Bonzini } 1286fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 128784aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1288b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1289e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 129049ab747fSPaolo Bonzini } 129149ab747fSPaolo Bonzini 129249ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 129349ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 1294*68dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 1295*68dbee3bSSai Pavan Boddu if (q == 0) { 1296*68dbee3bSSai Pavan Boddu gem_set_isr(s, 0, GEM_INT_TXUSED); 1297*68dbee3bSSai Pavan Boddu } 129849ab747fSPaolo Bonzini gem_update_int_status(s); 129949ab747fSPaolo Bonzini } 130049ab747fSPaolo Bonzini } 130167101725SAlistair Francis } 130249ab747fSPaolo Bonzini 1303448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 130449ab747fSPaolo Bonzini { 130549ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 130649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 130749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 130849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 130949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 131049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 131149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 131249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 131349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 131449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 131549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 131649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 131749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 131849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 13197777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 132049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 132149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 132249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 132349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 132449ab747fSPaolo Bonzini 132549ab747fSPaolo Bonzini phy_update_link(s); 132649ab747fSPaolo Bonzini } 132749ab747fSPaolo Bonzini 132849ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 132949ab747fSPaolo Bonzini { 133064eb9301SPeter Crosthwaite int i; 1331448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1332afb4c51fSSebastian Huber const uint8_t *a; 1333726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 133449ab747fSPaolo Bonzini 133549ab747fSPaolo Bonzini DB_PRINT("\n"); 133649ab747fSPaolo Bonzini 133749ab747fSPaolo Bonzini /* Set post reset register values */ 133849ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 133949ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 134049ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 134149ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 134249ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 134349ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 134449ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 134549ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1346a5517666SAlistair Francis s->regs[GEM_MODID] = s->revision; 134749ab747fSPaolo Bonzini s->regs[GEM_DESCONF] = 0x02500111; 134849ab747fSPaolo Bonzini s->regs[GEM_DESCONF2] = 0x2ab13fff; 1349b2d43091SEdgar E. Iglesias s->regs[GEM_DESCONF5] = 0x002f2045; 1350e2c0c4eeSEdgar E. Iglesias s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; 1351726a2a95SEdgar E. Iglesias 1352726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1353726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1354726a2a95SEdgar E. Iglesias s->regs[GEM_DESCONF6] |= queues_mask; 1355726a2a95SEdgar E. Iglesias } 135649ab747fSPaolo Bonzini 1357afb4c51fSSebastian Huber /* Set MAC address */ 1358afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1359afb4c51fSSebastian Huber s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1360afb4c51fSSebastian Huber s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1361afb4c51fSSebastian Huber 136264eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 136364eb9301SPeter Crosthwaite s->sar_active[i] = false; 136464eb9301SPeter Crosthwaite } 136564eb9301SPeter Crosthwaite 136649ab747fSPaolo Bonzini gem_phy_reset(s); 136749ab747fSPaolo Bonzini 136849ab747fSPaolo Bonzini gem_update_int_status(s); 136949ab747fSPaolo Bonzini } 137049ab747fSPaolo Bonzini 1371448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 137249ab747fSPaolo Bonzini { 137349ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 137449ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 137549ab747fSPaolo Bonzini } 137649ab747fSPaolo Bonzini 1377448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 137849ab747fSPaolo Bonzini { 137949ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 138049ab747fSPaolo Bonzini 138149ab747fSPaolo Bonzini switch (reg_num) { 138249ab747fSPaolo Bonzini case PHY_REG_CONTROL: 138349ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 138449ab747fSPaolo Bonzini /* Phy reset */ 138549ab747fSPaolo Bonzini gem_phy_reset(s); 138649ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 138749ab747fSPaolo Bonzini s->phy_loop = 0; 138849ab747fSPaolo Bonzini } 138949ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 139049ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 13916623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 139249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 139349ab747fSPaolo Bonzini } 139449ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 139549ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 139649ab747fSPaolo Bonzini s->phy_loop = 1; 139749ab747fSPaolo Bonzini } else { 139849ab747fSPaolo Bonzini s->phy_loop = 0; 139949ab747fSPaolo Bonzini } 140049ab747fSPaolo Bonzini break; 140149ab747fSPaolo Bonzini } 140249ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 140349ab747fSPaolo Bonzini } 140449ab747fSPaolo Bonzini 140549ab747fSPaolo Bonzini /* 140649ab747fSPaolo Bonzini * gem_read32: 140749ab747fSPaolo Bonzini * Read a GEM register. 140849ab747fSPaolo Bonzini */ 140949ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 141049ab747fSPaolo Bonzini { 1411448f19e2SPeter Crosthwaite CadenceGEMState *s; 141249ab747fSPaolo Bonzini uint32_t retval; 1413448f19e2SPeter Crosthwaite s = (CadenceGEMState *)opaque; 141449ab747fSPaolo Bonzini 141549ab747fSPaolo Bonzini offset >>= 2; 141649ab747fSPaolo Bonzini retval = s->regs[offset]; 141749ab747fSPaolo Bonzini 141849ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 141949ab747fSPaolo Bonzini 142049ab747fSPaolo Bonzini switch (offset) { 142149ab747fSPaolo Bonzini case GEM_ISR: 142267101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1423596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 142449ab747fSPaolo Bonzini break; 142549ab747fSPaolo Bonzini case GEM_PHYMNTNC: 142649ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 142749ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 142849ab747fSPaolo Bonzini 142949ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 143055389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 143149ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 143249ab747fSPaolo Bonzini retval &= 0xFFFF0000; 143349ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 143449ab747fSPaolo Bonzini } else { 143549ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 143649ab747fSPaolo Bonzini } 143749ab747fSPaolo Bonzini } 143849ab747fSPaolo Bonzini break; 143949ab747fSPaolo Bonzini } 144049ab747fSPaolo Bonzini 144149ab747fSPaolo Bonzini /* Squash read to clear bits */ 144249ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 144349ab747fSPaolo Bonzini 144449ab747fSPaolo Bonzini /* Do not provide write only bits */ 144549ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 144649ab747fSPaolo Bonzini 144749ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 144867101725SAlistair Francis gem_update_int_status(s); 144949ab747fSPaolo Bonzini return retval; 145049ab747fSPaolo Bonzini } 145149ab747fSPaolo Bonzini 145249ab747fSPaolo Bonzini /* 145349ab747fSPaolo Bonzini * gem_write32: 145449ab747fSPaolo Bonzini * Write a GEM register. 145549ab747fSPaolo Bonzini */ 145649ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 145749ab747fSPaolo Bonzini unsigned size) 145849ab747fSPaolo Bonzini { 1459448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 146049ab747fSPaolo Bonzini uint32_t readonly; 146167101725SAlistair Francis int i; 146249ab747fSPaolo Bonzini 146349ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 146449ab747fSPaolo Bonzini offset >>= 2; 146549ab747fSPaolo Bonzini 146649ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 146749ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1468e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1469e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 147049ab747fSPaolo Bonzini 147149ab747fSPaolo Bonzini /* Copy register write to backing store */ 1472e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1473e2314fdaSPeter Crosthwaite 1474e2314fdaSPeter Crosthwaite /* do w1c */ 1475e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 147649ab747fSPaolo Bonzini 147749ab747fSPaolo Bonzini /* Handle register write side effects */ 147849ab747fSPaolo Bonzini switch (offset) { 147949ab747fSPaolo Bonzini case GEM_NWCTRL: 148006c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 148167101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 148267101725SAlistair Francis gem_get_rx_desc(s, i); 148367101725SAlistair Francis } 148406c2fe95SPeter Crosthwaite } 148549ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 148649ab747fSPaolo Bonzini gem_transmit(s); 148749ab747fSPaolo Bonzini } 148849ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 148949ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 149067101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 149196ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 149267101725SAlistair Francis } 149349ab747fSPaolo Bonzini } 14948202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 149549ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 149649ab747fSPaolo Bonzini } 149749ab747fSPaolo Bonzini break; 149849ab747fSPaolo Bonzini 149949ab747fSPaolo Bonzini case GEM_TXSTATUS: 150049ab747fSPaolo Bonzini gem_update_int_status(s); 150149ab747fSPaolo Bonzini break; 150249ab747fSPaolo Bonzini case GEM_RXQBASE: 15032bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 150449ab747fSPaolo Bonzini break; 150579b2ac8fSAlistair Francis case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 150667101725SAlistair Francis s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 150767101725SAlistair Francis break; 150849ab747fSPaolo Bonzini case GEM_TXQBASE: 15092bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 151049ab747fSPaolo Bonzini break; 151179b2ac8fSAlistair Francis case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 151267101725SAlistair Francis s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 151367101725SAlistair Francis break; 151449ab747fSPaolo Bonzini case GEM_RXSTATUS: 151549ab747fSPaolo Bonzini gem_update_int_status(s); 151649ab747fSPaolo Bonzini break; 151749ab747fSPaolo Bonzini case GEM_IER: 151849ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 151949ab747fSPaolo Bonzini gem_update_int_status(s); 152049ab747fSPaolo Bonzini break; 152167101725SAlistair Francis case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 152267101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 152367101725SAlistair Francis gem_update_int_status(s); 152467101725SAlistair Francis break; 152549ab747fSPaolo Bonzini case GEM_IDR: 152649ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 152749ab747fSPaolo Bonzini gem_update_int_status(s); 152849ab747fSPaolo Bonzini break; 152967101725SAlistair Francis case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 153067101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 153167101725SAlistair Francis gem_update_int_status(s); 153267101725SAlistair Francis break; 153364eb9301SPeter Crosthwaite case GEM_SPADDR1LO: 153464eb9301SPeter Crosthwaite case GEM_SPADDR2LO: 153564eb9301SPeter Crosthwaite case GEM_SPADDR3LO: 153664eb9301SPeter Crosthwaite case GEM_SPADDR4LO: 153764eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 153864eb9301SPeter Crosthwaite break; 153964eb9301SPeter Crosthwaite case GEM_SPADDR1HI: 154064eb9301SPeter Crosthwaite case GEM_SPADDR2HI: 154164eb9301SPeter Crosthwaite case GEM_SPADDR3HI: 154264eb9301SPeter Crosthwaite case GEM_SPADDR4HI: 154364eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 154464eb9301SPeter Crosthwaite break; 154549ab747fSPaolo Bonzini case GEM_PHYMNTNC: 154649ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 154749ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 154849ab747fSPaolo Bonzini 154949ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 155055389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 155149ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 155249ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 155349ab747fSPaolo Bonzini } 155449ab747fSPaolo Bonzini } 155549ab747fSPaolo Bonzini break; 155649ab747fSPaolo Bonzini } 155749ab747fSPaolo Bonzini 155849ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 155949ab747fSPaolo Bonzini } 156049ab747fSPaolo Bonzini 156149ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 156249ab747fSPaolo Bonzini .read = gem_read, 156349ab747fSPaolo Bonzini .write = gem_write, 156449ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 156549ab747fSPaolo Bonzini }; 156649ab747fSPaolo Bonzini 156749ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 156849ab747fSPaolo Bonzini { 156967101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 157067101725SAlistair Francis 157149ab747fSPaolo Bonzini DB_PRINT("\n"); 157267101725SAlistair Francis phy_update_link(s); 157367101725SAlistair Francis gem_update_int_status(s); 157449ab747fSPaolo Bonzini } 157549ab747fSPaolo Bonzini 157649ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1577f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 157849ab747fSPaolo Bonzini .size = sizeof(NICState), 157949ab747fSPaolo Bonzini .can_receive = gem_can_receive, 158049ab747fSPaolo Bonzini .receive = gem_receive, 158149ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 158249ab747fSPaolo Bonzini }; 158349ab747fSPaolo Bonzini 1584bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 158549ab747fSPaolo Bonzini { 1586448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 158767101725SAlistair Francis int i; 158849ab747fSPaolo Bonzini 158984aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 159084aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 159184aec8efSEdgar E. Iglesias 15922bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 15932bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 15942bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 15952bf57f73SAlistair Francis s->num_priority_queues); 15962bf57f73SAlistair Francis return; 1597e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1598e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1599e8e49943SAlistair Francis s->num_type1_screeners); 1600e8e49943SAlistair Francis return; 1601e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1602e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1603e8e49943SAlistair Francis s->num_type2_screeners); 1604e8e49943SAlistair Francis return; 16052bf57f73SAlistair Francis } 16062bf57f73SAlistair Francis 160767101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 160867101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 160967101725SAlistair Francis } 1610bcb39a65SAlistair Francis 1611bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1612bcb39a65SAlistair Francis 1613bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1614bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 1615bcb39a65SAlistair Francis } 1616bcb39a65SAlistair Francis 1617bcb39a65SAlistair Francis static void gem_init(Object *obj) 1618bcb39a65SAlistair Francis { 1619bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1620bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1621bcb39a65SAlistair Francis 162249ab747fSPaolo Bonzini DB_PRINT("\n"); 162349ab747fSPaolo Bonzini 162449ab747fSPaolo Bonzini gem_init_register_masks(s); 1625eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1626eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 162749ab747fSPaolo Bonzini 1628bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 162984aec8efSEdgar E. Iglesias 163084aec8efSEdgar E. Iglesias object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 163184aec8efSEdgar E. Iglesias (Object **)&s->dma_mr, 163284aec8efSEdgar E. Iglesias qdev_prop_allow_set_link_before_realize, 1633d2623129SMarkus Armbruster OBJ_PROP_LINK_STRONG); 163449ab747fSPaolo Bonzini } 163549ab747fSPaolo Bonzini 163649ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 163749ab747fSPaolo Bonzini .name = "cadence_gem", 1638e8e49943SAlistair Francis .version_id = 4, 1639e8e49943SAlistair Francis .minimum_version_id = 4, 164049ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1641448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1642448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1643448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 16442bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 16452bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 16462bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 16472bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1648448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 164917cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 165049ab747fSPaolo Bonzini } 165149ab747fSPaolo Bonzini }; 165249ab747fSPaolo Bonzini 165349ab747fSPaolo Bonzini static Property gem_properties[] = { 1654448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1655a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1656a5517666SAlistair Francis GEM_MODID_VALUE), 16572bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 16582bf57f73SAlistair Francis num_priority_queues, 1), 1659e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1660e8e49943SAlistair Francis num_type1_screeners, 4), 1661e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1662e8e49943SAlistair Francis num_type2_screeners, 4), 166349ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 166449ab747fSPaolo Bonzini }; 166549ab747fSPaolo Bonzini 166649ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 166749ab747fSPaolo Bonzini { 166849ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 166949ab747fSPaolo Bonzini 1670bcb39a65SAlistair Francis dc->realize = gem_realize; 16714f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 167249ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 167349ab747fSPaolo Bonzini dc->reset = gem_reset; 167449ab747fSPaolo Bonzini } 167549ab747fSPaolo Bonzini 167649ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1677318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 167849ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1679448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1680bcb39a65SAlistair Francis .instance_init = gem_init, 1681318643beSAndreas Färber .class_init = gem_class_init, 168249ab747fSPaolo Bonzini }; 168349ab747fSPaolo Bonzini 168449ab747fSPaolo Bonzini static void gem_register_types(void) 168549ab747fSPaolo Bonzini { 168649ab747fSPaolo Bonzini type_register_static(&gem_info); 168749ab747fSPaolo Bonzini } 168849ab747fSPaolo Bonzini 168949ab747fSPaolo Bonzini type_init(gem_register_types) 1690