149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31d6454270SMarkus Armbruster #include "migration/vmstate.h" 322bf57f73SAlistair Francis #include "qapi/error.h" 33e8e49943SAlistair Francis #include "qemu/log.h" 340b8fa32fSMarkus Armbruster #include "qemu/module.h" 3584aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3649ab747fSPaolo Bonzini #include "net/checksum.h" 3749ab747fSPaolo Bonzini 386fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 3949ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 406fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 416fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 426fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 436fe7661dSSai Pavan Boddu } \ 442562755eSEric Blake } while (0) 4549ab747fSPaolo Bonzini 4649ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */ 4749ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */ 4849ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */ 4949ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C / 4) /* User IO reg */ 5049ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */ 5149ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */ 5249ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */ 5349ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */ 5449ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */ 5549ab747fSPaolo Bonzini #define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */ 5649ab747fSPaolo Bonzini #define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */ 5749ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */ 5849ab747fSPaolo Bonzini #define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */ 593048ed6aSPeter Crosthwaite #define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */ 6049ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */ 6149ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */ 6249ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */ 6349ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */ 64*7ca151c3SSai Pavan Boddu #define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size */ 6549ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */ 6649ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */ 6749ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */ 6849ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */ 6949ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */ 7049ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */ 7149ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */ 7249ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */ 7349ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */ 7449ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */ 7549ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */ 7649ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */ 7749ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */ 7849ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */ 7949ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */ 8049ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */ 8149ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */ 8249ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC / 4) /* Module ID reg */ 8349ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100 / 4) /* Octects transmitted Low reg */ 8449ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104 / 4) /* Octects transmitted High reg */ 8549ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted */ 8649ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */ 8749ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */ 8849ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted */ 8949ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */ 9049ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */ 9149ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */ 9249ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */ 9349ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */ 9449ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */ 9549ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519 TX */ 9649ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter */ 9749ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */ 9849ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames */ 9949ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames */ 10049ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */ 10149ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames */ 10249ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter */ 10349ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150 / 4) /* Octects Received register Low */ 10449ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154 / 4) /* Octects Received register High */ 10549ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */ 10649ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames RX */ 10749ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames RX */ 10849ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received Counter */ 10949ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX */ 11049ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX */ 11149ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames RX */ 11249ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames RX */ 11349ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B Frames RX */ 11449ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B Frames RX */ 11549ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames RX */ 11649ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received */ 11749ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */ 11849ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */ 11949ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter */ 12149ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */ 12249ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter */ 12349ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error Counter */ 12449ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */ 12588dba7edSSai Pavan Boddu #define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err Counter */ 12649ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error Counter */ 12749ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error Counter */ 12849ab747fSPaolo Bonzini 12949ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */ 13049ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */ 13149ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */ 13249ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */ 13349ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted (s) */ 13488dba7edSSai Pavan Boddu #define GEM_PTPETXNS (0x000001E4 / 4) /* 13588dba7edSSai Pavan Boddu * PTP Event Frame Transmitted (ns) 13688dba7edSSai Pavan Boddu */ 13749ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s) */ 13849ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received (ns) */ 13949ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s) */ 14049ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted (ns) */ 14149ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */ 14249ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns) */ 14349ab747fSPaolo Bonzini 14449ab747fSPaolo Bonzini /* Design Configuration Registers */ 14549ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280 / 4) 14649ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284 / 4) 14749ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288 / 4) 14849ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C / 4) 14949ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290 / 4) 15049ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294 / 4) 151e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 15249ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298 / 4) 15349ab747fSPaolo Bonzini 15467101725SAlistair Francis #define GEM_INT_Q1_STATUS (0x00000400 / 4) 15567101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 15667101725SAlistair Francis 15767101725SAlistair Francis #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 15879b2ac8fSAlistair Francis #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 15967101725SAlistair Francis 16067101725SAlistair Francis #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 16179b2ac8fSAlistair Francis #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 16267101725SAlistair Francis 163357aa013SEdgar E. Iglesias #define GEM_TBQPH (0x000004C8 / 4) 164357aa013SEdgar E. Iglesias #define GEM_RBQPH (0x000004D4 / 4) 165357aa013SEdgar E. Iglesias 16667101725SAlistair Francis #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 16767101725SAlistair Francis #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 16867101725SAlistair Francis 16967101725SAlistair Francis #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 17067101725SAlistair Francis #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 17167101725SAlistair Francis 17267101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 17367101725SAlistair Francis #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 17467101725SAlistair Francis 175e8e49943SAlistair Francis #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 176e8e49943SAlistair Francis 177e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 178e8e49943SAlistair Francis #define GEM_ST1R_DSTC_ENABLE (1 << 28) 179e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 180e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 181e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 182e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 183e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_SHIFT (0) 184e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 185e8e49943SAlistair Francis 186e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 187e8e49943SAlistair Francis 188e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 189e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_SHIFT (13) 190e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 191e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 192e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 193e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 194e8e49943SAlistair Francis + 1) 195e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_SHIFT (0) 196e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 197e8e49943SAlistair Francis 198e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 199e8e49943SAlistair Francis #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 200e8e49943SAlistair Francis 201e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 202e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 203e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 204e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 205e8e49943SAlistair Francis 20649ab747fSPaolo Bonzini /*****************************************/ 20749ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 20849ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 20949ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 21049ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 21149ab747fSPaolo Bonzini 21249ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2133048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 21449ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 21549ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 216*7ca151c3SSai Pavan Boddu #define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ 21749ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 21849ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 21949ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 22049ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 221*7ca151c3SSai Pavan Boddu #define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ 22249ab747fSPaolo Bonzini 223e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 224e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 225e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2262801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 22749ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 22849ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 22949ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 23049ab747fSPaolo Bonzini 23149ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 23249ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 23349ab747fSPaolo Bonzini 23449ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 23549ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 23649ab747fSPaolo Bonzini 23749ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 23849ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 239*7ca151c3SSai Pavan Boddu #define GEM_INT_AMBA_ERR 0x00000040 24049ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 24149ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 24249ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 24349ab747fSPaolo Bonzini 24449ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 24549ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 24649ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 24749ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 24849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 24949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 25049ab747fSPaolo Bonzini 25149ab747fSPaolo Bonzini /* Marvell PHY definitions */ 25249ab747fSPaolo Bonzini #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 25349ab747fSPaolo Bonzini 25449ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 25549ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 25649ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 25749ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 25849ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 25949ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 26049ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 26149ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 26249ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 26349ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 26449ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 26549ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 26649ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 26749ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 26849ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 26949ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 27049ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 27149ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 27249ab747fSPaolo Bonzini #define PHY_REG_EACD 22 27349ab747fSPaolo Bonzini #define PHY_REG_LED 24 27449ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 27549ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 27649ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 27749ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 27849ab747fSPaolo Bonzini 27949ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 28049ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 28149ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 2826623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 28349ab747fSPaolo Bonzini 28449ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 28549ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 28649ab747fSPaolo Bonzini 28749ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 28849ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 28949ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 29049ab747fSPaolo Bonzini 29149ab747fSPaolo Bonzini /***********************************************************************/ 29263af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 29363af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 29463af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 29563af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 29663af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 29763af1e0cSPeter Crosthwaite 29863af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 29949ab747fSPaolo Bonzini 30049ab747fSPaolo Bonzini /***********************************************************************/ 30149ab747fSPaolo Bonzini 30249ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 30349ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 30449ab747fSPaolo Bonzini 30549ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 30649ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 30749ab747fSPaolo Bonzini 30849ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 30949ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 31049ab747fSPaolo Bonzini 31163af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 31263af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 313a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 31463af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 31563af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 31663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 31763af1e0cSPeter Crosthwaite 31849ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 31949ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 32049ab747fSPaolo Bonzini 321a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 322a5517666SAlistair Francis 323e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 32449ab747fSPaolo Bonzini { 325e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 326e48fdd9dSEdgar E. Iglesias 327e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 328e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 329e48fdd9dSEdgar E. Iglesias } 330e48fdd9dSEdgar E. Iglesias return ret; 33149ab747fSPaolo Bonzini } 33249ab747fSPaolo Bonzini 333f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 33449ab747fSPaolo Bonzini { 33549ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 33649ab747fSPaolo Bonzini } 33749ab747fSPaolo Bonzini 338f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 33949ab747fSPaolo Bonzini { 34049ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 34149ab747fSPaolo Bonzini } 34249ab747fSPaolo Bonzini 343f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 34449ab747fSPaolo Bonzini { 34549ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 34649ab747fSPaolo Bonzini } 34749ab747fSPaolo Bonzini 348f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 34949ab747fSPaolo Bonzini { 35049ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 35149ab747fSPaolo Bonzini } 35249ab747fSPaolo Bonzini 353f0236182SEdgar E. Iglesias static inline void tx_desc_set_last(uint32_t *desc) 354cbdab58dSAlistair Francis { 355cbdab58dSAlistair Francis desc[1] |= DESC_1_TX_LAST; 356cbdab58dSAlistair Francis } 357cbdab58dSAlistair Francis 358f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 35949ab747fSPaolo Bonzini { 36049ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 36149ab747fSPaolo Bonzini } 36249ab747fSPaolo Bonzini 363f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 36449ab747fSPaolo Bonzini { 36567101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 36649ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 36749ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 36849ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 36949ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 37049ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 37149ab747fSPaolo Bonzini } 37249ab747fSPaolo Bonzini 373e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 37449ab747fSPaolo Bonzini { 375e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 376e48fdd9dSEdgar E. Iglesias 377e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 378e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 379e48fdd9dSEdgar E. Iglesias } 380e48fdd9dSEdgar E. Iglesias return ret; 381e48fdd9dSEdgar E. Iglesias } 382e48fdd9dSEdgar E. Iglesias 383e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 384e48fdd9dSEdgar E. Iglesias { 385e48fdd9dSEdgar E. Iglesias int ret = 2; 386e48fdd9dSEdgar E. Iglesias 387e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 388e48fdd9dSEdgar E. Iglesias ret += 2; 389e48fdd9dSEdgar E. Iglesias } 390e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 391e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 392e48fdd9dSEdgar E. Iglesias ret += 2; 393e48fdd9dSEdgar E. Iglesias } 394e48fdd9dSEdgar E. Iglesias 395e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 396e48fdd9dSEdgar E. Iglesias return ret; 39749ab747fSPaolo Bonzini } 39849ab747fSPaolo Bonzini 399f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 40049ab747fSPaolo Bonzini { 40149ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 40249ab747fSPaolo Bonzini } 40349ab747fSPaolo Bonzini 404f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 40549ab747fSPaolo Bonzini { 40649ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 40749ab747fSPaolo Bonzini } 40849ab747fSPaolo Bonzini 409f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 41049ab747fSPaolo Bonzini { 41149ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 41249ab747fSPaolo Bonzini } 41349ab747fSPaolo Bonzini 414f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 41549ab747fSPaolo Bonzini { 41649ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 41749ab747fSPaolo Bonzini } 41849ab747fSPaolo Bonzini 41959ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 42059ab136aSRamon Fried { 42159ab136aSRamon Fried desc[1] = 0; 42259ab136aSRamon Fried } 42359ab136aSRamon Fried 424f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 42549ab747fSPaolo Bonzini { 42649ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 42749ab747fSPaolo Bonzini } 42849ab747fSPaolo Bonzini 429f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 43049ab747fSPaolo Bonzini { 43149ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 43249ab747fSPaolo Bonzini desc[1] |= len; 43349ab747fSPaolo Bonzini } 43449ab747fSPaolo Bonzini 435f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 43663af1e0cSPeter Crosthwaite { 43763af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 43863af1e0cSPeter Crosthwaite } 43963af1e0cSPeter Crosthwaite 440f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 44163af1e0cSPeter Crosthwaite { 44263af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 44363af1e0cSPeter Crosthwaite } 44463af1e0cSPeter Crosthwaite 445f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 44663af1e0cSPeter Crosthwaite { 44763af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 44863af1e0cSPeter Crosthwaite } 44963af1e0cSPeter Crosthwaite 450f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 45163af1e0cSPeter Crosthwaite { 45263af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 45363af1e0cSPeter Crosthwaite sar_idx); 454a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 45563af1e0cSPeter Crosthwaite } 45663af1e0cSPeter Crosthwaite 45749ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4586a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 45949ab747fSPaolo Bonzini 460*7ca151c3SSai Pavan Boddu static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 461*7ca151c3SSai Pavan Boddu { 462*7ca151c3SSai Pavan Boddu uint32_t size; 463*7ca151c3SSai Pavan Boddu if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { 464*7ca151c3SSai Pavan Boddu size = s->regs[GEM_JUMBO_MAX_LEN]; 465*7ca151c3SSai Pavan Boddu if (size > s->jumbo_max_len) { 466*7ca151c3SSai Pavan Boddu size = s->jumbo_max_len; 467*7ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 468*7ca151c3SSai Pavan Boddu " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 469*7ca151c3SSai Pavan Boddu } 470*7ca151c3SSai Pavan Boddu } else if (tx) { 471*7ca151c3SSai Pavan Boddu size = 1518; 472*7ca151c3SSai Pavan Boddu } else { 473*7ca151c3SSai Pavan Boddu size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; 474*7ca151c3SSai Pavan Boddu } 475*7ca151c3SSai Pavan Boddu return size; 476*7ca151c3SSai Pavan Boddu } 477*7ca151c3SSai Pavan Boddu 47868dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 47968dbee3bSSai Pavan Boddu { 48068dbee3bSSai Pavan Boddu if (q == 0) { 48168dbee3bSSai Pavan Boddu s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]); 48268dbee3bSSai Pavan Boddu } else { 48368dbee3bSSai Pavan Boddu s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag & 48468dbee3bSSai Pavan Boddu ~(s->regs[GEM_INT_Q1_MASK + q - 1]); 48568dbee3bSSai Pavan Boddu } 48668dbee3bSSai Pavan Boddu } 48768dbee3bSSai Pavan Boddu 48849ab747fSPaolo Bonzini /* 48949ab747fSPaolo Bonzini * gem_init_register_masks: 49049ab747fSPaolo Bonzini * One time initialization. 49149ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 49249ab747fSPaolo Bonzini */ 493448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 49449ab747fSPaolo Bonzini { 4954c70e32fSSai Pavan Boddu unsigned int i; 49649ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 49749ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 49849ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 49949ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 500e48fdd9dSEdgar E. Iglesias s->regs_ro[GEM_DMACFG] = 0x8E00F000; 50149ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 50249ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 50349ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 50449ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 50549ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 50649ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 50749ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 5084c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 5094c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF; 5104c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319; 5114c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319; 5124c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF; 5134c70e32fSSai Pavan Boddu } 51449ab747fSPaolo Bonzini 51549ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 51649ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 51749ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 5184c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 5194c70e32fSSai Pavan Boddu s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6; 5204c70e32fSSai Pavan Boddu } 52149ab747fSPaolo Bonzini 52249ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 52349ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 52449ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 52549ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 52649ab747fSPaolo Bonzini 52749ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 52849ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 52949ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 53049ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 53149ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 5324c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 5334c70e32fSSai Pavan Boddu s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6; 5344c70e32fSSai Pavan Boddu s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6; 5354c70e32fSSai Pavan Boddu } 53649ab747fSPaolo Bonzini } 53749ab747fSPaolo Bonzini 53849ab747fSPaolo Bonzini /* 53949ab747fSPaolo Bonzini * phy_update_link: 54049ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 54149ab747fSPaolo Bonzini */ 542448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 54349ab747fSPaolo Bonzini { 54449ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 54549ab747fSPaolo Bonzini 54649ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 54749ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 54849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 54949ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 55049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 55149ab747fSPaolo Bonzini } else { 55249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 55349ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 55449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 55549ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 55649ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 55749ab747fSPaolo Bonzini } 55849ab747fSPaolo Bonzini } 55949ab747fSPaolo Bonzini 560b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 56149ab747fSPaolo Bonzini { 562448f19e2SPeter Crosthwaite CadenceGEMState *s; 56367101725SAlistair Francis int i; 56449ab747fSPaolo Bonzini 56549ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 56649ab747fSPaolo Bonzini 56749ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 56849ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 5693ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 5703ae5725fSPeter Crosthwaite s->can_rx_state = 1; 5713ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 5723ae5725fSPeter Crosthwaite } 573b8c4b67eSPhilippe Mathieu-Daudé return false; 57449ab747fSPaolo Bonzini } 57549ab747fSPaolo Bonzini 57667101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 577dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 578dacc0566SAlistair Francis break; 579dacc0566SAlistair Francis } 580dacc0566SAlistair Francis }; 581dacc0566SAlistair Francis 582dacc0566SAlistair Francis if (i == s->num_priority_queues) { 5838202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 5848202aa53SPeter Crosthwaite s->can_rx_state = 2; 585dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 5868202aa53SPeter Crosthwaite } 587b8c4b67eSPhilippe Mathieu-Daudé return false; 5888202aa53SPeter Crosthwaite } 5898202aa53SPeter Crosthwaite 5903ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 5913ae5725fSPeter Crosthwaite s->can_rx_state = 0; 59267101725SAlistair Francis DB_PRINT("can receive\n"); 5933ae5725fSPeter Crosthwaite } 594b8c4b67eSPhilippe Mathieu-Daudé return true; 59549ab747fSPaolo Bonzini } 59649ab747fSPaolo Bonzini 59749ab747fSPaolo Bonzini /* 59849ab747fSPaolo Bonzini * gem_update_int_status: 59949ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 60049ab747fSPaolo Bonzini */ 601448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 60249ab747fSPaolo Bonzini { 60367101725SAlistair Francis int i; 60467101725SAlistair Francis 60586a29d4cSSai Pavan Boddu qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]); 606596b6f51SAlistair Francis 60786a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 60886a29d4cSSai Pavan Boddu qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]); 60949ab747fSPaolo Bonzini } 61049ab747fSPaolo Bonzini } 61149ab747fSPaolo Bonzini 61249ab747fSPaolo Bonzini /* 61349ab747fSPaolo Bonzini * gem_receive_updatestats: 61449ab747fSPaolo Bonzini * Increment receive statistics. 61549ab747fSPaolo Bonzini */ 616448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 61749ab747fSPaolo Bonzini unsigned bytes) 61849ab747fSPaolo Bonzini { 61949ab747fSPaolo Bonzini uint64_t octets; 62049ab747fSPaolo Bonzini 62149ab747fSPaolo Bonzini /* Total octets (bytes) received */ 62249ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 62349ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 62449ab747fSPaolo Bonzini octets += bytes; 62549ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 62649ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 62749ab747fSPaolo Bonzini 62849ab747fSPaolo Bonzini /* Error-free Frames received */ 62949ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 63049ab747fSPaolo Bonzini 63149ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 63249ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 63349ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 63449ab747fSPaolo Bonzini } 63549ab747fSPaolo Bonzini 63649ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 63749ab747fSPaolo Bonzini if (packet[0] == 0x01) { 63849ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 63949ab747fSPaolo Bonzini } 64049ab747fSPaolo Bonzini 64149ab747fSPaolo Bonzini if (bytes <= 64) { 64249ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 64349ab747fSPaolo Bonzini } else if (bytes <= 127) { 64449ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 64549ab747fSPaolo Bonzini } else if (bytes <= 255) { 64649ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 64749ab747fSPaolo Bonzini } else if (bytes <= 511) { 64849ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 64949ab747fSPaolo Bonzini } else if (bytes <= 1023) { 65049ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 65149ab747fSPaolo Bonzini } else if (bytes <= 1518) { 65249ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 65349ab747fSPaolo Bonzini } else { 65449ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 65549ab747fSPaolo Bonzini } 65649ab747fSPaolo Bonzini } 65749ab747fSPaolo Bonzini 65849ab747fSPaolo Bonzini /* 65949ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 66049ab747fSPaolo Bonzini */ 66149ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 66249ab747fSPaolo Bonzini { 66349ab747fSPaolo Bonzini unsigned byte; 66449ab747fSPaolo Bonzini 66549ab747fSPaolo Bonzini byte = mac[bit / 8]; 66649ab747fSPaolo Bonzini byte >>= (bit & 0x7); 66749ab747fSPaolo Bonzini byte &= 1; 66849ab747fSPaolo Bonzini 66949ab747fSPaolo Bonzini return byte; 67049ab747fSPaolo Bonzini } 67149ab747fSPaolo Bonzini 67249ab747fSPaolo Bonzini /* 67349ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 67449ab747fSPaolo Bonzini */ 67549ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 67649ab747fSPaolo Bonzini { 67749ab747fSPaolo Bonzini int index_bit, mac_bit; 67849ab747fSPaolo Bonzini unsigned hash_index; 67949ab747fSPaolo Bonzini 68049ab747fSPaolo Bonzini hash_index = 0; 68149ab747fSPaolo Bonzini mac_bit = 5; 68249ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 68349ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 68449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 68549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 68649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 68749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 68849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 68949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 69049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 69149ab747fSPaolo Bonzini mac_bit--; 69249ab747fSPaolo Bonzini } 69349ab747fSPaolo Bonzini 69449ab747fSPaolo Bonzini return hash_index; 69549ab747fSPaolo Bonzini } 69649ab747fSPaolo Bonzini 69749ab747fSPaolo Bonzini /* 69849ab747fSPaolo Bonzini * gem_mac_address_filter: 69949ab747fSPaolo Bonzini * Accept or reject this destination address? 70049ab747fSPaolo Bonzini * Returns: 70149ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 70263af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 70363af1e0cSPeter Crosthwaite * others for various other modes of accept: 70463af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 70563af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 70649ab747fSPaolo Bonzini */ 707448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 70849ab747fSPaolo Bonzini { 70949ab747fSPaolo Bonzini uint8_t *gem_spaddr; 71049ab747fSPaolo Bonzini int i; 71149ab747fSPaolo Bonzini 71249ab747fSPaolo Bonzini /* Promiscuous mode? */ 71349ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 71463af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 71549ab747fSPaolo Bonzini } 71649ab747fSPaolo Bonzini 71749ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 71849ab747fSPaolo Bonzini /* Reject broadcast packets? */ 71949ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 72049ab747fSPaolo Bonzini return GEM_RX_REJECT; 72149ab747fSPaolo Bonzini } 72263af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 72349ab747fSPaolo Bonzini } 72449ab747fSPaolo Bonzini 72549ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 72649ab747fSPaolo Bonzini if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 72749ab747fSPaolo Bonzini (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 72849ab747fSPaolo Bonzini unsigned hash_index; 72949ab747fSPaolo Bonzini 73049ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 73149ab747fSPaolo Bonzini if (hash_index < 32) { 73249ab747fSPaolo Bonzini if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 73363af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 73463af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 73549ab747fSPaolo Bonzini } 73649ab747fSPaolo Bonzini } else { 73749ab747fSPaolo Bonzini hash_index -= 32; 73849ab747fSPaolo Bonzini if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 73963af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 74063af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 74149ab747fSPaolo Bonzini } 74249ab747fSPaolo Bonzini } 74349ab747fSPaolo Bonzini } 74449ab747fSPaolo Bonzini 74549ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 74649ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 74763af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 74864eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 74963af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 75049ab747fSPaolo Bonzini } 75149ab747fSPaolo Bonzini } 75249ab747fSPaolo Bonzini 75349ab747fSPaolo Bonzini /* No address match; reject the packet */ 75449ab747fSPaolo Bonzini return GEM_RX_REJECT; 75549ab747fSPaolo Bonzini } 75649ab747fSPaolo Bonzini 757e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 758e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 759e8e49943SAlistair Francis unsigned rxbufsize) 760e8e49943SAlistair Francis { 761e8e49943SAlistair Francis uint32_t reg; 762e8e49943SAlistair Francis bool matched, mismatched; 763e8e49943SAlistair Francis int i, j; 764e8e49943SAlistair Francis 765e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 766e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 767e8e49943SAlistair Francis matched = false; 768e8e49943SAlistair Francis mismatched = false; 769e8e49943SAlistair Francis 770e8e49943SAlistair Francis /* Screening is based on UDP Port */ 771e8e49943SAlistair Francis if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 772e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 773e8e49943SAlistair Francis if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 774e8e49943SAlistair Francis GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 775e8e49943SAlistair Francis matched = true; 776e8e49943SAlistair Francis } else { 777e8e49943SAlistair Francis mismatched = true; 778e8e49943SAlistair Francis } 779e8e49943SAlistair Francis } 780e8e49943SAlistair Francis 781e8e49943SAlistair Francis /* Screening is based on DS/TC */ 782e8e49943SAlistair Francis if (reg & GEM_ST1R_DSTC_ENABLE) { 783e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 784e8e49943SAlistair Francis if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 785e8e49943SAlistair Francis GEM_ST1R_DSTC_MATCH_WIDTH)) { 786e8e49943SAlistair Francis matched = true; 787e8e49943SAlistair Francis } else { 788e8e49943SAlistair Francis mismatched = true; 789e8e49943SAlistair Francis } 790e8e49943SAlistair Francis } 791e8e49943SAlistair Francis 792e8e49943SAlistair Francis if (matched && !mismatched) { 793e8e49943SAlistair Francis return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 794e8e49943SAlistair Francis } 795e8e49943SAlistair Francis } 796e8e49943SAlistair Francis 797e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 798e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 799e8e49943SAlistair Francis matched = false; 800e8e49943SAlistair Francis mismatched = false; 801e8e49943SAlistair Francis 802e8e49943SAlistair Francis if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 803e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 804e8e49943SAlistair Francis int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 805e8e49943SAlistair Francis GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 806e8e49943SAlistair Francis 807e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 808e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 809e8e49943SAlistair Francis "register index: %d\n", et_idx); 810e8e49943SAlistair Francis } 811e8e49943SAlistair Francis if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 812e8e49943SAlistair Francis et_idx]) { 813e8e49943SAlistair Francis matched = true; 814e8e49943SAlistair Francis } else { 815e8e49943SAlistair Francis mismatched = true; 816e8e49943SAlistair Francis } 817e8e49943SAlistair Francis } 818e8e49943SAlistair Francis 819e8e49943SAlistair Francis /* Compare A, B, C */ 820e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 821e8e49943SAlistair Francis uint32_t cr0, cr1, mask; 822e8e49943SAlistair Francis uint16_t rx_cmp; 823e8e49943SAlistair Francis int offset; 824e8e49943SAlistair Francis int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 825e8e49943SAlistair Francis GEM_ST2R_COMPARE_WIDTH); 826e8e49943SAlistair Francis 827e8e49943SAlistair Francis if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 828e8e49943SAlistair Francis continue; 829e8e49943SAlistair Francis } 830e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 831e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 832e8e49943SAlistair Francis "register index: %d\n", cr_idx); 833e8e49943SAlistair Francis } 834e8e49943SAlistair Francis 835e8e49943SAlistair Francis cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 836e8e49943SAlistair Francis cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 837e8e49943SAlistair Francis offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 838e8e49943SAlistair Francis GEM_T2CW1_OFFSET_VALUE_WIDTH); 839e8e49943SAlistair Francis 840e8e49943SAlistair Francis switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 841e8e49943SAlistair Francis GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 842e8e49943SAlistair Francis case 3: /* Skip UDP header */ 843e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 844e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 845e8e49943SAlistair Francis offset += 8; 846e8e49943SAlistair Francis /* Fallthrough */ 847e8e49943SAlistair Francis case 2: /* skip the IP header */ 848e8e49943SAlistair Francis offset += 20; 849e8e49943SAlistair Francis /* Fallthrough */ 850e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 851e8e49943SAlistair Francis offset += 14; 852e8e49943SAlistair Francis break; 853e8e49943SAlistair Francis case 0: 854e8e49943SAlistair Francis /* Offset from start of frame */ 855e8e49943SAlistair Francis break; 856e8e49943SAlistair Francis } 857e8e49943SAlistair Francis 858e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 859e8e49943SAlistair Francis mask = extract32(cr0, 0, 16); 860e8e49943SAlistair Francis 861e8e49943SAlistair Francis if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 862e8e49943SAlistair Francis matched = true; 863e8e49943SAlistair Francis } else { 864e8e49943SAlistair Francis mismatched = true; 865e8e49943SAlistair Francis } 866e8e49943SAlistair Francis } 867e8e49943SAlistair Francis 868e8e49943SAlistair Francis if (matched && !mismatched) { 869e8e49943SAlistair Francis return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 870e8e49943SAlistair Francis } 871e8e49943SAlistair Francis } 872e8e49943SAlistair Francis 873e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 874e8e49943SAlistair Francis return 0; 875e8e49943SAlistair Francis } 876e8e49943SAlistair Francis 87796ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 87896ea126aSSai Pavan Boddu { 87996ea126aSSai Pavan Boddu uint32_t base_addr = 0; 88096ea126aSSai Pavan Boddu 88196ea126aSSai Pavan Boddu switch (q) { 88296ea126aSSai Pavan Boddu case 0: 88396ea126aSSai Pavan Boddu base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE]; 88496ea126aSSai Pavan Boddu break; 88596ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 88696ea126aSSai Pavan Boddu base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR : 88796ea126aSSai Pavan Boddu GEM_RECEIVE_Q1_PTR) + q - 1]; 88896ea126aSSai Pavan Boddu break; 88996ea126aSSai Pavan Boddu default: 89096ea126aSSai Pavan Boddu g_assert_not_reached(); 89196ea126aSSai Pavan Boddu }; 89296ea126aSSai Pavan Boddu 89396ea126aSSai Pavan Boddu return base_addr; 89496ea126aSSai Pavan Boddu } 89596ea126aSSai Pavan Boddu 89696ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 89796ea126aSSai Pavan Boddu { 89896ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 89996ea126aSSai Pavan Boddu } 90096ea126aSSai Pavan Boddu 90196ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 90296ea126aSSai Pavan Boddu { 90396ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 90496ea126aSSai Pavan Boddu } 90596ea126aSSai Pavan Boddu 906357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 907357aa013SEdgar E. Iglesias { 908357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 909357aa013SEdgar E. Iglesias 910357aa013SEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 911357aa013SEdgar E. Iglesias desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; 912357aa013SEdgar E. Iglesias } 913357aa013SEdgar E. Iglesias desc_addr <<= 32; 914357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 915357aa013SEdgar E. Iglesias return desc_addr; 916357aa013SEdgar E. Iglesias } 917357aa013SEdgar E. Iglesias 918357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 919357aa013SEdgar E. Iglesias { 920357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 921357aa013SEdgar E. Iglesias } 922357aa013SEdgar E. Iglesias 923357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 924357aa013SEdgar E. Iglesias { 925357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 926357aa013SEdgar E. Iglesias } 927357aa013SEdgar E. Iglesias 92867101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 92906c2fe95SPeter Crosthwaite { 930357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 931357aa013SEdgar E. Iglesias 932357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 933357aa013SEdgar E. Iglesias 93406c2fe95SPeter Crosthwaite /* read current descriptor */ 935357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 936b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 937e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 93806c2fe95SPeter Crosthwaite 93906c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 94067101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 941357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 94206c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 94368dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXUSED); 94406c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 94506c2fe95SPeter Crosthwaite gem_update_int_status(s); 94606c2fe95SPeter Crosthwaite } 94706c2fe95SPeter Crosthwaite } 94806c2fe95SPeter Crosthwaite 94949ab747fSPaolo Bonzini /* 95049ab747fSPaolo Bonzini * gem_receive: 95149ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 95249ab747fSPaolo Bonzini */ 95349ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 95449ab747fSPaolo Bonzini { 95524d62fd5SSai Pavan Boddu CadenceGEMState *s = qemu_get_nic_opaque(nc); 95649ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 95749ab747fSPaolo Bonzini unsigned rxbuf_offset; 95849ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 9593b2c97f9SEdgar E. Iglesias bool first_desc = true; 96063af1e0cSPeter Crosthwaite int maf; 9612bf57f73SAlistair Francis int q = 0; 96249ab747fSPaolo Bonzini 96349ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 96463af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 96563af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 96649ab747fSPaolo Bonzini return -1; 96749ab747fSPaolo Bonzini } 96849ab747fSPaolo Bonzini 96949ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 97049ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 97149ab747fSPaolo Bonzini unsigned type_len; 97249ab747fSPaolo Bonzini 97349ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 97449ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 97549ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 97649ab747fSPaolo Bonzini if (type_len < 0x600) { 97749ab747fSPaolo Bonzini if (size < type_len) { 97849ab747fSPaolo Bonzini /* discard */ 97949ab747fSPaolo Bonzini return -1; 98049ab747fSPaolo Bonzini } 98149ab747fSPaolo Bonzini } 98249ab747fSPaolo Bonzini } 98349ab747fSPaolo Bonzini 98449ab747fSPaolo Bonzini /* 98549ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 98649ab747fSPaolo Bonzini */ 98749ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 98849ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 98949ab747fSPaolo Bonzini 99049ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 99149ab747fSPaolo Bonzini * buffers needed to hold this packet. 99249ab747fSPaolo Bonzini */ 99349ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 99449ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 99549ab747fSPaolo Bonzini bytes_to_copy = size; 99649ab747fSPaolo Bonzini 997f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 998f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 999f265ae8cSAlistair Francis */ 1000f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1001f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1002f265ae8cSAlistair Francis } 1003f265ae8cSAlistair Francis 1004191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 1005191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 1006191946c5SPeter Crosthwaite * not FCS stripping 1007191946c5SPeter Crosthwaite */ 1008191946c5SPeter Crosthwaite if (size < 60) { 1009191946c5SPeter Crosthwaite size = 60; 1010191946c5SPeter Crosthwaite } 1011191946c5SPeter Crosthwaite 101249ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 101349ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 101449ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 101549ab747fSPaolo Bonzini } else { 101649ab747fSPaolo Bonzini unsigned crc_val; 101749ab747fSPaolo Bonzini 101824d62fd5SSai Pavan Boddu if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 101924d62fd5SSai Pavan Boddu size = MAX_FRAME_SIZE - sizeof(crc_val); 1020244381ecSPrasad J Pandit } 1021244381ecSPrasad J Pandit bytes_to_copy = size; 102249ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 10233048ed6aSPeter Crosthwaite * We must try and calculate one. 102449ab747fSPaolo Bonzini */ 102549ab747fSPaolo Bonzini 102624d62fd5SSai Pavan Boddu memcpy(s->rx_packet, buf, size); 102724d62fd5SSai Pavan Boddu memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 102824d62fd5SSai Pavan Boddu rxbuf_ptr = s->rx_packet; 102924d62fd5SSai Pavan Boddu crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 103024d62fd5SSai Pavan Boddu memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 103149ab747fSPaolo Bonzini 103249ab747fSPaolo Bonzini bytes_to_copy += 4; 103349ab747fSPaolo Bonzini size += 4; 103449ab747fSPaolo Bonzini } 103549ab747fSPaolo Bonzini 10366fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 103749ab747fSPaolo Bonzini 1038b12227afSStefan Weil /* Find which queue we are targeting */ 1039e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1040e8e49943SAlistair Francis 1041*7ca151c3SSai Pavan Boddu if (size > gem_get_max_buf_len(s, false)) { 1042*7ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 1043*7ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1044*7ca151c3SSai Pavan Boddu return -1; 1045*7ca151c3SSai Pavan Boddu } 1046*7ca151c3SSai Pavan Boddu 10477cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1048357aa013SEdgar E. Iglesias hwaddr desc_addr; 1049357aa013SEdgar E. Iglesias 105006c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 105106c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 105249ab747fSPaolo Bonzini return -1; 105349ab747fSPaolo Bonzini } 105449ab747fSPaolo Bonzini 10556fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1056dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1057dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 105849ab747fSPaolo Bonzini 105949ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 106084aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 10612bf57f73SAlistair Francis rxbuf_offset, 106284aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1063e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 106449ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 106530570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 10663b2c97f9SEdgar E. Iglesias 106759ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 106859ab136aSRamon Fried 10693b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 10703b2c97f9SEdgar E. Iglesias if (first_desc) { 10712bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 10723b2c97f9SEdgar E. Iglesias first_desc = false; 10733b2c97f9SEdgar E. Iglesias } 10743b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 10752bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 10762bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 10773b2c97f9SEdgar E. Iglesias } 10782bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 107963af1e0cSPeter Crosthwaite 108063af1e0cSPeter Crosthwaite switch (maf) { 108163af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 108263af1e0cSPeter Crosthwaite break; 108363af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 10842bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 108563af1e0cSPeter Crosthwaite break; 108663af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 10872bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 108863af1e0cSPeter Crosthwaite break; 108963af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 10902bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 109163af1e0cSPeter Crosthwaite break; 109263af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 109363af1e0cSPeter Crosthwaite abort(); 109463af1e0cSPeter Crosthwaite default: /* SAR */ 10952bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 109663af1e0cSPeter Crosthwaite } 109763af1e0cSPeter Crosthwaite 10983b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1099357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1100b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1101b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1102e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 11033b2c97f9SEdgar E. Iglesias 110449ab747fSPaolo Bonzini /* Next descriptor */ 11052bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 110649ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 110796ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 110849ab747fSPaolo Bonzini } else { 110949ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1110e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 111149ab747fSPaolo Bonzini } 111267101725SAlistair Francis 111367101725SAlistair Francis gem_get_rx_desc(s, q); 11147cfd65e4SPeter Crosthwaite } 111549ab747fSPaolo Bonzini 111649ab747fSPaolo Bonzini /* Count it */ 111749ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 111849ab747fSPaolo Bonzini 111949ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 112068dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXCMPL); 112149ab747fSPaolo Bonzini 112249ab747fSPaolo Bonzini /* Handle interrupt consequences */ 112349ab747fSPaolo Bonzini gem_update_int_status(s); 112449ab747fSPaolo Bonzini 112549ab747fSPaolo Bonzini return size; 112649ab747fSPaolo Bonzini } 112749ab747fSPaolo Bonzini 112849ab747fSPaolo Bonzini /* 112949ab747fSPaolo Bonzini * gem_transmit_updatestats: 113049ab747fSPaolo Bonzini * Increment transmit statistics. 113149ab747fSPaolo Bonzini */ 1132448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 113349ab747fSPaolo Bonzini unsigned bytes) 113449ab747fSPaolo Bonzini { 113549ab747fSPaolo Bonzini uint64_t octets; 113649ab747fSPaolo Bonzini 113749ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 113849ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 113949ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 114049ab747fSPaolo Bonzini octets += bytes; 114149ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 114249ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 114349ab747fSPaolo Bonzini 114449ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 114549ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 114649ab747fSPaolo Bonzini 114749ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 114849ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 114949ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 115049ab747fSPaolo Bonzini } 115149ab747fSPaolo Bonzini 115249ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 115349ab747fSPaolo Bonzini if (packet[0] == 0x01) { 115449ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 115549ab747fSPaolo Bonzini } 115649ab747fSPaolo Bonzini 115749ab747fSPaolo Bonzini if (bytes <= 64) { 115849ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 115949ab747fSPaolo Bonzini } else if (bytes <= 127) { 116049ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 116149ab747fSPaolo Bonzini } else if (bytes <= 255) { 116249ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 116349ab747fSPaolo Bonzini } else if (bytes <= 511) { 116449ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 116549ab747fSPaolo Bonzini } else if (bytes <= 1023) { 116649ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 116749ab747fSPaolo Bonzini } else if (bytes <= 1518) { 116849ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 116949ab747fSPaolo Bonzini } else { 117049ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 117149ab747fSPaolo Bonzini } 117249ab747fSPaolo Bonzini } 117349ab747fSPaolo Bonzini 117449ab747fSPaolo Bonzini /* 117549ab747fSPaolo Bonzini * gem_transmit: 117649ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 117749ab747fSPaolo Bonzini */ 1178448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 117949ab747fSPaolo Bonzini { 11808568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 118149ab747fSPaolo Bonzini hwaddr packet_desc_addr; 118249ab747fSPaolo Bonzini uint8_t *p; 118349ab747fSPaolo Bonzini unsigned total_bytes; 11842bf57f73SAlistair Francis int q = 0; 118549ab747fSPaolo Bonzini 118649ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 118749ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 118849ab747fSPaolo Bonzini return; 118949ab747fSPaolo Bonzini } 119049ab747fSPaolo Bonzini 119149ab747fSPaolo Bonzini DB_PRINT("\n"); 119249ab747fSPaolo Bonzini 11933048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 119449ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 119549ab747fSPaolo Bonzini * one contiguous buffer first. 119649ab747fSPaolo Bonzini */ 119724d62fd5SSai Pavan Boddu p = s->tx_packet; 119849ab747fSPaolo Bonzini total_bytes = 0; 119949ab747fSPaolo Bonzini 120067101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 120149ab747fSPaolo Bonzini /* read current descriptor */ 1202357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1203fa15286aSPeter Crosthwaite 1204fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 120584aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1206b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1207e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 120849ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 120949ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 121049ab747fSPaolo Bonzini 121149ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 121249ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 121349ab747fSPaolo Bonzini return; 121449ab747fSPaolo Bonzini } 121567101725SAlistair Francis print_gem_tx_desc(desc, q); 121649ab747fSPaolo Bonzini 121749ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 121849ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 121949ab747fSPaolo Bonzini */ 1220e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 122149ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 12226fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 12236fe7661dSSai Pavan Boddu packet_desc_addr); 122449ab747fSPaolo Bonzini break; 122549ab747fSPaolo Bonzini } 122649ab747fSPaolo Bonzini 1227*7ca151c3SSai Pavan Boddu if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 122824d62fd5SSai Pavan Boddu (p - s->tx_packet)) { 1229*7ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 1230*7ca151c3SSai Pavan Boddu HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1231dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 1232*7ca151c3SSai Pavan Boddu gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 1233*7ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1234d7f05365SMichael S. Tsirkin break; 1235d7f05365SMichael S. Tsirkin } 1236d7f05365SMichael S. Tsirkin 123777524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 123877524d11SAlistair Francis * contig buffer. 123949ab747fSPaolo Bonzini */ 124084aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 124184aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 124284aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 124349ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 124449ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 124549ab747fSPaolo Bonzini 124649ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 124749ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 12488568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1249357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 12506ab57a6bSPeter Crosthwaite 125149ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 125249ab747fSPaolo Bonzini * the processor. 125349ab747fSPaolo Bonzini */ 1254357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1255b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12566ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12576ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1258357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1259b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12606ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12613048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 126249ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 126396ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 126449ab747fSPaolo Bonzini } else { 1265e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1266e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 126749ab747fSPaolo Bonzini } 12682bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 126949ab747fSPaolo Bonzini 127049ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 127168dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_TXCMPL); 127267101725SAlistair Francis 127349ab747fSPaolo Bonzini /* Handle interrupt consequences */ 127449ab747fSPaolo Bonzini gem_update_int_status(s); 127549ab747fSPaolo Bonzini 127649ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 127749ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 127824d62fd5SSai Pavan Boddu net_checksum_calculate(s->tx_packet, total_bytes); 127949ab747fSPaolo Bonzini } 128049ab747fSPaolo Bonzini 128149ab747fSPaolo Bonzini /* Update MAC statistics */ 128224d62fd5SSai Pavan Boddu gem_transmit_updatestats(s, s->tx_packet, total_bytes); 128349ab747fSPaolo Bonzini 128449ab747fSPaolo Bonzini /* Send the packet somewhere */ 128577524d11SAlistair Francis if (s->phy_loop || (s->regs[GEM_NWCTRL] & 128677524d11SAlistair Francis GEM_NWCTRL_LOCALLOOP)) { 128724d62fd5SSai Pavan Boddu gem_receive(qemu_get_queue(s->nic), s->tx_packet, 128877524d11SAlistair Francis total_bytes); 128949ab747fSPaolo Bonzini } else { 129024d62fd5SSai Pavan Boddu qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 129149ab747fSPaolo Bonzini total_bytes); 129249ab747fSPaolo Bonzini } 129349ab747fSPaolo Bonzini 129449ab747fSPaolo Bonzini /* Prepare for next packet */ 129524d62fd5SSai Pavan Boddu p = s->tx_packet; 129649ab747fSPaolo Bonzini total_bytes = 0; 129749ab747fSPaolo Bonzini } 129849ab747fSPaolo Bonzini 129949ab747fSPaolo Bonzini /* read next descriptor */ 130049ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1301cbdab58dSAlistair Francis tx_desc_set_last(desc); 1302f1e7cb13SRamon Fried 1303f1e7cb13SRamon Fried if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 1304f1e7cb13SRamon Fried packet_desc_addr = s->regs[GEM_TBQPH]; 1305f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1306f1e7cb13SRamon Fried } else { 1307f1e7cb13SRamon Fried packet_desc_addr = 0; 1308f1e7cb13SRamon Fried } 130996ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 131049ab747fSPaolo Bonzini } else { 1311e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 131249ab747fSPaolo Bonzini } 1313fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 131484aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1315b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1316e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 131749ab747fSPaolo Bonzini } 131849ab747fSPaolo Bonzini 131949ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 132049ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 132168dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 132268dbee3bSSai Pavan Boddu if (q == 0) { 132368dbee3bSSai Pavan Boddu gem_set_isr(s, 0, GEM_INT_TXUSED); 132468dbee3bSSai Pavan Boddu } 132549ab747fSPaolo Bonzini gem_update_int_status(s); 132649ab747fSPaolo Bonzini } 132749ab747fSPaolo Bonzini } 132867101725SAlistair Francis } 132949ab747fSPaolo Bonzini 1330448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 133149ab747fSPaolo Bonzini { 133249ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 133349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 133449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 133549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 133649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 133749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 133849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 133949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 134049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 134149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 134249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 134349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 134449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 134549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 13467777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 134749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 134849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 134949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 135049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 135149ab747fSPaolo Bonzini 135249ab747fSPaolo Bonzini phy_update_link(s); 135349ab747fSPaolo Bonzini } 135449ab747fSPaolo Bonzini 135549ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 135649ab747fSPaolo Bonzini { 135764eb9301SPeter Crosthwaite int i; 1358448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1359afb4c51fSSebastian Huber const uint8_t *a; 1360726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 136149ab747fSPaolo Bonzini 136249ab747fSPaolo Bonzini DB_PRINT("\n"); 136349ab747fSPaolo Bonzini 136449ab747fSPaolo Bonzini /* Set post reset register values */ 136549ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 136649ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 136749ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 136849ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 136949ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 137049ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 137149ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 137249ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1373a5517666SAlistair Francis s->regs[GEM_MODID] = s->revision; 137449ab747fSPaolo Bonzini s->regs[GEM_DESCONF] = 0x02500111; 1375*7ca151c3SSai Pavan Boddu s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1376b2d43091SEdgar E. Iglesias s->regs[GEM_DESCONF5] = 0x002f2045; 1377e2c0c4eeSEdgar E. Iglesias s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; 1378*7ca151c3SSai Pavan Boddu s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len; 1379726a2a95SEdgar E. Iglesias 1380726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1381726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1382726a2a95SEdgar E. Iglesias s->regs[GEM_DESCONF6] |= queues_mask; 1383726a2a95SEdgar E. Iglesias } 138449ab747fSPaolo Bonzini 1385afb4c51fSSebastian Huber /* Set MAC address */ 1386afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1387afb4c51fSSebastian Huber s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1388afb4c51fSSebastian Huber s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1389afb4c51fSSebastian Huber 139064eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 139164eb9301SPeter Crosthwaite s->sar_active[i] = false; 139264eb9301SPeter Crosthwaite } 139364eb9301SPeter Crosthwaite 139449ab747fSPaolo Bonzini gem_phy_reset(s); 139549ab747fSPaolo Bonzini 139649ab747fSPaolo Bonzini gem_update_int_status(s); 139749ab747fSPaolo Bonzini } 139849ab747fSPaolo Bonzini 1399448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 140049ab747fSPaolo Bonzini { 140149ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 140249ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 140349ab747fSPaolo Bonzini } 140449ab747fSPaolo Bonzini 1405448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 140649ab747fSPaolo Bonzini { 140749ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 140849ab747fSPaolo Bonzini 140949ab747fSPaolo Bonzini switch (reg_num) { 141049ab747fSPaolo Bonzini case PHY_REG_CONTROL: 141149ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 141249ab747fSPaolo Bonzini /* Phy reset */ 141349ab747fSPaolo Bonzini gem_phy_reset(s); 141449ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 141549ab747fSPaolo Bonzini s->phy_loop = 0; 141649ab747fSPaolo Bonzini } 141749ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 141849ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 14196623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 142049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 142149ab747fSPaolo Bonzini } 142249ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 142349ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 142449ab747fSPaolo Bonzini s->phy_loop = 1; 142549ab747fSPaolo Bonzini } else { 142649ab747fSPaolo Bonzini s->phy_loop = 0; 142749ab747fSPaolo Bonzini } 142849ab747fSPaolo Bonzini break; 142949ab747fSPaolo Bonzini } 143049ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 143149ab747fSPaolo Bonzini } 143249ab747fSPaolo Bonzini 143349ab747fSPaolo Bonzini /* 143449ab747fSPaolo Bonzini * gem_read32: 143549ab747fSPaolo Bonzini * Read a GEM register. 143649ab747fSPaolo Bonzini */ 143749ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 143849ab747fSPaolo Bonzini { 1439448f19e2SPeter Crosthwaite CadenceGEMState *s; 144049ab747fSPaolo Bonzini uint32_t retval; 1441448f19e2SPeter Crosthwaite s = (CadenceGEMState *)opaque; 144249ab747fSPaolo Bonzini 144349ab747fSPaolo Bonzini offset >>= 2; 144449ab747fSPaolo Bonzini retval = s->regs[offset]; 144549ab747fSPaolo Bonzini 144649ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 144749ab747fSPaolo Bonzini 144849ab747fSPaolo Bonzini switch (offset) { 144949ab747fSPaolo Bonzini case GEM_ISR: 145067101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1451596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 145249ab747fSPaolo Bonzini break; 145349ab747fSPaolo Bonzini case GEM_PHYMNTNC: 145449ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 145549ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 145649ab747fSPaolo Bonzini 145749ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 145855389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 145949ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 146049ab747fSPaolo Bonzini retval &= 0xFFFF0000; 146149ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 146249ab747fSPaolo Bonzini } else { 146349ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 146449ab747fSPaolo Bonzini } 146549ab747fSPaolo Bonzini } 146649ab747fSPaolo Bonzini break; 146749ab747fSPaolo Bonzini } 146849ab747fSPaolo Bonzini 146949ab747fSPaolo Bonzini /* Squash read to clear bits */ 147049ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 147149ab747fSPaolo Bonzini 147249ab747fSPaolo Bonzini /* Do not provide write only bits */ 147349ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 147449ab747fSPaolo Bonzini 147549ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 147667101725SAlistair Francis gem_update_int_status(s); 147749ab747fSPaolo Bonzini return retval; 147849ab747fSPaolo Bonzini } 147949ab747fSPaolo Bonzini 148049ab747fSPaolo Bonzini /* 148149ab747fSPaolo Bonzini * gem_write32: 148249ab747fSPaolo Bonzini * Write a GEM register. 148349ab747fSPaolo Bonzini */ 148449ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 148549ab747fSPaolo Bonzini unsigned size) 148649ab747fSPaolo Bonzini { 1487448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 148849ab747fSPaolo Bonzini uint32_t readonly; 148967101725SAlistair Francis int i; 149049ab747fSPaolo Bonzini 149149ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 149249ab747fSPaolo Bonzini offset >>= 2; 149349ab747fSPaolo Bonzini 149449ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 149549ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1496e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1497e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 149849ab747fSPaolo Bonzini 149949ab747fSPaolo Bonzini /* Copy register write to backing store */ 1500e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1501e2314fdaSPeter Crosthwaite 1502e2314fdaSPeter Crosthwaite /* do w1c */ 1503e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 150449ab747fSPaolo Bonzini 150549ab747fSPaolo Bonzini /* Handle register write side effects */ 150649ab747fSPaolo Bonzini switch (offset) { 150749ab747fSPaolo Bonzini case GEM_NWCTRL: 150806c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 150967101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 151067101725SAlistair Francis gem_get_rx_desc(s, i); 151167101725SAlistair Francis } 151206c2fe95SPeter Crosthwaite } 151349ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 151449ab747fSPaolo Bonzini gem_transmit(s); 151549ab747fSPaolo Bonzini } 151649ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 151749ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 151867101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 151996ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 152067101725SAlistair Francis } 152149ab747fSPaolo Bonzini } 15228202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 152349ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 152449ab747fSPaolo Bonzini } 152549ab747fSPaolo Bonzini break; 152649ab747fSPaolo Bonzini 152749ab747fSPaolo Bonzini case GEM_TXSTATUS: 152849ab747fSPaolo Bonzini gem_update_int_status(s); 152949ab747fSPaolo Bonzini break; 153049ab747fSPaolo Bonzini case GEM_RXQBASE: 15312bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 153249ab747fSPaolo Bonzini break; 153379b2ac8fSAlistair Francis case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 153467101725SAlistair Francis s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 153567101725SAlistair Francis break; 153649ab747fSPaolo Bonzini case GEM_TXQBASE: 15372bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 153849ab747fSPaolo Bonzini break; 153979b2ac8fSAlistair Francis case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 154067101725SAlistair Francis s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 154167101725SAlistair Francis break; 154249ab747fSPaolo Bonzini case GEM_RXSTATUS: 154349ab747fSPaolo Bonzini gem_update_int_status(s); 154449ab747fSPaolo Bonzini break; 154549ab747fSPaolo Bonzini case GEM_IER: 154649ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 154749ab747fSPaolo Bonzini gem_update_int_status(s); 154849ab747fSPaolo Bonzini break; 1549*7ca151c3SSai Pavan Boddu case GEM_JUMBO_MAX_LEN: 1550*7ca151c3SSai Pavan Boddu s->regs[GEM_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 1551*7ca151c3SSai Pavan Boddu break; 155267101725SAlistair Francis case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 155367101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 155467101725SAlistair Francis gem_update_int_status(s); 155567101725SAlistair Francis break; 155649ab747fSPaolo Bonzini case GEM_IDR: 155749ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 155849ab747fSPaolo Bonzini gem_update_int_status(s); 155949ab747fSPaolo Bonzini break; 156067101725SAlistair Francis case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 156167101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 156267101725SAlistair Francis gem_update_int_status(s); 156367101725SAlistair Francis break; 156464eb9301SPeter Crosthwaite case GEM_SPADDR1LO: 156564eb9301SPeter Crosthwaite case GEM_SPADDR2LO: 156664eb9301SPeter Crosthwaite case GEM_SPADDR3LO: 156764eb9301SPeter Crosthwaite case GEM_SPADDR4LO: 156864eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 156964eb9301SPeter Crosthwaite break; 157064eb9301SPeter Crosthwaite case GEM_SPADDR1HI: 157164eb9301SPeter Crosthwaite case GEM_SPADDR2HI: 157264eb9301SPeter Crosthwaite case GEM_SPADDR3HI: 157364eb9301SPeter Crosthwaite case GEM_SPADDR4HI: 157464eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 157564eb9301SPeter Crosthwaite break; 157649ab747fSPaolo Bonzini case GEM_PHYMNTNC: 157749ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 157849ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 157949ab747fSPaolo Bonzini 158049ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 158155389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 158249ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 158349ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 158449ab747fSPaolo Bonzini } 158549ab747fSPaolo Bonzini } 158649ab747fSPaolo Bonzini break; 158749ab747fSPaolo Bonzini } 158849ab747fSPaolo Bonzini 158949ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 159049ab747fSPaolo Bonzini } 159149ab747fSPaolo Bonzini 159249ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 159349ab747fSPaolo Bonzini .read = gem_read, 159449ab747fSPaolo Bonzini .write = gem_write, 159549ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 159649ab747fSPaolo Bonzini }; 159749ab747fSPaolo Bonzini 159849ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 159949ab747fSPaolo Bonzini { 160067101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 160167101725SAlistair Francis 160249ab747fSPaolo Bonzini DB_PRINT("\n"); 160367101725SAlistair Francis phy_update_link(s); 160467101725SAlistair Francis gem_update_int_status(s); 160549ab747fSPaolo Bonzini } 160649ab747fSPaolo Bonzini 160749ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1608f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 160949ab747fSPaolo Bonzini .size = sizeof(NICState), 161049ab747fSPaolo Bonzini .can_receive = gem_can_receive, 161149ab747fSPaolo Bonzini .receive = gem_receive, 161249ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 161349ab747fSPaolo Bonzini }; 161449ab747fSPaolo Bonzini 1615bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 161649ab747fSPaolo Bonzini { 1617448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 161867101725SAlistair Francis int i; 161949ab747fSPaolo Bonzini 162084aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 162184aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 162284aec8efSEdgar E. Iglesias 16232bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 16242bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 16252bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 16262bf57f73SAlistair Francis s->num_priority_queues); 16272bf57f73SAlistair Francis return; 1628e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1629e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1630e8e49943SAlistair Francis s->num_type1_screeners); 1631e8e49943SAlistair Francis return; 1632e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1633e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1634e8e49943SAlistair Francis s->num_type2_screeners); 1635e8e49943SAlistair Francis return; 16362bf57f73SAlistair Francis } 16372bf57f73SAlistair Francis 163867101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 163967101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 164067101725SAlistair Francis } 1641bcb39a65SAlistair Francis 1642bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1643bcb39a65SAlistair Francis 1644bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1645bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 1646*7ca151c3SSai Pavan Boddu 1647*7ca151c3SSai Pavan Boddu if (s->jumbo_max_len > MAX_FRAME_SIZE) { 1648*7ca151c3SSai Pavan Boddu error_setg(errp, "jumbo-max-len is greater than %d", 1649*7ca151c3SSai Pavan Boddu MAX_FRAME_SIZE); 1650*7ca151c3SSai Pavan Boddu return; 1651*7ca151c3SSai Pavan Boddu } 1652bcb39a65SAlistair Francis } 1653bcb39a65SAlistair Francis 1654bcb39a65SAlistair Francis static void gem_init(Object *obj) 1655bcb39a65SAlistair Francis { 1656bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1657bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1658bcb39a65SAlistair Francis 165949ab747fSPaolo Bonzini DB_PRINT("\n"); 166049ab747fSPaolo Bonzini 166149ab747fSPaolo Bonzini gem_init_register_masks(s); 1662eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1663eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 166449ab747fSPaolo Bonzini 1665bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 166684aec8efSEdgar E. Iglesias 166784aec8efSEdgar E. Iglesias object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 166884aec8efSEdgar E. Iglesias (Object **)&s->dma_mr, 166984aec8efSEdgar E. Iglesias qdev_prop_allow_set_link_before_realize, 1670d2623129SMarkus Armbruster OBJ_PROP_LINK_STRONG); 167149ab747fSPaolo Bonzini } 167249ab747fSPaolo Bonzini 167349ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 167449ab747fSPaolo Bonzini .name = "cadence_gem", 1675e8e49943SAlistair Francis .version_id = 4, 1676e8e49943SAlistair Francis .minimum_version_id = 4, 167749ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1678448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1679448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1680448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 16812bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 16822bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 16832bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 16842bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1685448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 168617cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 168749ab747fSPaolo Bonzini } 168849ab747fSPaolo Bonzini }; 168949ab747fSPaolo Bonzini 169049ab747fSPaolo Bonzini static Property gem_properties[] = { 1691448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1692a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1693a5517666SAlistair Francis GEM_MODID_VALUE), 16942bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 16952bf57f73SAlistair Francis num_priority_queues, 1), 1696e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1697e8e49943SAlistair Francis num_type1_screeners, 4), 1698e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1699e8e49943SAlistair Francis num_type2_screeners, 4), 1700*7ca151c3SSai Pavan Boddu DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 1701*7ca151c3SSai Pavan Boddu jumbo_max_len, 10240), 170249ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 170349ab747fSPaolo Bonzini }; 170449ab747fSPaolo Bonzini 170549ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 170649ab747fSPaolo Bonzini { 170749ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 170849ab747fSPaolo Bonzini 1709bcb39a65SAlistair Francis dc->realize = gem_realize; 17104f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 171149ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 171249ab747fSPaolo Bonzini dc->reset = gem_reset; 171349ab747fSPaolo Bonzini } 171449ab747fSPaolo Bonzini 171549ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1716318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 171749ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1718448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1719bcb39a65SAlistair Francis .instance_init = gem_init, 1720318643beSAndreas Färber .class_init = gem_class_init, 172149ab747fSPaolo Bonzini }; 172249ab747fSPaolo Bonzini 172349ab747fSPaolo Bonzini static void gem_register_types(void) 172449ab747fSPaolo Bonzini { 172549ab747fSPaolo Bonzini type_register_static(&gem_info); 172649ab747fSPaolo Bonzini } 172749ab747fSPaolo Bonzini 172849ab747fSPaolo Bonzini type_init(gem_register_types) 1729