149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 28f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 292bf57f73SAlistair Francis #include "qapi/error.h" 30e8e49943SAlistair Francis #include "qemu/log.h" 31*84aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3249ab747fSPaolo Bonzini #include "net/checksum.h" 3349ab747fSPaolo Bonzini 3449ab747fSPaolo Bonzini #ifdef CADENCE_GEM_ERR_DEBUG 3549ab747fSPaolo Bonzini #define DB_PRINT(...) do { \ 3649ab747fSPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 3749ab747fSPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 382562755eSEric Blake } while (0) 3949ab747fSPaolo Bonzini #else 4049ab747fSPaolo Bonzini #define DB_PRINT(...) 4149ab747fSPaolo Bonzini #endif 4249ab747fSPaolo Bonzini 4349ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 4449ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 4549ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 4649ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 4749ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 4849ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 4949ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 5049ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 5149ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 5249ab747fSPaolo Bonzini #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 5349ab747fSPaolo Bonzini #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 5449ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 5549ab747fSPaolo Bonzini #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 563048ed6aSPeter Crosthwaite #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 5749ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 5849ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 5949ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 6049ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 6149ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 6249ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 6349ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 6449ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 6549ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 6649ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 6749ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 6849ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 6949ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 7049ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 7149ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 7249ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 7349ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 7449ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 7549ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 7649ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 7749ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 7849ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 7949ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 8049ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 8149ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 8249ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 8349ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 8449ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 8549ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 8649ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 8749ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 8849ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 8949ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 9049ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 9149ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 9249ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 9349ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 9449ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 9549ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 9649ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 9749ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 9849ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 9949ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 10049ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 10149ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 10249ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 10349ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 10449ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 10549ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 10649ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 10749ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 10849ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 10949ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 11049ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 11149ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 11249ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 11349ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 11449ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 11549ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 11649ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 11749ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 11849ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 11949ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 12149ab747fSPaolo Bonzini #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 12249ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 12349ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 12449ab747fSPaolo Bonzini 12549ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 12649ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 12749ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 12849ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 12949ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 13049ab747fSPaolo Bonzini #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 13149ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 13249ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 13349ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 13449ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 13549ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 13649ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 13749ab747fSPaolo Bonzini 13849ab747fSPaolo Bonzini /* Design Configuration Registers */ 13949ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280/4) 14049ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284/4) 14149ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288/4) 14249ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C/4) 14349ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290/4) 14449ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294/4) 14549ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298/4) 14649ab747fSPaolo Bonzini 14767101725SAlistair Francis #define GEM_INT_Q1_STATUS (0x00000400 / 4) 14867101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 14967101725SAlistair Francis 15067101725SAlistair Francis #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 15179b2ac8fSAlistair Francis #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 15267101725SAlistair Francis 15367101725SAlistair Francis #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 15479b2ac8fSAlistair Francis #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 15567101725SAlistair Francis 15667101725SAlistair Francis #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 15767101725SAlistair Francis #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 15867101725SAlistair Francis 15967101725SAlistair Francis #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 16067101725SAlistair Francis #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 16167101725SAlistair Francis 16267101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 16367101725SAlistair Francis #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 16467101725SAlistair Francis 165e8e49943SAlistair Francis #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 166e8e49943SAlistair Francis 167e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 168e8e49943SAlistair Francis #define GEM_ST1R_DSTC_ENABLE (1 << 28) 169e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 170e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 171e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 172e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 173e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_SHIFT (0) 174e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 175e8e49943SAlistair Francis 176e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 177e8e49943SAlistair Francis 178e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 179e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_SHIFT (13) 180e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 181e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 182e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 183e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 184e8e49943SAlistair Francis + 1) 185e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_SHIFT (0) 186e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 187e8e49943SAlistair Francis 188e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 189e8e49943SAlistair Francis #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 190e8e49943SAlistair Francis 191e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 192e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 193e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 194e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 195e8e49943SAlistair Francis 19649ab747fSPaolo Bonzini /*****************************************/ 19749ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 19849ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 19949ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 20049ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 20149ab747fSPaolo Bonzini 20249ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2033048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 20449ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 20549ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 20649ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 20749ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 20849ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 20949ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 21049ab747fSPaolo Bonzini 211e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 212e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 213e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2142801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 21549ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 21649ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 21749ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 21849ab747fSPaolo Bonzini 21949ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 22049ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 22149ab747fSPaolo Bonzini 22249ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 22349ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 22449ab747fSPaolo Bonzini 22549ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 22649ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 22749ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 22849ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 22949ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 23049ab747fSPaolo Bonzini 23149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 23249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 23349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 23449ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 23549ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 23649ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 23749ab747fSPaolo Bonzini 23849ab747fSPaolo Bonzini /* Marvell PHY definitions */ 23949ab747fSPaolo Bonzini #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 24049ab747fSPaolo Bonzini 24149ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 24249ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 24349ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 24449ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 24549ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 24649ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 24749ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 24849ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 24949ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 25049ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 25149ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 25249ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 25349ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 25449ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 25549ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 25649ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 25749ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 25849ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 25949ab747fSPaolo Bonzini #define PHY_REG_EACD 22 26049ab747fSPaolo Bonzini #define PHY_REG_LED 24 26149ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 26249ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 26349ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 26449ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 26549ab747fSPaolo Bonzini 26649ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 26749ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 26849ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 26949ab747fSPaolo Bonzini 27049ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 27149ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 27249ab747fSPaolo Bonzini 27349ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 27449ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 27549ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 27649ab747fSPaolo Bonzini 27749ab747fSPaolo Bonzini /***********************************************************************/ 27863af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 27963af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 28063af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 28163af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 28263af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 28363af1e0cSPeter Crosthwaite 28463af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 28549ab747fSPaolo Bonzini 28649ab747fSPaolo Bonzini /***********************************************************************/ 28749ab747fSPaolo Bonzini 28849ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 28949ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 29049ab747fSPaolo Bonzini 29149ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 29249ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 29349ab747fSPaolo Bonzini 29449ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 29549ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 29649ab747fSPaolo Bonzini 29763af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 29863af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 299a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 30063af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 30163af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 30263af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 30363af1e0cSPeter Crosthwaite 30449ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 30549ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 30649ab747fSPaolo Bonzini 307a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 308a5517666SAlistair Francis 309e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 31049ab747fSPaolo Bonzini { 311e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 312e48fdd9dSEdgar E. Iglesias 313e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 314e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 315e48fdd9dSEdgar E. Iglesias } 316e48fdd9dSEdgar E. Iglesias return ret; 31749ab747fSPaolo Bonzini } 31849ab747fSPaolo Bonzini 319f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 32049ab747fSPaolo Bonzini { 32149ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 32249ab747fSPaolo Bonzini } 32349ab747fSPaolo Bonzini 324f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 32549ab747fSPaolo Bonzini { 32649ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 32749ab747fSPaolo Bonzini } 32849ab747fSPaolo Bonzini 329f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 33049ab747fSPaolo Bonzini { 33149ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 33249ab747fSPaolo Bonzini } 33349ab747fSPaolo Bonzini 334f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 33549ab747fSPaolo Bonzini { 33649ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 33749ab747fSPaolo Bonzini } 33849ab747fSPaolo Bonzini 339f0236182SEdgar E. Iglesias static inline void tx_desc_set_last(uint32_t *desc) 340cbdab58dSAlistair Francis { 341cbdab58dSAlistair Francis desc[1] |= DESC_1_TX_LAST; 342cbdab58dSAlistair Francis } 343cbdab58dSAlistair Francis 344f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 34549ab747fSPaolo Bonzini { 34649ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 34749ab747fSPaolo Bonzini } 34849ab747fSPaolo Bonzini 349f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 35049ab747fSPaolo Bonzini { 35167101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 35249ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 35349ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 35449ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 35549ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 35649ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 35749ab747fSPaolo Bonzini } 35849ab747fSPaolo Bonzini 359e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 36049ab747fSPaolo Bonzini { 361e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 362e48fdd9dSEdgar E. Iglesias 363e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 364e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 365e48fdd9dSEdgar E. Iglesias } 366e48fdd9dSEdgar E. Iglesias return ret; 367e48fdd9dSEdgar E. Iglesias } 368e48fdd9dSEdgar E. Iglesias 369e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 370e48fdd9dSEdgar E. Iglesias { 371e48fdd9dSEdgar E. Iglesias int ret = 2; 372e48fdd9dSEdgar E. Iglesias 373e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 374e48fdd9dSEdgar E. Iglesias ret += 2; 375e48fdd9dSEdgar E. Iglesias } 376e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 377e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 378e48fdd9dSEdgar E. Iglesias ret += 2; 379e48fdd9dSEdgar E. Iglesias } 380e48fdd9dSEdgar E. Iglesias 381e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 382e48fdd9dSEdgar E. Iglesias return ret; 38349ab747fSPaolo Bonzini } 38449ab747fSPaolo Bonzini 385f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 38649ab747fSPaolo Bonzini { 38749ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 38849ab747fSPaolo Bonzini } 38949ab747fSPaolo Bonzini 390f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 39149ab747fSPaolo Bonzini { 39249ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 39349ab747fSPaolo Bonzini } 39449ab747fSPaolo Bonzini 395f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 39649ab747fSPaolo Bonzini { 39749ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 39849ab747fSPaolo Bonzini } 39949ab747fSPaolo Bonzini 400f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 40149ab747fSPaolo Bonzini { 40249ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 40349ab747fSPaolo Bonzini } 40449ab747fSPaolo Bonzini 405f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 40649ab747fSPaolo Bonzini { 40749ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 40849ab747fSPaolo Bonzini } 40949ab747fSPaolo Bonzini 410f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 41149ab747fSPaolo Bonzini { 41249ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 41349ab747fSPaolo Bonzini desc[1] |= len; 41449ab747fSPaolo Bonzini } 41549ab747fSPaolo Bonzini 416f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 41763af1e0cSPeter Crosthwaite { 41863af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 41963af1e0cSPeter Crosthwaite } 42063af1e0cSPeter Crosthwaite 421f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 42263af1e0cSPeter Crosthwaite { 42363af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 42463af1e0cSPeter Crosthwaite } 42563af1e0cSPeter Crosthwaite 426f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 42763af1e0cSPeter Crosthwaite { 42863af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 42963af1e0cSPeter Crosthwaite } 43063af1e0cSPeter Crosthwaite 431f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 43263af1e0cSPeter Crosthwaite { 43363af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 43463af1e0cSPeter Crosthwaite sar_idx); 435a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 43663af1e0cSPeter Crosthwaite } 43763af1e0cSPeter Crosthwaite 43849ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4396a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 44049ab747fSPaolo Bonzini 44149ab747fSPaolo Bonzini /* 44249ab747fSPaolo Bonzini * gem_init_register_masks: 44349ab747fSPaolo Bonzini * One time initialization. 44449ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 44549ab747fSPaolo Bonzini */ 446448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 44749ab747fSPaolo Bonzini { 44849ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 44949ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 45049ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 45149ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 452e48fdd9dSEdgar E. Iglesias s->regs_ro[GEM_DMACFG] = 0x8E00F000; 45349ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 45449ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 45549ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 45649ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 45749ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 45849ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 45949ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 46049ab747fSPaolo Bonzini 46149ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 46249ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 46349ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 46449ab747fSPaolo Bonzini 46549ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 46649ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 46749ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 46849ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 46949ab747fSPaolo Bonzini 47049ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 47149ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 47249ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 47349ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 47449ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 47549ab747fSPaolo Bonzini } 47649ab747fSPaolo Bonzini 47749ab747fSPaolo Bonzini /* 47849ab747fSPaolo Bonzini * phy_update_link: 47949ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 48049ab747fSPaolo Bonzini */ 481448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 48249ab747fSPaolo Bonzini { 48349ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 48449ab747fSPaolo Bonzini 48549ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 48649ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 48749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 48849ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 48949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 49049ab747fSPaolo Bonzini } else { 49149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 49249ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 49349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 49449ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 49549ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 49649ab747fSPaolo Bonzini } 49749ab747fSPaolo Bonzini } 49849ab747fSPaolo Bonzini 49949ab747fSPaolo Bonzini static int gem_can_receive(NetClientState *nc) 50049ab747fSPaolo Bonzini { 501448f19e2SPeter Crosthwaite CadenceGEMState *s; 50267101725SAlistair Francis int i; 50349ab747fSPaolo Bonzini 50449ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 50549ab747fSPaolo Bonzini 50649ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 50749ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 5083ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 5093ae5725fSPeter Crosthwaite s->can_rx_state = 1; 5103ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 5113ae5725fSPeter Crosthwaite } 51249ab747fSPaolo Bonzini return 0; 51349ab747fSPaolo Bonzini } 51449ab747fSPaolo Bonzini 51567101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 516dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 517dacc0566SAlistair Francis break; 518dacc0566SAlistair Francis } 519dacc0566SAlistair Francis }; 520dacc0566SAlistair Francis 521dacc0566SAlistair Francis if (i == s->num_priority_queues) { 5228202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 5238202aa53SPeter Crosthwaite s->can_rx_state = 2; 524dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 5258202aa53SPeter Crosthwaite } 5268202aa53SPeter Crosthwaite return 0; 5278202aa53SPeter Crosthwaite } 5288202aa53SPeter Crosthwaite 5293ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 5303ae5725fSPeter Crosthwaite s->can_rx_state = 0; 53167101725SAlistair Francis DB_PRINT("can receive\n"); 5323ae5725fSPeter Crosthwaite } 53349ab747fSPaolo Bonzini return 1; 53449ab747fSPaolo Bonzini } 53549ab747fSPaolo Bonzini 53649ab747fSPaolo Bonzini /* 53749ab747fSPaolo Bonzini * gem_update_int_status: 53849ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 53949ab747fSPaolo Bonzini */ 540448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 54149ab747fSPaolo Bonzini { 54267101725SAlistair Francis int i; 54367101725SAlistair Francis 544596b6f51SAlistair Francis if (!s->regs[GEM_ISR]) { 545596b6f51SAlistair Francis /* ISR isn't set, clear all the interrupts */ 546596b6f51SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 547596b6f51SAlistair Francis qemu_set_irq(s->irq[i], 0); 548596b6f51SAlistair Francis } 549596b6f51SAlistair Francis return; 550596b6f51SAlistair Francis } 551596b6f51SAlistair Francis 552596b6f51SAlistair Francis /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to 553596b6f51SAlistair Francis * check it again. 554596b6f51SAlistair Francis */ 555596b6f51SAlistair Francis if (s->num_priority_queues == 1) { 55667101725SAlistair Francis /* No priority queues, just trigger the interrupt */ 5578ea1d056SFam Zheng DB_PRINT("asserting int.\n"); 5582bf57f73SAlistair Francis qemu_set_irq(s->irq[0], 1); 55967101725SAlistair Francis return; 56067101725SAlistair Francis } 56167101725SAlistair Francis 56267101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 56367101725SAlistair Francis if (s->regs[GEM_INT_Q1_STATUS + i]) { 56467101725SAlistair Francis DB_PRINT("asserting int. (q=%d)\n", i); 56567101725SAlistair Francis qemu_set_irq(s->irq[i], 1); 56667101725SAlistair Francis } 56749ab747fSPaolo Bonzini } 56849ab747fSPaolo Bonzini } 56949ab747fSPaolo Bonzini 57049ab747fSPaolo Bonzini /* 57149ab747fSPaolo Bonzini * gem_receive_updatestats: 57249ab747fSPaolo Bonzini * Increment receive statistics. 57349ab747fSPaolo Bonzini */ 574448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 57549ab747fSPaolo Bonzini unsigned bytes) 57649ab747fSPaolo Bonzini { 57749ab747fSPaolo Bonzini uint64_t octets; 57849ab747fSPaolo Bonzini 57949ab747fSPaolo Bonzini /* Total octets (bytes) received */ 58049ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 58149ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 58249ab747fSPaolo Bonzini octets += bytes; 58349ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 58449ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 58549ab747fSPaolo Bonzini 58649ab747fSPaolo Bonzini /* Error-free Frames received */ 58749ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 58849ab747fSPaolo Bonzini 58949ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 59049ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 59149ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 59249ab747fSPaolo Bonzini } 59349ab747fSPaolo Bonzini 59449ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 59549ab747fSPaolo Bonzini if (packet[0] == 0x01) { 59649ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 59749ab747fSPaolo Bonzini } 59849ab747fSPaolo Bonzini 59949ab747fSPaolo Bonzini if (bytes <= 64) { 60049ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 60149ab747fSPaolo Bonzini } else if (bytes <= 127) { 60249ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 60349ab747fSPaolo Bonzini } else if (bytes <= 255) { 60449ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 60549ab747fSPaolo Bonzini } else if (bytes <= 511) { 60649ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 60749ab747fSPaolo Bonzini } else if (bytes <= 1023) { 60849ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 60949ab747fSPaolo Bonzini } else if (bytes <= 1518) { 61049ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 61149ab747fSPaolo Bonzini } else { 61249ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 61349ab747fSPaolo Bonzini } 61449ab747fSPaolo Bonzini } 61549ab747fSPaolo Bonzini 61649ab747fSPaolo Bonzini /* 61749ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 61849ab747fSPaolo Bonzini */ 61949ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 62049ab747fSPaolo Bonzini { 62149ab747fSPaolo Bonzini unsigned byte; 62249ab747fSPaolo Bonzini 62349ab747fSPaolo Bonzini byte = mac[bit / 8]; 62449ab747fSPaolo Bonzini byte >>= (bit & 0x7); 62549ab747fSPaolo Bonzini byte &= 1; 62649ab747fSPaolo Bonzini 62749ab747fSPaolo Bonzini return byte; 62849ab747fSPaolo Bonzini } 62949ab747fSPaolo Bonzini 63049ab747fSPaolo Bonzini /* 63149ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 63249ab747fSPaolo Bonzini */ 63349ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 63449ab747fSPaolo Bonzini { 63549ab747fSPaolo Bonzini int index_bit, mac_bit; 63649ab747fSPaolo Bonzini unsigned hash_index; 63749ab747fSPaolo Bonzini 63849ab747fSPaolo Bonzini hash_index = 0; 63949ab747fSPaolo Bonzini mac_bit = 5; 64049ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 64149ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 64249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 64349ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 64449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 64549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 64649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 64749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 64849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 64949ab747fSPaolo Bonzini mac_bit--; 65049ab747fSPaolo Bonzini } 65149ab747fSPaolo Bonzini 65249ab747fSPaolo Bonzini return hash_index; 65349ab747fSPaolo Bonzini } 65449ab747fSPaolo Bonzini 65549ab747fSPaolo Bonzini /* 65649ab747fSPaolo Bonzini * gem_mac_address_filter: 65749ab747fSPaolo Bonzini * Accept or reject this destination address? 65849ab747fSPaolo Bonzini * Returns: 65949ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 66063af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 66163af1e0cSPeter Crosthwaite * others for various other modes of accept: 66263af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 66363af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 66449ab747fSPaolo Bonzini */ 665448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 66649ab747fSPaolo Bonzini { 66749ab747fSPaolo Bonzini uint8_t *gem_spaddr; 66849ab747fSPaolo Bonzini int i; 66949ab747fSPaolo Bonzini 67049ab747fSPaolo Bonzini /* Promiscuous mode? */ 67149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 67263af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 67349ab747fSPaolo Bonzini } 67449ab747fSPaolo Bonzini 67549ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 67649ab747fSPaolo Bonzini /* Reject broadcast packets? */ 67749ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 67849ab747fSPaolo Bonzini return GEM_RX_REJECT; 67949ab747fSPaolo Bonzini } 68063af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 68149ab747fSPaolo Bonzini } 68249ab747fSPaolo Bonzini 68349ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 68449ab747fSPaolo Bonzini if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 68549ab747fSPaolo Bonzini (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 68649ab747fSPaolo Bonzini unsigned hash_index; 68749ab747fSPaolo Bonzini 68849ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 68949ab747fSPaolo Bonzini if (hash_index < 32) { 69049ab747fSPaolo Bonzini if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 69163af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 69263af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 69349ab747fSPaolo Bonzini } 69449ab747fSPaolo Bonzini } else { 69549ab747fSPaolo Bonzini hash_index -= 32; 69649ab747fSPaolo Bonzini if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 69763af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 69863af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 69949ab747fSPaolo Bonzini } 70049ab747fSPaolo Bonzini } 70149ab747fSPaolo Bonzini } 70249ab747fSPaolo Bonzini 70349ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 70449ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 70563af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 70664eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 70763af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 70849ab747fSPaolo Bonzini } 70949ab747fSPaolo Bonzini } 71049ab747fSPaolo Bonzini 71149ab747fSPaolo Bonzini /* No address match; reject the packet */ 71249ab747fSPaolo Bonzini return GEM_RX_REJECT; 71349ab747fSPaolo Bonzini } 71449ab747fSPaolo Bonzini 715e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 716e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 717e8e49943SAlistair Francis unsigned rxbufsize) 718e8e49943SAlistair Francis { 719e8e49943SAlistair Francis uint32_t reg; 720e8e49943SAlistair Francis bool matched, mismatched; 721e8e49943SAlistair Francis int i, j; 722e8e49943SAlistair Francis 723e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 724e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 725e8e49943SAlistair Francis matched = false; 726e8e49943SAlistair Francis mismatched = false; 727e8e49943SAlistair Francis 728e8e49943SAlistair Francis /* Screening is based on UDP Port */ 729e8e49943SAlistair Francis if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 730e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 731e8e49943SAlistair Francis if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 732e8e49943SAlistair Francis GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 733e8e49943SAlistair Francis matched = true; 734e8e49943SAlistair Francis } else { 735e8e49943SAlistair Francis mismatched = true; 736e8e49943SAlistair Francis } 737e8e49943SAlistair Francis } 738e8e49943SAlistair Francis 739e8e49943SAlistair Francis /* Screening is based on DS/TC */ 740e8e49943SAlistair Francis if (reg & GEM_ST1R_DSTC_ENABLE) { 741e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 742e8e49943SAlistair Francis if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 743e8e49943SAlistair Francis GEM_ST1R_DSTC_MATCH_WIDTH)) { 744e8e49943SAlistair Francis matched = true; 745e8e49943SAlistair Francis } else { 746e8e49943SAlistair Francis mismatched = true; 747e8e49943SAlistair Francis } 748e8e49943SAlistair Francis } 749e8e49943SAlistair Francis 750e8e49943SAlistair Francis if (matched && !mismatched) { 751e8e49943SAlistair Francis return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 752e8e49943SAlistair Francis } 753e8e49943SAlistair Francis } 754e8e49943SAlistair Francis 755e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 756e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 757e8e49943SAlistair Francis matched = false; 758e8e49943SAlistair Francis mismatched = false; 759e8e49943SAlistair Francis 760e8e49943SAlistair Francis if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 761e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 762e8e49943SAlistair Francis int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 763e8e49943SAlistair Francis GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 764e8e49943SAlistair Francis 765e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 766e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 767e8e49943SAlistair Francis "register index: %d\n", et_idx); 768e8e49943SAlistair Francis } 769e8e49943SAlistair Francis if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 770e8e49943SAlistair Francis et_idx]) { 771e8e49943SAlistair Francis matched = true; 772e8e49943SAlistair Francis } else { 773e8e49943SAlistair Francis mismatched = true; 774e8e49943SAlistair Francis } 775e8e49943SAlistair Francis } 776e8e49943SAlistair Francis 777e8e49943SAlistair Francis /* Compare A, B, C */ 778e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 779e8e49943SAlistair Francis uint32_t cr0, cr1, mask; 780e8e49943SAlistair Francis uint16_t rx_cmp; 781e8e49943SAlistair Francis int offset; 782e8e49943SAlistair Francis int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 783e8e49943SAlistair Francis GEM_ST2R_COMPARE_WIDTH); 784e8e49943SAlistair Francis 785e8e49943SAlistair Francis if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 786e8e49943SAlistair Francis continue; 787e8e49943SAlistair Francis } 788e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 789e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 790e8e49943SAlistair Francis "register index: %d\n", cr_idx); 791e8e49943SAlistair Francis } 792e8e49943SAlistair Francis 793e8e49943SAlistair Francis cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 794e8e49943SAlistair Francis cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 795e8e49943SAlistair Francis offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 796e8e49943SAlistair Francis GEM_T2CW1_OFFSET_VALUE_WIDTH); 797e8e49943SAlistair Francis 798e8e49943SAlistair Francis switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 799e8e49943SAlistair Francis GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 800e8e49943SAlistair Francis case 3: /* Skip UDP header */ 801e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 802e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 803e8e49943SAlistair Francis offset += 8; 804e8e49943SAlistair Francis /* Fallthrough */ 805e8e49943SAlistair Francis case 2: /* skip the IP header */ 806e8e49943SAlistair Francis offset += 20; 807e8e49943SAlistair Francis /* Fallthrough */ 808e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 809e8e49943SAlistair Francis offset += 14; 810e8e49943SAlistair Francis break; 811e8e49943SAlistair Francis case 0: 812e8e49943SAlistair Francis /* Offset from start of frame */ 813e8e49943SAlistair Francis break; 814e8e49943SAlistair Francis } 815e8e49943SAlistair Francis 816e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 817e8e49943SAlistair Francis mask = extract32(cr0, 0, 16); 818e8e49943SAlistair Francis 819e8e49943SAlistair Francis if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 820e8e49943SAlistair Francis matched = true; 821e8e49943SAlistair Francis } else { 822e8e49943SAlistair Francis mismatched = true; 823e8e49943SAlistair Francis } 824e8e49943SAlistair Francis } 825e8e49943SAlistair Francis 826e8e49943SAlistair Francis if (matched && !mismatched) { 827e8e49943SAlistair Francis return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 828e8e49943SAlistair Francis } 829e8e49943SAlistair Francis } 830e8e49943SAlistair Francis 831e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 832e8e49943SAlistair Francis return 0; 833e8e49943SAlistair Francis } 834e8e49943SAlistair Francis 83567101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 83606c2fe95SPeter Crosthwaite { 83767101725SAlistair Francis DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); 83806c2fe95SPeter Crosthwaite /* read current descriptor */ 839*84aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED, 840e48fdd9dSEdgar E. Iglesias (uint8_t *)s->rx_desc[q], 841e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 84206c2fe95SPeter Crosthwaite 84306c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 84467101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 84506c2fe95SPeter Crosthwaite DB_PRINT("descriptor 0x%x owned by sw.\n", 84667101725SAlistair Francis (unsigned)s->rx_desc_addr[q]); 84706c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 84806c2fe95SPeter Crosthwaite s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 84906c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 85006c2fe95SPeter Crosthwaite gem_update_int_status(s); 85106c2fe95SPeter Crosthwaite } 85206c2fe95SPeter Crosthwaite } 85306c2fe95SPeter Crosthwaite 85449ab747fSPaolo Bonzini /* 85549ab747fSPaolo Bonzini * gem_receive: 85649ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 85749ab747fSPaolo Bonzini */ 85849ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 85949ab747fSPaolo Bonzini { 860448f19e2SPeter Crosthwaite CadenceGEMState *s; 86149ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 86249ab747fSPaolo Bonzini unsigned rxbuf_offset; 86349ab747fSPaolo Bonzini uint8_t rxbuf[2048]; 86449ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 8653b2c97f9SEdgar E. Iglesias bool first_desc = true; 86663af1e0cSPeter Crosthwaite int maf; 8672bf57f73SAlistair Francis int q = 0; 86849ab747fSPaolo Bonzini 86949ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 87049ab747fSPaolo Bonzini 87149ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 87263af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 87363af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 87449ab747fSPaolo Bonzini return -1; 87549ab747fSPaolo Bonzini } 87649ab747fSPaolo Bonzini 87749ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 87849ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 87949ab747fSPaolo Bonzini unsigned type_len; 88049ab747fSPaolo Bonzini 88149ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 88249ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 88349ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 88449ab747fSPaolo Bonzini if (type_len < 0x600) { 88549ab747fSPaolo Bonzini if (size < type_len) { 88649ab747fSPaolo Bonzini /* discard */ 88749ab747fSPaolo Bonzini return -1; 88849ab747fSPaolo Bonzini } 88949ab747fSPaolo Bonzini } 89049ab747fSPaolo Bonzini } 89149ab747fSPaolo Bonzini 89249ab747fSPaolo Bonzini /* 89349ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 89449ab747fSPaolo Bonzini */ 89549ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 89649ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 89749ab747fSPaolo Bonzini 89849ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 89949ab747fSPaolo Bonzini * buffers needed to hold this packet. 90049ab747fSPaolo Bonzini */ 90149ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 90249ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 90349ab747fSPaolo Bonzini bytes_to_copy = size; 90449ab747fSPaolo Bonzini 905f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 906f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 907f265ae8cSAlistair Francis */ 908f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 909f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 910f265ae8cSAlistair Francis } 911f265ae8cSAlistair Francis 912191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 913191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 914191946c5SPeter Crosthwaite * not FCS stripping 915191946c5SPeter Crosthwaite */ 916191946c5SPeter Crosthwaite if (size < 60) { 917191946c5SPeter Crosthwaite size = 60; 918191946c5SPeter Crosthwaite } 919191946c5SPeter Crosthwaite 92049ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 92149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 92249ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 92349ab747fSPaolo Bonzini } else { 92449ab747fSPaolo Bonzini unsigned crc_val; 92549ab747fSPaolo Bonzini 926244381ecSPrasad J Pandit if (size > sizeof(rxbuf) - sizeof(crc_val)) { 927244381ecSPrasad J Pandit size = sizeof(rxbuf) - sizeof(crc_val); 928244381ecSPrasad J Pandit } 929244381ecSPrasad J Pandit bytes_to_copy = size; 93049ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 9313048ed6aSPeter Crosthwaite * We must try and calculate one. 93249ab747fSPaolo Bonzini */ 93349ab747fSPaolo Bonzini 93449ab747fSPaolo Bonzini memcpy(rxbuf, buf, size); 93549ab747fSPaolo Bonzini memset(rxbuf + size, 0, sizeof(rxbuf) - size); 93649ab747fSPaolo Bonzini rxbuf_ptr = rxbuf; 93749ab747fSPaolo Bonzini crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 938c94239feSPeter Maydell memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 93949ab747fSPaolo Bonzini 94049ab747fSPaolo Bonzini bytes_to_copy += 4; 94149ab747fSPaolo Bonzini size += 4; 94249ab747fSPaolo Bonzini } 94349ab747fSPaolo Bonzini 94449ab747fSPaolo Bonzini DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 94549ab747fSPaolo Bonzini 946b12227afSStefan Weil /* Find which queue we are targeting */ 947e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 948e8e49943SAlistair Francis 9497cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 95006c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 95106c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 95206c2fe95SPeter Crosthwaite assert(!first_desc); 95349ab747fSPaolo Bonzini return -1; 95449ab747fSPaolo Bonzini } 95549ab747fSPaolo Bonzini 95649ab747fSPaolo Bonzini DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 9572bf57f73SAlistair Francis rx_desc_get_buffer(s->rx_desc[q])); 95849ab747fSPaolo Bonzini 95949ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 960*84aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 9612bf57f73SAlistair Francis rxbuf_offset, 962*84aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 963e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 96449ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 96530570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 9663b2c97f9SEdgar E. Iglesias 9673b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 9683b2c97f9SEdgar E. Iglesias if (first_desc) { 9692bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 9703b2c97f9SEdgar E. Iglesias first_desc = false; 9713b2c97f9SEdgar E. Iglesias } 9723b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 9732bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 9742bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 9753b2c97f9SEdgar E. Iglesias } 9762bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 97763af1e0cSPeter Crosthwaite 97863af1e0cSPeter Crosthwaite switch (maf) { 97963af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 98063af1e0cSPeter Crosthwaite break; 98163af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 9822bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 98363af1e0cSPeter Crosthwaite break; 98463af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 9852bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 98663af1e0cSPeter Crosthwaite break; 98763af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 9882bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 98963af1e0cSPeter Crosthwaite break; 99063af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 99163af1e0cSPeter Crosthwaite abort(); 99263af1e0cSPeter Crosthwaite default: /* SAR */ 9932bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 99463af1e0cSPeter Crosthwaite } 99563af1e0cSPeter Crosthwaite 9963b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 997*84aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, s->rx_desc_addr[q], 998*84aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 9992bf57f73SAlistair Francis (uint8_t *)s->rx_desc[q], 1000e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 10013b2c97f9SEdgar E. Iglesias 100249ab747fSPaolo Bonzini /* Next descriptor */ 10032bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 100449ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 10052bf57f73SAlistair Francis s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; 100649ab747fSPaolo Bonzini } else { 100749ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1008e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 100949ab747fSPaolo Bonzini } 101067101725SAlistair Francis 101167101725SAlistair Francis gem_get_rx_desc(s, q); 10127cfd65e4SPeter Crosthwaite } 101349ab747fSPaolo Bonzini 101449ab747fSPaolo Bonzini /* Count it */ 101549ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 101649ab747fSPaolo Bonzini 101749ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 101849ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 101949ab747fSPaolo Bonzini 102049ab747fSPaolo Bonzini /* Handle interrupt consequences */ 102149ab747fSPaolo Bonzini gem_update_int_status(s); 102249ab747fSPaolo Bonzini 102349ab747fSPaolo Bonzini return size; 102449ab747fSPaolo Bonzini } 102549ab747fSPaolo Bonzini 102649ab747fSPaolo Bonzini /* 102749ab747fSPaolo Bonzini * gem_transmit_updatestats: 102849ab747fSPaolo Bonzini * Increment transmit statistics. 102949ab747fSPaolo Bonzini */ 1030448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 103149ab747fSPaolo Bonzini unsigned bytes) 103249ab747fSPaolo Bonzini { 103349ab747fSPaolo Bonzini uint64_t octets; 103449ab747fSPaolo Bonzini 103549ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 103649ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 103749ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 103849ab747fSPaolo Bonzini octets += bytes; 103949ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 104049ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 104149ab747fSPaolo Bonzini 104249ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 104349ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 104449ab747fSPaolo Bonzini 104549ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 104649ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 104749ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 104849ab747fSPaolo Bonzini } 104949ab747fSPaolo Bonzini 105049ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 105149ab747fSPaolo Bonzini if (packet[0] == 0x01) { 105249ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 105349ab747fSPaolo Bonzini } 105449ab747fSPaolo Bonzini 105549ab747fSPaolo Bonzini if (bytes <= 64) { 105649ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 105749ab747fSPaolo Bonzini } else if (bytes <= 127) { 105849ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 105949ab747fSPaolo Bonzini } else if (bytes <= 255) { 106049ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 106149ab747fSPaolo Bonzini } else if (bytes <= 511) { 106249ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 106349ab747fSPaolo Bonzini } else if (bytes <= 1023) { 106449ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 106549ab747fSPaolo Bonzini } else if (bytes <= 1518) { 106649ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 106749ab747fSPaolo Bonzini } else { 106849ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 106949ab747fSPaolo Bonzini } 107049ab747fSPaolo Bonzini } 107149ab747fSPaolo Bonzini 107249ab747fSPaolo Bonzini /* 107349ab747fSPaolo Bonzini * gem_transmit: 107449ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 107549ab747fSPaolo Bonzini */ 1076448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 107749ab747fSPaolo Bonzini { 10788568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 107949ab747fSPaolo Bonzini hwaddr packet_desc_addr; 108049ab747fSPaolo Bonzini uint8_t tx_packet[2048]; 108149ab747fSPaolo Bonzini uint8_t *p; 108249ab747fSPaolo Bonzini unsigned total_bytes; 10832bf57f73SAlistair Francis int q = 0; 108449ab747fSPaolo Bonzini 108549ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 108649ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 108749ab747fSPaolo Bonzini return; 108849ab747fSPaolo Bonzini } 108949ab747fSPaolo Bonzini 109049ab747fSPaolo Bonzini DB_PRINT("\n"); 109149ab747fSPaolo Bonzini 10923048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 109349ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 109449ab747fSPaolo Bonzini * one contiguous buffer first. 109549ab747fSPaolo Bonzini */ 109649ab747fSPaolo Bonzini p = tx_packet; 109749ab747fSPaolo Bonzini total_bytes = 0; 109849ab747fSPaolo Bonzini 109967101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 110049ab747fSPaolo Bonzini /* read current descriptor */ 11012bf57f73SAlistair Francis packet_desc_addr = s->tx_desc_addr[q]; 1102fa15286aSPeter Crosthwaite 1103fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1104*84aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1105*84aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, 1106e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 110749ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 110849ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 110949ab747fSPaolo Bonzini 111049ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 111149ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 111249ab747fSPaolo Bonzini return; 111349ab747fSPaolo Bonzini } 111467101725SAlistair Francis print_gem_tx_desc(desc, q); 111549ab747fSPaolo Bonzini 111649ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 111749ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 111849ab747fSPaolo Bonzini */ 1119e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 112049ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 112149ab747fSPaolo Bonzini DB_PRINT("Invalid TX descriptor @ 0x%x\n", 112249ab747fSPaolo Bonzini (unsigned)packet_desc_addr); 112349ab747fSPaolo Bonzini break; 112449ab747fSPaolo Bonzini } 112549ab747fSPaolo Bonzini 112677524d11SAlistair Francis if (tx_desc_get_length(desc) > sizeof(tx_packet) - 112777524d11SAlistair Francis (p - tx_packet)) { 112877524d11SAlistair Francis DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \ 112977524d11SAlistair Francis "0x%x\n", (unsigned)packet_desc_addr, 1130d7f05365SMichael S. Tsirkin (unsigned)tx_desc_get_length(desc), 1131d7f05365SMichael S. Tsirkin sizeof(tx_packet) - (p - tx_packet)); 1132d7f05365SMichael S. Tsirkin break; 1133d7f05365SMichael S. Tsirkin } 1134d7f05365SMichael S. Tsirkin 113577524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 113677524d11SAlistair Francis * contig buffer. 113749ab747fSPaolo Bonzini */ 1138*84aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 1139*84aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 1140*84aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 114149ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 114249ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 114349ab747fSPaolo Bonzini 114449ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 114549ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 11468568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 11476ab57a6bSPeter Crosthwaite 114849ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 114949ab747fSPaolo Bonzini * the processor. 115049ab747fSPaolo Bonzini */ 1151*84aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, s->tx_desc_addr[q], 1152*84aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 115377524d11SAlistair Francis (uint8_t *)desc_first, 11546ab57a6bSPeter Crosthwaite sizeof(desc_first)); 11556ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1156*84aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, s->tx_desc_addr[q], 1157*84aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 115877524d11SAlistair Francis (uint8_t *)desc_first, 11596ab57a6bSPeter Crosthwaite sizeof(desc_first)); 11603048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 116149ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 11622bf57f73SAlistair Francis s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; 116349ab747fSPaolo Bonzini } else { 1164e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1165e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 116649ab747fSPaolo Bonzini } 11672bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 116849ab747fSPaolo Bonzini 116949ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 117049ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 117149ab747fSPaolo Bonzini 117267101725SAlistair Francis /* Update queue interrupt status */ 117367101725SAlistair Francis if (s->num_priority_queues > 1) { 117467101725SAlistair Francis s->regs[GEM_INT_Q1_STATUS + q] |= 117567101725SAlistair Francis GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]); 117667101725SAlistair Francis } 117767101725SAlistair Francis 117849ab747fSPaolo Bonzini /* Handle interrupt consequences */ 117949ab747fSPaolo Bonzini gem_update_int_status(s); 118049ab747fSPaolo Bonzini 118149ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 118249ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 118349ab747fSPaolo Bonzini net_checksum_calculate(tx_packet, total_bytes); 118449ab747fSPaolo Bonzini } 118549ab747fSPaolo Bonzini 118649ab747fSPaolo Bonzini /* Update MAC statistics */ 118749ab747fSPaolo Bonzini gem_transmit_updatestats(s, tx_packet, total_bytes); 118849ab747fSPaolo Bonzini 118949ab747fSPaolo Bonzini /* Send the packet somewhere */ 119077524d11SAlistair Francis if (s->phy_loop || (s->regs[GEM_NWCTRL] & 119177524d11SAlistair Francis GEM_NWCTRL_LOCALLOOP)) { 119277524d11SAlistair Francis gem_receive(qemu_get_queue(s->nic), tx_packet, 119377524d11SAlistair Francis total_bytes); 119449ab747fSPaolo Bonzini } else { 119549ab747fSPaolo Bonzini qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 119649ab747fSPaolo Bonzini total_bytes); 119749ab747fSPaolo Bonzini } 119849ab747fSPaolo Bonzini 119949ab747fSPaolo Bonzini /* Prepare for next packet */ 120049ab747fSPaolo Bonzini p = tx_packet; 120149ab747fSPaolo Bonzini total_bytes = 0; 120249ab747fSPaolo Bonzini } 120349ab747fSPaolo Bonzini 120449ab747fSPaolo Bonzini /* read next descriptor */ 120549ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1206cbdab58dSAlistair Francis tx_desc_set_last(desc); 120749ab747fSPaolo Bonzini packet_desc_addr = s->regs[GEM_TXQBASE]; 120849ab747fSPaolo Bonzini } else { 1209e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 121049ab747fSPaolo Bonzini } 1211fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 1212*84aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1213*84aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, 1214e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 121549ab747fSPaolo Bonzini } 121649ab747fSPaolo Bonzini 121749ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 121849ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 121949ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 122049ab747fSPaolo Bonzini gem_update_int_status(s); 122149ab747fSPaolo Bonzini } 122249ab747fSPaolo Bonzini } 122367101725SAlistair Francis } 122449ab747fSPaolo Bonzini 1225448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 122649ab747fSPaolo Bonzini { 122749ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 122849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 122949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 123049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 123149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 123249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 123349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 123449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 123549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 123649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 123749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 123849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 123949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 124049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 12417777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 124249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 124349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 124449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 124549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 124649ab747fSPaolo Bonzini 124749ab747fSPaolo Bonzini phy_update_link(s); 124849ab747fSPaolo Bonzini } 124949ab747fSPaolo Bonzini 125049ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 125149ab747fSPaolo Bonzini { 125264eb9301SPeter Crosthwaite int i; 1253448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1254afb4c51fSSebastian Huber const uint8_t *a; 125549ab747fSPaolo Bonzini 125649ab747fSPaolo Bonzini DB_PRINT("\n"); 125749ab747fSPaolo Bonzini 125849ab747fSPaolo Bonzini /* Set post reset register values */ 125949ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 126049ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 126149ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 126249ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 126349ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 126449ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 126549ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 126649ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1267a5517666SAlistair Francis s->regs[GEM_MODID] = s->revision; 126849ab747fSPaolo Bonzini s->regs[GEM_DESCONF] = 0x02500111; 126949ab747fSPaolo Bonzini s->regs[GEM_DESCONF2] = 0x2ab13fff; 1270b2d43091SEdgar E. Iglesias s->regs[GEM_DESCONF5] = 0x002f2045; 127149ab747fSPaolo Bonzini s->regs[GEM_DESCONF6] = 0x00000200; 127249ab747fSPaolo Bonzini 1273afb4c51fSSebastian Huber /* Set MAC address */ 1274afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1275afb4c51fSSebastian Huber s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1276afb4c51fSSebastian Huber s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1277afb4c51fSSebastian Huber 127864eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 127964eb9301SPeter Crosthwaite s->sar_active[i] = false; 128064eb9301SPeter Crosthwaite } 128164eb9301SPeter Crosthwaite 128249ab747fSPaolo Bonzini gem_phy_reset(s); 128349ab747fSPaolo Bonzini 128449ab747fSPaolo Bonzini gem_update_int_status(s); 128549ab747fSPaolo Bonzini } 128649ab747fSPaolo Bonzini 1287448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 128849ab747fSPaolo Bonzini { 128949ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 129049ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 129149ab747fSPaolo Bonzini } 129249ab747fSPaolo Bonzini 1293448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 129449ab747fSPaolo Bonzini { 129549ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 129649ab747fSPaolo Bonzini 129749ab747fSPaolo Bonzini switch (reg_num) { 129849ab747fSPaolo Bonzini case PHY_REG_CONTROL: 129949ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 130049ab747fSPaolo Bonzini /* Phy reset */ 130149ab747fSPaolo Bonzini gem_phy_reset(s); 130249ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 130349ab747fSPaolo Bonzini s->phy_loop = 0; 130449ab747fSPaolo Bonzini } 130549ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 130649ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 130749ab747fSPaolo Bonzini val &= ~PHY_REG_CONTROL_ANEG; 130849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 130949ab747fSPaolo Bonzini } 131049ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 131149ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 131249ab747fSPaolo Bonzini s->phy_loop = 1; 131349ab747fSPaolo Bonzini } else { 131449ab747fSPaolo Bonzini s->phy_loop = 0; 131549ab747fSPaolo Bonzini } 131649ab747fSPaolo Bonzini break; 131749ab747fSPaolo Bonzini } 131849ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 131949ab747fSPaolo Bonzini } 132049ab747fSPaolo Bonzini 132149ab747fSPaolo Bonzini /* 132249ab747fSPaolo Bonzini * gem_read32: 132349ab747fSPaolo Bonzini * Read a GEM register. 132449ab747fSPaolo Bonzini */ 132549ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 132649ab747fSPaolo Bonzini { 1327448f19e2SPeter Crosthwaite CadenceGEMState *s; 132849ab747fSPaolo Bonzini uint32_t retval; 1329448f19e2SPeter Crosthwaite s = (CadenceGEMState *)opaque; 133049ab747fSPaolo Bonzini 133149ab747fSPaolo Bonzini offset >>= 2; 133249ab747fSPaolo Bonzini retval = s->regs[offset]; 133349ab747fSPaolo Bonzini 133449ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 133549ab747fSPaolo Bonzini 133649ab747fSPaolo Bonzini switch (offset) { 133749ab747fSPaolo Bonzini case GEM_ISR: 133867101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1339596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 134049ab747fSPaolo Bonzini break; 134149ab747fSPaolo Bonzini case GEM_PHYMNTNC: 134249ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 134349ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 134449ab747fSPaolo Bonzini 134549ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 134655389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 134749ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 134849ab747fSPaolo Bonzini retval &= 0xFFFF0000; 134949ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 135049ab747fSPaolo Bonzini } else { 135149ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 135249ab747fSPaolo Bonzini } 135349ab747fSPaolo Bonzini } 135449ab747fSPaolo Bonzini break; 135549ab747fSPaolo Bonzini } 135649ab747fSPaolo Bonzini 135749ab747fSPaolo Bonzini /* Squash read to clear bits */ 135849ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 135949ab747fSPaolo Bonzini 136049ab747fSPaolo Bonzini /* Do not provide write only bits */ 136149ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 136249ab747fSPaolo Bonzini 136349ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 136467101725SAlistair Francis gem_update_int_status(s); 136549ab747fSPaolo Bonzini return retval; 136649ab747fSPaolo Bonzini } 136749ab747fSPaolo Bonzini 136849ab747fSPaolo Bonzini /* 136949ab747fSPaolo Bonzini * gem_write32: 137049ab747fSPaolo Bonzini * Write a GEM register. 137149ab747fSPaolo Bonzini */ 137249ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 137349ab747fSPaolo Bonzini unsigned size) 137449ab747fSPaolo Bonzini { 1375448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 137649ab747fSPaolo Bonzini uint32_t readonly; 137767101725SAlistair Francis int i; 137849ab747fSPaolo Bonzini 137949ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 138049ab747fSPaolo Bonzini offset >>= 2; 138149ab747fSPaolo Bonzini 138249ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 138349ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1384e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1385e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 138649ab747fSPaolo Bonzini 138749ab747fSPaolo Bonzini /* Copy register write to backing store */ 1388e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1389e2314fdaSPeter Crosthwaite 1390e2314fdaSPeter Crosthwaite /* do w1c */ 1391e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 139249ab747fSPaolo Bonzini 139349ab747fSPaolo Bonzini /* Handle register write side effects */ 139449ab747fSPaolo Bonzini switch (offset) { 139549ab747fSPaolo Bonzini case GEM_NWCTRL: 139606c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 139767101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 139867101725SAlistair Francis gem_get_rx_desc(s, i); 139967101725SAlistair Francis } 140006c2fe95SPeter Crosthwaite } 140149ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 140249ab747fSPaolo Bonzini gem_transmit(s); 140349ab747fSPaolo Bonzini } 140449ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 140549ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 140667101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 140767101725SAlistair Francis s->tx_desc_addr[i] = s->regs[GEM_TXQBASE]; 140867101725SAlistair Francis } 140949ab747fSPaolo Bonzini } 14108202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 141149ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 141249ab747fSPaolo Bonzini } 141349ab747fSPaolo Bonzini break; 141449ab747fSPaolo Bonzini 141549ab747fSPaolo Bonzini case GEM_TXSTATUS: 141649ab747fSPaolo Bonzini gem_update_int_status(s); 141749ab747fSPaolo Bonzini break; 141849ab747fSPaolo Bonzini case GEM_RXQBASE: 14192bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 142049ab747fSPaolo Bonzini break; 142179b2ac8fSAlistair Francis case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 142267101725SAlistair Francis s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 142367101725SAlistair Francis break; 142449ab747fSPaolo Bonzini case GEM_TXQBASE: 14252bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 142649ab747fSPaolo Bonzini break; 142779b2ac8fSAlistair Francis case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 142867101725SAlistair Francis s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 142967101725SAlistair Francis break; 143049ab747fSPaolo Bonzini case GEM_RXSTATUS: 143149ab747fSPaolo Bonzini gem_update_int_status(s); 143249ab747fSPaolo Bonzini break; 143349ab747fSPaolo Bonzini case GEM_IER: 143449ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 143549ab747fSPaolo Bonzini gem_update_int_status(s); 143649ab747fSPaolo Bonzini break; 143767101725SAlistair Francis case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 143867101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 143967101725SAlistair Francis gem_update_int_status(s); 144067101725SAlistair Francis break; 144149ab747fSPaolo Bonzini case GEM_IDR: 144249ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 144349ab747fSPaolo Bonzini gem_update_int_status(s); 144449ab747fSPaolo Bonzini break; 144567101725SAlistair Francis case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 144667101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 144767101725SAlistair Francis gem_update_int_status(s); 144867101725SAlistair Francis break; 144964eb9301SPeter Crosthwaite case GEM_SPADDR1LO: 145064eb9301SPeter Crosthwaite case GEM_SPADDR2LO: 145164eb9301SPeter Crosthwaite case GEM_SPADDR3LO: 145264eb9301SPeter Crosthwaite case GEM_SPADDR4LO: 145364eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 145464eb9301SPeter Crosthwaite break; 145564eb9301SPeter Crosthwaite case GEM_SPADDR1HI: 145664eb9301SPeter Crosthwaite case GEM_SPADDR2HI: 145764eb9301SPeter Crosthwaite case GEM_SPADDR3HI: 145864eb9301SPeter Crosthwaite case GEM_SPADDR4HI: 145964eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 146064eb9301SPeter Crosthwaite break; 146149ab747fSPaolo Bonzini case GEM_PHYMNTNC: 146249ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 146349ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 146449ab747fSPaolo Bonzini 146549ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 146655389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 146749ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 146849ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 146949ab747fSPaolo Bonzini } 147049ab747fSPaolo Bonzini } 147149ab747fSPaolo Bonzini break; 147249ab747fSPaolo Bonzini } 147349ab747fSPaolo Bonzini 147449ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 147549ab747fSPaolo Bonzini } 147649ab747fSPaolo Bonzini 147749ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 147849ab747fSPaolo Bonzini .read = gem_read, 147949ab747fSPaolo Bonzini .write = gem_write, 148049ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 148149ab747fSPaolo Bonzini }; 148249ab747fSPaolo Bonzini 148349ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 148449ab747fSPaolo Bonzini { 148567101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 148667101725SAlistair Francis 148749ab747fSPaolo Bonzini DB_PRINT("\n"); 148867101725SAlistair Francis phy_update_link(s); 148967101725SAlistair Francis gem_update_int_status(s); 149049ab747fSPaolo Bonzini } 149149ab747fSPaolo Bonzini 149249ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1493f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 149449ab747fSPaolo Bonzini .size = sizeof(NICState), 149549ab747fSPaolo Bonzini .can_receive = gem_can_receive, 149649ab747fSPaolo Bonzini .receive = gem_receive, 149749ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 149849ab747fSPaolo Bonzini }; 149949ab747fSPaolo Bonzini 1500bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 150149ab747fSPaolo Bonzini { 1502448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 150367101725SAlistair Francis int i; 150449ab747fSPaolo Bonzini 1505*84aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 1506*84aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 1507*84aec8efSEdgar E. Iglesias 15082bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 15092bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 15102bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 15112bf57f73SAlistair Francis s->num_priority_queues); 15122bf57f73SAlistair Francis return; 1513e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1514e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1515e8e49943SAlistair Francis s->num_type1_screeners); 1516e8e49943SAlistair Francis return; 1517e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1518e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1519e8e49943SAlistair Francis s->num_type2_screeners); 1520e8e49943SAlistair Francis return; 15212bf57f73SAlistair Francis } 15222bf57f73SAlistair Francis 152367101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 152467101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 152567101725SAlistair Francis } 1526bcb39a65SAlistair Francis 1527bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1528bcb39a65SAlistair Francis 1529bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1530bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 1531bcb39a65SAlistair Francis } 1532bcb39a65SAlistair Francis 1533bcb39a65SAlistair Francis static void gem_init(Object *obj) 1534bcb39a65SAlistair Francis { 1535bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1536bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1537bcb39a65SAlistair Francis 153849ab747fSPaolo Bonzini DB_PRINT("\n"); 153949ab747fSPaolo Bonzini 154049ab747fSPaolo Bonzini gem_init_register_masks(s); 1541eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1542eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 154349ab747fSPaolo Bonzini 1544bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 1545*84aec8efSEdgar E. Iglesias 1546*84aec8efSEdgar E. Iglesias object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 1547*84aec8efSEdgar E. Iglesias (Object **)&s->dma_mr, 1548*84aec8efSEdgar E. Iglesias qdev_prop_allow_set_link_before_realize, 1549*84aec8efSEdgar E. Iglesias OBJ_PROP_LINK_STRONG, 1550*84aec8efSEdgar E. Iglesias &error_abort); 155149ab747fSPaolo Bonzini } 155249ab747fSPaolo Bonzini 155349ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 155449ab747fSPaolo Bonzini .name = "cadence_gem", 1555e8e49943SAlistair Francis .version_id = 4, 1556e8e49943SAlistair Francis .minimum_version_id = 4, 155749ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1558448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1559448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1560448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 15612bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 15622bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 15632bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 15642bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1565448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 156617cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 156749ab747fSPaolo Bonzini } 156849ab747fSPaolo Bonzini }; 156949ab747fSPaolo Bonzini 157049ab747fSPaolo Bonzini static Property gem_properties[] = { 1571448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1572a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1573a5517666SAlistair Francis GEM_MODID_VALUE), 15742bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 15752bf57f73SAlistair Francis num_priority_queues, 1), 1576e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1577e8e49943SAlistair Francis num_type1_screeners, 4), 1578e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1579e8e49943SAlistair Francis num_type2_screeners, 4), 158049ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 158149ab747fSPaolo Bonzini }; 158249ab747fSPaolo Bonzini 158349ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 158449ab747fSPaolo Bonzini { 158549ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 158649ab747fSPaolo Bonzini 1587bcb39a65SAlistair Francis dc->realize = gem_realize; 158849ab747fSPaolo Bonzini dc->props = gem_properties; 158949ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 159049ab747fSPaolo Bonzini dc->reset = gem_reset; 159149ab747fSPaolo Bonzini } 159249ab747fSPaolo Bonzini 159349ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1594318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 159549ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1596448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1597bcb39a65SAlistair Francis .instance_init = gem_init, 1598318643beSAndreas Färber .class_init = gem_class_init, 159949ab747fSPaolo Bonzini }; 160049ab747fSPaolo Bonzini 160149ab747fSPaolo Bonzini static void gem_register_types(void) 160249ab747fSPaolo Bonzini { 160349ab747fSPaolo Bonzini type_register_static(&gem_info); 160449ab747fSPaolo Bonzini } 160549ab747fSPaolo Bonzini 160649ab747fSPaolo Bonzini type_init(gem_register_types) 1607