149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31c755c943SLuc Michel #include "hw/registerfields.h" 32d6454270SMarkus Armbruster #include "migration/vmstate.h" 332bf57f73SAlistair Francis #include "qapi/error.h" 34e8e49943SAlistair Francis #include "qemu/log.h" 350b8fa32fSMarkus Armbruster #include "qemu/module.h" 3684aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3749ab747fSPaolo Bonzini #include "net/checksum.h" 38fbc14a09STong Ho #include "net/eth.h" 3949ab747fSPaolo Bonzini 406fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 4149ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 426fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 436fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 446fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 456fe7661dSSai Pavan Boddu } \ 462562755eSEric Blake } while (0) 4749ab747fSPaolo Bonzini 48c755c943SLuc Michel REG32(NWCTRL, 0x0) /* Network Control reg */ 49bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK , 0, 1) 50bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) 51bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) 52bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) 53bd8a922dSLuc Michel FIELD(NWCTRL, MAN_PORT_EN , 4, 1) 54bd8a922dSLuc Michel FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) 55bd8a922dSLuc Michel FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) 56bd8a922dSLuc Michel FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) 57bd8a922dSLuc Michel FIELD(NWCTRL, BACK_PRESSURE, 8, 1) 58bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_START , 9, 1) 59bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) 60bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) 61bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) 62bd8a922dSLuc Michel FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) 63bd8a922dSLuc Michel FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) 64bd8a922dSLuc Michel FIELD(NWCTRL, STORE_RX_TS, 15, 1) 65bd8a922dSLuc Michel FIELD(NWCTRL, PFC_ENABLE, 16, 1) 66bd8a922dSLuc Michel FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) 67bd8a922dSLuc Michel FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) 68bd8a922dSLuc Michel FIELD(NWCTRL, TX_LPI_EN, 19, 1) 69bd8a922dSLuc Michel FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) 70bd8a922dSLuc Michel FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) 71bd8a922dSLuc Michel FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) 72bd8a922dSLuc Michel FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) 73bd8a922dSLuc Michel FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) 74bd8a922dSLuc Michel FIELD(NWCTRL, PFC_CTRL , 25, 1) 75bd8a922dSLuc Michel FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) 76bd8a922dSLuc Michel FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) 77bd8a922dSLuc Michel FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) 78bd8a922dSLuc Michel FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) 79bd8a922dSLuc Michel FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) 80bd8a922dSLuc Michel 81c755c943SLuc Michel REG32(NWCFG, 0x4) /* Network Config reg */ 8287a49c3fSLuc Michel FIELD(NWCFG, SPEED, 0, 1) 8387a49c3fSLuc Michel FIELD(NWCFG, FULL_DUPLEX, 1, 1) 8487a49c3fSLuc Michel FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) 8587a49c3fSLuc Michel FIELD(NWCFG, JUMBO_FRAMES, 3, 1) 8687a49c3fSLuc Michel FIELD(NWCFG, PROMISC, 4, 1) 8787a49c3fSLuc Michel FIELD(NWCFG, NO_BROADCAST, 5, 1) 8887a49c3fSLuc Michel FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) 8987a49c3fSLuc Michel FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) 9087a49c3fSLuc Michel FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) 9187a49c3fSLuc Michel FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) 9287a49c3fSLuc Michel FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) 9387a49c3fSLuc Michel FIELD(NWCFG, PCS_SELECT, 11, 1) 9487a49c3fSLuc Michel FIELD(NWCFG, RETRY_TEST, 12, 1) 9587a49c3fSLuc Michel FIELD(NWCFG, PAUSE_ENABLE, 13, 1) 9687a49c3fSLuc Michel FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) 9787a49c3fSLuc Michel FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) 9887a49c3fSLuc Michel FIELD(NWCFG, FCS_REMOVE, 17, 1) 9987a49c3fSLuc Michel FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) 10087a49c3fSLuc Michel FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) 10187a49c3fSLuc Michel FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) 10287a49c3fSLuc Michel FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) 10387a49c3fSLuc Michel FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) 10487a49c3fSLuc Michel FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) 10587a49c3fSLuc Michel FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) 10687a49c3fSLuc Michel FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) 10787a49c3fSLuc Michel FIELD(NWCFG, NSP_ACCEPT, 29, 1) 10887a49c3fSLuc Michel FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) 10987a49c3fSLuc Michel FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) 11087a49c3fSLuc Michel 111c755c943SLuc Michel REG32(NWSTATUS, 0x8) /* Network Status reg */ 112c755c943SLuc Michel REG32(USERIO, 0xc) /* User IO reg */ 113c755c943SLuc Michel REG32(DMACFG, 0x10) /* DMA Control reg */ 114c755c943SLuc Michel REG32(TXSTATUS, 0x14) /* TX Status reg */ 115c755c943SLuc Michel REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 116c755c943SLuc Michel REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 117c755c943SLuc Michel REG32(RXSTATUS, 0x20) /* RX Status reg */ 118c755c943SLuc Michel REG32(ISR, 0x24) /* Interrupt Status reg */ 119c755c943SLuc Michel REG32(IER, 0x28) /* Interrupt Enable reg */ 120c755c943SLuc Michel REG32(IDR, 0x2c) /* Interrupt Disable reg */ 121c755c943SLuc Michel REG32(IMR, 0x30) /* Interrupt Mask reg */ 122c755c943SLuc Michel REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 123c755c943SLuc Michel REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 124c755c943SLuc Michel REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 125c755c943SLuc Michel REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 126c755c943SLuc Michel REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 127c755c943SLuc Michel REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 128c755c943SLuc Michel REG32(HASHLO, 0x80) /* Hash Low address reg */ 129c755c943SLuc Michel REG32(HASHHI, 0x84) /* Hash High address reg */ 130c755c943SLuc Michel REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 131c755c943SLuc Michel REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 132c755c943SLuc Michel REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 133c755c943SLuc Michel REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 134c755c943SLuc Michel REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 135c755c943SLuc Michel REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 136c755c943SLuc Michel REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 137c755c943SLuc Michel REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 138c755c943SLuc Michel REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 139c755c943SLuc Michel REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 140c755c943SLuc Michel REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 141c755c943SLuc Michel REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 142c755c943SLuc Michel REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 143c755c943SLuc Michel REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 144c755c943SLuc Michel REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 145c755c943SLuc Michel REG32(MODID, 0xfc) /* Module ID reg */ 146c755c943SLuc Michel REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 147c755c943SLuc Michel REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 148c755c943SLuc Michel REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 149c755c943SLuc Michel REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 150c755c943SLuc Michel REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 151c755c943SLuc Michel REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 152c755c943SLuc Michel REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 153c755c943SLuc Michel REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 154c755c943SLuc Michel REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 155c755c943SLuc Michel REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 156c755c943SLuc Michel REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 157c755c943SLuc Michel REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 158c755c943SLuc Michel REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 159c755c943SLuc Michel REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 160c755c943SLuc Michel REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 161c755c943SLuc Michel REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 162c755c943SLuc Michel REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 163c755c943SLuc Michel REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 164c755c943SLuc Michel REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 165c755c943SLuc Michel REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 166c755c943SLuc Michel REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 167c755c943SLuc Michel REG32(OCTRXHI, 0x154) /* Octects Received register High */ 168c755c943SLuc Michel REG32(RXCNT, 0x158) /* Error-free Frames Received */ 169c755c943SLuc Michel REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 170c755c943SLuc Michel REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 171c755c943SLuc Michel REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 172c755c943SLuc Michel REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 173c755c943SLuc Michel REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 174c755c943SLuc Michel REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 175c755c943SLuc Michel REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 176c755c943SLuc Michel REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 177c755c943SLuc Michel REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 178c755c943SLuc Michel REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 179c755c943SLuc Michel REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 180c755c943SLuc Michel REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 181c755c943SLuc Michel REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 182c755c943SLuc Michel REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 183c755c943SLuc Michel REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 184c755c943SLuc Michel REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 185c755c943SLuc Michel REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 186c755c943SLuc Michel REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 187c755c943SLuc Michel REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 188c755c943SLuc Michel REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 189c755c943SLuc Michel REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 190c755c943SLuc Michel REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 19149ab747fSPaolo Bonzini 192c755c943SLuc Michel REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 193c755c943SLuc Michel REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 194c755c943SLuc Michel REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 195c755c943SLuc Michel REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 196c755c943SLuc Michel REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 197c755c943SLuc Michel REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 198c755c943SLuc Michel REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 199c755c943SLuc Michel REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 200c755c943SLuc Michel REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 201c755c943SLuc Michel REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 202c755c943SLuc Michel REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 203c755c943SLuc Michel REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 20449ab747fSPaolo Bonzini 20549ab747fSPaolo Bonzini /* Design Configuration Registers */ 206c755c943SLuc Michel REG32(DESCONF, 0x280) 207c755c943SLuc Michel REG32(DESCONF2, 0x284) 208c755c943SLuc Michel REG32(DESCONF3, 0x288) 209c755c943SLuc Michel REG32(DESCONF4, 0x28c) 210c755c943SLuc Michel REG32(DESCONF5, 0x290) 211c755c943SLuc Michel REG32(DESCONF6, 0x294) 212e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 213c755c943SLuc Michel REG32(DESCONF7, 0x298) 21449ab747fSPaolo Bonzini 215c755c943SLuc Michel REG32(INT_Q1_STATUS, 0x400) 216c755c943SLuc Michel REG32(INT_Q1_MASK, 0x640) 21767101725SAlistair Francis 218c755c943SLuc Michel REG32(TRANSMIT_Q1_PTR, 0x440) 219c755c943SLuc Michel REG32(TRANSMIT_Q7_PTR, 0x458) 22067101725SAlistair Francis 221c755c943SLuc Michel REG32(RECEIVE_Q1_PTR, 0x480) 222c755c943SLuc Michel REG32(RECEIVE_Q7_PTR, 0x498) 22367101725SAlistair Francis 224c755c943SLuc Michel REG32(TBQPH, 0x4c8) 225c755c943SLuc Michel REG32(RBQPH, 0x4d4) 226357aa013SEdgar E. Iglesias 227c755c943SLuc Michel REG32(INT_Q1_ENABLE, 0x600) 228c755c943SLuc Michel REG32(INT_Q7_ENABLE, 0x618) 22967101725SAlistair Francis 230c755c943SLuc Michel REG32(INT_Q1_DISABLE, 0x620) 231c755c943SLuc Michel REG32(INT_Q7_DISABLE, 0x638) 23267101725SAlistair Francis 233c755c943SLuc Michel REG32(SCREENING_TYPE1_REG0, 0x500) 234b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) 235b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) 236b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) 237b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) 238b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) 239b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) 240e8e49943SAlistair Francis 241c755c943SLuc Michel REG32(SCREENING_TYPE2_REG0, 0x540) 242b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) 243b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) 244b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) 245b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) 246b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) 247b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) 248b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) 249b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) 250b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) 251b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) 252b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) 253b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) 254e8e49943SAlistair Francis 255c755c943SLuc Michel REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 256e8e49943SAlistair Francis 257b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 258b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) 259b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) 260b46b526cSLuc Michel 261b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_1, 0x704) 262b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) 263b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) 264b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) 265b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) 266e8e49943SAlistair Francis 26749ab747fSPaolo Bonzini /*****************************************/ 268e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 269e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 270e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2712801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 27249ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 27349ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 27449ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 27549ab747fSPaolo Bonzini 27649ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 27749ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 27849ab747fSPaolo Bonzini 27949ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 28049ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 28149ab747fSPaolo Bonzini 28249ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 28349ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 2847ca151c3SSai Pavan Boddu #define GEM_INT_AMBA_ERR 0x00000040 28549ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 28649ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 28749ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 28849ab747fSPaolo Bonzini 28949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 29049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 29149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 29249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 29349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 29449ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 29549ab747fSPaolo Bonzini 29649ab747fSPaolo Bonzini /* Marvell PHY definitions */ 297dfc38879SBin Meng #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 29849ab747fSPaolo Bonzini 29949ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 30049ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 30149ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 30249ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 30349ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 30449ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 30549ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 30649ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 30749ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 30849ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 30949ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 31049ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 31149ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 31249ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 31349ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 31449ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 31549ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 31649ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 31749ab747fSPaolo Bonzini #define PHY_REG_EACD 22 31849ab747fSPaolo Bonzini #define PHY_REG_LED 24 31949ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 32049ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 32149ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 32249ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 32349ab747fSPaolo Bonzini 32449ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 32549ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 32649ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 3276623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 32849ab747fSPaolo Bonzini 32949ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 33049ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 33149ab747fSPaolo Bonzini 33249ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 33349ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 33449ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 33549ab747fSPaolo Bonzini 33649ab747fSPaolo Bonzini /***********************************************************************/ 33763af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 33863af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 33963af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 34063af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 34163af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 34263af1e0cSPeter Crosthwaite 34363af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 34449ab747fSPaolo Bonzini 34549ab747fSPaolo Bonzini /***********************************************************************/ 34649ab747fSPaolo Bonzini 34749ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 34849ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 34949ab747fSPaolo Bonzini 35049ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 35149ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 35249ab747fSPaolo Bonzini 35349ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 35449ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 35549ab747fSPaolo Bonzini 35663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 35763af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 358a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 35963af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 36063af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 36163af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 36263af1e0cSPeter Crosthwaite 36349ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 36449ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 36549ab747fSPaolo Bonzini 366a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 367a5517666SAlistair Francis 368e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 36949ab747fSPaolo Bonzini { 370e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 371e48fdd9dSEdgar E. Iglesias 372c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 373e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 374e48fdd9dSEdgar E. Iglesias } 375e48fdd9dSEdgar E. Iglesias return ret; 37649ab747fSPaolo Bonzini } 37749ab747fSPaolo Bonzini 378f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 37949ab747fSPaolo Bonzini { 38049ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 38149ab747fSPaolo Bonzini } 38249ab747fSPaolo Bonzini 383f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 38449ab747fSPaolo Bonzini { 38549ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 38649ab747fSPaolo Bonzini } 38749ab747fSPaolo Bonzini 388f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 38949ab747fSPaolo Bonzini { 39049ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 39149ab747fSPaolo Bonzini } 39249ab747fSPaolo Bonzini 393f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 39449ab747fSPaolo Bonzini { 39549ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 39649ab747fSPaolo Bonzini } 39749ab747fSPaolo Bonzini 398f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 39949ab747fSPaolo Bonzini { 40049ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 40149ab747fSPaolo Bonzini } 40249ab747fSPaolo Bonzini 403f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 40449ab747fSPaolo Bonzini { 40567101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 40649ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 40749ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 40849ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 40949ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 41049ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 41149ab747fSPaolo Bonzini } 41249ab747fSPaolo Bonzini 413e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 41449ab747fSPaolo Bonzini { 415e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 416e48fdd9dSEdgar E. Iglesias 417c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 418e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 419e48fdd9dSEdgar E. Iglesias } 420e48fdd9dSEdgar E. Iglesias return ret; 421e48fdd9dSEdgar E. Iglesias } 422e48fdd9dSEdgar E. Iglesias 423e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 424e48fdd9dSEdgar E. Iglesias { 425e48fdd9dSEdgar E. Iglesias int ret = 2; 426e48fdd9dSEdgar E. Iglesias 427c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 428e48fdd9dSEdgar E. Iglesias ret += 2; 429e48fdd9dSEdgar E. Iglesias } 430c755c943SLuc Michel if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 431e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 432e48fdd9dSEdgar E. Iglesias ret += 2; 433e48fdd9dSEdgar E. Iglesias } 434e48fdd9dSEdgar E. Iglesias 435e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 436e48fdd9dSEdgar E. Iglesias return ret; 43749ab747fSPaolo Bonzini } 43849ab747fSPaolo Bonzini 439f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 44049ab747fSPaolo Bonzini { 44149ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 44249ab747fSPaolo Bonzini } 44349ab747fSPaolo Bonzini 444f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 44549ab747fSPaolo Bonzini { 44649ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 44749ab747fSPaolo Bonzini } 44849ab747fSPaolo Bonzini 449f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 45049ab747fSPaolo Bonzini { 45149ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 45249ab747fSPaolo Bonzini } 45349ab747fSPaolo Bonzini 454f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 45549ab747fSPaolo Bonzini { 45649ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 45749ab747fSPaolo Bonzini } 45849ab747fSPaolo Bonzini 45959ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 46059ab136aSRamon Fried { 46159ab136aSRamon Fried desc[1] = 0; 46259ab136aSRamon Fried } 46359ab136aSRamon Fried 464f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 46549ab747fSPaolo Bonzini { 46649ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 46749ab747fSPaolo Bonzini } 46849ab747fSPaolo Bonzini 469f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 47049ab747fSPaolo Bonzini { 47149ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 47249ab747fSPaolo Bonzini desc[1] |= len; 47349ab747fSPaolo Bonzini } 47449ab747fSPaolo Bonzini 475f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 47663af1e0cSPeter Crosthwaite { 47763af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 47863af1e0cSPeter Crosthwaite } 47963af1e0cSPeter Crosthwaite 480f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 48163af1e0cSPeter Crosthwaite { 48263af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 48363af1e0cSPeter Crosthwaite } 48463af1e0cSPeter Crosthwaite 485f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 48663af1e0cSPeter Crosthwaite { 48763af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 48863af1e0cSPeter Crosthwaite } 48963af1e0cSPeter Crosthwaite 490f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 49163af1e0cSPeter Crosthwaite { 49263af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 49363af1e0cSPeter Crosthwaite sar_idx); 494a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 49563af1e0cSPeter Crosthwaite } 49663af1e0cSPeter Crosthwaite 49749ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4986a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 49949ab747fSPaolo Bonzini 5007ca151c3SSai Pavan Boddu static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 5017ca151c3SSai Pavan Boddu { 5027ca151c3SSai Pavan Boddu uint32_t size; 50387a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { 504c755c943SLuc Michel size = s->regs[R_JUMBO_MAX_LEN]; 5057ca151c3SSai Pavan Boddu if (size > s->jumbo_max_len) { 5067ca151c3SSai Pavan Boddu size = s->jumbo_max_len; 5077ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 5087ca151c3SSai Pavan Boddu " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 5097ca151c3SSai Pavan Boddu } 5107ca151c3SSai Pavan Boddu } else if (tx) { 5117ca151c3SSai Pavan Boddu size = 1518; 5127ca151c3SSai Pavan Boddu } else { 51387a49c3fSLuc Michel size = FIELD_EX32(s->regs[R_NWCFG], 51487a49c3fSLuc Michel NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; 5157ca151c3SSai Pavan Boddu } 5167ca151c3SSai Pavan Boddu return size; 5177ca151c3SSai Pavan Boddu } 5187ca151c3SSai Pavan Boddu 51968dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 52068dbee3bSSai Pavan Boddu { 52168dbee3bSSai Pavan Boddu if (q == 0) { 522c755c943SLuc Michel s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 52368dbee3bSSai Pavan Boddu } else { 524c755c943SLuc Michel s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 525c755c943SLuc Michel ~(s->regs[R_INT_Q1_MASK + q - 1]); 52668dbee3bSSai Pavan Boddu } 52768dbee3bSSai Pavan Boddu } 52868dbee3bSSai Pavan Boddu 52949ab747fSPaolo Bonzini /* 53049ab747fSPaolo Bonzini * gem_init_register_masks: 53149ab747fSPaolo Bonzini * One time initialization. 53249ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 53349ab747fSPaolo Bonzini */ 534448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 53549ab747fSPaolo Bonzini { 5364c70e32fSSai Pavan Boddu unsigned int i; 53749ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 53849ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 539c755c943SLuc Michel s->regs_ro[R_NWCTRL] = 0xFFF80000; 540c755c943SLuc Michel s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 541c755c943SLuc Michel s->regs_ro[R_DMACFG] = 0x8E00F000; 542c755c943SLuc Michel s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 543c755c943SLuc Michel s->regs_ro[R_RXQBASE] = 0x00000003; 544c755c943SLuc Michel s->regs_ro[R_TXQBASE] = 0x00000003; 545c755c943SLuc Michel s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 546c755c943SLuc Michel s->regs_ro[R_ISR] = 0xFFFFFFFF; 547c755c943SLuc Michel s->regs_ro[R_IMR] = 0xFFFFFFFF; 548c755c943SLuc Michel s->regs_ro[R_MODID] = 0xFFFFFFFF; 5494c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 550c755c943SLuc Michel s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 551c755c943SLuc Michel s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 552c755c943SLuc Michel s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 553c755c943SLuc Michel s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 5544c70e32fSSai Pavan Boddu } 55549ab747fSPaolo Bonzini 55649ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 55749ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 558c755c943SLuc Michel s->regs_rtc[R_ISR] = 0xFFFFFFFF; 5594c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 560c755c943SLuc Michel s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 5614c70e32fSSai Pavan Boddu } 56249ab747fSPaolo Bonzini 56349ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 56449ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 565c755c943SLuc Michel s->regs_w1c[R_TXSTATUS] = 0x000001F7; 566c755c943SLuc Michel s->regs_w1c[R_RXSTATUS] = 0x0000000F; 56749ab747fSPaolo Bonzini 56849ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 56949ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 570c755c943SLuc Michel s->regs_wo[R_NWCTRL] = 0x00073E60; 571c755c943SLuc Michel s->regs_wo[R_IER] = 0x07FFFFFF; 572c755c943SLuc Michel s->regs_wo[R_IDR] = 0x07FFFFFF; 5734c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 574c755c943SLuc Michel s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 575c755c943SLuc Michel s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 5764c70e32fSSai Pavan Boddu } 57749ab747fSPaolo Bonzini } 57849ab747fSPaolo Bonzini 57949ab747fSPaolo Bonzini /* 58049ab747fSPaolo Bonzini * phy_update_link: 58149ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 58249ab747fSPaolo Bonzini */ 583448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 58449ab747fSPaolo Bonzini { 58549ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 58649ab747fSPaolo Bonzini 58749ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 58849ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 58949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 59049ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 59149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 59249ab747fSPaolo Bonzini } else { 59349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 59449ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 59549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 59649ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 59749ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 59849ab747fSPaolo Bonzini } 59949ab747fSPaolo Bonzini } 60049ab747fSPaolo Bonzini 601b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 60249ab747fSPaolo Bonzini { 603448f19e2SPeter Crosthwaite CadenceGEMState *s; 60467101725SAlistair Francis int i; 60549ab747fSPaolo Bonzini 60649ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 60749ab747fSPaolo Bonzini 60849ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 609bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { 6103ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 6113ae5725fSPeter Crosthwaite s->can_rx_state = 1; 6123ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 6133ae5725fSPeter Crosthwaite } 614b8c4b67eSPhilippe Mathieu-Daudé return false; 61549ab747fSPaolo Bonzini } 61649ab747fSPaolo Bonzini 61767101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 618dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 619dacc0566SAlistair Francis break; 620dacc0566SAlistair Francis } 621dacc0566SAlistair Francis }; 622dacc0566SAlistair Francis 623dacc0566SAlistair Francis if (i == s->num_priority_queues) { 6248202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 6258202aa53SPeter Crosthwaite s->can_rx_state = 2; 626dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 6278202aa53SPeter Crosthwaite } 628b8c4b67eSPhilippe Mathieu-Daudé return false; 6298202aa53SPeter Crosthwaite } 6308202aa53SPeter Crosthwaite 6313ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 6323ae5725fSPeter Crosthwaite s->can_rx_state = 0; 63367101725SAlistair Francis DB_PRINT("can receive\n"); 6343ae5725fSPeter Crosthwaite } 635b8c4b67eSPhilippe Mathieu-Daudé return true; 63649ab747fSPaolo Bonzini } 63749ab747fSPaolo Bonzini 63849ab747fSPaolo Bonzini /* 63949ab747fSPaolo Bonzini * gem_update_int_status: 64049ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 64149ab747fSPaolo Bonzini */ 642448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 64349ab747fSPaolo Bonzini { 64467101725SAlistair Francis int i; 64567101725SAlistair Francis 646c755c943SLuc Michel qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 647596b6f51SAlistair Francis 64886a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 649c755c943SLuc Michel qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 65049ab747fSPaolo Bonzini } 65149ab747fSPaolo Bonzini } 65249ab747fSPaolo Bonzini 65349ab747fSPaolo Bonzini /* 65449ab747fSPaolo Bonzini * gem_receive_updatestats: 65549ab747fSPaolo Bonzini * Increment receive statistics. 65649ab747fSPaolo Bonzini */ 657448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 65849ab747fSPaolo Bonzini unsigned bytes) 65949ab747fSPaolo Bonzini { 66049ab747fSPaolo Bonzini uint64_t octets; 66149ab747fSPaolo Bonzini 66249ab747fSPaolo Bonzini /* Total octets (bytes) received */ 663c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 664c755c943SLuc Michel s->regs[R_OCTRXHI]; 66549ab747fSPaolo Bonzini octets += bytes; 666c755c943SLuc Michel s->regs[R_OCTRXLO] = octets >> 32; 667c755c943SLuc Michel s->regs[R_OCTRXHI] = octets; 66849ab747fSPaolo Bonzini 66949ab747fSPaolo Bonzini /* Error-free Frames received */ 670c755c943SLuc Michel s->regs[R_RXCNT]++; 67149ab747fSPaolo Bonzini 67249ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 67349ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 674c755c943SLuc Michel s->regs[R_RXBROADCNT]++; 67549ab747fSPaolo Bonzini } 67649ab747fSPaolo Bonzini 67749ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 67849ab747fSPaolo Bonzini if (packet[0] == 0x01) { 679c755c943SLuc Michel s->regs[R_RXMULTICNT]++; 68049ab747fSPaolo Bonzini } 68149ab747fSPaolo Bonzini 68249ab747fSPaolo Bonzini if (bytes <= 64) { 683c755c943SLuc Michel s->regs[R_RX64CNT]++; 68449ab747fSPaolo Bonzini } else if (bytes <= 127) { 685c755c943SLuc Michel s->regs[R_RX65CNT]++; 68649ab747fSPaolo Bonzini } else if (bytes <= 255) { 687c755c943SLuc Michel s->regs[R_RX128CNT]++; 68849ab747fSPaolo Bonzini } else if (bytes <= 511) { 689c755c943SLuc Michel s->regs[R_RX256CNT]++; 69049ab747fSPaolo Bonzini } else if (bytes <= 1023) { 691c755c943SLuc Michel s->regs[R_RX512CNT]++; 69249ab747fSPaolo Bonzini } else if (bytes <= 1518) { 693c755c943SLuc Michel s->regs[R_RX1024CNT]++; 69449ab747fSPaolo Bonzini } else { 695c755c943SLuc Michel s->regs[R_RX1519CNT]++; 69649ab747fSPaolo Bonzini } 69749ab747fSPaolo Bonzini } 69849ab747fSPaolo Bonzini 69949ab747fSPaolo Bonzini /* 70049ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 70149ab747fSPaolo Bonzini */ 70249ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 70349ab747fSPaolo Bonzini { 70449ab747fSPaolo Bonzini unsigned byte; 70549ab747fSPaolo Bonzini 70649ab747fSPaolo Bonzini byte = mac[bit / 8]; 70749ab747fSPaolo Bonzini byte >>= (bit & 0x7); 70849ab747fSPaolo Bonzini byte &= 1; 70949ab747fSPaolo Bonzini 71049ab747fSPaolo Bonzini return byte; 71149ab747fSPaolo Bonzini } 71249ab747fSPaolo Bonzini 71349ab747fSPaolo Bonzini /* 71449ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 71549ab747fSPaolo Bonzini */ 71649ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 71749ab747fSPaolo Bonzini { 71849ab747fSPaolo Bonzini int index_bit, mac_bit; 71949ab747fSPaolo Bonzini unsigned hash_index; 72049ab747fSPaolo Bonzini 72149ab747fSPaolo Bonzini hash_index = 0; 72249ab747fSPaolo Bonzini mac_bit = 5; 72349ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 72449ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 72549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 72649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 72749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 72849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 72949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 73049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 73149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 73249ab747fSPaolo Bonzini mac_bit--; 73349ab747fSPaolo Bonzini } 73449ab747fSPaolo Bonzini 73549ab747fSPaolo Bonzini return hash_index; 73649ab747fSPaolo Bonzini } 73749ab747fSPaolo Bonzini 73849ab747fSPaolo Bonzini /* 73949ab747fSPaolo Bonzini * gem_mac_address_filter: 74049ab747fSPaolo Bonzini * Accept or reject this destination address? 74149ab747fSPaolo Bonzini * Returns: 74249ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 74363af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 74463af1e0cSPeter Crosthwaite * others for various other modes of accept: 74563af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 74663af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 74749ab747fSPaolo Bonzini */ 748448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 74949ab747fSPaolo Bonzini { 75049ab747fSPaolo Bonzini uint8_t *gem_spaddr; 751fbc14a09STong Ho int i, is_mc; 75249ab747fSPaolo Bonzini 75349ab747fSPaolo Bonzini /* Promiscuous mode? */ 75487a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { 75563af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 75649ab747fSPaolo Bonzini } 75749ab747fSPaolo Bonzini 75849ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 75949ab747fSPaolo Bonzini /* Reject broadcast packets? */ 76087a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { 76149ab747fSPaolo Bonzini return GEM_RX_REJECT; 76249ab747fSPaolo Bonzini } 76363af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 76449ab747fSPaolo Bonzini } 76549ab747fSPaolo Bonzini 76649ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 767fbc14a09STong Ho is_mc = is_multicast_ether_addr(packet); 76887a49c3fSLuc Michel if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || 76987a49c3fSLuc Michel (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { 770fbc14a09STong Ho uint64_t buckets; 77149ab747fSPaolo Bonzini unsigned hash_index; 77249ab747fSPaolo Bonzini 77349ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 774c755c943SLuc Michel buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 775fbc14a09STong Ho if ((buckets >> hash_index) & 1) { 776fbc14a09STong Ho return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 777fbc14a09STong Ho : GEM_RX_UNICAST_HASH_ACCEPT; 77849ab747fSPaolo Bonzini } 77949ab747fSPaolo Bonzini } 78049ab747fSPaolo Bonzini 78149ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 782c755c943SLuc Michel gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 78363af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 78464eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 78563af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 78649ab747fSPaolo Bonzini } 78749ab747fSPaolo Bonzini } 78849ab747fSPaolo Bonzini 78949ab747fSPaolo Bonzini /* No address match; reject the packet */ 79049ab747fSPaolo Bonzini return GEM_RX_REJECT; 79149ab747fSPaolo Bonzini } 79249ab747fSPaolo Bonzini 793e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 794e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 795e8e49943SAlistair Francis unsigned rxbufsize) 796e8e49943SAlistair Francis { 797e8e49943SAlistair Francis uint32_t reg; 798e8e49943SAlistair Francis bool matched, mismatched; 799e8e49943SAlistair Francis int i, j; 800e8e49943SAlistair Francis 801e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 802c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 803e8e49943SAlistair Francis matched = false; 804e8e49943SAlistair Francis mismatched = false; 805e8e49943SAlistair Francis 806e8e49943SAlistair Francis /* Screening is based on UDP Port */ 807b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { 808e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 809b46b526cSLuc Michel if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { 810e8e49943SAlistair Francis matched = true; 811e8e49943SAlistair Francis } else { 812e8e49943SAlistair Francis mismatched = true; 813e8e49943SAlistair Francis } 814e8e49943SAlistair Francis } 815e8e49943SAlistair Francis 816e8e49943SAlistair Francis /* Screening is based on DS/TC */ 817b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { 818e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 819b46b526cSLuc Michel if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { 820e8e49943SAlistair Francis matched = true; 821e8e49943SAlistair Francis } else { 822e8e49943SAlistair Francis mismatched = true; 823e8e49943SAlistair Francis } 824e8e49943SAlistair Francis } 825e8e49943SAlistair Francis 826e8e49943SAlistair Francis if (matched && !mismatched) { 827b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); 828e8e49943SAlistair Francis } 829e8e49943SAlistair Francis } 830e8e49943SAlistair Francis 831e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 832c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 833e8e49943SAlistair Francis matched = false; 834e8e49943SAlistair Francis mismatched = false; 835e8e49943SAlistair Francis 836b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { 837e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 838b46b526cSLuc Michel int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, 839b46b526cSLuc Michel ETHERTYPE_REG_INDEX); 840e8e49943SAlistair Francis 841e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 842e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 843e8e49943SAlistair Francis "register index: %d\n", et_idx); 844e8e49943SAlistair Francis } 845c755c943SLuc Michel if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 846e8e49943SAlistair Francis et_idx]) { 847e8e49943SAlistair Francis matched = true; 848e8e49943SAlistair Francis } else { 849e8e49943SAlistair Francis mismatched = true; 850e8e49943SAlistair Francis } 851e8e49943SAlistair Francis } 852e8e49943SAlistair Francis 853e8e49943SAlistair Francis /* Compare A, B, C */ 854e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 855b46b526cSLuc Michel uint32_t cr0, cr1, mask, compare; 856e8e49943SAlistair Francis uint16_t rx_cmp; 857e8e49943SAlistair Francis int offset; 858b46b526cSLuc Michel int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, 859b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); 860e8e49943SAlistair Francis 861b46b526cSLuc Michel if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, 862b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { 863e8e49943SAlistair Francis continue; 864e8e49943SAlistair Francis } 865b46b526cSLuc Michel 866e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 867e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 868e8e49943SAlistair Francis "register index: %d\n", cr_idx); 869e8e49943SAlistair Francis } 870e8e49943SAlistair Francis 871c755c943SLuc Michel cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 872b46b526cSLuc Michel cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; 873b46b526cSLuc Michel offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); 874e8e49943SAlistair Francis 875b46b526cSLuc Michel switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { 876e8e49943SAlistair Francis case 3: /* Skip UDP header */ 877e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 878e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 879e8e49943SAlistair Francis offset += 8; 880e8e49943SAlistair Francis /* Fallthrough */ 881e8e49943SAlistair Francis case 2: /* skip the IP header */ 882e8e49943SAlistair Francis offset += 20; 883e8e49943SAlistair Francis /* Fallthrough */ 884e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 885e8e49943SAlistair Francis offset += 14; 886e8e49943SAlistair Francis break; 887e8e49943SAlistair Francis case 0: 888e8e49943SAlistair Francis /* Offset from start of frame */ 889e8e49943SAlistair Francis break; 890e8e49943SAlistair Francis } 891e8e49943SAlistair Francis 892e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 893b46b526cSLuc Michel mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); 894b46b526cSLuc Michel compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); 895e8e49943SAlistair Francis 896b46b526cSLuc Michel if ((rx_cmp & mask) == (compare & mask)) { 897e8e49943SAlistair Francis matched = true; 898e8e49943SAlistair Francis } else { 899e8e49943SAlistair Francis mismatched = true; 900e8e49943SAlistair Francis } 901e8e49943SAlistair Francis } 902e8e49943SAlistair Francis 903e8e49943SAlistair Francis if (matched && !mismatched) { 904b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); 905e8e49943SAlistair Francis } 906e8e49943SAlistair Francis } 907e8e49943SAlistair Francis 908e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 909e8e49943SAlistair Francis return 0; 910e8e49943SAlistair Francis } 911e8e49943SAlistair Francis 91296ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 91396ea126aSSai Pavan Boddu { 91496ea126aSSai Pavan Boddu uint32_t base_addr = 0; 91596ea126aSSai Pavan Boddu 91696ea126aSSai Pavan Boddu switch (q) { 91796ea126aSSai Pavan Boddu case 0: 918c755c943SLuc Michel base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 91996ea126aSSai Pavan Boddu break; 92096ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 921c755c943SLuc Michel base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 922c755c943SLuc Michel R_RECEIVE_Q1_PTR) + q - 1]; 92396ea126aSSai Pavan Boddu break; 92496ea126aSSai Pavan Boddu default: 92596ea126aSSai Pavan Boddu g_assert_not_reached(); 92696ea126aSSai Pavan Boddu }; 92796ea126aSSai Pavan Boddu 92896ea126aSSai Pavan Boddu return base_addr; 92996ea126aSSai Pavan Boddu } 93096ea126aSSai Pavan Boddu 93196ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 93296ea126aSSai Pavan Boddu { 93396ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 93496ea126aSSai Pavan Boddu } 93596ea126aSSai Pavan Boddu 93696ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 93796ea126aSSai Pavan Boddu { 93896ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 93996ea126aSSai Pavan Boddu } 94096ea126aSSai Pavan Boddu 941357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 942357aa013SEdgar E. Iglesias { 943357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 944357aa013SEdgar E. Iglesias 945c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 946c755c943SLuc Michel desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 947357aa013SEdgar E. Iglesias } 948357aa013SEdgar E. Iglesias desc_addr <<= 32; 949357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 950357aa013SEdgar E. Iglesias return desc_addr; 951357aa013SEdgar E. Iglesias } 952357aa013SEdgar E. Iglesias 953357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 954357aa013SEdgar E. Iglesias { 955357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 956357aa013SEdgar E. Iglesias } 957357aa013SEdgar E. Iglesias 958357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 959357aa013SEdgar E. Iglesias { 960357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 961357aa013SEdgar E. Iglesias } 962357aa013SEdgar E. Iglesias 96367101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 96406c2fe95SPeter Crosthwaite { 965357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 966357aa013SEdgar E. Iglesias 967357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 968357aa013SEdgar E. Iglesias 96906c2fe95SPeter Crosthwaite /* read current descriptor */ 970357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 971b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 972e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 97306c2fe95SPeter Crosthwaite 97406c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 97567101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 976357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 977c755c943SLuc Michel s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 97868dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXUSED); 97906c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 98006c2fe95SPeter Crosthwaite gem_update_int_status(s); 98106c2fe95SPeter Crosthwaite } 98206c2fe95SPeter Crosthwaite } 98306c2fe95SPeter Crosthwaite 98449ab747fSPaolo Bonzini /* 98549ab747fSPaolo Bonzini * gem_receive: 98649ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 98749ab747fSPaolo Bonzini */ 98849ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 98949ab747fSPaolo Bonzini { 99024d62fd5SSai Pavan Boddu CadenceGEMState *s = qemu_get_nic_opaque(nc); 99149ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 99249ab747fSPaolo Bonzini unsigned rxbuf_offset; 99349ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 9943b2c97f9SEdgar E. Iglesias bool first_desc = true; 99563af1e0cSPeter Crosthwaite int maf; 9962bf57f73SAlistair Francis int q = 0; 99749ab747fSPaolo Bonzini 99849ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 99963af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 100063af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 10012431f4f1SMichael Tokarev return size; /* no, drop silently b/c it's not an error */ 100249ab747fSPaolo Bonzini } 100349ab747fSPaolo Bonzini 100449ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 100587a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { 100649ab747fSPaolo Bonzini unsigned type_len; 100749ab747fSPaolo Bonzini 100849ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 100949ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 101049ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 101149ab747fSPaolo Bonzini if (type_len < 0x600) { 101249ab747fSPaolo Bonzini if (size < type_len) { 101349ab747fSPaolo Bonzini /* discard */ 101449ab747fSPaolo Bonzini return -1; 101549ab747fSPaolo Bonzini } 101649ab747fSPaolo Bonzini } 101749ab747fSPaolo Bonzini } 101849ab747fSPaolo Bonzini 101949ab747fSPaolo Bonzini /* 102049ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 102149ab747fSPaolo Bonzini */ 102287a49c3fSLuc Michel rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); 102349ab747fSPaolo Bonzini 102449ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 102549ab747fSPaolo Bonzini * buffers needed to hold this packet. 102649ab747fSPaolo Bonzini */ 1027c755c943SLuc Michel rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 102849ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 102949ab747fSPaolo Bonzini bytes_to_copy = size; 103049ab747fSPaolo Bonzini 1031f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 1032f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 1033f265ae8cSAlistair Francis */ 1034f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1035f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1036f265ae8cSAlistair Francis } 1037f265ae8cSAlistair Francis 1038191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 1039191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 1040191946c5SPeter Crosthwaite * not FCS stripping 1041191946c5SPeter Crosthwaite */ 1042191946c5SPeter Crosthwaite if (size < 60) { 1043191946c5SPeter Crosthwaite size = 60; 1044191946c5SPeter Crosthwaite } 1045191946c5SPeter Crosthwaite 104649ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 104787a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { 104849ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 104949ab747fSPaolo Bonzini } else { 105049ab747fSPaolo Bonzini unsigned crc_val; 105149ab747fSPaolo Bonzini 105224d62fd5SSai Pavan Boddu if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 105324d62fd5SSai Pavan Boddu size = MAX_FRAME_SIZE - sizeof(crc_val); 1054244381ecSPrasad J Pandit } 1055244381ecSPrasad J Pandit bytes_to_copy = size; 105649ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 10573048ed6aSPeter Crosthwaite * We must try and calculate one. 105849ab747fSPaolo Bonzini */ 105949ab747fSPaolo Bonzini 106024d62fd5SSai Pavan Boddu memcpy(s->rx_packet, buf, size); 106124d62fd5SSai Pavan Boddu memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 106224d62fd5SSai Pavan Boddu rxbuf_ptr = s->rx_packet; 106324d62fd5SSai Pavan Boddu crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 106424d62fd5SSai Pavan Boddu memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 106549ab747fSPaolo Bonzini 106649ab747fSPaolo Bonzini bytes_to_copy += 4; 106749ab747fSPaolo Bonzini size += 4; 106849ab747fSPaolo Bonzini } 106949ab747fSPaolo Bonzini 10706fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 107149ab747fSPaolo Bonzini 1072b12227afSStefan Weil /* Find which queue we are targeting */ 1073e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1074e8e49943SAlistair Francis 10757ca151c3SSai Pavan Boddu if (size > gem_get_max_buf_len(s, false)) { 10767ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 10777ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 10787ca151c3SSai Pavan Boddu return -1; 10797ca151c3SSai Pavan Boddu } 10807ca151c3SSai Pavan Boddu 10817cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1082357aa013SEdgar E. Iglesias hwaddr desc_addr; 1083357aa013SEdgar E. Iglesias 108406c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 108506c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 108649ab747fSPaolo Bonzini return -1; 108749ab747fSPaolo Bonzini } 108849ab747fSPaolo Bonzini 10896fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1090dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1091dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 109249ab747fSPaolo Bonzini 109349ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 109484aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 10952bf57f73SAlistair Francis rxbuf_offset, 109684aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1097e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 109849ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 109930570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 11003b2c97f9SEdgar E. Iglesias 110159ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 110259ab136aSRamon Fried 11033b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 11043b2c97f9SEdgar E. Iglesias if (first_desc) { 11052bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 11063b2c97f9SEdgar E. Iglesias first_desc = false; 11073b2c97f9SEdgar E. Iglesias } 11083b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 11092bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 11102bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 11113b2c97f9SEdgar E. Iglesias } 11122bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 111363af1e0cSPeter Crosthwaite 111463af1e0cSPeter Crosthwaite switch (maf) { 111563af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 111663af1e0cSPeter Crosthwaite break; 111763af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 11182bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 111963af1e0cSPeter Crosthwaite break; 112063af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 11212bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 112263af1e0cSPeter Crosthwaite break; 112363af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 11242bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 112563af1e0cSPeter Crosthwaite break; 112663af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 112763af1e0cSPeter Crosthwaite abort(); 112863af1e0cSPeter Crosthwaite default: /* SAR */ 11292bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 113063af1e0cSPeter Crosthwaite } 113163af1e0cSPeter Crosthwaite 11323b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1133357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1134b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1135b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1136e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 11373b2c97f9SEdgar E. Iglesias 113849ab747fSPaolo Bonzini /* Next descriptor */ 11392bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 114049ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 114196ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 114249ab747fSPaolo Bonzini } else { 114349ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1144e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 114549ab747fSPaolo Bonzini } 114667101725SAlistair Francis 114767101725SAlistair Francis gem_get_rx_desc(s, q); 11487cfd65e4SPeter Crosthwaite } 114949ab747fSPaolo Bonzini 115049ab747fSPaolo Bonzini /* Count it */ 115149ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 115249ab747fSPaolo Bonzini 1153c755c943SLuc Michel s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 115468dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXCMPL); 115549ab747fSPaolo Bonzini 115649ab747fSPaolo Bonzini /* Handle interrupt consequences */ 115749ab747fSPaolo Bonzini gem_update_int_status(s); 115849ab747fSPaolo Bonzini 115949ab747fSPaolo Bonzini return size; 116049ab747fSPaolo Bonzini } 116149ab747fSPaolo Bonzini 116249ab747fSPaolo Bonzini /* 116349ab747fSPaolo Bonzini * gem_transmit_updatestats: 116449ab747fSPaolo Bonzini * Increment transmit statistics. 116549ab747fSPaolo Bonzini */ 1166448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 116749ab747fSPaolo Bonzini unsigned bytes) 116849ab747fSPaolo Bonzini { 116949ab747fSPaolo Bonzini uint64_t octets; 117049ab747fSPaolo Bonzini 117149ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 1172c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1173c755c943SLuc Michel s->regs[R_OCTTXHI]; 117449ab747fSPaolo Bonzini octets += bytes; 1175c755c943SLuc Michel s->regs[R_OCTTXLO] = octets >> 32; 1176c755c943SLuc Michel s->regs[R_OCTTXHI] = octets; 117749ab747fSPaolo Bonzini 117849ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 1179c755c943SLuc Michel s->regs[R_TXCNT]++; 118049ab747fSPaolo Bonzini 118149ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 118249ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 1183c755c943SLuc Michel s->regs[R_TXBCNT]++; 118449ab747fSPaolo Bonzini } 118549ab747fSPaolo Bonzini 118649ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 118749ab747fSPaolo Bonzini if (packet[0] == 0x01) { 1188c755c943SLuc Michel s->regs[R_TXMCNT]++; 118949ab747fSPaolo Bonzini } 119049ab747fSPaolo Bonzini 119149ab747fSPaolo Bonzini if (bytes <= 64) { 1192c755c943SLuc Michel s->regs[R_TX64CNT]++; 119349ab747fSPaolo Bonzini } else if (bytes <= 127) { 1194c755c943SLuc Michel s->regs[R_TX65CNT]++; 119549ab747fSPaolo Bonzini } else if (bytes <= 255) { 1196c755c943SLuc Michel s->regs[R_TX128CNT]++; 119749ab747fSPaolo Bonzini } else if (bytes <= 511) { 1198c755c943SLuc Michel s->regs[R_TX256CNT]++; 119949ab747fSPaolo Bonzini } else if (bytes <= 1023) { 1200c755c943SLuc Michel s->regs[R_TX512CNT]++; 120149ab747fSPaolo Bonzini } else if (bytes <= 1518) { 1202c755c943SLuc Michel s->regs[R_TX1024CNT]++; 120349ab747fSPaolo Bonzini } else { 1204c755c943SLuc Michel s->regs[R_TX1519CNT]++; 120549ab747fSPaolo Bonzini } 120649ab747fSPaolo Bonzini } 120749ab747fSPaolo Bonzini 120849ab747fSPaolo Bonzini /* 120949ab747fSPaolo Bonzini * gem_transmit: 121049ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 121149ab747fSPaolo Bonzini */ 1212448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 121349ab747fSPaolo Bonzini { 12148568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 121549ab747fSPaolo Bonzini hwaddr packet_desc_addr; 121649ab747fSPaolo Bonzini uint8_t *p; 121749ab747fSPaolo Bonzini unsigned total_bytes; 12182bf57f73SAlistair Francis int q = 0; 121949ab747fSPaolo Bonzini 122049ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1221bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 122249ab747fSPaolo Bonzini return; 122349ab747fSPaolo Bonzini } 122449ab747fSPaolo Bonzini 122549ab747fSPaolo Bonzini DB_PRINT("\n"); 122649ab747fSPaolo Bonzini 12273048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 122849ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 122949ab747fSPaolo Bonzini * one contiguous buffer first. 123049ab747fSPaolo Bonzini */ 123124d62fd5SSai Pavan Boddu p = s->tx_packet; 123249ab747fSPaolo Bonzini total_bytes = 0; 123349ab747fSPaolo Bonzini 123467101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 123549ab747fSPaolo Bonzini /* read current descriptor */ 1236357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1237fa15286aSPeter Crosthwaite 1238fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 123984aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1240b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1241e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 124249ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 124349ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 124449ab747fSPaolo Bonzini 124549ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1246bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 124749ab747fSPaolo Bonzini return; 124849ab747fSPaolo Bonzini } 124967101725SAlistair Francis print_gem_tx_desc(desc, q); 125049ab747fSPaolo Bonzini 125149ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 125249ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 125349ab747fSPaolo Bonzini */ 1254e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 125549ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 12566fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 12576fe7661dSSai Pavan Boddu packet_desc_addr); 125849ab747fSPaolo Bonzini break; 125949ab747fSPaolo Bonzini } 126049ab747fSPaolo Bonzini 12617ca151c3SSai Pavan Boddu if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 126224d62fd5SSai Pavan Boddu (p - s->tx_packet)) { 12637ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 12647ca151c3SSai Pavan Boddu HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1265dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 12667ca151c3SSai Pavan Boddu gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 12677ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1268d7f05365SMichael S. Tsirkin break; 1269d7f05365SMichael S. Tsirkin } 1270d7f05365SMichael S. Tsirkin 127177524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 127277524d11SAlistair Francis * contig buffer. 127349ab747fSPaolo Bonzini */ 127484aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 127584aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 127684aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 127749ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 127849ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 127949ab747fSPaolo Bonzini 128049ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 128149ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 12828568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1283357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 12846ab57a6bSPeter Crosthwaite 128549ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 128649ab747fSPaolo Bonzini * the processor. 128749ab747fSPaolo Bonzini */ 1288357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1289b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12906ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12916ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1292357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1293b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12946ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12953048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 129649ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 129796ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 129849ab747fSPaolo Bonzini } else { 1299e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1300e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 130149ab747fSPaolo Bonzini } 13022bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 130349ab747fSPaolo Bonzini 1304c755c943SLuc Michel s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 130568dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_TXCMPL); 130667101725SAlistair Francis 130749ab747fSPaolo Bonzini /* Handle interrupt consequences */ 130849ab747fSPaolo Bonzini gem_update_int_status(s); 130949ab747fSPaolo Bonzini 131049ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 1311c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1312f5746335SBin Meng net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 131349ab747fSPaolo Bonzini } 131449ab747fSPaolo Bonzini 131549ab747fSPaolo Bonzini /* Update MAC statistics */ 131624d62fd5SSai Pavan Boddu gem_transmit_updatestats(s, s->tx_packet, total_bytes); 131749ab747fSPaolo Bonzini 131849ab747fSPaolo Bonzini /* Send the packet somewhere */ 1319bd8a922dSLuc Michel if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, 1320bd8a922dSLuc Michel LOOPBACK_LOCAL)) { 1321e73adfbeSAlexander Bulekov qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 132277524d11SAlistair Francis total_bytes); 132349ab747fSPaolo Bonzini } else { 132424d62fd5SSai Pavan Boddu qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 132549ab747fSPaolo Bonzini total_bytes); 132649ab747fSPaolo Bonzini } 132749ab747fSPaolo Bonzini 132849ab747fSPaolo Bonzini /* Prepare for next packet */ 132924d62fd5SSai Pavan Boddu p = s->tx_packet; 133049ab747fSPaolo Bonzini total_bytes = 0; 133149ab747fSPaolo Bonzini } 133249ab747fSPaolo Bonzini 133349ab747fSPaolo Bonzini /* read next descriptor */ 133449ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1335c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 1336c755c943SLuc Michel packet_desc_addr = s->regs[R_TBQPH]; 1337f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1338f1e7cb13SRamon Fried } else { 1339f1e7cb13SRamon Fried packet_desc_addr = 0; 1340f1e7cb13SRamon Fried } 134196ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 134249ab747fSPaolo Bonzini } else { 1343e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 134449ab747fSPaolo Bonzini } 1345fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 134684aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1347b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1348e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 134949ab747fSPaolo Bonzini } 135049ab747fSPaolo Bonzini 135149ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 1352c755c943SLuc Michel s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; 135368dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 135468dbee3bSSai Pavan Boddu if (q == 0) { 135568dbee3bSSai Pavan Boddu gem_set_isr(s, 0, GEM_INT_TXUSED); 135668dbee3bSSai Pavan Boddu } 135749ab747fSPaolo Bonzini gem_update_int_status(s); 135849ab747fSPaolo Bonzini } 135949ab747fSPaolo Bonzini } 136067101725SAlistair Francis } 136149ab747fSPaolo Bonzini 1362448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 136349ab747fSPaolo Bonzini { 136449ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 136549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 136649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 136749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 136849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 136949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 137049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 137149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 137249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 137349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 137449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 137549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 137649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 137749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 13787777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 137949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 138049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 138149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 138249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 138349ab747fSPaolo Bonzini 138449ab747fSPaolo Bonzini phy_update_link(s); 138549ab747fSPaolo Bonzini } 138649ab747fSPaolo Bonzini 138749ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 138849ab747fSPaolo Bonzini { 138964eb9301SPeter Crosthwaite int i; 1390448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1391afb4c51fSSebastian Huber const uint8_t *a; 1392726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 139349ab747fSPaolo Bonzini 139449ab747fSPaolo Bonzini DB_PRINT("\n"); 139549ab747fSPaolo Bonzini 139649ab747fSPaolo Bonzini /* Set post reset register values */ 139749ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 1398c755c943SLuc Michel s->regs[R_NWCFG] = 0x00080000; 1399c755c943SLuc Michel s->regs[R_NWSTATUS] = 0x00000006; 1400c755c943SLuc Michel s->regs[R_DMACFG] = 0x00020784; 1401c755c943SLuc Michel s->regs[R_IMR] = 0x07ffffff; 1402c755c943SLuc Michel s->regs[R_TXPAUSE] = 0x0000ffff; 1403c755c943SLuc Michel s->regs[R_TXPARTIALSF] = 0x000003ff; 1404c755c943SLuc Michel s->regs[R_RXPARTIALSF] = 0x000003ff; 1405c755c943SLuc Michel s->regs[R_MODID] = s->revision; 1406c755c943SLuc Michel s->regs[R_DESCONF] = 0x02D00111; 1407c755c943SLuc Michel s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1408c755c943SLuc Michel s->regs[R_DESCONF5] = 0x002f2045; 1409c755c943SLuc Michel s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; 1410c755c943SLuc Michel s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1411c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1412726a2a95SEdgar E. Iglesias 1413726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1414726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1415c755c943SLuc Michel s->regs[R_DESCONF6] |= queues_mask; 1416726a2a95SEdgar E. Iglesias } 141749ab747fSPaolo Bonzini 1418afb4c51fSSebastian Huber /* Set MAC address */ 1419afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1420c755c943SLuc Michel s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1421c755c943SLuc Michel s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1422afb4c51fSSebastian Huber 142364eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 142464eb9301SPeter Crosthwaite s->sar_active[i] = false; 142564eb9301SPeter Crosthwaite } 142664eb9301SPeter Crosthwaite 142749ab747fSPaolo Bonzini gem_phy_reset(s); 142849ab747fSPaolo Bonzini 142949ab747fSPaolo Bonzini gem_update_int_status(s); 143049ab747fSPaolo Bonzini } 143149ab747fSPaolo Bonzini 1432448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 143349ab747fSPaolo Bonzini { 143449ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 143549ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 143649ab747fSPaolo Bonzini } 143749ab747fSPaolo Bonzini 1438448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 143949ab747fSPaolo Bonzini { 144049ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 144149ab747fSPaolo Bonzini 144249ab747fSPaolo Bonzini switch (reg_num) { 144349ab747fSPaolo Bonzini case PHY_REG_CONTROL: 144449ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 144549ab747fSPaolo Bonzini /* Phy reset */ 144649ab747fSPaolo Bonzini gem_phy_reset(s); 144749ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 144849ab747fSPaolo Bonzini s->phy_loop = 0; 144949ab747fSPaolo Bonzini } 145049ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 145149ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 14526623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 145349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 145449ab747fSPaolo Bonzini } 145549ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 145649ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 145749ab747fSPaolo Bonzini s->phy_loop = 1; 145849ab747fSPaolo Bonzini } else { 145949ab747fSPaolo Bonzini s->phy_loop = 0; 146049ab747fSPaolo Bonzini } 146149ab747fSPaolo Bonzini break; 146249ab747fSPaolo Bonzini } 146349ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 146449ab747fSPaolo Bonzini } 146549ab747fSPaolo Bonzini 146649ab747fSPaolo Bonzini /* 146749ab747fSPaolo Bonzini * gem_read32: 146849ab747fSPaolo Bonzini * Read a GEM register. 146949ab747fSPaolo Bonzini */ 147049ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 147149ab747fSPaolo Bonzini { 1472448f19e2SPeter Crosthwaite CadenceGEMState *s; 147349ab747fSPaolo Bonzini uint32_t retval; 14743d558330SMarkus Armbruster s = opaque; 147549ab747fSPaolo Bonzini 147649ab747fSPaolo Bonzini offset >>= 2; 147749ab747fSPaolo Bonzini retval = s->regs[offset]; 147849ab747fSPaolo Bonzini 147949ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 148049ab747fSPaolo Bonzini 148149ab747fSPaolo Bonzini switch (offset) { 1482c755c943SLuc Michel case R_ISR: 148367101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1484596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 148549ab747fSPaolo Bonzini break; 1486c755c943SLuc Michel case R_PHYMNTNC: 148749ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 148849ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 148949ab747fSPaolo Bonzini 149049ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1491dfc38879SBin Meng if (phy_addr == s->phy_addr) { 149249ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 149349ab747fSPaolo Bonzini retval &= 0xFFFF0000; 149449ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 149549ab747fSPaolo Bonzini } else { 149649ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 149749ab747fSPaolo Bonzini } 149849ab747fSPaolo Bonzini } 149949ab747fSPaolo Bonzini break; 150049ab747fSPaolo Bonzini } 150149ab747fSPaolo Bonzini 150249ab747fSPaolo Bonzini /* Squash read to clear bits */ 150349ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 150449ab747fSPaolo Bonzini 150549ab747fSPaolo Bonzini /* Do not provide write only bits */ 150649ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 150749ab747fSPaolo Bonzini 150849ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 150967101725SAlistair Francis gem_update_int_status(s); 151049ab747fSPaolo Bonzini return retval; 151149ab747fSPaolo Bonzini } 151249ab747fSPaolo Bonzini 151349ab747fSPaolo Bonzini /* 151449ab747fSPaolo Bonzini * gem_write32: 151549ab747fSPaolo Bonzini * Write a GEM register. 151649ab747fSPaolo Bonzini */ 151749ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 151849ab747fSPaolo Bonzini unsigned size) 151949ab747fSPaolo Bonzini { 1520448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 152149ab747fSPaolo Bonzini uint32_t readonly; 152267101725SAlistair Francis int i; 152349ab747fSPaolo Bonzini 152449ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 152549ab747fSPaolo Bonzini offset >>= 2; 152649ab747fSPaolo Bonzini 152749ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 152849ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1529e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1530e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 153149ab747fSPaolo Bonzini 153249ab747fSPaolo Bonzini /* Copy register write to backing store */ 1533e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1534e2314fdaSPeter Crosthwaite 1535e2314fdaSPeter Crosthwaite /* do w1c */ 1536e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 153749ab747fSPaolo Bonzini 153849ab747fSPaolo Bonzini /* Handle register write side effects */ 153949ab747fSPaolo Bonzini switch (offset) { 1540c755c943SLuc Michel case R_NWCTRL: 1541bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { 154267101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 154367101725SAlistair Francis gem_get_rx_desc(s, i); 154467101725SAlistair Francis } 154506c2fe95SPeter Crosthwaite } 1546bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { 154749ab747fSPaolo Bonzini gem_transmit(s); 154849ab747fSPaolo Bonzini } 1549bd8a922dSLuc Michel if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { 155049ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 155167101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 155296ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 155367101725SAlistair Francis } 155449ab747fSPaolo Bonzini } 15558202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 155649ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 155749ab747fSPaolo Bonzini } 155849ab747fSPaolo Bonzini break; 155949ab747fSPaolo Bonzini 1560c755c943SLuc Michel case R_TXSTATUS: 156149ab747fSPaolo Bonzini gem_update_int_status(s); 156249ab747fSPaolo Bonzini break; 1563c755c943SLuc Michel case R_RXQBASE: 15642bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 156549ab747fSPaolo Bonzini break; 1566c755c943SLuc Michel case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1567c755c943SLuc Michel s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 156867101725SAlistair Francis break; 1569c755c943SLuc Michel case R_TXQBASE: 15702bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 157149ab747fSPaolo Bonzini break; 1572c755c943SLuc Michel case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1573c755c943SLuc Michel s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 157467101725SAlistair Francis break; 1575c755c943SLuc Michel case R_RXSTATUS: 157649ab747fSPaolo Bonzini gem_update_int_status(s); 157749ab747fSPaolo Bonzini break; 1578c755c943SLuc Michel case R_IER: 1579c755c943SLuc Michel s->regs[R_IMR] &= ~val; 158049ab747fSPaolo Bonzini gem_update_int_status(s); 158149ab747fSPaolo Bonzini break; 1582c755c943SLuc Michel case R_JUMBO_MAX_LEN: 1583c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 15847ca151c3SSai Pavan Boddu break; 1585c755c943SLuc Michel case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1586c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 158767101725SAlistair Francis gem_update_int_status(s); 158867101725SAlistair Francis break; 1589c755c943SLuc Michel case R_IDR: 1590c755c943SLuc Michel s->regs[R_IMR] |= val; 159149ab747fSPaolo Bonzini gem_update_int_status(s); 159249ab747fSPaolo Bonzini break; 1593c755c943SLuc Michel case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1594c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 159567101725SAlistair Francis gem_update_int_status(s); 159667101725SAlistair Francis break; 1597c755c943SLuc Michel case R_SPADDR1LO: 1598c755c943SLuc Michel case R_SPADDR2LO: 1599c755c943SLuc Michel case R_SPADDR3LO: 1600c755c943SLuc Michel case R_SPADDR4LO: 1601c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 160264eb9301SPeter Crosthwaite break; 1603c755c943SLuc Michel case R_SPADDR1HI: 1604c755c943SLuc Michel case R_SPADDR2HI: 1605c755c943SLuc Michel case R_SPADDR3HI: 1606c755c943SLuc Michel case R_SPADDR4HI: 1607c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 160864eb9301SPeter Crosthwaite break; 1609c755c943SLuc Michel case R_PHYMNTNC: 161049ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 161149ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 161249ab747fSPaolo Bonzini 161349ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1614dfc38879SBin Meng if (phy_addr == s->phy_addr) { 161549ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 161649ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 161749ab747fSPaolo Bonzini } 161849ab747fSPaolo Bonzini } 161949ab747fSPaolo Bonzini break; 162049ab747fSPaolo Bonzini } 162149ab747fSPaolo Bonzini 162249ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 162349ab747fSPaolo Bonzini } 162449ab747fSPaolo Bonzini 162549ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 162649ab747fSPaolo Bonzini .read = gem_read, 162749ab747fSPaolo Bonzini .write = gem_write, 162849ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 162949ab747fSPaolo Bonzini }; 163049ab747fSPaolo Bonzini 163149ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 163249ab747fSPaolo Bonzini { 163367101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 163467101725SAlistair Francis 163549ab747fSPaolo Bonzini DB_PRINT("\n"); 163667101725SAlistair Francis phy_update_link(s); 163767101725SAlistair Francis gem_update_int_status(s); 163849ab747fSPaolo Bonzini } 163949ab747fSPaolo Bonzini 164049ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1641f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 164249ab747fSPaolo Bonzini .size = sizeof(NICState), 164349ab747fSPaolo Bonzini .can_receive = gem_can_receive, 164449ab747fSPaolo Bonzini .receive = gem_receive, 164549ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 164649ab747fSPaolo Bonzini }; 164749ab747fSPaolo Bonzini 1648bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 164949ab747fSPaolo Bonzini { 1650448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 165167101725SAlistair Francis int i; 165249ab747fSPaolo Bonzini 165384aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 165484aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 165584aec8efSEdgar E. Iglesias 16562bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 16572bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 16582bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 16592bf57f73SAlistair Francis s->num_priority_queues); 16602bf57f73SAlistair Francis return; 1661e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1662e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1663e8e49943SAlistair Francis s->num_type1_screeners); 1664e8e49943SAlistair Francis return; 1665e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1666e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1667e8e49943SAlistair Francis s->num_type2_screeners); 1668e8e49943SAlistair Francis return; 16692bf57f73SAlistair Francis } 16702bf57f73SAlistair Francis 167167101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 167267101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 167367101725SAlistair Francis } 1674bcb39a65SAlistair Francis 1675bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1676bcb39a65SAlistair Francis 1677bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1678bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 16797ca151c3SSai Pavan Boddu 16807ca151c3SSai Pavan Boddu if (s->jumbo_max_len > MAX_FRAME_SIZE) { 16817ca151c3SSai Pavan Boddu error_setg(errp, "jumbo-max-len is greater than %d", 16827ca151c3SSai Pavan Boddu MAX_FRAME_SIZE); 16837ca151c3SSai Pavan Boddu return; 16847ca151c3SSai Pavan Boddu } 1685bcb39a65SAlistair Francis } 1686bcb39a65SAlistair Francis 1687bcb39a65SAlistair Francis static void gem_init(Object *obj) 1688bcb39a65SAlistair Francis { 1689bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1690bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1691bcb39a65SAlistair Francis 169249ab747fSPaolo Bonzini DB_PRINT("\n"); 169349ab747fSPaolo Bonzini 169449ab747fSPaolo Bonzini gem_init_register_masks(s); 1695eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1696eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 169749ab747fSPaolo Bonzini 1698bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 169949ab747fSPaolo Bonzini } 170049ab747fSPaolo Bonzini 170149ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 170249ab747fSPaolo Bonzini .name = "cadence_gem", 1703e8e49943SAlistair Francis .version_id = 4, 1704e8e49943SAlistair Francis .minimum_version_id = 4, 170549ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1706448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1707448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1708448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 17092bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 17102bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 17112bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 17122bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1713448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 171417cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 171549ab747fSPaolo Bonzini } 171649ab747fSPaolo Bonzini }; 171749ab747fSPaolo Bonzini 171849ab747fSPaolo Bonzini static Property gem_properties[] = { 1719448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1720a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1721a5517666SAlistair Francis GEM_MODID_VALUE), 172264ac1363SBin Meng DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 17232bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 17242bf57f73SAlistair Francis num_priority_queues, 1), 1725e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1726e8e49943SAlistair Francis num_type1_screeners, 4), 1727e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1728e8e49943SAlistair Francis num_type2_screeners, 4), 17297ca151c3SSai Pavan Boddu DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 17307ca151c3SSai Pavan Boddu jumbo_max_len, 10240), 173108d45942SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 173208d45942SPhilippe Mathieu-Daudé TYPE_MEMORY_REGION, MemoryRegion *), 173349ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 173449ab747fSPaolo Bonzini }; 173549ab747fSPaolo Bonzini 173649ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 173749ab747fSPaolo Bonzini { 173849ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 173949ab747fSPaolo Bonzini 1740bcb39a65SAlistair Francis dc->realize = gem_realize; 17414f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 174249ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 174349ab747fSPaolo Bonzini dc->reset = gem_reset; 174449ab747fSPaolo Bonzini } 174549ab747fSPaolo Bonzini 174649ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1747318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 174849ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1749448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1750bcb39a65SAlistair Francis .instance_init = gem_init, 1751318643beSAndreas Färber .class_init = gem_class_init, 175249ab747fSPaolo Bonzini }; 175349ab747fSPaolo Bonzini 175449ab747fSPaolo Bonzini static void gem_register_types(void) 175549ab747fSPaolo Bonzini { 175649ab747fSPaolo Bonzini type_register_static(&gem_info); 175749ab747fSPaolo Bonzini } 175849ab747fSPaolo Bonzini 175949ab747fSPaolo Bonzini type_init(gem_register_types) 1760