149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 28f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 292bf57f73SAlistair Francis #include "qapi/error.h" 30e8e49943SAlistair Francis #include "qemu/log.h" 3149ab747fSPaolo Bonzini #include "net/checksum.h" 3249ab747fSPaolo Bonzini 3349ab747fSPaolo Bonzini #ifdef CADENCE_GEM_ERR_DEBUG 3449ab747fSPaolo Bonzini #define DB_PRINT(...) do { \ 3549ab747fSPaolo Bonzini fprintf(stderr, ": %s: ", __func__); \ 3649ab747fSPaolo Bonzini fprintf(stderr, ## __VA_ARGS__); \ 3749ab747fSPaolo Bonzini } while (0); 3849ab747fSPaolo Bonzini #else 3949ab747fSPaolo Bonzini #define DB_PRINT(...) 4049ab747fSPaolo Bonzini #endif 4149ab747fSPaolo Bonzini 4249ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 4349ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 4449ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 4549ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 4649ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 4749ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 4849ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 4949ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 5049ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 5149ab747fSPaolo Bonzini #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 5249ab747fSPaolo Bonzini #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 5349ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 5449ab747fSPaolo Bonzini #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 553048ed6aSPeter Crosthwaite #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */ 5649ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 5749ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 5849ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 5949ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 6049ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 6149ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 6249ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 6349ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 6449ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 6549ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 6649ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 6749ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 6849ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 6949ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 7049ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 7149ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 7249ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 7349ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 7449ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 7549ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 7649ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 7749ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 7849ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 7949ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 8049ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 8149ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 8249ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 8349ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 8449ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 8549ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 8649ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 8749ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 8849ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 8949ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 9049ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 9149ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 9249ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 9349ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 9449ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 9549ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 9649ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 9749ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 9849ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 9949ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 10049ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 10149ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 10249ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 10349ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 10449ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 10549ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 10649ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 10749ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 10849ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 10949ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 11049ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 11149ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 11249ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 11349ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 11449ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 11549ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 11649ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 11749ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 11849ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 11949ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 12149ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 12249ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 12349ab747fSPaolo Bonzini 12449ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 12549ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 12649ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 12749ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 12849ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 12949ab747fSPaolo Bonzini #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 13049ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 13149ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 13249ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 13349ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 13449ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 13549ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 13649ab747fSPaolo Bonzini 13749ab747fSPaolo Bonzini /* Design Configuration Registers */ 13849ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280/4) 13949ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284/4) 14049ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288/4) 14149ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C/4) 14249ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290/4) 14349ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294/4) 14449ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298/4) 14549ab747fSPaolo Bonzini 14667101725SAlistair Francis #define GEM_INT_Q1_STATUS (0x00000400 / 4) 14767101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 14867101725SAlistair Francis 14967101725SAlistair Francis #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 15079b2ac8fSAlistair Francis #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 15167101725SAlistair Francis 15267101725SAlistair Francis #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 15379b2ac8fSAlistair Francis #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 15467101725SAlistair Francis 15567101725SAlistair Francis #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 15667101725SAlistair Francis #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 15767101725SAlistair Francis 15867101725SAlistair Francis #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 15967101725SAlistair Francis #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 16067101725SAlistair Francis 16167101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 16267101725SAlistair Francis #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 16367101725SAlistair Francis 164e8e49943SAlistair Francis #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 165e8e49943SAlistair Francis 166e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 167e8e49943SAlistair Francis #define GEM_ST1R_DSTC_ENABLE (1 << 28) 168e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 169e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 170e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 171e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 172e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_SHIFT (0) 173e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 174e8e49943SAlistair Francis 175e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 176e8e49943SAlistair Francis 177e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 178e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_SHIFT (13) 179e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 180e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 181e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 182e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 183e8e49943SAlistair Francis + 1) 184e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_SHIFT (0) 185e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 186e8e49943SAlistair Francis 187e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 188e8e49943SAlistair Francis #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 189e8e49943SAlistair Francis 190e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 191e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 192e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 193e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 194e8e49943SAlistair Francis 19549ab747fSPaolo Bonzini /*****************************************/ 19649ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 19749ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 19849ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 19949ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 20049ab747fSPaolo Bonzini 20149ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2023048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 20349ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 20449ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 20549ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 20649ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 20749ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 20849ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 20949ab747fSPaolo Bonzini 2102801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 21149ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 21249ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 21349ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 21449ab747fSPaolo Bonzini 21549ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 21649ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 21749ab747fSPaolo Bonzini 21849ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 21949ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 22049ab747fSPaolo Bonzini 22149ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 22249ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 22349ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 22449ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 22549ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 22649ab747fSPaolo Bonzini 22749ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 22849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 22949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 23049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 23149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 23249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 23349ab747fSPaolo Bonzini 23449ab747fSPaolo Bonzini /* Marvell PHY definitions */ 23549ab747fSPaolo Bonzini #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 23649ab747fSPaolo Bonzini 23749ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 23849ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 23949ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 24049ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 24149ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 24249ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 24349ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 24449ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 24549ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 24649ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 24749ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 24849ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 24949ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 25049ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 25149ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 25249ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 25349ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 25449ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 25549ab747fSPaolo Bonzini #define PHY_REG_EACD 22 25649ab747fSPaolo Bonzini #define PHY_REG_LED 24 25749ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 25849ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 25949ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 26049ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 26149ab747fSPaolo Bonzini 26249ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 26349ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 26449ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 26549ab747fSPaolo Bonzini 26649ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 26749ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 26849ab747fSPaolo Bonzini 26949ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 27049ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 27149ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 27249ab747fSPaolo Bonzini 27349ab747fSPaolo Bonzini /***********************************************************************/ 27463af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 27563af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 27663af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 27763af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 27863af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 27963af1e0cSPeter Crosthwaite 28063af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 28149ab747fSPaolo Bonzini 28249ab747fSPaolo Bonzini /***********************************************************************/ 28349ab747fSPaolo Bonzini 28449ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 28549ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 28649ab747fSPaolo Bonzini 28749ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 28849ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 28949ab747fSPaolo Bonzini 29049ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 29149ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 29249ab747fSPaolo Bonzini 29363af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 29463af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 295a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 29663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 29763af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 29863af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 29963af1e0cSPeter Crosthwaite 30049ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 30149ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 30249ab747fSPaolo Bonzini 30349ab747fSPaolo Bonzini static inline unsigned tx_desc_get_buffer(unsigned *desc) 30449ab747fSPaolo Bonzini { 30549ab747fSPaolo Bonzini return desc[0]; 30649ab747fSPaolo Bonzini } 30749ab747fSPaolo Bonzini 30849ab747fSPaolo Bonzini static inline unsigned tx_desc_get_used(unsigned *desc) 30949ab747fSPaolo Bonzini { 31049ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 31149ab747fSPaolo Bonzini } 31249ab747fSPaolo Bonzini 31349ab747fSPaolo Bonzini static inline void tx_desc_set_used(unsigned *desc) 31449ab747fSPaolo Bonzini { 31549ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 31649ab747fSPaolo Bonzini } 31749ab747fSPaolo Bonzini 31849ab747fSPaolo Bonzini static inline unsigned tx_desc_get_wrap(unsigned *desc) 31949ab747fSPaolo Bonzini { 32049ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 32149ab747fSPaolo Bonzini } 32249ab747fSPaolo Bonzini 32349ab747fSPaolo Bonzini static inline unsigned tx_desc_get_last(unsigned *desc) 32449ab747fSPaolo Bonzini { 32549ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 32649ab747fSPaolo Bonzini } 32749ab747fSPaolo Bonzini 328cbdab58dSAlistair Francis static inline void tx_desc_set_last(unsigned *desc) 329cbdab58dSAlistair Francis { 330cbdab58dSAlistair Francis desc[1] |= DESC_1_TX_LAST; 331cbdab58dSAlistair Francis } 332cbdab58dSAlistair Francis 33349ab747fSPaolo Bonzini static inline unsigned tx_desc_get_length(unsigned *desc) 33449ab747fSPaolo Bonzini { 33549ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 33649ab747fSPaolo Bonzini } 33749ab747fSPaolo Bonzini 33867101725SAlistair Francis static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) 33949ab747fSPaolo Bonzini { 34067101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 34149ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 34249ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 34349ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 34449ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 34549ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 34649ab747fSPaolo Bonzini } 34749ab747fSPaolo Bonzini 34849ab747fSPaolo Bonzini static inline unsigned rx_desc_get_buffer(unsigned *desc) 34949ab747fSPaolo Bonzini { 35049ab747fSPaolo Bonzini return desc[0] & ~0x3UL; 35149ab747fSPaolo Bonzini } 35249ab747fSPaolo Bonzini 35349ab747fSPaolo Bonzini static inline unsigned rx_desc_get_wrap(unsigned *desc) 35449ab747fSPaolo Bonzini { 35549ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 35649ab747fSPaolo Bonzini } 35749ab747fSPaolo Bonzini 35849ab747fSPaolo Bonzini static inline unsigned rx_desc_get_ownership(unsigned *desc) 35949ab747fSPaolo Bonzini { 36049ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 36149ab747fSPaolo Bonzini } 36249ab747fSPaolo Bonzini 36349ab747fSPaolo Bonzini static inline void rx_desc_set_ownership(unsigned *desc) 36449ab747fSPaolo Bonzini { 36549ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 36649ab747fSPaolo Bonzini } 36749ab747fSPaolo Bonzini 36849ab747fSPaolo Bonzini static inline void rx_desc_set_sof(unsigned *desc) 36949ab747fSPaolo Bonzini { 37049ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 37149ab747fSPaolo Bonzini } 37249ab747fSPaolo Bonzini 37349ab747fSPaolo Bonzini static inline void rx_desc_set_eof(unsigned *desc) 37449ab747fSPaolo Bonzini { 37549ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 37649ab747fSPaolo Bonzini } 37749ab747fSPaolo Bonzini 37849ab747fSPaolo Bonzini static inline void rx_desc_set_length(unsigned *desc, unsigned len) 37949ab747fSPaolo Bonzini { 38049ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 38149ab747fSPaolo Bonzini desc[1] |= len; 38249ab747fSPaolo Bonzini } 38349ab747fSPaolo Bonzini 38463af1e0cSPeter Crosthwaite static inline void rx_desc_set_broadcast(unsigned *desc) 38563af1e0cSPeter Crosthwaite { 38663af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 38763af1e0cSPeter Crosthwaite } 38863af1e0cSPeter Crosthwaite 38963af1e0cSPeter Crosthwaite static inline void rx_desc_set_unicast_hash(unsigned *desc) 39063af1e0cSPeter Crosthwaite { 39163af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 39263af1e0cSPeter Crosthwaite } 39363af1e0cSPeter Crosthwaite 39463af1e0cSPeter Crosthwaite static inline void rx_desc_set_multicast_hash(unsigned *desc) 39563af1e0cSPeter Crosthwaite { 39663af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 39763af1e0cSPeter Crosthwaite } 39863af1e0cSPeter Crosthwaite 39963af1e0cSPeter Crosthwaite static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) 40063af1e0cSPeter Crosthwaite { 40163af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 40263af1e0cSPeter Crosthwaite sar_idx); 403a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 40463af1e0cSPeter Crosthwaite } 40563af1e0cSPeter Crosthwaite 40649ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4076a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 40849ab747fSPaolo Bonzini 40949ab747fSPaolo Bonzini /* 41049ab747fSPaolo Bonzini * gem_init_register_masks: 41149ab747fSPaolo Bonzini * One time initialization. 41249ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 41349ab747fSPaolo Bonzini */ 414448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 41549ab747fSPaolo Bonzini { 41649ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 41749ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 41849ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 41949ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 42049ab747fSPaolo Bonzini s->regs_ro[GEM_DMACFG] = 0xFE00F000; 42149ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 42249ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 42349ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 42449ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 42549ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 42649ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 42749ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 42849ab747fSPaolo Bonzini 42949ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 43049ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 43149ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 43249ab747fSPaolo Bonzini 43349ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 43449ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 43549ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 43649ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 43749ab747fSPaolo Bonzini 43849ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 43949ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 44049ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 44149ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 44249ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 44349ab747fSPaolo Bonzini } 44449ab747fSPaolo Bonzini 44549ab747fSPaolo Bonzini /* 44649ab747fSPaolo Bonzini * phy_update_link: 44749ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 44849ab747fSPaolo Bonzini */ 449448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 45049ab747fSPaolo Bonzini { 45149ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 45249ab747fSPaolo Bonzini 45349ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 45449ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 45549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 45649ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 45749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 45849ab747fSPaolo Bonzini } else { 45949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 46049ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 46149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 46249ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 46349ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 46449ab747fSPaolo Bonzini } 46549ab747fSPaolo Bonzini } 46649ab747fSPaolo Bonzini 46749ab747fSPaolo Bonzini static int gem_can_receive(NetClientState *nc) 46849ab747fSPaolo Bonzini { 469448f19e2SPeter Crosthwaite CadenceGEMState *s; 47067101725SAlistair Francis int i; 47149ab747fSPaolo Bonzini 47249ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 47349ab747fSPaolo Bonzini 47449ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 47549ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 4763ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 4773ae5725fSPeter Crosthwaite s->can_rx_state = 1; 4783ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 4793ae5725fSPeter Crosthwaite } 48049ab747fSPaolo Bonzini return 0; 48149ab747fSPaolo Bonzini } 48249ab747fSPaolo Bonzini 48367101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 48467101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) == 1) { 4858202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 4868202aa53SPeter Crosthwaite s->can_rx_state = 2; 48767101725SAlistair Francis DB_PRINT("can't receive - busy buffer descriptor (q%d) 0x%x\n", 48867101725SAlistair Francis i, s->rx_desc_addr[i]); 4898202aa53SPeter Crosthwaite } 4908202aa53SPeter Crosthwaite return 0; 4918202aa53SPeter Crosthwaite } 49267101725SAlistair Francis } 4938202aa53SPeter Crosthwaite 4943ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 4953ae5725fSPeter Crosthwaite s->can_rx_state = 0; 49667101725SAlistair Francis DB_PRINT("can receive\n"); 4973ae5725fSPeter Crosthwaite } 49849ab747fSPaolo Bonzini return 1; 49949ab747fSPaolo Bonzini } 50049ab747fSPaolo Bonzini 50149ab747fSPaolo Bonzini /* 50249ab747fSPaolo Bonzini * gem_update_int_status: 50349ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 50449ab747fSPaolo Bonzini */ 505448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 50649ab747fSPaolo Bonzini { 50767101725SAlistair Francis int i; 50867101725SAlistair Francis 50967101725SAlistair Francis if ((s->num_priority_queues == 1) && s->regs[GEM_ISR]) { 51067101725SAlistair Francis /* No priority queues, just trigger the interrupt */ 51167101725SAlistair Francis DB_PRINT("asserting int.\n", i); 5122bf57f73SAlistair Francis qemu_set_irq(s->irq[0], 1); 51367101725SAlistair Francis return; 51467101725SAlistair Francis } 51567101725SAlistair Francis 51667101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 51767101725SAlistair Francis if (s->regs[GEM_INT_Q1_STATUS + i]) { 51867101725SAlistair Francis DB_PRINT("asserting int. (q=%d)\n", i); 51967101725SAlistair Francis qemu_set_irq(s->irq[i], 1); 52067101725SAlistair Francis } 52149ab747fSPaolo Bonzini } 52249ab747fSPaolo Bonzini } 52349ab747fSPaolo Bonzini 52449ab747fSPaolo Bonzini /* 52549ab747fSPaolo Bonzini * gem_receive_updatestats: 52649ab747fSPaolo Bonzini * Increment receive statistics. 52749ab747fSPaolo Bonzini */ 528448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 52949ab747fSPaolo Bonzini unsigned bytes) 53049ab747fSPaolo Bonzini { 53149ab747fSPaolo Bonzini uint64_t octets; 53249ab747fSPaolo Bonzini 53349ab747fSPaolo Bonzini /* Total octets (bytes) received */ 53449ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 53549ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 53649ab747fSPaolo Bonzini octets += bytes; 53749ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 53849ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 53949ab747fSPaolo Bonzini 54049ab747fSPaolo Bonzini /* Error-free Frames received */ 54149ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 54249ab747fSPaolo Bonzini 54349ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 54449ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 54549ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 54649ab747fSPaolo Bonzini } 54749ab747fSPaolo Bonzini 54849ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 54949ab747fSPaolo Bonzini if (packet[0] == 0x01) { 55049ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 55149ab747fSPaolo Bonzini } 55249ab747fSPaolo Bonzini 55349ab747fSPaolo Bonzini if (bytes <= 64) { 55449ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 55549ab747fSPaolo Bonzini } else if (bytes <= 127) { 55649ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 55749ab747fSPaolo Bonzini } else if (bytes <= 255) { 55849ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 55949ab747fSPaolo Bonzini } else if (bytes <= 511) { 56049ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 56149ab747fSPaolo Bonzini } else if (bytes <= 1023) { 56249ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 56349ab747fSPaolo Bonzini } else if (bytes <= 1518) { 56449ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 56549ab747fSPaolo Bonzini } else { 56649ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 56749ab747fSPaolo Bonzini } 56849ab747fSPaolo Bonzini } 56949ab747fSPaolo Bonzini 57049ab747fSPaolo Bonzini /* 57149ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 57249ab747fSPaolo Bonzini */ 57349ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 57449ab747fSPaolo Bonzini { 57549ab747fSPaolo Bonzini unsigned byte; 57649ab747fSPaolo Bonzini 57749ab747fSPaolo Bonzini byte = mac[bit / 8]; 57849ab747fSPaolo Bonzini byte >>= (bit & 0x7); 57949ab747fSPaolo Bonzini byte &= 1; 58049ab747fSPaolo Bonzini 58149ab747fSPaolo Bonzini return byte; 58249ab747fSPaolo Bonzini } 58349ab747fSPaolo Bonzini 58449ab747fSPaolo Bonzini /* 58549ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 58649ab747fSPaolo Bonzini */ 58749ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 58849ab747fSPaolo Bonzini { 58949ab747fSPaolo Bonzini int index_bit, mac_bit; 59049ab747fSPaolo Bonzini unsigned hash_index; 59149ab747fSPaolo Bonzini 59249ab747fSPaolo Bonzini hash_index = 0; 59349ab747fSPaolo Bonzini mac_bit = 5; 59449ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 59549ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 59649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 59749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 59849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 59949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 60049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 60149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 60249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 60349ab747fSPaolo Bonzini mac_bit--; 60449ab747fSPaolo Bonzini } 60549ab747fSPaolo Bonzini 60649ab747fSPaolo Bonzini return hash_index; 60749ab747fSPaolo Bonzini } 60849ab747fSPaolo Bonzini 60949ab747fSPaolo Bonzini /* 61049ab747fSPaolo Bonzini * gem_mac_address_filter: 61149ab747fSPaolo Bonzini * Accept or reject this destination address? 61249ab747fSPaolo Bonzini * Returns: 61349ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 61463af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 61563af1e0cSPeter Crosthwaite * others for various other modes of accept: 61663af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 61763af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 61849ab747fSPaolo Bonzini */ 619448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 62049ab747fSPaolo Bonzini { 62149ab747fSPaolo Bonzini uint8_t *gem_spaddr; 62249ab747fSPaolo Bonzini int i; 62349ab747fSPaolo Bonzini 62449ab747fSPaolo Bonzini /* Promiscuous mode? */ 62549ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 62663af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 62749ab747fSPaolo Bonzini } 62849ab747fSPaolo Bonzini 62949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 63049ab747fSPaolo Bonzini /* Reject broadcast packets? */ 63149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 63249ab747fSPaolo Bonzini return GEM_RX_REJECT; 63349ab747fSPaolo Bonzini } 63463af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 63549ab747fSPaolo Bonzini } 63649ab747fSPaolo Bonzini 63749ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 63849ab747fSPaolo Bonzini if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 63949ab747fSPaolo Bonzini (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 64049ab747fSPaolo Bonzini unsigned hash_index; 64149ab747fSPaolo Bonzini 64249ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 64349ab747fSPaolo Bonzini if (hash_index < 32) { 64449ab747fSPaolo Bonzini if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 64563af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 64663af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 64749ab747fSPaolo Bonzini } 64849ab747fSPaolo Bonzini } else { 64949ab747fSPaolo Bonzini hash_index -= 32; 65049ab747fSPaolo Bonzini if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 65163af1e0cSPeter Crosthwaite return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 65263af1e0cSPeter Crosthwaite GEM_RX_UNICAST_HASH_ACCEPT; 65349ab747fSPaolo Bonzini } 65449ab747fSPaolo Bonzini } 65549ab747fSPaolo Bonzini } 65649ab747fSPaolo Bonzini 65749ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 65849ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 65963af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 66064eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 66163af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 66249ab747fSPaolo Bonzini } 66349ab747fSPaolo Bonzini } 66449ab747fSPaolo Bonzini 66549ab747fSPaolo Bonzini /* No address match; reject the packet */ 66649ab747fSPaolo Bonzini return GEM_RX_REJECT; 66749ab747fSPaolo Bonzini } 66849ab747fSPaolo Bonzini 669e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 670e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 671e8e49943SAlistair Francis unsigned rxbufsize) 672e8e49943SAlistair Francis { 673e8e49943SAlistair Francis uint32_t reg; 674e8e49943SAlistair Francis bool matched, mismatched; 675e8e49943SAlistair Francis int i, j; 676e8e49943SAlistair Francis 677e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 678e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 679e8e49943SAlistair Francis matched = false; 680e8e49943SAlistair Francis mismatched = false; 681e8e49943SAlistair Francis 682e8e49943SAlistair Francis /* Screening is based on UDP Port */ 683e8e49943SAlistair Francis if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 684e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 685e8e49943SAlistair Francis if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 686e8e49943SAlistair Francis GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 687e8e49943SAlistair Francis matched = true; 688e8e49943SAlistair Francis } else { 689e8e49943SAlistair Francis mismatched = true; 690e8e49943SAlistair Francis } 691e8e49943SAlistair Francis } 692e8e49943SAlistair Francis 693e8e49943SAlistair Francis /* Screening is based on DS/TC */ 694e8e49943SAlistair Francis if (reg & GEM_ST1R_DSTC_ENABLE) { 695e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 696e8e49943SAlistair Francis if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 697e8e49943SAlistair Francis GEM_ST1R_DSTC_MATCH_WIDTH)) { 698e8e49943SAlistair Francis matched = true; 699e8e49943SAlistair Francis } else { 700e8e49943SAlistair Francis mismatched = true; 701e8e49943SAlistair Francis } 702e8e49943SAlistair Francis } 703e8e49943SAlistair Francis 704e8e49943SAlistair Francis if (matched && !mismatched) { 705e8e49943SAlistair Francis return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 706e8e49943SAlistair Francis } 707e8e49943SAlistair Francis } 708e8e49943SAlistair Francis 709e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 710e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 711e8e49943SAlistair Francis matched = false; 712e8e49943SAlistair Francis mismatched = false; 713e8e49943SAlistair Francis 714e8e49943SAlistair Francis if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 715e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 716e8e49943SAlistair Francis int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 717e8e49943SAlistair Francis GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 718e8e49943SAlistair Francis 719e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 720e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 721e8e49943SAlistair Francis "register index: %d\n", et_idx); 722e8e49943SAlistair Francis } 723e8e49943SAlistair Francis if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 724e8e49943SAlistair Francis et_idx]) { 725e8e49943SAlistair Francis matched = true; 726e8e49943SAlistair Francis } else { 727e8e49943SAlistair Francis mismatched = true; 728e8e49943SAlistair Francis } 729e8e49943SAlistair Francis } 730e8e49943SAlistair Francis 731e8e49943SAlistair Francis /* Compare A, B, C */ 732e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 733e8e49943SAlistair Francis uint32_t cr0, cr1, mask; 734e8e49943SAlistair Francis uint16_t rx_cmp; 735e8e49943SAlistair Francis int offset; 736e8e49943SAlistair Francis int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 737e8e49943SAlistair Francis GEM_ST2R_COMPARE_WIDTH); 738e8e49943SAlistair Francis 739e8e49943SAlistair Francis if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 740e8e49943SAlistair Francis continue; 741e8e49943SAlistair Francis } 742e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 743e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 744e8e49943SAlistair Francis "register index: %d\n", cr_idx); 745e8e49943SAlistair Francis } 746e8e49943SAlistair Francis 747e8e49943SAlistair Francis cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 748e8e49943SAlistair Francis cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 749e8e49943SAlistair Francis offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 750e8e49943SAlistair Francis GEM_T2CW1_OFFSET_VALUE_WIDTH); 751e8e49943SAlistair Francis 752e8e49943SAlistair Francis switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 753e8e49943SAlistair Francis GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 754e8e49943SAlistair Francis case 3: /* Skip UDP header */ 755e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 756e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 757e8e49943SAlistair Francis offset += 8; 758e8e49943SAlistair Francis /* Fallthrough */ 759e8e49943SAlistair Francis case 2: /* skip the IP header */ 760e8e49943SAlistair Francis offset += 20; 761e8e49943SAlistair Francis /* Fallthrough */ 762e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 763e8e49943SAlistair Francis offset += 14; 764e8e49943SAlistair Francis break; 765e8e49943SAlistair Francis case 0: 766e8e49943SAlistair Francis /* Offset from start of frame */ 767e8e49943SAlistair Francis break; 768e8e49943SAlistair Francis } 769e8e49943SAlistair Francis 770e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 771e8e49943SAlistair Francis mask = extract32(cr0, 0, 16); 772e8e49943SAlistair Francis 773e8e49943SAlistair Francis if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 774e8e49943SAlistair Francis matched = true; 775e8e49943SAlistair Francis } else { 776e8e49943SAlistair Francis mismatched = true; 777e8e49943SAlistair Francis } 778e8e49943SAlistair Francis } 779e8e49943SAlistair Francis 780e8e49943SAlistair Francis if (matched && !mismatched) { 781e8e49943SAlistair Francis return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 782e8e49943SAlistair Francis } 783e8e49943SAlistair Francis } 784e8e49943SAlistair Francis 785e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 786e8e49943SAlistair Francis return 0; 787e8e49943SAlistair Francis } 788e8e49943SAlistair Francis 78967101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 79006c2fe95SPeter Crosthwaite { 79167101725SAlistair Francis DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); 79206c2fe95SPeter Crosthwaite /* read current descriptor */ 7932bf57f73SAlistair Francis cpu_physical_memory_read(s->rx_desc_addr[0], 7942bf57f73SAlistair Francis (uint8_t *)s->rx_desc[0], sizeof(s->rx_desc[0])); 79506c2fe95SPeter Crosthwaite 79606c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 79767101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 79806c2fe95SPeter Crosthwaite DB_PRINT("descriptor 0x%x owned by sw.\n", 79967101725SAlistair Francis (unsigned)s->rx_desc_addr[q]); 80006c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 80106c2fe95SPeter Crosthwaite s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 80206c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 80306c2fe95SPeter Crosthwaite gem_update_int_status(s); 80406c2fe95SPeter Crosthwaite } 80506c2fe95SPeter Crosthwaite } 80606c2fe95SPeter Crosthwaite 80749ab747fSPaolo Bonzini /* 80849ab747fSPaolo Bonzini * gem_receive: 80949ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 81049ab747fSPaolo Bonzini */ 81149ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 81249ab747fSPaolo Bonzini { 813448f19e2SPeter Crosthwaite CadenceGEMState *s; 81449ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 81549ab747fSPaolo Bonzini unsigned rxbuf_offset; 81649ab747fSPaolo Bonzini uint8_t rxbuf[2048]; 81749ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 8183b2c97f9SEdgar E. Iglesias bool first_desc = true; 81963af1e0cSPeter Crosthwaite int maf; 8202bf57f73SAlistair Francis int q = 0; 82149ab747fSPaolo Bonzini 82249ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 82349ab747fSPaolo Bonzini 82449ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 82563af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 82663af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 82749ab747fSPaolo Bonzini return -1; 82849ab747fSPaolo Bonzini } 82949ab747fSPaolo Bonzini 83049ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 83149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 83249ab747fSPaolo Bonzini unsigned type_len; 83349ab747fSPaolo Bonzini 83449ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 83549ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 83649ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 83749ab747fSPaolo Bonzini if (type_len < 0x600) { 83849ab747fSPaolo Bonzini if (size < type_len) { 83949ab747fSPaolo Bonzini /* discard */ 84049ab747fSPaolo Bonzini return -1; 84149ab747fSPaolo Bonzini } 84249ab747fSPaolo Bonzini } 84349ab747fSPaolo Bonzini } 84449ab747fSPaolo Bonzini 84549ab747fSPaolo Bonzini /* 84649ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 84749ab747fSPaolo Bonzini */ 84849ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 84949ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 85049ab747fSPaolo Bonzini 85149ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 85249ab747fSPaolo Bonzini * buffers needed to hold this packet. 85349ab747fSPaolo Bonzini */ 85449ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 85549ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 85649ab747fSPaolo Bonzini bytes_to_copy = size; 85749ab747fSPaolo Bonzini 858f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 859f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 860f265ae8cSAlistair Francis */ 861f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 862f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 863f265ae8cSAlistair Francis } 864f265ae8cSAlistair Francis 865191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 866191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 867191946c5SPeter Crosthwaite * not FCS stripping 868191946c5SPeter Crosthwaite */ 869191946c5SPeter Crosthwaite if (size < 60) { 870191946c5SPeter Crosthwaite size = 60; 871191946c5SPeter Crosthwaite } 872191946c5SPeter Crosthwaite 87349ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 87449ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 87549ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 87649ab747fSPaolo Bonzini } else { 87749ab747fSPaolo Bonzini unsigned crc_val; 87849ab747fSPaolo Bonzini 879244381ecSPrasad J Pandit if (size > sizeof(rxbuf) - sizeof(crc_val)) { 880244381ecSPrasad J Pandit size = sizeof(rxbuf) - sizeof(crc_val); 881244381ecSPrasad J Pandit } 882244381ecSPrasad J Pandit bytes_to_copy = size; 88349ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 8843048ed6aSPeter Crosthwaite * We must try and calculate one. 88549ab747fSPaolo Bonzini */ 88649ab747fSPaolo Bonzini 88749ab747fSPaolo Bonzini memcpy(rxbuf, buf, size); 88849ab747fSPaolo Bonzini memset(rxbuf + size, 0, sizeof(rxbuf) - size); 88949ab747fSPaolo Bonzini rxbuf_ptr = rxbuf; 89049ab747fSPaolo Bonzini crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 891c94239feSPeter Maydell memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 89249ab747fSPaolo Bonzini 89349ab747fSPaolo Bonzini bytes_to_copy += 4; 89449ab747fSPaolo Bonzini size += 4; 89549ab747fSPaolo Bonzini } 89649ab747fSPaolo Bonzini 89749ab747fSPaolo Bonzini DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 89849ab747fSPaolo Bonzini 899*b12227afSStefan Weil /* Find which queue we are targeting */ 900e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 901e8e49943SAlistair Francis 9027cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 90306c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 90406c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 90506c2fe95SPeter Crosthwaite assert(!first_desc); 90649ab747fSPaolo Bonzini return -1; 90749ab747fSPaolo Bonzini } 90849ab747fSPaolo Bonzini 90949ab747fSPaolo Bonzini DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 9102bf57f73SAlistair Francis rx_desc_get_buffer(s->rx_desc[q])); 91149ab747fSPaolo Bonzini 91249ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 9132bf57f73SAlistair Francis cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) + 9142bf57f73SAlistair Francis rxbuf_offset, 91549ab747fSPaolo Bonzini rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 91649ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 91730570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 9183b2c97f9SEdgar E. Iglesias 9193b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 9203b2c97f9SEdgar E. Iglesias if (first_desc) { 9212bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 9223b2c97f9SEdgar E. Iglesias first_desc = false; 9233b2c97f9SEdgar E. Iglesias } 9243b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 9252bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 9262bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 9273b2c97f9SEdgar E. Iglesias } 9282bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 92963af1e0cSPeter Crosthwaite 93063af1e0cSPeter Crosthwaite switch (maf) { 93163af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 93263af1e0cSPeter Crosthwaite break; 93363af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 9342bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 93563af1e0cSPeter Crosthwaite break; 93663af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 9372bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 93863af1e0cSPeter Crosthwaite break; 93963af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 9402bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 94163af1e0cSPeter Crosthwaite break; 94263af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 94363af1e0cSPeter Crosthwaite abort(); 94463af1e0cSPeter Crosthwaite default: /* SAR */ 9452bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 94663af1e0cSPeter Crosthwaite } 94763af1e0cSPeter Crosthwaite 9483b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 9492bf57f73SAlistair Francis cpu_physical_memory_write(s->rx_desc_addr[q], 9502bf57f73SAlistair Francis (uint8_t *)s->rx_desc[q], 9512bf57f73SAlistair Francis sizeof(s->rx_desc[q])); 9523b2c97f9SEdgar E. Iglesias 95349ab747fSPaolo Bonzini /* Next descriptor */ 9542bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 95549ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 9562bf57f73SAlistair Francis s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; 95749ab747fSPaolo Bonzini } else { 95849ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 9592bf57f73SAlistair Francis s->rx_desc_addr[q] += 8; 96049ab747fSPaolo Bonzini } 96167101725SAlistair Francis 96267101725SAlistair Francis gem_get_rx_desc(s, q); 9637cfd65e4SPeter Crosthwaite } 96449ab747fSPaolo Bonzini 96549ab747fSPaolo Bonzini /* Count it */ 96649ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 96749ab747fSPaolo Bonzini 96849ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 96949ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 97049ab747fSPaolo Bonzini 97149ab747fSPaolo Bonzini /* Handle interrupt consequences */ 97249ab747fSPaolo Bonzini gem_update_int_status(s); 97349ab747fSPaolo Bonzini 97449ab747fSPaolo Bonzini return size; 97549ab747fSPaolo Bonzini } 97649ab747fSPaolo Bonzini 97749ab747fSPaolo Bonzini /* 97849ab747fSPaolo Bonzini * gem_transmit_updatestats: 97949ab747fSPaolo Bonzini * Increment transmit statistics. 98049ab747fSPaolo Bonzini */ 981448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 98249ab747fSPaolo Bonzini unsigned bytes) 98349ab747fSPaolo Bonzini { 98449ab747fSPaolo Bonzini uint64_t octets; 98549ab747fSPaolo Bonzini 98649ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 98749ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 98849ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 98949ab747fSPaolo Bonzini octets += bytes; 99049ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 99149ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 99249ab747fSPaolo Bonzini 99349ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 99449ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 99549ab747fSPaolo Bonzini 99649ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 99749ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 99849ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 99949ab747fSPaolo Bonzini } 100049ab747fSPaolo Bonzini 100149ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 100249ab747fSPaolo Bonzini if (packet[0] == 0x01) { 100349ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 100449ab747fSPaolo Bonzini } 100549ab747fSPaolo Bonzini 100649ab747fSPaolo Bonzini if (bytes <= 64) { 100749ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 100849ab747fSPaolo Bonzini } else if (bytes <= 127) { 100949ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 101049ab747fSPaolo Bonzini } else if (bytes <= 255) { 101149ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 101249ab747fSPaolo Bonzini } else if (bytes <= 511) { 101349ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 101449ab747fSPaolo Bonzini } else if (bytes <= 1023) { 101549ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 101649ab747fSPaolo Bonzini } else if (bytes <= 1518) { 101749ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 101849ab747fSPaolo Bonzini } else { 101949ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 102049ab747fSPaolo Bonzini } 102149ab747fSPaolo Bonzini } 102249ab747fSPaolo Bonzini 102349ab747fSPaolo Bonzini /* 102449ab747fSPaolo Bonzini * gem_transmit: 102549ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 102649ab747fSPaolo Bonzini */ 1027448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 102849ab747fSPaolo Bonzini { 102949ab747fSPaolo Bonzini unsigned desc[2]; 103049ab747fSPaolo Bonzini hwaddr packet_desc_addr; 103149ab747fSPaolo Bonzini uint8_t tx_packet[2048]; 103249ab747fSPaolo Bonzini uint8_t *p; 103349ab747fSPaolo Bonzini unsigned total_bytes; 10342bf57f73SAlistair Francis int q = 0; 103549ab747fSPaolo Bonzini 103649ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 103749ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 103849ab747fSPaolo Bonzini return; 103949ab747fSPaolo Bonzini } 104049ab747fSPaolo Bonzini 104149ab747fSPaolo Bonzini DB_PRINT("\n"); 104249ab747fSPaolo Bonzini 10433048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 104449ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 104549ab747fSPaolo Bonzini * one contiguous buffer first. 104649ab747fSPaolo Bonzini */ 104749ab747fSPaolo Bonzini p = tx_packet; 104849ab747fSPaolo Bonzini total_bytes = 0; 104949ab747fSPaolo Bonzini 105067101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 105149ab747fSPaolo Bonzini /* read current descriptor */ 10522bf57f73SAlistair Francis packet_desc_addr = s->tx_desc_addr[q]; 1053fa15286aSPeter Crosthwaite 1054fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 105549ab747fSPaolo Bonzini cpu_physical_memory_read(packet_desc_addr, 1056ef18c2f5SPeter Crosthwaite (uint8_t *)desc, sizeof(desc)); 105749ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 105849ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 105949ab747fSPaolo Bonzini 106049ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 106149ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 106249ab747fSPaolo Bonzini return; 106349ab747fSPaolo Bonzini } 106467101725SAlistair Francis print_gem_tx_desc(desc, q); 106549ab747fSPaolo Bonzini 106649ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 106749ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 106849ab747fSPaolo Bonzini */ 106949ab747fSPaolo Bonzini if ((tx_desc_get_buffer(desc) == 0) || 107049ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 107149ab747fSPaolo Bonzini DB_PRINT("Invalid TX descriptor @ 0x%x\n", 107249ab747fSPaolo Bonzini (unsigned)packet_desc_addr); 107349ab747fSPaolo Bonzini break; 107449ab747fSPaolo Bonzini } 107549ab747fSPaolo Bonzini 107677524d11SAlistair Francis if (tx_desc_get_length(desc) > sizeof(tx_packet) - 107777524d11SAlistair Francis (p - tx_packet)) { 107877524d11SAlistair Francis DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \ 107977524d11SAlistair Francis "0x%x\n", (unsigned)packet_desc_addr, 1080d7f05365SMichael S. Tsirkin (unsigned)tx_desc_get_length(desc), 1081d7f05365SMichael S. Tsirkin sizeof(tx_packet) - (p - tx_packet)); 1082d7f05365SMichael S. Tsirkin break; 1083d7f05365SMichael S. Tsirkin } 1084d7f05365SMichael S. Tsirkin 108577524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 108677524d11SAlistair Francis * contig buffer. 108749ab747fSPaolo Bonzini */ 108849ab747fSPaolo Bonzini cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 108949ab747fSPaolo Bonzini tx_desc_get_length(desc)); 109049ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 109149ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 109249ab747fSPaolo Bonzini 109349ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 109449ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 10956ab57a6bSPeter Crosthwaite unsigned desc_first[2]; 10966ab57a6bSPeter Crosthwaite 109749ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 109849ab747fSPaolo Bonzini * the processor. 109949ab747fSPaolo Bonzini */ 110077524d11SAlistair Francis cpu_physical_memory_read(s->tx_desc_addr[q], 110177524d11SAlistair Francis (uint8_t *)desc_first, 11026ab57a6bSPeter Crosthwaite sizeof(desc_first)); 11036ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 110477524d11SAlistair Francis cpu_physical_memory_write(s->tx_desc_addr[q], 110577524d11SAlistair Francis (uint8_t *)desc_first, 11066ab57a6bSPeter Crosthwaite sizeof(desc_first)); 11073048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 110849ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 11092bf57f73SAlistair Francis s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; 111049ab747fSPaolo Bonzini } else { 11112bf57f73SAlistair Francis s->tx_desc_addr[q] = packet_desc_addr + 8; 111249ab747fSPaolo Bonzini } 11132bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 111449ab747fSPaolo Bonzini 111549ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 111649ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 111749ab747fSPaolo Bonzini 111867101725SAlistair Francis /* Update queue interrupt status */ 111967101725SAlistair Francis if (s->num_priority_queues > 1) { 112067101725SAlistair Francis s->regs[GEM_INT_Q1_STATUS + q] |= 112167101725SAlistair Francis GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]); 112267101725SAlistair Francis } 112367101725SAlistair Francis 112449ab747fSPaolo Bonzini /* Handle interrupt consequences */ 112549ab747fSPaolo Bonzini gem_update_int_status(s); 112649ab747fSPaolo Bonzini 112749ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 112849ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 112949ab747fSPaolo Bonzini net_checksum_calculate(tx_packet, total_bytes); 113049ab747fSPaolo Bonzini } 113149ab747fSPaolo Bonzini 113249ab747fSPaolo Bonzini /* Update MAC statistics */ 113349ab747fSPaolo Bonzini gem_transmit_updatestats(s, tx_packet, total_bytes); 113449ab747fSPaolo Bonzini 113549ab747fSPaolo Bonzini /* Send the packet somewhere */ 113677524d11SAlistair Francis if (s->phy_loop || (s->regs[GEM_NWCTRL] & 113777524d11SAlistair Francis GEM_NWCTRL_LOCALLOOP)) { 113877524d11SAlistair Francis gem_receive(qemu_get_queue(s->nic), tx_packet, 113977524d11SAlistair Francis total_bytes); 114049ab747fSPaolo Bonzini } else { 114149ab747fSPaolo Bonzini qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 114249ab747fSPaolo Bonzini total_bytes); 114349ab747fSPaolo Bonzini } 114449ab747fSPaolo Bonzini 114549ab747fSPaolo Bonzini /* Prepare for next packet */ 114649ab747fSPaolo Bonzini p = tx_packet; 114749ab747fSPaolo Bonzini total_bytes = 0; 114849ab747fSPaolo Bonzini } 114949ab747fSPaolo Bonzini 115049ab747fSPaolo Bonzini /* read next descriptor */ 115149ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1152cbdab58dSAlistair Francis tx_desc_set_last(desc); 115349ab747fSPaolo Bonzini packet_desc_addr = s->regs[GEM_TXQBASE]; 115449ab747fSPaolo Bonzini } else { 115549ab747fSPaolo Bonzini packet_desc_addr += 8; 115649ab747fSPaolo Bonzini } 1157fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 115849ab747fSPaolo Bonzini cpu_physical_memory_read(packet_desc_addr, 1159ef18c2f5SPeter Crosthwaite (uint8_t *)desc, sizeof(desc)); 116049ab747fSPaolo Bonzini } 116149ab747fSPaolo Bonzini 116249ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 116349ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 116449ab747fSPaolo Bonzini s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 116549ab747fSPaolo Bonzini gem_update_int_status(s); 116649ab747fSPaolo Bonzini } 116749ab747fSPaolo Bonzini } 116867101725SAlistair Francis } 116949ab747fSPaolo Bonzini 1170448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 117149ab747fSPaolo Bonzini { 117249ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 117349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 117449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 117549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 117649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 117749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 117849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 117949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 118049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 118149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 118249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 118349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 118449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 118549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 11867777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 118749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 118849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 118949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 119049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 119149ab747fSPaolo Bonzini 119249ab747fSPaolo Bonzini phy_update_link(s); 119349ab747fSPaolo Bonzini } 119449ab747fSPaolo Bonzini 119549ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 119649ab747fSPaolo Bonzini { 119764eb9301SPeter Crosthwaite int i; 1198448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1199afb4c51fSSebastian Huber const uint8_t *a; 120049ab747fSPaolo Bonzini 120149ab747fSPaolo Bonzini DB_PRINT("\n"); 120249ab747fSPaolo Bonzini 120349ab747fSPaolo Bonzini /* Set post reset register values */ 120449ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 120549ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 120649ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 120749ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 120849ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 120949ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 121049ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 121149ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 121249ab747fSPaolo Bonzini s->regs[GEM_MODID] = 0x00020118; 121349ab747fSPaolo Bonzini s->regs[GEM_DESCONF] = 0x02500111; 121449ab747fSPaolo Bonzini s->regs[GEM_DESCONF2] = 0x2ab13fff; 121549ab747fSPaolo Bonzini s->regs[GEM_DESCONF5] = 0x002f2145; 121649ab747fSPaolo Bonzini s->regs[GEM_DESCONF6] = 0x00000200; 121749ab747fSPaolo Bonzini 1218afb4c51fSSebastian Huber /* Set MAC address */ 1219afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1220afb4c51fSSebastian Huber s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1221afb4c51fSSebastian Huber s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1222afb4c51fSSebastian Huber 122364eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 122464eb9301SPeter Crosthwaite s->sar_active[i] = false; 122564eb9301SPeter Crosthwaite } 122664eb9301SPeter Crosthwaite 122749ab747fSPaolo Bonzini gem_phy_reset(s); 122849ab747fSPaolo Bonzini 122949ab747fSPaolo Bonzini gem_update_int_status(s); 123049ab747fSPaolo Bonzini } 123149ab747fSPaolo Bonzini 1232448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 123349ab747fSPaolo Bonzini { 123449ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 123549ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 123649ab747fSPaolo Bonzini } 123749ab747fSPaolo Bonzini 1238448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 123949ab747fSPaolo Bonzini { 124049ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 124149ab747fSPaolo Bonzini 124249ab747fSPaolo Bonzini switch (reg_num) { 124349ab747fSPaolo Bonzini case PHY_REG_CONTROL: 124449ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 124549ab747fSPaolo Bonzini /* Phy reset */ 124649ab747fSPaolo Bonzini gem_phy_reset(s); 124749ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 124849ab747fSPaolo Bonzini s->phy_loop = 0; 124949ab747fSPaolo Bonzini } 125049ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 125149ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 125249ab747fSPaolo Bonzini val &= ~PHY_REG_CONTROL_ANEG; 125349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 125449ab747fSPaolo Bonzini } 125549ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 125649ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 125749ab747fSPaolo Bonzini s->phy_loop = 1; 125849ab747fSPaolo Bonzini } else { 125949ab747fSPaolo Bonzini s->phy_loop = 0; 126049ab747fSPaolo Bonzini } 126149ab747fSPaolo Bonzini break; 126249ab747fSPaolo Bonzini } 126349ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 126449ab747fSPaolo Bonzini } 126549ab747fSPaolo Bonzini 126649ab747fSPaolo Bonzini /* 126749ab747fSPaolo Bonzini * gem_read32: 126849ab747fSPaolo Bonzini * Read a GEM register. 126949ab747fSPaolo Bonzini */ 127049ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 127149ab747fSPaolo Bonzini { 1272448f19e2SPeter Crosthwaite CadenceGEMState *s; 127349ab747fSPaolo Bonzini uint32_t retval; 127467101725SAlistair Francis int i; 1275448f19e2SPeter Crosthwaite s = (CadenceGEMState *)opaque; 127649ab747fSPaolo Bonzini 127749ab747fSPaolo Bonzini offset >>= 2; 127849ab747fSPaolo Bonzini retval = s->regs[offset]; 127949ab747fSPaolo Bonzini 128049ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 128149ab747fSPaolo Bonzini 128249ab747fSPaolo Bonzini switch (offset) { 128349ab747fSPaolo Bonzini case GEM_ISR: 128467101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 128567101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 128667101725SAlistair Francis qemu_set_irq(s->irq[i], 0); 128767101725SAlistair Francis } 128849ab747fSPaolo Bonzini break; 128949ab747fSPaolo Bonzini case GEM_PHYMNTNC: 129049ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 129149ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 129249ab747fSPaolo Bonzini 129349ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 129455389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 129549ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 129649ab747fSPaolo Bonzini retval &= 0xFFFF0000; 129749ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 129849ab747fSPaolo Bonzini } else { 129949ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 130049ab747fSPaolo Bonzini } 130149ab747fSPaolo Bonzini } 130249ab747fSPaolo Bonzini break; 130349ab747fSPaolo Bonzini } 130449ab747fSPaolo Bonzini 130549ab747fSPaolo Bonzini /* Squash read to clear bits */ 130649ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 130749ab747fSPaolo Bonzini 130849ab747fSPaolo Bonzini /* Do not provide write only bits */ 130949ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 131049ab747fSPaolo Bonzini 131149ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 131267101725SAlistair Francis gem_update_int_status(s); 131349ab747fSPaolo Bonzini return retval; 131449ab747fSPaolo Bonzini } 131549ab747fSPaolo Bonzini 131649ab747fSPaolo Bonzini /* 131749ab747fSPaolo Bonzini * gem_write32: 131849ab747fSPaolo Bonzini * Write a GEM register. 131949ab747fSPaolo Bonzini */ 132049ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 132149ab747fSPaolo Bonzini unsigned size) 132249ab747fSPaolo Bonzini { 1323448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 132449ab747fSPaolo Bonzini uint32_t readonly; 132567101725SAlistair Francis int i; 132649ab747fSPaolo Bonzini 132749ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 132849ab747fSPaolo Bonzini offset >>= 2; 132949ab747fSPaolo Bonzini 133049ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 133149ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1332e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1333e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 133449ab747fSPaolo Bonzini 133549ab747fSPaolo Bonzini /* Copy register write to backing store */ 1336e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1337e2314fdaSPeter Crosthwaite 1338e2314fdaSPeter Crosthwaite /* do w1c */ 1339e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 134049ab747fSPaolo Bonzini 134149ab747fSPaolo Bonzini /* Handle register write side effects */ 134249ab747fSPaolo Bonzini switch (offset) { 134349ab747fSPaolo Bonzini case GEM_NWCTRL: 134406c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 134567101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 134667101725SAlistair Francis gem_get_rx_desc(s, i); 134767101725SAlistair Francis } 134806c2fe95SPeter Crosthwaite } 134949ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 135049ab747fSPaolo Bonzini gem_transmit(s); 135149ab747fSPaolo Bonzini } 135249ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 135349ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 135467101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 135567101725SAlistair Francis s->tx_desc_addr[i] = s->regs[GEM_TXQBASE]; 135667101725SAlistair Francis } 135749ab747fSPaolo Bonzini } 13588202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 135949ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 136049ab747fSPaolo Bonzini } 136149ab747fSPaolo Bonzini break; 136249ab747fSPaolo Bonzini 136349ab747fSPaolo Bonzini case GEM_TXSTATUS: 136449ab747fSPaolo Bonzini gem_update_int_status(s); 136549ab747fSPaolo Bonzini break; 136649ab747fSPaolo Bonzini case GEM_RXQBASE: 13672bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 136849ab747fSPaolo Bonzini break; 136979b2ac8fSAlistair Francis case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 137067101725SAlistair Francis s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 137167101725SAlistair Francis break; 137249ab747fSPaolo Bonzini case GEM_TXQBASE: 13732bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 137449ab747fSPaolo Bonzini break; 137579b2ac8fSAlistair Francis case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 137667101725SAlistair Francis s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 137767101725SAlistair Francis break; 137849ab747fSPaolo Bonzini case GEM_RXSTATUS: 137949ab747fSPaolo Bonzini gem_update_int_status(s); 138049ab747fSPaolo Bonzini break; 138149ab747fSPaolo Bonzini case GEM_IER: 138249ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 138349ab747fSPaolo Bonzini gem_update_int_status(s); 138449ab747fSPaolo Bonzini break; 138567101725SAlistair Francis case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 138667101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 138767101725SAlistair Francis gem_update_int_status(s); 138867101725SAlistair Francis break; 138949ab747fSPaolo Bonzini case GEM_IDR: 139049ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 139149ab747fSPaolo Bonzini gem_update_int_status(s); 139249ab747fSPaolo Bonzini break; 139367101725SAlistair Francis case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 139467101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 139567101725SAlistair Francis gem_update_int_status(s); 139667101725SAlistair Francis break; 139764eb9301SPeter Crosthwaite case GEM_SPADDR1LO: 139864eb9301SPeter Crosthwaite case GEM_SPADDR2LO: 139964eb9301SPeter Crosthwaite case GEM_SPADDR3LO: 140064eb9301SPeter Crosthwaite case GEM_SPADDR4LO: 140164eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 140264eb9301SPeter Crosthwaite break; 140364eb9301SPeter Crosthwaite case GEM_SPADDR1HI: 140464eb9301SPeter Crosthwaite case GEM_SPADDR2HI: 140564eb9301SPeter Crosthwaite case GEM_SPADDR3HI: 140664eb9301SPeter Crosthwaite case GEM_SPADDR4HI: 140764eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 140864eb9301SPeter Crosthwaite break; 140949ab747fSPaolo Bonzini case GEM_PHYMNTNC: 141049ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 141149ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 141249ab747fSPaolo Bonzini 141349ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 141455389373SPeter Crosthwaite if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 141549ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 141649ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 141749ab747fSPaolo Bonzini } 141849ab747fSPaolo Bonzini } 141949ab747fSPaolo Bonzini break; 142049ab747fSPaolo Bonzini } 142149ab747fSPaolo Bonzini 142249ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 142349ab747fSPaolo Bonzini } 142449ab747fSPaolo Bonzini 142549ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 142649ab747fSPaolo Bonzini .read = gem_read, 142749ab747fSPaolo Bonzini .write = gem_write, 142849ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 142949ab747fSPaolo Bonzini }; 143049ab747fSPaolo Bonzini 143149ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 143249ab747fSPaolo Bonzini { 143367101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 143467101725SAlistair Francis 143549ab747fSPaolo Bonzini DB_PRINT("\n"); 143667101725SAlistair Francis phy_update_link(s); 143767101725SAlistair Francis gem_update_int_status(s); 143849ab747fSPaolo Bonzini } 143949ab747fSPaolo Bonzini 144049ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1441f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 144249ab747fSPaolo Bonzini .size = sizeof(NICState), 144349ab747fSPaolo Bonzini .can_receive = gem_can_receive, 144449ab747fSPaolo Bonzini .receive = gem_receive, 144549ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 144649ab747fSPaolo Bonzini }; 144749ab747fSPaolo Bonzini 1448bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 144949ab747fSPaolo Bonzini { 1450448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 145167101725SAlistair Francis int i; 145249ab747fSPaolo Bonzini 14532bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 14542bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 14552bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 14562bf57f73SAlistair Francis s->num_priority_queues); 14572bf57f73SAlistair Francis return; 1458e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1459e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1460e8e49943SAlistair Francis s->num_type1_screeners); 1461e8e49943SAlistair Francis return; 1462e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1463e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1464e8e49943SAlistair Francis s->num_type2_screeners); 1465e8e49943SAlistair Francis return; 14662bf57f73SAlistair Francis } 14672bf57f73SAlistair Francis 146867101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 146967101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 147067101725SAlistair Francis } 1471bcb39a65SAlistair Francis 1472bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1473bcb39a65SAlistair Francis 1474bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1475bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 1476bcb39a65SAlistair Francis } 1477bcb39a65SAlistair Francis 1478bcb39a65SAlistair Francis static void gem_init(Object *obj) 1479bcb39a65SAlistair Francis { 1480bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1481bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1482bcb39a65SAlistair Francis 148349ab747fSPaolo Bonzini DB_PRINT("\n"); 148449ab747fSPaolo Bonzini 148549ab747fSPaolo Bonzini gem_init_register_masks(s); 1486eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1487eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 148849ab747fSPaolo Bonzini 1489bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 149049ab747fSPaolo Bonzini } 149149ab747fSPaolo Bonzini 149249ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 149349ab747fSPaolo Bonzini .name = "cadence_gem", 1494e8e49943SAlistair Francis .version_id = 4, 1495e8e49943SAlistair Francis .minimum_version_id = 4, 149649ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1497448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1498448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1499448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 15002bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 15012bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 15022bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 15032bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1504448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 150517cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 150649ab747fSPaolo Bonzini } 150749ab747fSPaolo Bonzini }; 150849ab747fSPaolo Bonzini 150949ab747fSPaolo Bonzini static Property gem_properties[] = { 1510448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 15112bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 15122bf57f73SAlistair Francis num_priority_queues, 1), 1513e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1514e8e49943SAlistair Francis num_type1_screeners, 4), 1515e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1516e8e49943SAlistair Francis num_type2_screeners, 4), 151749ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 151849ab747fSPaolo Bonzini }; 151949ab747fSPaolo Bonzini 152049ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 152149ab747fSPaolo Bonzini { 152249ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 152349ab747fSPaolo Bonzini 1524bcb39a65SAlistair Francis dc->realize = gem_realize; 152549ab747fSPaolo Bonzini dc->props = gem_properties; 152649ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 152749ab747fSPaolo Bonzini dc->reset = gem_reset; 152849ab747fSPaolo Bonzini } 152949ab747fSPaolo Bonzini 153049ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1531318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 153249ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1533448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1534bcb39a65SAlistair Francis .instance_init = gem_init, 1535318643beSAndreas Färber .class_init = gem_class_init, 153649ab747fSPaolo Bonzini }; 153749ab747fSPaolo Bonzini 153849ab747fSPaolo Bonzini static void gem_register_types(void) 153949ab747fSPaolo Bonzini { 154049ab747fSPaolo Bonzini type_register_static(&gem_info); 154149ab747fSPaolo Bonzini } 154249ab747fSPaolo Bonzini 154349ab747fSPaolo Bonzini type_init(gem_register_types) 1544