149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31c755c943SLuc Michel #include "hw/registerfields.h" 32d6454270SMarkus Armbruster #include "migration/vmstate.h" 332bf57f73SAlistair Francis #include "qapi/error.h" 34e8e49943SAlistair Francis #include "qemu/log.h" 350b8fa32fSMarkus Armbruster #include "qemu/module.h" 3684aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3749ab747fSPaolo Bonzini #include "net/checksum.h" 38fbc14a09STong Ho #include "net/eth.h" 3949ab747fSPaolo Bonzini 406fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 4149ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 426fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 436fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 446fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 456fe7661dSSai Pavan Boddu } \ 462562755eSEric Blake } while (0) 4749ab747fSPaolo Bonzini 48c755c943SLuc Michel REG32(NWCTRL, 0x0) /* Network Control reg */ 49bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK , 0, 1) 50bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) 51bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) 52bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) 53bd8a922dSLuc Michel FIELD(NWCTRL, MAN_PORT_EN , 4, 1) 54bd8a922dSLuc Michel FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) 55bd8a922dSLuc Michel FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) 56bd8a922dSLuc Michel FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) 57bd8a922dSLuc Michel FIELD(NWCTRL, BACK_PRESSURE, 8, 1) 58bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_START , 9, 1) 59bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) 60bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) 61bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) 62bd8a922dSLuc Michel FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) 63bd8a922dSLuc Michel FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) 64bd8a922dSLuc Michel FIELD(NWCTRL, STORE_RX_TS, 15, 1) 65bd8a922dSLuc Michel FIELD(NWCTRL, PFC_ENABLE, 16, 1) 66bd8a922dSLuc Michel FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) 67bd8a922dSLuc Michel FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) 68bd8a922dSLuc Michel FIELD(NWCTRL, TX_LPI_EN, 19, 1) 69bd8a922dSLuc Michel FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) 70bd8a922dSLuc Michel FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) 71bd8a922dSLuc Michel FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) 72bd8a922dSLuc Michel FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) 73bd8a922dSLuc Michel FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) 74bd8a922dSLuc Michel FIELD(NWCTRL, PFC_CTRL , 25, 1) 75bd8a922dSLuc Michel FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) 76bd8a922dSLuc Michel FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) 77bd8a922dSLuc Michel FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) 78bd8a922dSLuc Michel FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) 79bd8a922dSLuc Michel FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) 80bd8a922dSLuc Michel 81c755c943SLuc Michel REG32(NWCFG, 0x4) /* Network Config reg */ 82c755c943SLuc Michel REG32(NWSTATUS, 0x8) /* Network Status reg */ 83c755c943SLuc Michel REG32(USERIO, 0xc) /* User IO reg */ 84c755c943SLuc Michel REG32(DMACFG, 0x10) /* DMA Control reg */ 85c755c943SLuc Michel REG32(TXSTATUS, 0x14) /* TX Status reg */ 86c755c943SLuc Michel REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 87c755c943SLuc Michel REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 88c755c943SLuc Michel REG32(RXSTATUS, 0x20) /* RX Status reg */ 89c755c943SLuc Michel REG32(ISR, 0x24) /* Interrupt Status reg */ 90c755c943SLuc Michel REG32(IER, 0x28) /* Interrupt Enable reg */ 91c755c943SLuc Michel REG32(IDR, 0x2c) /* Interrupt Disable reg */ 92c755c943SLuc Michel REG32(IMR, 0x30) /* Interrupt Mask reg */ 93c755c943SLuc Michel REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 94c755c943SLuc Michel REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 95c755c943SLuc Michel REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 96c755c943SLuc Michel REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 97c755c943SLuc Michel REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 98c755c943SLuc Michel REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 99c755c943SLuc Michel REG32(HASHLO, 0x80) /* Hash Low address reg */ 100c755c943SLuc Michel REG32(HASHHI, 0x84) /* Hash High address reg */ 101c755c943SLuc Michel REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 102c755c943SLuc Michel REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 103c755c943SLuc Michel REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 104c755c943SLuc Michel REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 105c755c943SLuc Michel REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 106c755c943SLuc Michel REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 107c755c943SLuc Michel REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 108c755c943SLuc Michel REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 109c755c943SLuc Michel REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 110c755c943SLuc Michel REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 111c755c943SLuc Michel REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 112c755c943SLuc Michel REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 113c755c943SLuc Michel REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 114c755c943SLuc Michel REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 115c755c943SLuc Michel REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 116c755c943SLuc Michel REG32(MODID, 0xfc) /* Module ID reg */ 117c755c943SLuc Michel REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 118c755c943SLuc Michel REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 119c755c943SLuc Michel REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 120c755c943SLuc Michel REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 121c755c943SLuc Michel REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 122c755c943SLuc Michel REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 123c755c943SLuc Michel REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 124c755c943SLuc Michel REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 125c755c943SLuc Michel REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 126c755c943SLuc Michel REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 127c755c943SLuc Michel REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 128c755c943SLuc Michel REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 129c755c943SLuc Michel REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 130c755c943SLuc Michel REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 131c755c943SLuc Michel REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 132c755c943SLuc Michel REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 133c755c943SLuc Michel REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 134c755c943SLuc Michel REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 135c755c943SLuc Michel REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 136c755c943SLuc Michel REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 137c755c943SLuc Michel REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 138c755c943SLuc Michel REG32(OCTRXHI, 0x154) /* Octects Received register High */ 139c755c943SLuc Michel REG32(RXCNT, 0x158) /* Error-free Frames Received */ 140c755c943SLuc Michel REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 141c755c943SLuc Michel REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 142c755c943SLuc Michel REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 143c755c943SLuc Michel REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 144c755c943SLuc Michel REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 145c755c943SLuc Michel REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 146c755c943SLuc Michel REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 147c755c943SLuc Michel REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 148c755c943SLuc Michel REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 149c755c943SLuc Michel REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 150c755c943SLuc Michel REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 151c755c943SLuc Michel REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 152c755c943SLuc Michel REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 153c755c943SLuc Michel REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 154c755c943SLuc Michel REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 155c755c943SLuc Michel REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 156c755c943SLuc Michel REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 157c755c943SLuc Michel REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 158c755c943SLuc Michel REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 159c755c943SLuc Michel REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 160c755c943SLuc Michel REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 161c755c943SLuc Michel REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 16249ab747fSPaolo Bonzini 163c755c943SLuc Michel REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 164c755c943SLuc Michel REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 165c755c943SLuc Michel REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 166c755c943SLuc Michel REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 167c755c943SLuc Michel REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 168c755c943SLuc Michel REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 169c755c943SLuc Michel REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 170c755c943SLuc Michel REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 171c755c943SLuc Michel REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 172c755c943SLuc Michel REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 173c755c943SLuc Michel REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 174c755c943SLuc Michel REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 17549ab747fSPaolo Bonzini 17649ab747fSPaolo Bonzini /* Design Configuration Registers */ 177c755c943SLuc Michel REG32(DESCONF, 0x280) 178c755c943SLuc Michel REG32(DESCONF2, 0x284) 179c755c943SLuc Michel REG32(DESCONF3, 0x288) 180c755c943SLuc Michel REG32(DESCONF4, 0x28c) 181c755c943SLuc Michel REG32(DESCONF5, 0x290) 182c755c943SLuc Michel REG32(DESCONF6, 0x294) 183e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 184c755c943SLuc Michel REG32(DESCONF7, 0x298) 18549ab747fSPaolo Bonzini 186c755c943SLuc Michel REG32(INT_Q1_STATUS, 0x400) 187c755c943SLuc Michel REG32(INT_Q1_MASK, 0x640) 18867101725SAlistair Francis 189c755c943SLuc Michel REG32(TRANSMIT_Q1_PTR, 0x440) 190c755c943SLuc Michel REG32(TRANSMIT_Q7_PTR, 0x458) 19167101725SAlistair Francis 192c755c943SLuc Michel REG32(RECEIVE_Q1_PTR, 0x480) 193c755c943SLuc Michel REG32(RECEIVE_Q7_PTR, 0x498) 19467101725SAlistair Francis 195c755c943SLuc Michel REG32(TBQPH, 0x4c8) 196c755c943SLuc Michel REG32(RBQPH, 0x4d4) 197357aa013SEdgar E. Iglesias 198c755c943SLuc Michel REG32(INT_Q1_ENABLE, 0x600) 199c755c943SLuc Michel REG32(INT_Q7_ENABLE, 0x618) 20067101725SAlistair Francis 201c755c943SLuc Michel REG32(INT_Q1_DISABLE, 0x620) 202c755c943SLuc Michel REG32(INT_Q7_DISABLE, 0x638) 20367101725SAlistair Francis 204c755c943SLuc Michel REG32(SCREENING_TYPE1_REG0, 0x500) 205b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) 206b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) 207b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) 208b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) 209b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) 210b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) 211e8e49943SAlistair Francis 212c755c943SLuc Michel REG32(SCREENING_TYPE2_REG0, 0x540) 213b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) 214b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) 215b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) 216b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) 217b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) 218b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) 219b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) 220b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) 221b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) 222b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) 223b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) 224b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) 225e8e49943SAlistair Francis 226c755c943SLuc Michel REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 227e8e49943SAlistair Francis 228b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 229b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) 230b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) 231b46b526cSLuc Michel 232b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_1, 0x704) 233b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) 234b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) 235b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) 236b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) 237e8e49943SAlistair Francis 23849ab747fSPaolo Bonzini /*****************************************/ 23949ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2403048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 24149ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 24249ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 2437ca151c3SSai Pavan Boddu #define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ 24449ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 24549ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 24649ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 24749ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 2487ca151c3SSai Pavan Boddu #define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ 24949ab747fSPaolo Bonzini 250e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 251e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 252e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2532801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 25449ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 25549ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 25649ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 25749ab747fSPaolo Bonzini 25849ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 25949ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 26049ab747fSPaolo Bonzini 26149ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 26249ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 26349ab747fSPaolo Bonzini 26449ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 26549ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 2667ca151c3SSai Pavan Boddu #define GEM_INT_AMBA_ERR 0x00000040 26749ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 26849ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 26949ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 27049ab747fSPaolo Bonzini 27149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 27249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 27349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 27449ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 27549ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 27649ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 27749ab747fSPaolo Bonzini 27849ab747fSPaolo Bonzini /* Marvell PHY definitions */ 279dfc38879SBin Meng #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 28049ab747fSPaolo Bonzini 28149ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 28249ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 28349ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 28449ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 28549ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 28649ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 28749ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 28849ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 28949ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 29049ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 29149ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 29249ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 29349ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 29449ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 29549ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 29649ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 29749ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 29849ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 29949ab747fSPaolo Bonzini #define PHY_REG_EACD 22 30049ab747fSPaolo Bonzini #define PHY_REG_LED 24 30149ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 30249ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 30349ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 30449ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 30549ab747fSPaolo Bonzini 30649ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 30749ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 30849ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 3096623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 31049ab747fSPaolo Bonzini 31149ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 31249ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 31349ab747fSPaolo Bonzini 31449ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 31549ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 31649ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 31749ab747fSPaolo Bonzini 31849ab747fSPaolo Bonzini /***********************************************************************/ 31963af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 32063af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 32163af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 32263af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 32363af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 32463af1e0cSPeter Crosthwaite 32563af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 32649ab747fSPaolo Bonzini 32749ab747fSPaolo Bonzini /***********************************************************************/ 32849ab747fSPaolo Bonzini 32949ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 33049ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 33149ab747fSPaolo Bonzini 33249ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 33349ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 33449ab747fSPaolo Bonzini 33549ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 33649ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 33749ab747fSPaolo Bonzini 33863af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 33963af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 340a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 34163af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 34263af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 34363af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 34463af1e0cSPeter Crosthwaite 34549ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 34649ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 34749ab747fSPaolo Bonzini 348a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 349a5517666SAlistair Francis 350e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 35149ab747fSPaolo Bonzini { 352e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 353e48fdd9dSEdgar E. Iglesias 354c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 355e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 356e48fdd9dSEdgar E. Iglesias } 357e48fdd9dSEdgar E. Iglesias return ret; 35849ab747fSPaolo Bonzini } 35949ab747fSPaolo Bonzini 360f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 36149ab747fSPaolo Bonzini { 36249ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 36349ab747fSPaolo Bonzini } 36449ab747fSPaolo Bonzini 365f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 36649ab747fSPaolo Bonzini { 36749ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 36849ab747fSPaolo Bonzini } 36949ab747fSPaolo Bonzini 370f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 37149ab747fSPaolo Bonzini { 37249ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 37349ab747fSPaolo Bonzini } 37449ab747fSPaolo Bonzini 375f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 37649ab747fSPaolo Bonzini { 37749ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 37849ab747fSPaolo Bonzini } 37949ab747fSPaolo Bonzini 380f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 38149ab747fSPaolo Bonzini { 38249ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 38349ab747fSPaolo Bonzini } 38449ab747fSPaolo Bonzini 385f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 38649ab747fSPaolo Bonzini { 38767101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 38849ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 38949ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 39049ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 39149ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 39249ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 39349ab747fSPaolo Bonzini } 39449ab747fSPaolo Bonzini 395e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 39649ab747fSPaolo Bonzini { 397e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 398e48fdd9dSEdgar E. Iglesias 399c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 400e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 401e48fdd9dSEdgar E. Iglesias } 402e48fdd9dSEdgar E. Iglesias return ret; 403e48fdd9dSEdgar E. Iglesias } 404e48fdd9dSEdgar E. Iglesias 405e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 406e48fdd9dSEdgar E. Iglesias { 407e48fdd9dSEdgar E. Iglesias int ret = 2; 408e48fdd9dSEdgar E. Iglesias 409c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 410e48fdd9dSEdgar E. Iglesias ret += 2; 411e48fdd9dSEdgar E. Iglesias } 412c755c943SLuc Michel if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 413e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 414e48fdd9dSEdgar E. Iglesias ret += 2; 415e48fdd9dSEdgar E. Iglesias } 416e48fdd9dSEdgar E. Iglesias 417e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 418e48fdd9dSEdgar E. Iglesias return ret; 41949ab747fSPaolo Bonzini } 42049ab747fSPaolo Bonzini 421f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 42249ab747fSPaolo Bonzini { 42349ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 42449ab747fSPaolo Bonzini } 42549ab747fSPaolo Bonzini 426f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 42749ab747fSPaolo Bonzini { 42849ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 42949ab747fSPaolo Bonzini } 43049ab747fSPaolo Bonzini 431f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 43249ab747fSPaolo Bonzini { 43349ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 43449ab747fSPaolo Bonzini } 43549ab747fSPaolo Bonzini 436f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 43749ab747fSPaolo Bonzini { 43849ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 43949ab747fSPaolo Bonzini } 44049ab747fSPaolo Bonzini 44159ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 44259ab136aSRamon Fried { 44359ab136aSRamon Fried desc[1] = 0; 44459ab136aSRamon Fried } 44559ab136aSRamon Fried 446f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 44749ab747fSPaolo Bonzini { 44849ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 44949ab747fSPaolo Bonzini } 45049ab747fSPaolo Bonzini 451f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 45249ab747fSPaolo Bonzini { 45349ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 45449ab747fSPaolo Bonzini desc[1] |= len; 45549ab747fSPaolo Bonzini } 45649ab747fSPaolo Bonzini 457f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 45863af1e0cSPeter Crosthwaite { 45963af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 46063af1e0cSPeter Crosthwaite } 46163af1e0cSPeter Crosthwaite 462f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 46363af1e0cSPeter Crosthwaite { 46463af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 46563af1e0cSPeter Crosthwaite } 46663af1e0cSPeter Crosthwaite 467f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 46863af1e0cSPeter Crosthwaite { 46963af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 47063af1e0cSPeter Crosthwaite } 47163af1e0cSPeter Crosthwaite 472f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 47363af1e0cSPeter Crosthwaite { 47463af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 47563af1e0cSPeter Crosthwaite sar_idx); 476a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 47763af1e0cSPeter Crosthwaite } 47863af1e0cSPeter Crosthwaite 47949ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4806a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 48149ab747fSPaolo Bonzini 4827ca151c3SSai Pavan Boddu static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 4837ca151c3SSai Pavan Boddu { 4847ca151c3SSai Pavan Boddu uint32_t size; 485c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { 486c755c943SLuc Michel size = s->regs[R_JUMBO_MAX_LEN]; 4877ca151c3SSai Pavan Boddu if (size > s->jumbo_max_len) { 4887ca151c3SSai Pavan Boddu size = s->jumbo_max_len; 4897ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 4907ca151c3SSai Pavan Boddu " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 4917ca151c3SSai Pavan Boddu } 4927ca151c3SSai Pavan Boddu } else if (tx) { 4937ca151c3SSai Pavan Boddu size = 1518; 4947ca151c3SSai Pavan Boddu } else { 495c755c943SLuc Michel size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; 4967ca151c3SSai Pavan Boddu } 4977ca151c3SSai Pavan Boddu return size; 4987ca151c3SSai Pavan Boddu } 4997ca151c3SSai Pavan Boddu 50068dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 50168dbee3bSSai Pavan Boddu { 50268dbee3bSSai Pavan Boddu if (q == 0) { 503c755c943SLuc Michel s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 50468dbee3bSSai Pavan Boddu } else { 505c755c943SLuc Michel s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 506c755c943SLuc Michel ~(s->regs[R_INT_Q1_MASK + q - 1]); 50768dbee3bSSai Pavan Boddu } 50868dbee3bSSai Pavan Boddu } 50968dbee3bSSai Pavan Boddu 51049ab747fSPaolo Bonzini /* 51149ab747fSPaolo Bonzini * gem_init_register_masks: 51249ab747fSPaolo Bonzini * One time initialization. 51349ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 51449ab747fSPaolo Bonzini */ 515448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 51649ab747fSPaolo Bonzini { 5174c70e32fSSai Pavan Boddu unsigned int i; 51849ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 51949ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 520c755c943SLuc Michel s->regs_ro[R_NWCTRL] = 0xFFF80000; 521c755c943SLuc Michel s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 522c755c943SLuc Michel s->regs_ro[R_DMACFG] = 0x8E00F000; 523c755c943SLuc Michel s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 524c755c943SLuc Michel s->regs_ro[R_RXQBASE] = 0x00000003; 525c755c943SLuc Michel s->regs_ro[R_TXQBASE] = 0x00000003; 526c755c943SLuc Michel s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 527c755c943SLuc Michel s->regs_ro[R_ISR] = 0xFFFFFFFF; 528c755c943SLuc Michel s->regs_ro[R_IMR] = 0xFFFFFFFF; 529c755c943SLuc Michel s->regs_ro[R_MODID] = 0xFFFFFFFF; 5304c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 531c755c943SLuc Michel s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 532c755c943SLuc Michel s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 533c755c943SLuc Michel s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 534c755c943SLuc Michel s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 5354c70e32fSSai Pavan Boddu } 53649ab747fSPaolo Bonzini 53749ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 53849ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 539c755c943SLuc Michel s->regs_rtc[R_ISR] = 0xFFFFFFFF; 5404c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 541c755c943SLuc Michel s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 5424c70e32fSSai Pavan Boddu } 54349ab747fSPaolo Bonzini 54449ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 54549ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 546c755c943SLuc Michel s->regs_w1c[R_TXSTATUS] = 0x000001F7; 547c755c943SLuc Michel s->regs_w1c[R_RXSTATUS] = 0x0000000F; 54849ab747fSPaolo Bonzini 54949ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 55049ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 551c755c943SLuc Michel s->regs_wo[R_NWCTRL] = 0x00073E60; 552c755c943SLuc Michel s->regs_wo[R_IER] = 0x07FFFFFF; 553c755c943SLuc Michel s->regs_wo[R_IDR] = 0x07FFFFFF; 5544c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 555c755c943SLuc Michel s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 556c755c943SLuc Michel s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 5574c70e32fSSai Pavan Boddu } 55849ab747fSPaolo Bonzini } 55949ab747fSPaolo Bonzini 56049ab747fSPaolo Bonzini /* 56149ab747fSPaolo Bonzini * phy_update_link: 56249ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 56349ab747fSPaolo Bonzini */ 564448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 56549ab747fSPaolo Bonzini { 56649ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 56749ab747fSPaolo Bonzini 56849ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 56949ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 57049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 57149ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 57249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 57349ab747fSPaolo Bonzini } else { 57449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 57549ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 57649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 57749ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 57849ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 57949ab747fSPaolo Bonzini } 58049ab747fSPaolo Bonzini } 58149ab747fSPaolo Bonzini 582b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 58349ab747fSPaolo Bonzini { 584448f19e2SPeter Crosthwaite CadenceGEMState *s; 58567101725SAlistair Francis int i; 58649ab747fSPaolo Bonzini 58749ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 58849ab747fSPaolo Bonzini 58949ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 590bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { 5913ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 5923ae5725fSPeter Crosthwaite s->can_rx_state = 1; 5933ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 5943ae5725fSPeter Crosthwaite } 595b8c4b67eSPhilippe Mathieu-Daudé return false; 59649ab747fSPaolo Bonzini } 59749ab747fSPaolo Bonzini 59867101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 599dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 600dacc0566SAlistair Francis break; 601dacc0566SAlistair Francis } 602dacc0566SAlistair Francis }; 603dacc0566SAlistair Francis 604dacc0566SAlistair Francis if (i == s->num_priority_queues) { 6058202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 6068202aa53SPeter Crosthwaite s->can_rx_state = 2; 607dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 6088202aa53SPeter Crosthwaite } 609b8c4b67eSPhilippe Mathieu-Daudé return false; 6108202aa53SPeter Crosthwaite } 6118202aa53SPeter Crosthwaite 6123ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 6133ae5725fSPeter Crosthwaite s->can_rx_state = 0; 61467101725SAlistair Francis DB_PRINT("can receive\n"); 6153ae5725fSPeter Crosthwaite } 616b8c4b67eSPhilippe Mathieu-Daudé return true; 61749ab747fSPaolo Bonzini } 61849ab747fSPaolo Bonzini 61949ab747fSPaolo Bonzini /* 62049ab747fSPaolo Bonzini * gem_update_int_status: 62149ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 62249ab747fSPaolo Bonzini */ 623448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 62449ab747fSPaolo Bonzini { 62567101725SAlistair Francis int i; 62667101725SAlistair Francis 627c755c943SLuc Michel qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 628596b6f51SAlistair Francis 62986a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 630c755c943SLuc Michel qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 63149ab747fSPaolo Bonzini } 63249ab747fSPaolo Bonzini } 63349ab747fSPaolo Bonzini 63449ab747fSPaolo Bonzini /* 63549ab747fSPaolo Bonzini * gem_receive_updatestats: 63649ab747fSPaolo Bonzini * Increment receive statistics. 63749ab747fSPaolo Bonzini */ 638448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 63949ab747fSPaolo Bonzini unsigned bytes) 64049ab747fSPaolo Bonzini { 64149ab747fSPaolo Bonzini uint64_t octets; 64249ab747fSPaolo Bonzini 64349ab747fSPaolo Bonzini /* Total octets (bytes) received */ 644c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 645c755c943SLuc Michel s->regs[R_OCTRXHI]; 64649ab747fSPaolo Bonzini octets += bytes; 647c755c943SLuc Michel s->regs[R_OCTRXLO] = octets >> 32; 648c755c943SLuc Michel s->regs[R_OCTRXHI] = octets; 64949ab747fSPaolo Bonzini 65049ab747fSPaolo Bonzini /* Error-free Frames received */ 651c755c943SLuc Michel s->regs[R_RXCNT]++; 65249ab747fSPaolo Bonzini 65349ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 65449ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 655c755c943SLuc Michel s->regs[R_RXBROADCNT]++; 65649ab747fSPaolo Bonzini } 65749ab747fSPaolo Bonzini 65849ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 65949ab747fSPaolo Bonzini if (packet[0] == 0x01) { 660c755c943SLuc Michel s->regs[R_RXMULTICNT]++; 66149ab747fSPaolo Bonzini } 66249ab747fSPaolo Bonzini 66349ab747fSPaolo Bonzini if (bytes <= 64) { 664c755c943SLuc Michel s->regs[R_RX64CNT]++; 66549ab747fSPaolo Bonzini } else if (bytes <= 127) { 666c755c943SLuc Michel s->regs[R_RX65CNT]++; 66749ab747fSPaolo Bonzini } else if (bytes <= 255) { 668c755c943SLuc Michel s->regs[R_RX128CNT]++; 66949ab747fSPaolo Bonzini } else if (bytes <= 511) { 670c755c943SLuc Michel s->regs[R_RX256CNT]++; 67149ab747fSPaolo Bonzini } else if (bytes <= 1023) { 672c755c943SLuc Michel s->regs[R_RX512CNT]++; 67349ab747fSPaolo Bonzini } else if (bytes <= 1518) { 674c755c943SLuc Michel s->regs[R_RX1024CNT]++; 67549ab747fSPaolo Bonzini } else { 676c755c943SLuc Michel s->regs[R_RX1519CNT]++; 67749ab747fSPaolo Bonzini } 67849ab747fSPaolo Bonzini } 67949ab747fSPaolo Bonzini 68049ab747fSPaolo Bonzini /* 68149ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 68249ab747fSPaolo Bonzini */ 68349ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 68449ab747fSPaolo Bonzini { 68549ab747fSPaolo Bonzini unsigned byte; 68649ab747fSPaolo Bonzini 68749ab747fSPaolo Bonzini byte = mac[bit / 8]; 68849ab747fSPaolo Bonzini byte >>= (bit & 0x7); 68949ab747fSPaolo Bonzini byte &= 1; 69049ab747fSPaolo Bonzini 69149ab747fSPaolo Bonzini return byte; 69249ab747fSPaolo Bonzini } 69349ab747fSPaolo Bonzini 69449ab747fSPaolo Bonzini /* 69549ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 69649ab747fSPaolo Bonzini */ 69749ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 69849ab747fSPaolo Bonzini { 69949ab747fSPaolo Bonzini int index_bit, mac_bit; 70049ab747fSPaolo Bonzini unsigned hash_index; 70149ab747fSPaolo Bonzini 70249ab747fSPaolo Bonzini hash_index = 0; 70349ab747fSPaolo Bonzini mac_bit = 5; 70449ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 70549ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 70649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 70749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 70849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 70949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 71049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 71149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 71249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 71349ab747fSPaolo Bonzini mac_bit--; 71449ab747fSPaolo Bonzini } 71549ab747fSPaolo Bonzini 71649ab747fSPaolo Bonzini return hash_index; 71749ab747fSPaolo Bonzini } 71849ab747fSPaolo Bonzini 71949ab747fSPaolo Bonzini /* 72049ab747fSPaolo Bonzini * gem_mac_address_filter: 72149ab747fSPaolo Bonzini * Accept or reject this destination address? 72249ab747fSPaolo Bonzini * Returns: 72349ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 72463af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 72563af1e0cSPeter Crosthwaite * others for various other modes of accept: 72663af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 72763af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 72849ab747fSPaolo Bonzini */ 729448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 73049ab747fSPaolo Bonzini { 73149ab747fSPaolo Bonzini uint8_t *gem_spaddr; 732fbc14a09STong Ho int i, is_mc; 73349ab747fSPaolo Bonzini 73449ab747fSPaolo Bonzini /* Promiscuous mode? */ 735c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { 73663af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 73749ab747fSPaolo Bonzini } 73849ab747fSPaolo Bonzini 73949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 74049ab747fSPaolo Bonzini /* Reject broadcast packets? */ 741c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { 74249ab747fSPaolo Bonzini return GEM_RX_REJECT; 74349ab747fSPaolo Bonzini } 74463af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 74549ab747fSPaolo Bonzini } 74649ab747fSPaolo Bonzini 74749ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 748fbc14a09STong Ho is_mc = is_multicast_ether_addr(packet); 749c755c943SLuc Michel if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 750c755c943SLuc Michel (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 751fbc14a09STong Ho uint64_t buckets; 75249ab747fSPaolo Bonzini unsigned hash_index; 75349ab747fSPaolo Bonzini 75449ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 755c755c943SLuc Michel buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 756fbc14a09STong Ho if ((buckets >> hash_index) & 1) { 757fbc14a09STong Ho return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 758fbc14a09STong Ho : GEM_RX_UNICAST_HASH_ACCEPT; 75949ab747fSPaolo Bonzini } 76049ab747fSPaolo Bonzini } 76149ab747fSPaolo Bonzini 76249ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 763c755c943SLuc Michel gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 76463af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 76564eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 76663af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 76749ab747fSPaolo Bonzini } 76849ab747fSPaolo Bonzini } 76949ab747fSPaolo Bonzini 77049ab747fSPaolo Bonzini /* No address match; reject the packet */ 77149ab747fSPaolo Bonzini return GEM_RX_REJECT; 77249ab747fSPaolo Bonzini } 77349ab747fSPaolo Bonzini 774e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 775e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 776e8e49943SAlistair Francis unsigned rxbufsize) 777e8e49943SAlistair Francis { 778e8e49943SAlistair Francis uint32_t reg; 779e8e49943SAlistair Francis bool matched, mismatched; 780e8e49943SAlistair Francis int i, j; 781e8e49943SAlistair Francis 782e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 783c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 784e8e49943SAlistair Francis matched = false; 785e8e49943SAlistair Francis mismatched = false; 786e8e49943SAlistair Francis 787e8e49943SAlistair Francis /* Screening is based on UDP Port */ 788b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { 789e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 790b46b526cSLuc Michel if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { 791e8e49943SAlistair Francis matched = true; 792e8e49943SAlistair Francis } else { 793e8e49943SAlistair Francis mismatched = true; 794e8e49943SAlistair Francis } 795e8e49943SAlistair Francis } 796e8e49943SAlistair Francis 797e8e49943SAlistair Francis /* Screening is based on DS/TC */ 798b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { 799e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 800b46b526cSLuc Michel if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { 801e8e49943SAlistair Francis matched = true; 802e8e49943SAlistair Francis } else { 803e8e49943SAlistair Francis mismatched = true; 804e8e49943SAlistair Francis } 805e8e49943SAlistair Francis } 806e8e49943SAlistair Francis 807e8e49943SAlistair Francis if (matched && !mismatched) { 808b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); 809e8e49943SAlistair Francis } 810e8e49943SAlistair Francis } 811e8e49943SAlistair Francis 812e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 813c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 814e8e49943SAlistair Francis matched = false; 815e8e49943SAlistair Francis mismatched = false; 816e8e49943SAlistair Francis 817b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { 818e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 819b46b526cSLuc Michel int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, 820b46b526cSLuc Michel ETHERTYPE_REG_INDEX); 821e8e49943SAlistair Francis 822e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 823e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 824e8e49943SAlistair Francis "register index: %d\n", et_idx); 825e8e49943SAlistair Francis } 826c755c943SLuc Michel if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 827e8e49943SAlistair Francis et_idx]) { 828e8e49943SAlistair Francis matched = true; 829e8e49943SAlistair Francis } else { 830e8e49943SAlistair Francis mismatched = true; 831e8e49943SAlistair Francis } 832e8e49943SAlistair Francis } 833e8e49943SAlistair Francis 834e8e49943SAlistair Francis /* Compare A, B, C */ 835e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 836b46b526cSLuc Michel uint32_t cr0, cr1, mask, compare; 837e8e49943SAlistair Francis uint16_t rx_cmp; 838e8e49943SAlistair Francis int offset; 839b46b526cSLuc Michel int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, 840b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); 841e8e49943SAlistair Francis 842b46b526cSLuc Michel if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, 843b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { 844e8e49943SAlistair Francis continue; 845e8e49943SAlistair Francis } 846b46b526cSLuc Michel 847e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 848e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 849e8e49943SAlistair Francis "register index: %d\n", cr_idx); 850e8e49943SAlistair Francis } 851e8e49943SAlistair Francis 852c755c943SLuc Michel cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 853b46b526cSLuc Michel cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; 854b46b526cSLuc Michel offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); 855e8e49943SAlistair Francis 856b46b526cSLuc Michel switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { 857e8e49943SAlistair Francis case 3: /* Skip UDP header */ 858e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 859e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 860e8e49943SAlistair Francis offset += 8; 861e8e49943SAlistair Francis /* Fallthrough */ 862e8e49943SAlistair Francis case 2: /* skip the IP header */ 863e8e49943SAlistair Francis offset += 20; 864e8e49943SAlistair Francis /* Fallthrough */ 865e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 866e8e49943SAlistair Francis offset += 14; 867e8e49943SAlistair Francis break; 868e8e49943SAlistair Francis case 0: 869e8e49943SAlistair Francis /* Offset from start of frame */ 870e8e49943SAlistair Francis break; 871e8e49943SAlistair Francis } 872e8e49943SAlistair Francis 873e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 874b46b526cSLuc Michel mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); 875b46b526cSLuc Michel compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); 876e8e49943SAlistair Francis 877b46b526cSLuc Michel if ((rx_cmp & mask) == (compare & mask)) { 878e8e49943SAlistair Francis matched = true; 879e8e49943SAlistair Francis } else { 880e8e49943SAlistair Francis mismatched = true; 881e8e49943SAlistair Francis } 882e8e49943SAlistair Francis } 883e8e49943SAlistair Francis 884e8e49943SAlistair Francis if (matched && !mismatched) { 885b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); 886e8e49943SAlistair Francis } 887e8e49943SAlistair Francis } 888e8e49943SAlistair Francis 889e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 890e8e49943SAlistair Francis return 0; 891e8e49943SAlistair Francis } 892e8e49943SAlistair Francis 89396ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 89496ea126aSSai Pavan Boddu { 89596ea126aSSai Pavan Boddu uint32_t base_addr = 0; 89696ea126aSSai Pavan Boddu 89796ea126aSSai Pavan Boddu switch (q) { 89896ea126aSSai Pavan Boddu case 0: 899c755c943SLuc Michel base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 90096ea126aSSai Pavan Boddu break; 90196ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 902c755c943SLuc Michel base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 903c755c943SLuc Michel R_RECEIVE_Q1_PTR) + q - 1]; 90496ea126aSSai Pavan Boddu break; 90596ea126aSSai Pavan Boddu default: 90696ea126aSSai Pavan Boddu g_assert_not_reached(); 90796ea126aSSai Pavan Boddu }; 90896ea126aSSai Pavan Boddu 90996ea126aSSai Pavan Boddu return base_addr; 91096ea126aSSai Pavan Boddu } 91196ea126aSSai Pavan Boddu 91296ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 91396ea126aSSai Pavan Boddu { 91496ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 91596ea126aSSai Pavan Boddu } 91696ea126aSSai Pavan Boddu 91796ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 91896ea126aSSai Pavan Boddu { 91996ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 92096ea126aSSai Pavan Boddu } 92196ea126aSSai Pavan Boddu 922357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 923357aa013SEdgar E. Iglesias { 924357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 925357aa013SEdgar E. Iglesias 926c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 927c755c943SLuc Michel desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 928357aa013SEdgar E. Iglesias } 929357aa013SEdgar E. Iglesias desc_addr <<= 32; 930357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 931357aa013SEdgar E. Iglesias return desc_addr; 932357aa013SEdgar E. Iglesias } 933357aa013SEdgar E. Iglesias 934357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 935357aa013SEdgar E. Iglesias { 936357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 937357aa013SEdgar E. Iglesias } 938357aa013SEdgar E. Iglesias 939357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 940357aa013SEdgar E. Iglesias { 941357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 942357aa013SEdgar E. Iglesias } 943357aa013SEdgar E. Iglesias 94467101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 94506c2fe95SPeter Crosthwaite { 946357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 947357aa013SEdgar E. Iglesias 948357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 949357aa013SEdgar E. Iglesias 95006c2fe95SPeter Crosthwaite /* read current descriptor */ 951357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 952b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 953e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 95406c2fe95SPeter Crosthwaite 95506c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 95667101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 957357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 958c755c943SLuc Michel s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 95968dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXUSED); 96006c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 96106c2fe95SPeter Crosthwaite gem_update_int_status(s); 96206c2fe95SPeter Crosthwaite } 96306c2fe95SPeter Crosthwaite } 96406c2fe95SPeter Crosthwaite 96549ab747fSPaolo Bonzini /* 96649ab747fSPaolo Bonzini * gem_receive: 96749ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 96849ab747fSPaolo Bonzini */ 96949ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 97049ab747fSPaolo Bonzini { 97124d62fd5SSai Pavan Boddu CadenceGEMState *s = qemu_get_nic_opaque(nc); 97249ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 97349ab747fSPaolo Bonzini unsigned rxbuf_offset; 97449ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 9753b2c97f9SEdgar E. Iglesias bool first_desc = true; 97663af1e0cSPeter Crosthwaite int maf; 9772bf57f73SAlistair Francis int q = 0; 97849ab747fSPaolo Bonzini 97949ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 98063af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 98163af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 9822431f4f1SMichael Tokarev return size; /* no, drop silently b/c it's not an error */ 98349ab747fSPaolo Bonzini } 98449ab747fSPaolo Bonzini 98549ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 986c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { 98749ab747fSPaolo Bonzini unsigned type_len; 98849ab747fSPaolo Bonzini 98949ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 99049ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 99149ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 99249ab747fSPaolo Bonzini if (type_len < 0x600) { 99349ab747fSPaolo Bonzini if (size < type_len) { 99449ab747fSPaolo Bonzini /* discard */ 99549ab747fSPaolo Bonzini return -1; 99649ab747fSPaolo Bonzini } 99749ab747fSPaolo Bonzini } 99849ab747fSPaolo Bonzini } 99949ab747fSPaolo Bonzini 100049ab747fSPaolo Bonzini /* 100149ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 100249ab747fSPaolo Bonzini */ 1003c755c943SLuc Michel rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 100449ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 100549ab747fSPaolo Bonzini 100649ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 100749ab747fSPaolo Bonzini * buffers needed to hold this packet. 100849ab747fSPaolo Bonzini */ 1009c755c943SLuc Michel rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 101049ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 101149ab747fSPaolo Bonzini bytes_to_copy = size; 101249ab747fSPaolo Bonzini 1013f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 1014f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 1015f265ae8cSAlistair Francis */ 1016f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1017f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1018f265ae8cSAlistair Francis } 1019f265ae8cSAlistair Francis 1020191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 1021191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 1022191946c5SPeter Crosthwaite * not FCS stripping 1023191946c5SPeter Crosthwaite */ 1024191946c5SPeter Crosthwaite if (size < 60) { 1025191946c5SPeter Crosthwaite size = 60; 1026191946c5SPeter Crosthwaite } 1027191946c5SPeter Crosthwaite 102849ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 1029c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { 103049ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 103149ab747fSPaolo Bonzini } else { 103249ab747fSPaolo Bonzini unsigned crc_val; 103349ab747fSPaolo Bonzini 103424d62fd5SSai Pavan Boddu if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 103524d62fd5SSai Pavan Boddu size = MAX_FRAME_SIZE - sizeof(crc_val); 1036244381ecSPrasad J Pandit } 1037244381ecSPrasad J Pandit bytes_to_copy = size; 103849ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 10393048ed6aSPeter Crosthwaite * We must try and calculate one. 104049ab747fSPaolo Bonzini */ 104149ab747fSPaolo Bonzini 104224d62fd5SSai Pavan Boddu memcpy(s->rx_packet, buf, size); 104324d62fd5SSai Pavan Boddu memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 104424d62fd5SSai Pavan Boddu rxbuf_ptr = s->rx_packet; 104524d62fd5SSai Pavan Boddu crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 104624d62fd5SSai Pavan Boddu memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 104749ab747fSPaolo Bonzini 104849ab747fSPaolo Bonzini bytes_to_copy += 4; 104949ab747fSPaolo Bonzini size += 4; 105049ab747fSPaolo Bonzini } 105149ab747fSPaolo Bonzini 10526fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 105349ab747fSPaolo Bonzini 1054b12227afSStefan Weil /* Find which queue we are targeting */ 1055e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1056e8e49943SAlistair Francis 10577ca151c3SSai Pavan Boddu if (size > gem_get_max_buf_len(s, false)) { 10587ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 10597ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 10607ca151c3SSai Pavan Boddu return -1; 10617ca151c3SSai Pavan Boddu } 10627ca151c3SSai Pavan Boddu 10637cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1064357aa013SEdgar E. Iglesias hwaddr desc_addr; 1065357aa013SEdgar E. Iglesias 106606c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 106706c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 106849ab747fSPaolo Bonzini return -1; 106949ab747fSPaolo Bonzini } 107049ab747fSPaolo Bonzini 10716fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1072dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1073dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 107449ab747fSPaolo Bonzini 107549ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 107684aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 10772bf57f73SAlistair Francis rxbuf_offset, 107884aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1079e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 108049ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 108130570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 10823b2c97f9SEdgar E. Iglesias 108359ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 108459ab136aSRamon Fried 10853b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 10863b2c97f9SEdgar E. Iglesias if (first_desc) { 10872bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 10883b2c97f9SEdgar E. Iglesias first_desc = false; 10893b2c97f9SEdgar E. Iglesias } 10903b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 10912bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 10922bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 10933b2c97f9SEdgar E. Iglesias } 10942bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 109563af1e0cSPeter Crosthwaite 109663af1e0cSPeter Crosthwaite switch (maf) { 109763af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 109863af1e0cSPeter Crosthwaite break; 109963af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 11002bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 110163af1e0cSPeter Crosthwaite break; 110263af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 11032bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 110463af1e0cSPeter Crosthwaite break; 110563af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 11062bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 110763af1e0cSPeter Crosthwaite break; 110863af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 110963af1e0cSPeter Crosthwaite abort(); 111063af1e0cSPeter Crosthwaite default: /* SAR */ 11112bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 111263af1e0cSPeter Crosthwaite } 111363af1e0cSPeter Crosthwaite 11143b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1115357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1116b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1117b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1118e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 11193b2c97f9SEdgar E. Iglesias 112049ab747fSPaolo Bonzini /* Next descriptor */ 11212bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 112249ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 112396ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 112449ab747fSPaolo Bonzini } else { 112549ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1126e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 112749ab747fSPaolo Bonzini } 112867101725SAlistair Francis 112967101725SAlistair Francis gem_get_rx_desc(s, q); 11307cfd65e4SPeter Crosthwaite } 113149ab747fSPaolo Bonzini 113249ab747fSPaolo Bonzini /* Count it */ 113349ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 113449ab747fSPaolo Bonzini 1135c755c943SLuc Michel s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 113668dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXCMPL); 113749ab747fSPaolo Bonzini 113849ab747fSPaolo Bonzini /* Handle interrupt consequences */ 113949ab747fSPaolo Bonzini gem_update_int_status(s); 114049ab747fSPaolo Bonzini 114149ab747fSPaolo Bonzini return size; 114249ab747fSPaolo Bonzini } 114349ab747fSPaolo Bonzini 114449ab747fSPaolo Bonzini /* 114549ab747fSPaolo Bonzini * gem_transmit_updatestats: 114649ab747fSPaolo Bonzini * Increment transmit statistics. 114749ab747fSPaolo Bonzini */ 1148448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 114949ab747fSPaolo Bonzini unsigned bytes) 115049ab747fSPaolo Bonzini { 115149ab747fSPaolo Bonzini uint64_t octets; 115249ab747fSPaolo Bonzini 115349ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 1154c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1155c755c943SLuc Michel s->regs[R_OCTTXHI]; 115649ab747fSPaolo Bonzini octets += bytes; 1157c755c943SLuc Michel s->regs[R_OCTTXLO] = octets >> 32; 1158c755c943SLuc Michel s->regs[R_OCTTXHI] = octets; 115949ab747fSPaolo Bonzini 116049ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 1161c755c943SLuc Michel s->regs[R_TXCNT]++; 116249ab747fSPaolo Bonzini 116349ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 116449ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 1165c755c943SLuc Michel s->regs[R_TXBCNT]++; 116649ab747fSPaolo Bonzini } 116749ab747fSPaolo Bonzini 116849ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 116949ab747fSPaolo Bonzini if (packet[0] == 0x01) { 1170c755c943SLuc Michel s->regs[R_TXMCNT]++; 117149ab747fSPaolo Bonzini } 117249ab747fSPaolo Bonzini 117349ab747fSPaolo Bonzini if (bytes <= 64) { 1174c755c943SLuc Michel s->regs[R_TX64CNT]++; 117549ab747fSPaolo Bonzini } else if (bytes <= 127) { 1176c755c943SLuc Michel s->regs[R_TX65CNT]++; 117749ab747fSPaolo Bonzini } else if (bytes <= 255) { 1178c755c943SLuc Michel s->regs[R_TX128CNT]++; 117949ab747fSPaolo Bonzini } else if (bytes <= 511) { 1180c755c943SLuc Michel s->regs[R_TX256CNT]++; 118149ab747fSPaolo Bonzini } else if (bytes <= 1023) { 1182c755c943SLuc Michel s->regs[R_TX512CNT]++; 118349ab747fSPaolo Bonzini } else if (bytes <= 1518) { 1184c755c943SLuc Michel s->regs[R_TX1024CNT]++; 118549ab747fSPaolo Bonzini } else { 1186c755c943SLuc Michel s->regs[R_TX1519CNT]++; 118749ab747fSPaolo Bonzini } 118849ab747fSPaolo Bonzini } 118949ab747fSPaolo Bonzini 119049ab747fSPaolo Bonzini /* 119149ab747fSPaolo Bonzini * gem_transmit: 119249ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 119349ab747fSPaolo Bonzini */ 1194448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 119549ab747fSPaolo Bonzini { 11968568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 119749ab747fSPaolo Bonzini hwaddr packet_desc_addr; 119849ab747fSPaolo Bonzini uint8_t *p; 119949ab747fSPaolo Bonzini unsigned total_bytes; 12002bf57f73SAlistair Francis int q = 0; 120149ab747fSPaolo Bonzini 120249ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1203bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 120449ab747fSPaolo Bonzini return; 120549ab747fSPaolo Bonzini } 120649ab747fSPaolo Bonzini 120749ab747fSPaolo Bonzini DB_PRINT("\n"); 120849ab747fSPaolo Bonzini 12093048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 121049ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 121149ab747fSPaolo Bonzini * one contiguous buffer first. 121249ab747fSPaolo Bonzini */ 121324d62fd5SSai Pavan Boddu p = s->tx_packet; 121449ab747fSPaolo Bonzini total_bytes = 0; 121549ab747fSPaolo Bonzini 121667101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 121749ab747fSPaolo Bonzini /* read current descriptor */ 1218357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1219fa15286aSPeter Crosthwaite 1220fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 122184aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1222b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1223e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 122449ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 122549ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 122649ab747fSPaolo Bonzini 122749ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1228bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 122949ab747fSPaolo Bonzini return; 123049ab747fSPaolo Bonzini } 123167101725SAlistair Francis print_gem_tx_desc(desc, q); 123249ab747fSPaolo Bonzini 123349ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 123449ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 123549ab747fSPaolo Bonzini */ 1236e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 123749ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 12386fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 12396fe7661dSSai Pavan Boddu packet_desc_addr); 124049ab747fSPaolo Bonzini break; 124149ab747fSPaolo Bonzini } 124249ab747fSPaolo Bonzini 12437ca151c3SSai Pavan Boddu if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 124424d62fd5SSai Pavan Boddu (p - s->tx_packet)) { 12457ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 12467ca151c3SSai Pavan Boddu HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1247dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 12487ca151c3SSai Pavan Boddu gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 12497ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1250d7f05365SMichael S. Tsirkin break; 1251d7f05365SMichael S. Tsirkin } 1252d7f05365SMichael S. Tsirkin 125377524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 125477524d11SAlistair Francis * contig buffer. 125549ab747fSPaolo Bonzini */ 125684aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 125784aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 125884aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 125949ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 126049ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 126149ab747fSPaolo Bonzini 126249ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 126349ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 12648568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1265357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 12666ab57a6bSPeter Crosthwaite 126749ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 126849ab747fSPaolo Bonzini * the processor. 126949ab747fSPaolo Bonzini */ 1270357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1271b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12726ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12736ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1274357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1275b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12766ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12773048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 127849ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 127996ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 128049ab747fSPaolo Bonzini } else { 1281e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1282e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 128349ab747fSPaolo Bonzini } 12842bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 128549ab747fSPaolo Bonzini 1286c755c943SLuc Michel s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 128768dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_TXCMPL); 128867101725SAlistair Francis 128949ab747fSPaolo Bonzini /* Handle interrupt consequences */ 129049ab747fSPaolo Bonzini gem_update_int_status(s); 129149ab747fSPaolo Bonzini 129249ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 1293c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1294f5746335SBin Meng net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 129549ab747fSPaolo Bonzini } 129649ab747fSPaolo Bonzini 129749ab747fSPaolo Bonzini /* Update MAC statistics */ 129824d62fd5SSai Pavan Boddu gem_transmit_updatestats(s, s->tx_packet, total_bytes); 129949ab747fSPaolo Bonzini 130049ab747fSPaolo Bonzini /* Send the packet somewhere */ 1301bd8a922dSLuc Michel if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, 1302bd8a922dSLuc Michel LOOPBACK_LOCAL)) { 1303e73adfbeSAlexander Bulekov qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 130477524d11SAlistair Francis total_bytes); 130549ab747fSPaolo Bonzini } else { 130624d62fd5SSai Pavan Boddu qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 130749ab747fSPaolo Bonzini total_bytes); 130849ab747fSPaolo Bonzini } 130949ab747fSPaolo Bonzini 131049ab747fSPaolo Bonzini /* Prepare for next packet */ 131124d62fd5SSai Pavan Boddu p = s->tx_packet; 131249ab747fSPaolo Bonzini total_bytes = 0; 131349ab747fSPaolo Bonzini } 131449ab747fSPaolo Bonzini 131549ab747fSPaolo Bonzini /* read next descriptor */ 131649ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1317c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 1318c755c943SLuc Michel packet_desc_addr = s->regs[R_TBQPH]; 1319f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1320f1e7cb13SRamon Fried } else { 1321f1e7cb13SRamon Fried packet_desc_addr = 0; 1322f1e7cb13SRamon Fried } 132396ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 132449ab747fSPaolo Bonzini } else { 1325e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 132649ab747fSPaolo Bonzini } 1327fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 132884aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1329b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1330e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 133149ab747fSPaolo Bonzini } 133249ab747fSPaolo Bonzini 133349ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 1334c755c943SLuc Michel s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; 133568dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 133668dbee3bSSai Pavan Boddu if (q == 0) { 133768dbee3bSSai Pavan Boddu gem_set_isr(s, 0, GEM_INT_TXUSED); 133868dbee3bSSai Pavan Boddu } 133949ab747fSPaolo Bonzini gem_update_int_status(s); 134049ab747fSPaolo Bonzini } 134149ab747fSPaolo Bonzini } 134267101725SAlistair Francis } 134349ab747fSPaolo Bonzini 1344448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 134549ab747fSPaolo Bonzini { 134649ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 134749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 134849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 134949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 135049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 135149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 135249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 135349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 135449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 135549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 135649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 135749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 135849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 135949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 13607777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 136149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 136249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 136349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 136449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 136549ab747fSPaolo Bonzini 136649ab747fSPaolo Bonzini phy_update_link(s); 136749ab747fSPaolo Bonzini } 136849ab747fSPaolo Bonzini 136949ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 137049ab747fSPaolo Bonzini { 137164eb9301SPeter Crosthwaite int i; 1372448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1373afb4c51fSSebastian Huber const uint8_t *a; 1374726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 137549ab747fSPaolo Bonzini 137649ab747fSPaolo Bonzini DB_PRINT("\n"); 137749ab747fSPaolo Bonzini 137849ab747fSPaolo Bonzini /* Set post reset register values */ 137949ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 1380c755c943SLuc Michel s->regs[R_NWCFG] = 0x00080000; 1381c755c943SLuc Michel s->regs[R_NWSTATUS] = 0x00000006; 1382c755c943SLuc Michel s->regs[R_DMACFG] = 0x00020784; 1383c755c943SLuc Michel s->regs[R_IMR] = 0x07ffffff; 1384c755c943SLuc Michel s->regs[R_TXPAUSE] = 0x0000ffff; 1385c755c943SLuc Michel s->regs[R_TXPARTIALSF] = 0x000003ff; 1386c755c943SLuc Michel s->regs[R_RXPARTIALSF] = 0x000003ff; 1387c755c943SLuc Michel s->regs[R_MODID] = s->revision; 1388c755c943SLuc Michel s->regs[R_DESCONF] = 0x02D00111; 1389c755c943SLuc Michel s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1390c755c943SLuc Michel s->regs[R_DESCONF5] = 0x002f2045; 1391c755c943SLuc Michel s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; 1392c755c943SLuc Michel s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1393c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1394726a2a95SEdgar E. Iglesias 1395726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1396726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1397c755c943SLuc Michel s->regs[R_DESCONF6] |= queues_mask; 1398726a2a95SEdgar E. Iglesias } 139949ab747fSPaolo Bonzini 1400afb4c51fSSebastian Huber /* Set MAC address */ 1401afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1402c755c943SLuc Michel s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1403c755c943SLuc Michel s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1404afb4c51fSSebastian Huber 140564eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 140664eb9301SPeter Crosthwaite s->sar_active[i] = false; 140764eb9301SPeter Crosthwaite } 140864eb9301SPeter Crosthwaite 140949ab747fSPaolo Bonzini gem_phy_reset(s); 141049ab747fSPaolo Bonzini 141149ab747fSPaolo Bonzini gem_update_int_status(s); 141249ab747fSPaolo Bonzini } 141349ab747fSPaolo Bonzini 1414448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 141549ab747fSPaolo Bonzini { 141649ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 141749ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 141849ab747fSPaolo Bonzini } 141949ab747fSPaolo Bonzini 1420448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 142149ab747fSPaolo Bonzini { 142249ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 142349ab747fSPaolo Bonzini 142449ab747fSPaolo Bonzini switch (reg_num) { 142549ab747fSPaolo Bonzini case PHY_REG_CONTROL: 142649ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 142749ab747fSPaolo Bonzini /* Phy reset */ 142849ab747fSPaolo Bonzini gem_phy_reset(s); 142949ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 143049ab747fSPaolo Bonzini s->phy_loop = 0; 143149ab747fSPaolo Bonzini } 143249ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 143349ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 14346623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 143549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 143649ab747fSPaolo Bonzini } 143749ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 143849ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 143949ab747fSPaolo Bonzini s->phy_loop = 1; 144049ab747fSPaolo Bonzini } else { 144149ab747fSPaolo Bonzini s->phy_loop = 0; 144249ab747fSPaolo Bonzini } 144349ab747fSPaolo Bonzini break; 144449ab747fSPaolo Bonzini } 144549ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 144649ab747fSPaolo Bonzini } 144749ab747fSPaolo Bonzini 144849ab747fSPaolo Bonzini /* 144949ab747fSPaolo Bonzini * gem_read32: 145049ab747fSPaolo Bonzini * Read a GEM register. 145149ab747fSPaolo Bonzini */ 145249ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 145349ab747fSPaolo Bonzini { 1454448f19e2SPeter Crosthwaite CadenceGEMState *s; 145549ab747fSPaolo Bonzini uint32_t retval; 14563d558330SMarkus Armbruster s = opaque; 145749ab747fSPaolo Bonzini 145849ab747fSPaolo Bonzini offset >>= 2; 145949ab747fSPaolo Bonzini retval = s->regs[offset]; 146049ab747fSPaolo Bonzini 146149ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 146249ab747fSPaolo Bonzini 146349ab747fSPaolo Bonzini switch (offset) { 1464c755c943SLuc Michel case R_ISR: 146567101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1466596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 146749ab747fSPaolo Bonzini break; 1468c755c943SLuc Michel case R_PHYMNTNC: 146949ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 147049ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 147149ab747fSPaolo Bonzini 147249ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1473dfc38879SBin Meng if (phy_addr == s->phy_addr) { 147449ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 147549ab747fSPaolo Bonzini retval &= 0xFFFF0000; 147649ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 147749ab747fSPaolo Bonzini } else { 147849ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 147949ab747fSPaolo Bonzini } 148049ab747fSPaolo Bonzini } 148149ab747fSPaolo Bonzini break; 148249ab747fSPaolo Bonzini } 148349ab747fSPaolo Bonzini 148449ab747fSPaolo Bonzini /* Squash read to clear bits */ 148549ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 148649ab747fSPaolo Bonzini 148749ab747fSPaolo Bonzini /* Do not provide write only bits */ 148849ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 148949ab747fSPaolo Bonzini 149049ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 149167101725SAlistair Francis gem_update_int_status(s); 149249ab747fSPaolo Bonzini return retval; 149349ab747fSPaolo Bonzini } 149449ab747fSPaolo Bonzini 149549ab747fSPaolo Bonzini /* 149649ab747fSPaolo Bonzini * gem_write32: 149749ab747fSPaolo Bonzini * Write a GEM register. 149849ab747fSPaolo Bonzini */ 149949ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 150049ab747fSPaolo Bonzini unsigned size) 150149ab747fSPaolo Bonzini { 1502448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 150349ab747fSPaolo Bonzini uint32_t readonly; 150467101725SAlistair Francis int i; 150549ab747fSPaolo Bonzini 150649ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 150749ab747fSPaolo Bonzini offset >>= 2; 150849ab747fSPaolo Bonzini 150949ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 151049ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1511e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1512e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 151349ab747fSPaolo Bonzini 151449ab747fSPaolo Bonzini /* Copy register write to backing store */ 1515e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1516e2314fdaSPeter Crosthwaite 1517e2314fdaSPeter Crosthwaite /* do w1c */ 1518e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 151949ab747fSPaolo Bonzini 152049ab747fSPaolo Bonzini /* Handle register write side effects */ 152149ab747fSPaolo Bonzini switch (offset) { 1522c755c943SLuc Michel case R_NWCTRL: 1523bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { 152467101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 152567101725SAlistair Francis gem_get_rx_desc(s, i); 152667101725SAlistair Francis } 152706c2fe95SPeter Crosthwaite } 1528bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { 152949ab747fSPaolo Bonzini gem_transmit(s); 153049ab747fSPaolo Bonzini } 1531bd8a922dSLuc Michel if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { 153249ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 153367101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 153496ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 153567101725SAlistair Francis } 153649ab747fSPaolo Bonzini } 15378202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 153849ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 153949ab747fSPaolo Bonzini } 154049ab747fSPaolo Bonzini break; 154149ab747fSPaolo Bonzini 1542c755c943SLuc Michel case R_TXSTATUS: 154349ab747fSPaolo Bonzini gem_update_int_status(s); 154449ab747fSPaolo Bonzini break; 1545c755c943SLuc Michel case R_RXQBASE: 15462bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 154749ab747fSPaolo Bonzini break; 1548c755c943SLuc Michel case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1549c755c943SLuc Michel s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 155067101725SAlistair Francis break; 1551c755c943SLuc Michel case R_TXQBASE: 15522bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 155349ab747fSPaolo Bonzini break; 1554c755c943SLuc Michel case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1555c755c943SLuc Michel s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 155667101725SAlistair Francis break; 1557c755c943SLuc Michel case R_RXSTATUS: 155849ab747fSPaolo Bonzini gem_update_int_status(s); 155949ab747fSPaolo Bonzini break; 1560c755c943SLuc Michel case R_IER: 1561c755c943SLuc Michel s->regs[R_IMR] &= ~val; 156249ab747fSPaolo Bonzini gem_update_int_status(s); 156349ab747fSPaolo Bonzini break; 1564c755c943SLuc Michel case R_JUMBO_MAX_LEN: 1565c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 15667ca151c3SSai Pavan Boddu break; 1567c755c943SLuc Michel case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1568c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 156967101725SAlistair Francis gem_update_int_status(s); 157067101725SAlistair Francis break; 1571c755c943SLuc Michel case R_IDR: 1572c755c943SLuc Michel s->regs[R_IMR] |= val; 157349ab747fSPaolo Bonzini gem_update_int_status(s); 157449ab747fSPaolo Bonzini break; 1575c755c943SLuc Michel case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1576c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 157767101725SAlistair Francis gem_update_int_status(s); 157867101725SAlistair Francis break; 1579c755c943SLuc Michel case R_SPADDR1LO: 1580c755c943SLuc Michel case R_SPADDR2LO: 1581c755c943SLuc Michel case R_SPADDR3LO: 1582c755c943SLuc Michel case R_SPADDR4LO: 1583c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 158464eb9301SPeter Crosthwaite break; 1585c755c943SLuc Michel case R_SPADDR1HI: 1586c755c943SLuc Michel case R_SPADDR2HI: 1587c755c943SLuc Michel case R_SPADDR3HI: 1588c755c943SLuc Michel case R_SPADDR4HI: 1589c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 159064eb9301SPeter Crosthwaite break; 1591c755c943SLuc Michel case R_PHYMNTNC: 159249ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 159349ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 159449ab747fSPaolo Bonzini 159549ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1596dfc38879SBin Meng if (phy_addr == s->phy_addr) { 159749ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 159849ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 159949ab747fSPaolo Bonzini } 160049ab747fSPaolo Bonzini } 160149ab747fSPaolo Bonzini break; 160249ab747fSPaolo Bonzini } 160349ab747fSPaolo Bonzini 160449ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 160549ab747fSPaolo Bonzini } 160649ab747fSPaolo Bonzini 160749ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 160849ab747fSPaolo Bonzini .read = gem_read, 160949ab747fSPaolo Bonzini .write = gem_write, 161049ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 161149ab747fSPaolo Bonzini }; 161249ab747fSPaolo Bonzini 161349ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 161449ab747fSPaolo Bonzini { 161567101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 161667101725SAlistair Francis 161749ab747fSPaolo Bonzini DB_PRINT("\n"); 161867101725SAlistair Francis phy_update_link(s); 161967101725SAlistair Francis gem_update_int_status(s); 162049ab747fSPaolo Bonzini } 162149ab747fSPaolo Bonzini 162249ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1623f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 162449ab747fSPaolo Bonzini .size = sizeof(NICState), 162549ab747fSPaolo Bonzini .can_receive = gem_can_receive, 162649ab747fSPaolo Bonzini .receive = gem_receive, 162749ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 162849ab747fSPaolo Bonzini }; 162949ab747fSPaolo Bonzini 1630bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 163149ab747fSPaolo Bonzini { 1632448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 163367101725SAlistair Francis int i; 163449ab747fSPaolo Bonzini 163584aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 163684aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 163784aec8efSEdgar E. Iglesias 16382bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 16392bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 16402bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 16412bf57f73SAlistair Francis s->num_priority_queues); 16422bf57f73SAlistair Francis return; 1643e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1644e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1645e8e49943SAlistair Francis s->num_type1_screeners); 1646e8e49943SAlistair Francis return; 1647e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1648e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1649e8e49943SAlistair Francis s->num_type2_screeners); 1650e8e49943SAlistair Francis return; 16512bf57f73SAlistair Francis } 16522bf57f73SAlistair Francis 165367101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 165467101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 165567101725SAlistair Francis } 1656bcb39a65SAlistair Francis 1657bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1658bcb39a65SAlistair Francis 1659bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1660bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 16617ca151c3SSai Pavan Boddu 16627ca151c3SSai Pavan Boddu if (s->jumbo_max_len > MAX_FRAME_SIZE) { 16637ca151c3SSai Pavan Boddu error_setg(errp, "jumbo-max-len is greater than %d", 16647ca151c3SSai Pavan Boddu MAX_FRAME_SIZE); 16657ca151c3SSai Pavan Boddu return; 16667ca151c3SSai Pavan Boddu } 1667bcb39a65SAlistair Francis } 1668bcb39a65SAlistair Francis 1669bcb39a65SAlistair Francis static void gem_init(Object *obj) 1670bcb39a65SAlistair Francis { 1671bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1672bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1673bcb39a65SAlistair Francis 167449ab747fSPaolo Bonzini DB_PRINT("\n"); 167549ab747fSPaolo Bonzini 167649ab747fSPaolo Bonzini gem_init_register_masks(s); 1677eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1678eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 167949ab747fSPaolo Bonzini 1680bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 168149ab747fSPaolo Bonzini } 168249ab747fSPaolo Bonzini 168349ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 168449ab747fSPaolo Bonzini .name = "cadence_gem", 1685e8e49943SAlistair Francis .version_id = 4, 1686e8e49943SAlistair Francis .minimum_version_id = 4, 168749ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1688448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1689448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1690448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 16912bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 16922bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 16932bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 16942bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1695448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 169617cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 169749ab747fSPaolo Bonzini } 169849ab747fSPaolo Bonzini }; 169949ab747fSPaolo Bonzini 170049ab747fSPaolo Bonzini static Property gem_properties[] = { 1701448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1702a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1703a5517666SAlistair Francis GEM_MODID_VALUE), 170464ac1363SBin Meng DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 17052bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 17062bf57f73SAlistair Francis num_priority_queues, 1), 1707e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1708e8e49943SAlistair Francis num_type1_screeners, 4), 1709e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1710e8e49943SAlistair Francis num_type2_screeners, 4), 17117ca151c3SSai Pavan Boddu DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 17127ca151c3SSai Pavan Boddu jumbo_max_len, 10240), 171308d45942SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 171408d45942SPhilippe Mathieu-Daudé TYPE_MEMORY_REGION, MemoryRegion *), 171549ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 171649ab747fSPaolo Bonzini }; 171749ab747fSPaolo Bonzini 171849ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 171949ab747fSPaolo Bonzini { 172049ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 172149ab747fSPaolo Bonzini 1722bcb39a65SAlistair Francis dc->realize = gem_realize; 17234f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 172449ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 172549ab747fSPaolo Bonzini dc->reset = gem_reset; 172649ab747fSPaolo Bonzini } 172749ab747fSPaolo Bonzini 172849ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1729318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 173049ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1731448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1732bcb39a65SAlistair Francis .instance_init = gem_init, 1733318643beSAndreas Färber .class_init = gem_class_init, 173449ab747fSPaolo Bonzini }; 173549ab747fSPaolo Bonzini 173649ab747fSPaolo Bonzini static void gem_register_types(void) 173749ab747fSPaolo Bonzini { 173849ab747fSPaolo Bonzini type_register_static(&gem_info); 173949ab747fSPaolo Bonzini } 174049ab747fSPaolo Bonzini 174149ab747fSPaolo Bonzini type_init(gem_register_types) 1742