149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31c755c943SLuc Michel #include "hw/registerfields.h" 32d6454270SMarkus Armbruster #include "migration/vmstate.h" 332bf57f73SAlistair Francis #include "qapi/error.h" 34e8e49943SAlistair Francis #include "qemu/log.h" 350b8fa32fSMarkus Armbruster #include "qemu/module.h" 3684aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3749ab747fSPaolo Bonzini #include "net/checksum.h" 38fbc14a09STong Ho #include "net/eth.h" 3949ab747fSPaolo Bonzini 406fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 4149ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 426fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 436fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 446fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 456fe7661dSSai Pavan Boddu } \ 462562755eSEric Blake } while (0) 4749ab747fSPaolo Bonzini 48c755c943SLuc Michel REG32(NWCTRL, 0x0) /* Network Control reg */ 49c755c943SLuc Michel REG32(NWCFG, 0x4) /* Network Config reg */ 50c755c943SLuc Michel REG32(NWSTATUS, 0x8) /* Network Status reg */ 51c755c943SLuc Michel REG32(USERIO, 0xc) /* User IO reg */ 52c755c943SLuc Michel REG32(DMACFG, 0x10) /* DMA Control reg */ 53c755c943SLuc Michel REG32(TXSTATUS, 0x14) /* TX Status reg */ 54c755c943SLuc Michel REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 55c755c943SLuc Michel REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 56c755c943SLuc Michel REG32(RXSTATUS, 0x20) /* RX Status reg */ 57c755c943SLuc Michel REG32(ISR, 0x24) /* Interrupt Status reg */ 58c755c943SLuc Michel REG32(IER, 0x28) /* Interrupt Enable reg */ 59c755c943SLuc Michel REG32(IDR, 0x2c) /* Interrupt Disable reg */ 60c755c943SLuc Michel REG32(IMR, 0x30) /* Interrupt Mask reg */ 61c755c943SLuc Michel REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 62c755c943SLuc Michel REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 63c755c943SLuc Michel REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 64c755c943SLuc Michel REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 65c755c943SLuc Michel REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 66c755c943SLuc Michel REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 67c755c943SLuc Michel REG32(HASHLO, 0x80) /* Hash Low address reg */ 68c755c943SLuc Michel REG32(HASHHI, 0x84) /* Hash High address reg */ 69c755c943SLuc Michel REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 70c755c943SLuc Michel REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 71c755c943SLuc Michel REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 72c755c943SLuc Michel REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 73c755c943SLuc Michel REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 74c755c943SLuc Michel REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 75c755c943SLuc Michel REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 76c755c943SLuc Michel REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 77c755c943SLuc Michel REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 78c755c943SLuc Michel REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 79c755c943SLuc Michel REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 80c755c943SLuc Michel REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 81c755c943SLuc Michel REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 82c755c943SLuc Michel REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 83c755c943SLuc Michel REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 84c755c943SLuc Michel REG32(MODID, 0xfc) /* Module ID reg */ 85c755c943SLuc Michel REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 86c755c943SLuc Michel REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 87c755c943SLuc Michel REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 88c755c943SLuc Michel REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 89c755c943SLuc Michel REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 90c755c943SLuc Michel REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 91c755c943SLuc Michel REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 92c755c943SLuc Michel REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 93c755c943SLuc Michel REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 94c755c943SLuc Michel REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 95c755c943SLuc Michel REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 96c755c943SLuc Michel REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 97c755c943SLuc Michel REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 98c755c943SLuc Michel REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 99c755c943SLuc Michel REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 100c755c943SLuc Michel REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 101c755c943SLuc Michel REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 102c755c943SLuc Michel REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 103c755c943SLuc Michel REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 104c755c943SLuc Michel REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 105c755c943SLuc Michel REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 106c755c943SLuc Michel REG32(OCTRXHI, 0x154) /* Octects Received register High */ 107c755c943SLuc Michel REG32(RXCNT, 0x158) /* Error-free Frames Received */ 108c755c943SLuc Michel REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 109c755c943SLuc Michel REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 110c755c943SLuc Michel REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 111c755c943SLuc Michel REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 112c755c943SLuc Michel REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 113c755c943SLuc Michel REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 114c755c943SLuc Michel REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 115c755c943SLuc Michel REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 116c755c943SLuc Michel REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 117c755c943SLuc Michel REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 118c755c943SLuc Michel REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 119c755c943SLuc Michel REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 120c755c943SLuc Michel REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 121c755c943SLuc Michel REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 122c755c943SLuc Michel REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 123c755c943SLuc Michel REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 124c755c943SLuc Michel REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 125c755c943SLuc Michel REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 126c755c943SLuc Michel REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 127c755c943SLuc Michel REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 128c755c943SLuc Michel REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 129c755c943SLuc Michel REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 13049ab747fSPaolo Bonzini 131c755c943SLuc Michel REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 132c755c943SLuc Michel REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 133c755c943SLuc Michel REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 134c755c943SLuc Michel REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 135c755c943SLuc Michel REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 136c755c943SLuc Michel REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 137c755c943SLuc Michel REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 138c755c943SLuc Michel REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 139c755c943SLuc Michel REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 140c755c943SLuc Michel REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 141c755c943SLuc Michel REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 142c755c943SLuc Michel REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 14349ab747fSPaolo Bonzini 14449ab747fSPaolo Bonzini /* Design Configuration Registers */ 145c755c943SLuc Michel REG32(DESCONF, 0x280) 146c755c943SLuc Michel REG32(DESCONF2, 0x284) 147c755c943SLuc Michel REG32(DESCONF3, 0x288) 148c755c943SLuc Michel REG32(DESCONF4, 0x28c) 149c755c943SLuc Michel REG32(DESCONF5, 0x290) 150c755c943SLuc Michel REG32(DESCONF6, 0x294) 151e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 152c755c943SLuc Michel REG32(DESCONF7, 0x298) 15349ab747fSPaolo Bonzini 154c755c943SLuc Michel REG32(INT_Q1_STATUS, 0x400) 155c755c943SLuc Michel REG32(INT_Q1_MASK, 0x640) 15667101725SAlistair Francis 157c755c943SLuc Michel REG32(TRANSMIT_Q1_PTR, 0x440) 158c755c943SLuc Michel REG32(TRANSMIT_Q7_PTR, 0x458) 15967101725SAlistair Francis 160c755c943SLuc Michel REG32(RECEIVE_Q1_PTR, 0x480) 161c755c943SLuc Michel REG32(RECEIVE_Q7_PTR, 0x498) 16267101725SAlistair Francis 163c755c943SLuc Michel REG32(TBQPH, 0x4c8) 164c755c943SLuc Michel REG32(RBQPH, 0x4d4) 165357aa013SEdgar E. Iglesias 166c755c943SLuc Michel REG32(INT_Q1_ENABLE, 0x600) 167c755c943SLuc Michel REG32(INT_Q7_ENABLE, 0x618) 16867101725SAlistair Francis 169c755c943SLuc Michel REG32(INT_Q1_DISABLE, 0x620) 170c755c943SLuc Michel REG32(INT_Q7_DISABLE, 0x638) 17167101725SAlistair Francis 172c755c943SLuc Michel REG32(SCREENING_TYPE1_REG0, 0x500) 173e8e49943SAlistair Francis 174e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 175e8e49943SAlistair Francis #define GEM_ST1R_DSTC_ENABLE (1 << 28) 176e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 177e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 178e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 179e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 180e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_SHIFT (0) 181e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 182e8e49943SAlistair Francis 183c755c943SLuc Michel REG32(SCREENING_TYPE2_REG0, 0x540) 184e8e49943SAlistair Francis 185e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 186e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_SHIFT (13) 187e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 188e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 189e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 190e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 191e8e49943SAlistair Francis + 1) 192e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_SHIFT (0) 193e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 194e8e49943SAlistair Francis 195c755c943SLuc Michel REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 196c755c943SLuc Michel REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 197e8e49943SAlistair Francis 198e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 199e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 200e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 201e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 202e8e49943SAlistair Francis 20349ab747fSPaolo Bonzini /*****************************************/ 20449ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 20549ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 20649ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 20749ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 20849ab747fSPaolo Bonzini 20949ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2103048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 21149ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 21249ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 2137ca151c3SSai Pavan Boddu #define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ 21449ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 21549ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 21649ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 21749ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 2187ca151c3SSai Pavan Boddu #define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ 21949ab747fSPaolo Bonzini 220e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 221e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 222e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2232801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 22449ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 22549ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 22649ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 22749ab747fSPaolo Bonzini 22849ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 22949ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 23049ab747fSPaolo Bonzini 23149ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 23249ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 23349ab747fSPaolo Bonzini 23449ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 23549ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 2367ca151c3SSai Pavan Boddu #define GEM_INT_AMBA_ERR 0x00000040 23749ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 23849ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 23949ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 24049ab747fSPaolo Bonzini 24149ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 24249ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 24349ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 24449ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 24549ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 24649ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 24749ab747fSPaolo Bonzini 24849ab747fSPaolo Bonzini /* Marvell PHY definitions */ 249dfc38879SBin Meng #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 25049ab747fSPaolo Bonzini 25149ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 25249ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 25349ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 25449ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 25549ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 25649ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 25749ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 25849ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 25949ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 26049ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 26149ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 26249ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 26349ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 26449ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 26549ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 26649ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 26749ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 26849ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 26949ab747fSPaolo Bonzini #define PHY_REG_EACD 22 27049ab747fSPaolo Bonzini #define PHY_REG_LED 24 27149ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 27249ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 27349ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 27449ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 27549ab747fSPaolo Bonzini 27649ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 27749ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 27849ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 2796623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 28049ab747fSPaolo Bonzini 28149ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 28249ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 28349ab747fSPaolo Bonzini 28449ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 28549ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 28649ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 28749ab747fSPaolo Bonzini 28849ab747fSPaolo Bonzini /***********************************************************************/ 28963af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 29063af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 29163af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 29263af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 29363af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 29463af1e0cSPeter Crosthwaite 29563af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 29649ab747fSPaolo Bonzini 29749ab747fSPaolo Bonzini /***********************************************************************/ 29849ab747fSPaolo Bonzini 29949ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 30049ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 30149ab747fSPaolo Bonzini 30249ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 30349ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 30449ab747fSPaolo Bonzini 30549ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 30649ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 30749ab747fSPaolo Bonzini 30863af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 30963af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 310a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 31163af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 31263af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 31363af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 31463af1e0cSPeter Crosthwaite 31549ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 31649ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 31749ab747fSPaolo Bonzini 318a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 319a5517666SAlistair Francis 320e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 32149ab747fSPaolo Bonzini { 322e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 323e48fdd9dSEdgar E. Iglesias 324c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 325e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 326e48fdd9dSEdgar E. Iglesias } 327e48fdd9dSEdgar E. Iglesias return ret; 32849ab747fSPaolo Bonzini } 32949ab747fSPaolo Bonzini 330f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 33149ab747fSPaolo Bonzini { 33249ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 33349ab747fSPaolo Bonzini } 33449ab747fSPaolo Bonzini 335f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 33649ab747fSPaolo Bonzini { 33749ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 33849ab747fSPaolo Bonzini } 33949ab747fSPaolo Bonzini 340f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 34149ab747fSPaolo Bonzini { 34249ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 34349ab747fSPaolo Bonzini } 34449ab747fSPaolo Bonzini 345f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 34649ab747fSPaolo Bonzini { 34749ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 34849ab747fSPaolo Bonzini } 34949ab747fSPaolo Bonzini 350f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 35149ab747fSPaolo Bonzini { 35249ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 35349ab747fSPaolo Bonzini } 35449ab747fSPaolo Bonzini 355f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 35649ab747fSPaolo Bonzini { 35767101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 35849ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 35949ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 36049ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 36149ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 36249ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 36349ab747fSPaolo Bonzini } 36449ab747fSPaolo Bonzini 365e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 36649ab747fSPaolo Bonzini { 367e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 368e48fdd9dSEdgar E. Iglesias 369c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 370e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 371e48fdd9dSEdgar E. Iglesias } 372e48fdd9dSEdgar E. Iglesias return ret; 373e48fdd9dSEdgar E. Iglesias } 374e48fdd9dSEdgar E. Iglesias 375e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 376e48fdd9dSEdgar E. Iglesias { 377e48fdd9dSEdgar E. Iglesias int ret = 2; 378e48fdd9dSEdgar E. Iglesias 379c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 380e48fdd9dSEdgar E. Iglesias ret += 2; 381e48fdd9dSEdgar E. Iglesias } 382c755c943SLuc Michel if (s->regs[R_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 383e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 384e48fdd9dSEdgar E. Iglesias ret += 2; 385e48fdd9dSEdgar E. Iglesias } 386e48fdd9dSEdgar E. Iglesias 387e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 388e48fdd9dSEdgar E. Iglesias return ret; 38949ab747fSPaolo Bonzini } 39049ab747fSPaolo Bonzini 391f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 39249ab747fSPaolo Bonzini { 39349ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 39449ab747fSPaolo Bonzini } 39549ab747fSPaolo Bonzini 396f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 39749ab747fSPaolo Bonzini { 39849ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 39949ab747fSPaolo Bonzini } 40049ab747fSPaolo Bonzini 401f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 40249ab747fSPaolo Bonzini { 40349ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 40449ab747fSPaolo Bonzini } 40549ab747fSPaolo Bonzini 406f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 40749ab747fSPaolo Bonzini { 40849ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 40949ab747fSPaolo Bonzini } 41049ab747fSPaolo Bonzini 41159ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 41259ab136aSRamon Fried { 41359ab136aSRamon Fried desc[1] = 0; 41459ab136aSRamon Fried } 41559ab136aSRamon Fried 416f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 41749ab747fSPaolo Bonzini { 41849ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 41949ab747fSPaolo Bonzini } 42049ab747fSPaolo Bonzini 421f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 42249ab747fSPaolo Bonzini { 42349ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 42449ab747fSPaolo Bonzini desc[1] |= len; 42549ab747fSPaolo Bonzini } 42649ab747fSPaolo Bonzini 427f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 42863af1e0cSPeter Crosthwaite { 42963af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 43063af1e0cSPeter Crosthwaite } 43163af1e0cSPeter Crosthwaite 432f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 43363af1e0cSPeter Crosthwaite { 43463af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 43563af1e0cSPeter Crosthwaite } 43663af1e0cSPeter Crosthwaite 437f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 43863af1e0cSPeter Crosthwaite { 43963af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 44063af1e0cSPeter Crosthwaite } 44163af1e0cSPeter Crosthwaite 442f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 44363af1e0cSPeter Crosthwaite { 44463af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 44563af1e0cSPeter Crosthwaite sar_idx); 446a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 44763af1e0cSPeter Crosthwaite } 44863af1e0cSPeter Crosthwaite 44949ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4506a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 45149ab747fSPaolo Bonzini 4527ca151c3SSai Pavan Boddu static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 4537ca151c3SSai Pavan Boddu { 4547ca151c3SSai Pavan Boddu uint32_t size; 455c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { 456c755c943SLuc Michel size = s->regs[R_JUMBO_MAX_LEN]; 4577ca151c3SSai Pavan Boddu if (size > s->jumbo_max_len) { 4587ca151c3SSai Pavan Boddu size = s->jumbo_max_len; 4597ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 4607ca151c3SSai Pavan Boddu " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 4617ca151c3SSai Pavan Boddu } 4627ca151c3SSai Pavan Boddu } else if (tx) { 4637ca151c3SSai Pavan Boddu size = 1518; 4647ca151c3SSai Pavan Boddu } else { 465c755c943SLuc Michel size = s->regs[R_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; 4667ca151c3SSai Pavan Boddu } 4677ca151c3SSai Pavan Boddu return size; 4687ca151c3SSai Pavan Boddu } 4697ca151c3SSai Pavan Boddu 47068dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 47168dbee3bSSai Pavan Boddu { 47268dbee3bSSai Pavan Boddu if (q == 0) { 473c755c943SLuc Michel s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 47468dbee3bSSai Pavan Boddu } else { 475c755c943SLuc Michel s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 476c755c943SLuc Michel ~(s->regs[R_INT_Q1_MASK + q - 1]); 47768dbee3bSSai Pavan Boddu } 47868dbee3bSSai Pavan Boddu } 47968dbee3bSSai Pavan Boddu 48049ab747fSPaolo Bonzini /* 48149ab747fSPaolo Bonzini * gem_init_register_masks: 48249ab747fSPaolo Bonzini * One time initialization. 48349ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 48449ab747fSPaolo Bonzini */ 485448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 48649ab747fSPaolo Bonzini { 4874c70e32fSSai Pavan Boddu unsigned int i; 48849ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 48949ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 490c755c943SLuc Michel s->regs_ro[R_NWCTRL] = 0xFFF80000; 491c755c943SLuc Michel s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 492c755c943SLuc Michel s->regs_ro[R_DMACFG] = 0x8E00F000; 493c755c943SLuc Michel s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 494c755c943SLuc Michel s->regs_ro[R_RXQBASE] = 0x00000003; 495c755c943SLuc Michel s->regs_ro[R_TXQBASE] = 0x00000003; 496c755c943SLuc Michel s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 497c755c943SLuc Michel s->regs_ro[R_ISR] = 0xFFFFFFFF; 498c755c943SLuc Michel s->regs_ro[R_IMR] = 0xFFFFFFFF; 499c755c943SLuc Michel s->regs_ro[R_MODID] = 0xFFFFFFFF; 5004c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 501c755c943SLuc Michel s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 502c755c943SLuc Michel s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 503c755c943SLuc Michel s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 504c755c943SLuc Michel s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 5054c70e32fSSai Pavan Boddu } 50649ab747fSPaolo Bonzini 50749ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 50849ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 509c755c943SLuc Michel s->regs_rtc[R_ISR] = 0xFFFFFFFF; 5104c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 511c755c943SLuc Michel s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 5124c70e32fSSai Pavan Boddu } 51349ab747fSPaolo Bonzini 51449ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 51549ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 516c755c943SLuc Michel s->regs_w1c[R_TXSTATUS] = 0x000001F7; 517c755c943SLuc Michel s->regs_w1c[R_RXSTATUS] = 0x0000000F; 51849ab747fSPaolo Bonzini 51949ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 52049ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 521c755c943SLuc Michel s->regs_wo[R_NWCTRL] = 0x00073E60; 522c755c943SLuc Michel s->regs_wo[R_IER] = 0x07FFFFFF; 523c755c943SLuc Michel s->regs_wo[R_IDR] = 0x07FFFFFF; 5244c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 525c755c943SLuc Michel s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 526c755c943SLuc Michel s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 5274c70e32fSSai Pavan Boddu } 52849ab747fSPaolo Bonzini } 52949ab747fSPaolo Bonzini 53049ab747fSPaolo Bonzini /* 53149ab747fSPaolo Bonzini * phy_update_link: 53249ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 53349ab747fSPaolo Bonzini */ 534448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 53549ab747fSPaolo Bonzini { 53649ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 53749ab747fSPaolo Bonzini 53849ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 53949ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 54049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 54149ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 54249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 54349ab747fSPaolo Bonzini } else { 54449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 54549ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 54649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 54749ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 54849ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 54949ab747fSPaolo Bonzini } 55049ab747fSPaolo Bonzini } 55149ab747fSPaolo Bonzini 552b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 55349ab747fSPaolo Bonzini { 554448f19e2SPeter Crosthwaite CadenceGEMState *s; 55567101725SAlistair Francis int i; 55649ab747fSPaolo Bonzini 55749ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 55849ab747fSPaolo Bonzini 55949ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 560c755c943SLuc Michel if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_RXENA)) { 5613ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 5623ae5725fSPeter Crosthwaite s->can_rx_state = 1; 5633ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 5643ae5725fSPeter Crosthwaite } 565b8c4b67eSPhilippe Mathieu-Daudé return false; 56649ab747fSPaolo Bonzini } 56749ab747fSPaolo Bonzini 56867101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 569dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 570dacc0566SAlistair Francis break; 571dacc0566SAlistair Francis } 572dacc0566SAlistair Francis }; 573dacc0566SAlistair Francis 574dacc0566SAlistair Francis if (i == s->num_priority_queues) { 5758202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 5768202aa53SPeter Crosthwaite s->can_rx_state = 2; 577dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 5788202aa53SPeter Crosthwaite } 579b8c4b67eSPhilippe Mathieu-Daudé return false; 5808202aa53SPeter Crosthwaite } 5818202aa53SPeter Crosthwaite 5823ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 5833ae5725fSPeter Crosthwaite s->can_rx_state = 0; 58467101725SAlistair Francis DB_PRINT("can receive\n"); 5853ae5725fSPeter Crosthwaite } 586b8c4b67eSPhilippe Mathieu-Daudé return true; 58749ab747fSPaolo Bonzini } 58849ab747fSPaolo Bonzini 58949ab747fSPaolo Bonzini /* 59049ab747fSPaolo Bonzini * gem_update_int_status: 59149ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 59249ab747fSPaolo Bonzini */ 593448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 59449ab747fSPaolo Bonzini { 59567101725SAlistair Francis int i; 59667101725SAlistair Francis 597c755c943SLuc Michel qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 598596b6f51SAlistair Francis 59986a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 600c755c943SLuc Michel qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 60149ab747fSPaolo Bonzini } 60249ab747fSPaolo Bonzini } 60349ab747fSPaolo Bonzini 60449ab747fSPaolo Bonzini /* 60549ab747fSPaolo Bonzini * gem_receive_updatestats: 60649ab747fSPaolo Bonzini * Increment receive statistics. 60749ab747fSPaolo Bonzini */ 608448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 60949ab747fSPaolo Bonzini unsigned bytes) 61049ab747fSPaolo Bonzini { 61149ab747fSPaolo Bonzini uint64_t octets; 61249ab747fSPaolo Bonzini 61349ab747fSPaolo Bonzini /* Total octets (bytes) received */ 614c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 615c755c943SLuc Michel s->regs[R_OCTRXHI]; 61649ab747fSPaolo Bonzini octets += bytes; 617c755c943SLuc Michel s->regs[R_OCTRXLO] = octets >> 32; 618c755c943SLuc Michel s->regs[R_OCTRXHI] = octets; 61949ab747fSPaolo Bonzini 62049ab747fSPaolo Bonzini /* Error-free Frames received */ 621c755c943SLuc Michel s->regs[R_RXCNT]++; 62249ab747fSPaolo Bonzini 62349ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 62449ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 625c755c943SLuc Michel s->regs[R_RXBROADCNT]++; 62649ab747fSPaolo Bonzini } 62749ab747fSPaolo Bonzini 62849ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 62949ab747fSPaolo Bonzini if (packet[0] == 0x01) { 630c755c943SLuc Michel s->regs[R_RXMULTICNT]++; 63149ab747fSPaolo Bonzini } 63249ab747fSPaolo Bonzini 63349ab747fSPaolo Bonzini if (bytes <= 64) { 634c755c943SLuc Michel s->regs[R_RX64CNT]++; 63549ab747fSPaolo Bonzini } else if (bytes <= 127) { 636c755c943SLuc Michel s->regs[R_RX65CNT]++; 63749ab747fSPaolo Bonzini } else if (bytes <= 255) { 638c755c943SLuc Michel s->regs[R_RX128CNT]++; 63949ab747fSPaolo Bonzini } else if (bytes <= 511) { 640c755c943SLuc Michel s->regs[R_RX256CNT]++; 64149ab747fSPaolo Bonzini } else if (bytes <= 1023) { 642c755c943SLuc Michel s->regs[R_RX512CNT]++; 64349ab747fSPaolo Bonzini } else if (bytes <= 1518) { 644c755c943SLuc Michel s->regs[R_RX1024CNT]++; 64549ab747fSPaolo Bonzini } else { 646c755c943SLuc Michel s->regs[R_RX1519CNT]++; 64749ab747fSPaolo Bonzini } 64849ab747fSPaolo Bonzini } 64949ab747fSPaolo Bonzini 65049ab747fSPaolo Bonzini /* 65149ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 65249ab747fSPaolo Bonzini */ 65349ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 65449ab747fSPaolo Bonzini { 65549ab747fSPaolo Bonzini unsigned byte; 65649ab747fSPaolo Bonzini 65749ab747fSPaolo Bonzini byte = mac[bit / 8]; 65849ab747fSPaolo Bonzini byte >>= (bit & 0x7); 65949ab747fSPaolo Bonzini byte &= 1; 66049ab747fSPaolo Bonzini 66149ab747fSPaolo Bonzini return byte; 66249ab747fSPaolo Bonzini } 66349ab747fSPaolo Bonzini 66449ab747fSPaolo Bonzini /* 66549ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 66649ab747fSPaolo Bonzini */ 66749ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 66849ab747fSPaolo Bonzini { 66949ab747fSPaolo Bonzini int index_bit, mac_bit; 67049ab747fSPaolo Bonzini unsigned hash_index; 67149ab747fSPaolo Bonzini 67249ab747fSPaolo Bonzini hash_index = 0; 67349ab747fSPaolo Bonzini mac_bit = 5; 67449ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 67549ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 67649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 67749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 67849ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 67949ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 68049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 68149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 68249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 68349ab747fSPaolo Bonzini mac_bit--; 68449ab747fSPaolo Bonzini } 68549ab747fSPaolo Bonzini 68649ab747fSPaolo Bonzini return hash_index; 68749ab747fSPaolo Bonzini } 68849ab747fSPaolo Bonzini 68949ab747fSPaolo Bonzini /* 69049ab747fSPaolo Bonzini * gem_mac_address_filter: 69149ab747fSPaolo Bonzini * Accept or reject this destination address? 69249ab747fSPaolo Bonzini * Returns: 69349ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 69463af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 69563af1e0cSPeter Crosthwaite * others for various other modes of accept: 69663af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 69763af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 69849ab747fSPaolo Bonzini */ 699448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 70049ab747fSPaolo Bonzini { 70149ab747fSPaolo Bonzini uint8_t *gem_spaddr; 702fbc14a09STong Ho int i, is_mc; 70349ab747fSPaolo Bonzini 70449ab747fSPaolo Bonzini /* Promiscuous mode? */ 705c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_PROMISC) { 70663af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 70749ab747fSPaolo Bonzini } 70849ab747fSPaolo Bonzini 70949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 71049ab747fSPaolo Bonzini /* Reject broadcast packets? */ 711c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_BCAST_REJ) { 71249ab747fSPaolo Bonzini return GEM_RX_REJECT; 71349ab747fSPaolo Bonzini } 71463af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 71549ab747fSPaolo Bonzini } 71649ab747fSPaolo Bonzini 71749ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 718fbc14a09STong Ho is_mc = is_multicast_ether_addr(packet); 719c755c943SLuc Michel if ((is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 720c755c943SLuc Michel (!is_mc && (s->regs[R_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 721fbc14a09STong Ho uint64_t buckets; 72249ab747fSPaolo Bonzini unsigned hash_index; 72349ab747fSPaolo Bonzini 72449ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 725c755c943SLuc Michel buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 726fbc14a09STong Ho if ((buckets >> hash_index) & 1) { 727fbc14a09STong Ho return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 728fbc14a09STong Ho : GEM_RX_UNICAST_HASH_ACCEPT; 72949ab747fSPaolo Bonzini } 73049ab747fSPaolo Bonzini } 73149ab747fSPaolo Bonzini 73249ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 733c755c943SLuc Michel gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 73463af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 73564eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 73663af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 73749ab747fSPaolo Bonzini } 73849ab747fSPaolo Bonzini } 73949ab747fSPaolo Bonzini 74049ab747fSPaolo Bonzini /* No address match; reject the packet */ 74149ab747fSPaolo Bonzini return GEM_RX_REJECT; 74249ab747fSPaolo Bonzini } 74349ab747fSPaolo Bonzini 744e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 745e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 746e8e49943SAlistair Francis unsigned rxbufsize) 747e8e49943SAlistair Francis { 748e8e49943SAlistair Francis uint32_t reg; 749e8e49943SAlistair Francis bool matched, mismatched; 750e8e49943SAlistair Francis int i, j; 751e8e49943SAlistair Francis 752e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 753c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 754e8e49943SAlistair Francis matched = false; 755e8e49943SAlistair Francis mismatched = false; 756e8e49943SAlistair Francis 757e8e49943SAlistair Francis /* Screening is based on UDP Port */ 758e8e49943SAlistair Francis if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 759e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 760e8e49943SAlistair Francis if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 761e8e49943SAlistair Francis GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 762e8e49943SAlistair Francis matched = true; 763e8e49943SAlistair Francis } else { 764e8e49943SAlistair Francis mismatched = true; 765e8e49943SAlistair Francis } 766e8e49943SAlistair Francis } 767e8e49943SAlistair Francis 768e8e49943SAlistair Francis /* Screening is based on DS/TC */ 769e8e49943SAlistair Francis if (reg & GEM_ST1R_DSTC_ENABLE) { 770e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 771e8e49943SAlistair Francis if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 772e8e49943SAlistair Francis GEM_ST1R_DSTC_MATCH_WIDTH)) { 773e8e49943SAlistair Francis matched = true; 774e8e49943SAlistair Francis } else { 775e8e49943SAlistair Francis mismatched = true; 776e8e49943SAlistair Francis } 777e8e49943SAlistair Francis } 778e8e49943SAlistair Francis 779e8e49943SAlistair Francis if (matched && !mismatched) { 780e8e49943SAlistair Francis return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 781e8e49943SAlistair Francis } 782e8e49943SAlistair Francis } 783e8e49943SAlistair Francis 784e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 785c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 786e8e49943SAlistair Francis matched = false; 787e8e49943SAlistair Francis mismatched = false; 788e8e49943SAlistair Francis 789e8e49943SAlistair Francis if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 790e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 791e8e49943SAlistair Francis int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 792e8e49943SAlistair Francis GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 793e8e49943SAlistair Francis 794e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 795e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 796e8e49943SAlistair Francis "register index: %d\n", et_idx); 797e8e49943SAlistair Francis } 798c755c943SLuc Michel if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 799e8e49943SAlistair Francis et_idx]) { 800e8e49943SAlistair Francis matched = true; 801e8e49943SAlistair Francis } else { 802e8e49943SAlistair Francis mismatched = true; 803e8e49943SAlistair Francis } 804e8e49943SAlistair Francis } 805e8e49943SAlistair Francis 806e8e49943SAlistair Francis /* Compare A, B, C */ 807e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 808e8e49943SAlistair Francis uint32_t cr0, cr1, mask; 809e8e49943SAlistair Francis uint16_t rx_cmp; 810e8e49943SAlistair Francis int offset; 811e8e49943SAlistair Francis int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 812e8e49943SAlistair Francis GEM_ST2R_COMPARE_WIDTH); 813e8e49943SAlistair Francis 814e8e49943SAlistair Francis if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 815e8e49943SAlistair Francis continue; 816e8e49943SAlistair Francis } 817e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 818e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 819e8e49943SAlistair Francis "register index: %d\n", cr_idx); 820e8e49943SAlistair Francis } 821e8e49943SAlistair Francis 822c755c943SLuc Michel cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 823c755c943SLuc Michel cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 824e8e49943SAlistair Francis offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 825e8e49943SAlistair Francis GEM_T2CW1_OFFSET_VALUE_WIDTH); 826e8e49943SAlistair Francis 827e8e49943SAlistair Francis switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 828e8e49943SAlistair Francis GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 829e8e49943SAlistair Francis case 3: /* Skip UDP header */ 830e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 831e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 832e8e49943SAlistair Francis offset += 8; 833e8e49943SAlistair Francis /* Fallthrough */ 834e8e49943SAlistair Francis case 2: /* skip the IP header */ 835e8e49943SAlistair Francis offset += 20; 836e8e49943SAlistair Francis /* Fallthrough */ 837e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 838e8e49943SAlistair Francis offset += 14; 839e8e49943SAlistair Francis break; 840e8e49943SAlistair Francis case 0: 841e8e49943SAlistair Francis /* Offset from start of frame */ 842e8e49943SAlistair Francis break; 843e8e49943SAlistair Francis } 844e8e49943SAlistair Francis 845e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 846e8e49943SAlistair Francis mask = extract32(cr0, 0, 16); 847e8e49943SAlistair Francis 848e8e49943SAlistair Francis if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 849e8e49943SAlistair Francis matched = true; 850e8e49943SAlistair Francis } else { 851e8e49943SAlistair Francis mismatched = true; 852e8e49943SAlistair Francis } 853e8e49943SAlistair Francis } 854e8e49943SAlistair Francis 855e8e49943SAlistair Francis if (matched && !mismatched) { 856e8e49943SAlistair Francis return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 857e8e49943SAlistair Francis } 858e8e49943SAlistair Francis } 859e8e49943SAlistair Francis 860e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 861e8e49943SAlistair Francis return 0; 862e8e49943SAlistair Francis } 863e8e49943SAlistair Francis 86496ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 86596ea126aSSai Pavan Boddu { 86696ea126aSSai Pavan Boddu uint32_t base_addr = 0; 86796ea126aSSai Pavan Boddu 86896ea126aSSai Pavan Boddu switch (q) { 86996ea126aSSai Pavan Boddu case 0: 870c755c943SLuc Michel base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 87196ea126aSSai Pavan Boddu break; 87296ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 873c755c943SLuc Michel base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 874c755c943SLuc Michel R_RECEIVE_Q1_PTR) + q - 1]; 87596ea126aSSai Pavan Boddu break; 87696ea126aSSai Pavan Boddu default: 87796ea126aSSai Pavan Boddu g_assert_not_reached(); 87896ea126aSSai Pavan Boddu }; 87996ea126aSSai Pavan Boddu 88096ea126aSSai Pavan Boddu return base_addr; 88196ea126aSSai Pavan Boddu } 88296ea126aSSai Pavan Boddu 88396ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 88496ea126aSSai Pavan Boddu { 88596ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 88696ea126aSSai Pavan Boddu } 88796ea126aSSai Pavan Boddu 88896ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 88996ea126aSSai Pavan Boddu { 89096ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 89196ea126aSSai Pavan Boddu } 89296ea126aSSai Pavan Boddu 893357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 894357aa013SEdgar E. Iglesias { 895357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 896357aa013SEdgar E. Iglesias 897c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 898c755c943SLuc Michel desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 899357aa013SEdgar E. Iglesias } 900357aa013SEdgar E. Iglesias desc_addr <<= 32; 901357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 902357aa013SEdgar E. Iglesias return desc_addr; 903357aa013SEdgar E. Iglesias } 904357aa013SEdgar E. Iglesias 905357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 906357aa013SEdgar E. Iglesias { 907357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 908357aa013SEdgar E. Iglesias } 909357aa013SEdgar E. Iglesias 910357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 911357aa013SEdgar E. Iglesias { 912357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 913357aa013SEdgar E. Iglesias } 914357aa013SEdgar E. Iglesias 91567101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 91606c2fe95SPeter Crosthwaite { 917357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 918357aa013SEdgar E. Iglesias 919357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 920357aa013SEdgar E. Iglesias 92106c2fe95SPeter Crosthwaite /* read current descriptor */ 922357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 923b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 924e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 92506c2fe95SPeter Crosthwaite 92606c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 92767101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 928357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 929c755c943SLuc Michel s->regs[R_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 93068dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXUSED); 93106c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 93206c2fe95SPeter Crosthwaite gem_update_int_status(s); 93306c2fe95SPeter Crosthwaite } 93406c2fe95SPeter Crosthwaite } 93506c2fe95SPeter Crosthwaite 93649ab747fSPaolo Bonzini /* 93749ab747fSPaolo Bonzini * gem_receive: 93849ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 93949ab747fSPaolo Bonzini */ 94049ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 94149ab747fSPaolo Bonzini { 94224d62fd5SSai Pavan Boddu CadenceGEMState *s = qemu_get_nic_opaque(nc); 94349ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 94449ab747fSPaolo Bonzini unsigned rxbuf_offset; 94549ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 9463b2c97f9SEdgar E. Iglesias bool first_desc = true; 94763af1e0cSPeter Crosthwaite int maf; 9482bf57f73SAlistair Francis int q = 0; 94949ab747fSPaolo Bonzini 95049ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 95163af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 95263af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 9532431f4f1SMichael Tokarev return size; /* no, drop silently b/c it's not an error */ 95449ab747fSPaolo Bonzini } 95549ab747fSPaolo Bonzini 95649ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 957c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_LERR_DISC) { 95849ab747fSPaolo Bonzini unsigned type_len; 95949ab747fSPaolo Bonzini 96049ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 96149ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 96249ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 96349ab747fSPaolo Bonzini if (type_len < 0x600) { 96449ab747fSPaolo Bonzini if (size < type_len) { 96549ab747fSPaolo Bonzini /* discard */ 96649ab747fSPaolo Bonzini return -1; 96749ab747fSPaolo Bonzini } 96849ab747fSPaolo Bonzini } 96949ab747fSPaolo Bonzini } 97049ab747fSPaolo Bonzini 97149ab747fSPaolo Bonzini /* 97249ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 97349ab747fSPaolo Bonzini */ 974c755c943SLuc Michel rxbuf_offset = (s->regs[R_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 97549ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 97649ab747fSPaolo Bonzini 97749ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 97849ab747fSPaolo Bonzini * buffers needed to hold this packet. 97949ab747fSPaolo Bonzini */ 980c755c943SLuc Michel rxbufsize = ((s->regs[R_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 98149ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 98249ab747fSPaolo Bonzini bytes_to_copy = size; 98349ab747fSPaolo Bonzini 984f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 985f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 986f265ae8cSAlistair Francis */ 987f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 988f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 989f265ae8cSAlistair Francis } 990f265ae8cSAlistair Francis 991191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 992191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 993191946c5SPeter Crosthwaite * not FCS stripping 994191946c5SPeter Crosthwaite */ 995191946c5SPeter Crosthwaite if (size < 60) { 996191946c5SPeter Crosthwaite size = 60; 997191946c5SPeter Crosthwaite } 998191946c5SPeter Crosthwaite 99949ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 1000c755c943SLuc Michel if (s->regs[R_NWCFG] & GEM_NWCFG_STRIP_FCS) { 100149ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 100249ab747fSPaolo Bonzini } else { 100349ab747fSPaolo Bonzini unsigned crc_val; 100449ab747fSPaolo Bonzini 100524d62fd5SSai Pavan Boddu if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 100624d62fd5SSai Pavan Boddu size = MAX_FRAME_SIZE - sizeof(crc_val); 1007244381ecSPrasad J Pandit } 1008244381ecSPrasad J Pandit bytes_to_copy = size; 100949ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 10103048ed6aSPeter Crosthwaite * We must try and calculate one. 101149ab747fSPaolo Bonzini */ 101249ab747fSPaolo Bonzini 101324d62fd5SSai Pavan Boddu memcpy(s->rx_packet, buf, size); 101424d62fd5SSai Pavan Boddu memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 101524d62fd5SSai Pavan Boddu rxbuf_ptr = s->rx_packet; 101624d62fd5SSai Pavan Boddu crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 101724d62fd5SSai Pavan Boddu memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 101849ab747fSPaolo Bonzini 101949ab747fSPaolo Bonzini bytes_to_copy += 4; 102049ab747fSPaolo Bonzini size += 4; 102149ab747fSPaolo Bonzini } 102249ab747fSPaolo Bonzini 10236fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 102449ab747fSPaolo Bonzini 1025b12227afSStefan Weil /* Find which queue we are targeting */ 1026e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1027e8e49943SAlistair Francis 10287ca151c3SSai Pavan Boddu if (size > gem_get_max_buf_len(s, false)) { 10297ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 10307ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 10317ca151c3SSai Pavan Boddu return -1; 10327ca151c3SSai Pavan Boddu } 10337ca151c3SSai Pavan Boddu 10347cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1035357aa013SEdgar E. Iglesias hwaddr desc_addr; 1036357aa013SEdgar E. Iglesias 103706c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 103806c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 103949ab747fSPaolo Bonzini return -1; 104049ab747fSPaolo Bonzini } 104149ab747fSPaolo Bonzini 10426fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1043dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1044dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 104549ab747fSPaolo Bonzini 104649ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 104784aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 10482bf57f73SAlistair Francis rxbuf_offset, 104984aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1050e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 105149ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 105230570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 10533b2c97f9SEdgar E. Iglesias 105459ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 105559ab136aSRamon Fried 10563b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 10573b2c97f9SEdgar E. Iglesias if (first_desc) { 10582bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 10593b2c97f9SEdgar E. Iglesias first_desc = false; 10603b2c97f9SEdgar E. Iglesias } 10613b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 10622bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 10632bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 10643b2c97f9SEdgar E. Iglesias } 10652bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 106663af1e0cSPeter Crosthwaite 106763af1e0cSPeter Crosthwaite switch (maf) { 106863af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 106963af1e0cSPeter Crosthwaite break; 107063af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 10712bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 107263af1e0cSPeter Crosthwaite break; 107363af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 10742bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 107563af1e0cSPeter Crosthwaite break; 107663af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 10772bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 107863af1e0cSPeter Crosthwaite break; 107963af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 108063af1e0cSPeter Crosthwaite abort(); 108163af1e0cSPeter Crosthwaite default: /* SAR */ 10822bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 108363af1e0cSPeter Crosthwaite } 108463af1e0cSPeter Crosthwaite 10853b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1086357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1087b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1088b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1089e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 10903b2c97f9SEdgar E. Iglesias 109149ab747fSPaolo Bonzini /* Next descriptor */ 10922bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 109349ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 109496ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 109549ab747fSPaolo Bonzini } else { 109649ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1097e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 109849ab747fSPaolo Bonzini } 109967101725SAlistair Francis 110067101725SAlistair Francis gem_get_rx_desc(s, q); 11017cfd65e4SPeter Crosthwaite } 110249ab747fSPaolo Bonzini 110349ab747fSPaolo Bonzini /* Count it */ 110449ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 110549ab747fSPaolo Bonzini 1106c755c943SLuc Michel s->regs[R_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 110768dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXCMPL); 110849ab747fSPaolo Bonzini 110949ab747fSPaolo Bonzini /* Handle interrupt consequences */ 111049ab747fSPaolo Bonzini gem_update_int_status(s); 111149ab747fSPaolo Bonzini 111249ab747fSPaolo Bonzini return size; 111349ab747fSPaolo Bonzini } 111449ab747fSPaolo Bonzini 111549ab747fSPaolo Bonzini /* 111649ab747fSPaolo Bonzini * gem_transmit_updatestats: 111749ab747fSPaolo Bonzini * Increment transmit statistics. 111849ab747fSPaolo Bonzini */ 1119448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 112049ab747fSPaolo Bonzini unsigned bytes) 112149ab747fSPaolo Bonzini { 112249ab747fSPaolo Bonzini uint64_t octets; 112349ab747fSPaolo Bonzini 112449ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 1125c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1126c755c943SLuc Michel s->regs[R_OCTTXHI]; 112749ab747fSPaolo Bonzini octets += bytes; 1128c755c943SLuc Michel s->regs[R_OCTTXLO] = octets >> 32; 1129c755c943SLuc Michel s->regs[R_OCTTXHI] = octets; 113049ab747fSPaolo Bonzini 113149ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 1132c755c943SLuc Michel s->regs[R_TXCNT]++; 113349ab747fSPaolo Bonzini 113449ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 113549ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 1136c755c943SLuc Michel s->regs[R_TXBCNT]++; 113749ab747fSPaolo Bonzini } 113849ab747fSPaolo Bonzini 113949ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 114049ab747fSPaolo Bonzini if (packet[0] == 0x01) { 1141c755c943SLuc Michel s->regs[R_TXMCNT]++; 114249ab747fSPaolo Bonzini } 114349ab747fSPaolo Bonzini 114449ab747fSPaolo Bonzini if (bytes <= 64) { 1145c755c943SLuc Michel s->regs[R_TX64CNT]++; 114649ab747fSPaolo Bonzini } else if (bytes <= 127) { 1147c755c943SLuc Michel s->regs[R_TX65CNT]++; 114849ab747fSPaolo Bonzini } else if (bytes <= 255) { 1149c755c943SLuc Michel s->regs[R_TX128CNT]++; 115049ab747fSPaolo Bonzini } else if (bytes <= 511) { 1151c755c943SLuc Michel s->regs[R_TX256CNT]++; 115249ab747fSPaolo Bonzini } else if (bytes <= 1023) { 1153c755c943SLuc Michel s->regs[R_TX512CNT]++; 115449ab747fSPaolo Bonzini } else if (bytes <= 1518) { 1155c755c943SLuc Michel s->regs[R_TX1024CNT]++; 115649ab747fSPaolo Bonzini } else { 1157c755c943SLuc Michel s->regs[R_TX1519CNT]++; 115849ab747fSPaolo Bonzini } 115949ab747fSPaolo Bonzini } 116049ab747fSPaolo Bonzini 116149ab747fSPaolo Bonzini /* 116249ab747fSPaolo Bonzini * gem_transmit: 116349ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 116449ab747fSPaolo Bonzini */ 1165448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 116649ab747fSPaolo Bonzini { 11678568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 116849ab747fSPaolo Bonzini hwaddr packet_desc_addr; 116949ab747fSPaolo Bonzini uint8_t *p; 117049ab747fSPaolo Bonzini unsigned total_bytes; 11712bf57f73SAlistair Francis int q = 0; 117249ab747fSPaolo Bonzini 117349ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1174c755c943SLuc Michel if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { 117549ab747fSPaolo Bonzini return; 117649ab747fSPaolo Bonzini } 117749ab747fSPaolo Bonzini 117849ab747fSPaolo Bonzini DB_PRINT("\n"); 117949ab747fSPaolo Bonzini 11803048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 118149ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 118249ab747fSPaolo Bonzini * one contiguous buffer first. 118349ab747fSPaolo Bonzini */ 118424d62fd5SSai Pavan Boddu p = s->tx_packet; 118549ab747fSPaolo Bonzini total_bytes = 0; 118649ab747fSPaolo Bonzini 118767101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 118849ab747fSPaolo Bonzini /* read current descriptor */ 1189357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1190fa15286aSPeter Crosthwaite 1191fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 119284aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1193b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1194e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 119549ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 119649ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 119749ab747fSPaolo Bonzini 119849ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1199c755c943SLuc Michel if (!(s->regs[R_NWCTRL] & GEM_NWCTRL_TXENA)) { 120049ab747fSPaolo Bonzini return; 120149ab747fSPaolo Bonzini } 120267101725SAlistair Francis print_gem_tx_desc(desc, q); 120349ab747fSPaolo Bonzini 120449ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 120549ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 120649ab747fSPaolo Bonzini */ 1207e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 120849ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 12096fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 12106fe7661dSSai Pavan Boddu packet_desc_addr); 121149ab747fSPaolo Bonzini break; 121249ab747fSPaolo Bonzini } 121349ab747fSPaolo Bonzini 12147ca151c3SSai Pavan Boddu if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 121524d62fd5SSai Pavan Boddu (p - s->tx_packet)) { 12167ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 12177ca151c3SSai Pavan Boddu HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1218dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 12197ca151c3SSai Pavan Boddu gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 12207ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1221d7f05365SMichael S. Tsirkin break; 1222d7f05365SMichael S. Tsirkin } 1223d7f05365SMichael S. Tsirkin 122477524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 122577524d11SAlistair Francis * contig buffer. 122649ab747fSPaolo Bonzini */ 122784aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 122884aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 122984aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 123049ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 123149ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 123249ab747fSPaolo Bonzini 123349ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 123449ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 12358568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1236357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 12376ab57a6bSPeter Crosthwaite 123849ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 123949ab747fSPaolo Bonzini * the processor. 124049ab747fSPaolo Bonzini */ 1241357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1242b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12436ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12446ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1245357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1246b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12476ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12483048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 124949ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 125096ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 125149ab747fSPaolo Bonzini } else { 1252e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1253e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 125449ab747fSPaolo Bonzini } 12552bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 125649ab747fSPaolo Bonzini 1257c755c943SLuc Michel s->regs[R_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 125868dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_TXCMPL); 125967101725SAlistair Francis 126049ab747fSPaolo Bonzini /* Handle interrupt consequences */ 126149ab747fSPaolo Bonzini gem_update_int_status(s); 126249ab747fSPaolo Bonzini 126349ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 1264c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1265f5746335SBin Meng net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 126649ab747fSPaolo Bonzini } 126749ab747fSPaolo Bonzini 126849ab747fSPaolo Bonzini /* Update MAC statistics */ 126924d62fd5SSai Pavan Boddu gem_transmit_updatestats(s, s->tx_packet, total_bytes); 127049ab747fSPaolo Bonzini 127149ab747fSPaolo Bonzini /* Send the packet somewhere */ 1272c755c943SLuc Michel if (s->phy_loop || (s->regs[R_NWCTRL] & 127377524d11SAlistair Francis GEM_NWCTRL_LOCALLOOP)) { 1274e73adfbeSAlexander Bulekov qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 127577524d11SAlistair Francis total_bytes); 127649ab747fSPaolo Bonzini } else { 127724d62fd5SSai Pavan Boddu qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 127849ab747fSPaolo Bonzini total_bytes); 127949ab747fSPaolo Bonzini } 128049ab747fSPaolo Bonzini 128149ab747fSPaolo Bonzini /* Prepare for next packet */ 128224d62fd5SSai Pavan Boddu p = s->tx_packet; 128349ab747fSPaolo Bonzini total_bytes = 0; 128449ab747fSPaolo Bonzini } 128549ab747fSPaolo Bonzini 128649ab747fSPaolo Bonzini /* read next descriptor */ 128749ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1288c755c943SLuc Michel if (s->regs[R_DMACFG] & GEM_DMACFG_ADDR_64B) { 1289c755c943SLuc Michel packet_desc_addr = s->regs[R_TBQPH]; 1290f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1291f1e7cb13SRamon Fried } else { 1292f1e7cb13SRamon Fried packet_desc_addr = 0; 1293f1e7cb13SRamon Fried } 129496ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 129549ab747fSPaolo Bonzini } else { 1296e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 129749ab747fSPaolo Bonzini } 1298fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 129984aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1300b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1301e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 130249ab747fSPaolo Bonzini } 130349ab747fSPaolo Bonzini 130449ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 1305c755c943SLuc Michel s->regs[R_TXSTATUS] |= GEM_TXSTATUS_USED; 130668dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 130768dbee3bSSai Pavan Boddu if (q == 0) { 130868dbee3bSSai Pavan Boddu gem_set_isr(s, 0, GEM_INT_TXUSED); 130968dbee3bSSai Pavan Boddu } 131049ab747fSPaolo Bonzini gem_update_int_status(s); 131149ab747fSPaolo Bonzini } 131249ab747fSPaolo Bonzini } 131367101725SAlistair Francis } 131449ab747fSPaolo Bonzini 1315448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 131649ab747fSPaolo Bonzini { 131749ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 131849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 131949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 132049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 132149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 132249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 132349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 132449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 132549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 132649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 132749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 132849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 132949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 133049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 13317777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 133249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 133349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 133449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 133549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 133649ab747fSPaolo Bonzini 133749ab747fSPaolo Bonzini phy_update_link(s); 133849ab747fSPaolo Bonzini } 133949ab747fSPaolo Bonzini 134049ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 134149ab747fSPaolo Bonzini { 134264eb9301SPeter Crosthwaite int i; 1343448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1344afb4c51fSSebastian Huber const uint8_t *a; 1345726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 134649ab747fSPaolo Bonzini 134749ab747fSPaolo Bonzini DB_PRINT("\n"); 134849ab747fSPaolo Bonzini 134949ab747fSPaolo Bonzini /* Set post reset register values */ 135049ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 1351c755c943SLuc Michel s->regs[R_NWCFG] = 0x00080000; 1352c755c943SLuc Michel s->regs[R_NWSTATUS] = 0x00000006; 1353c755c943SLuc Michel s->regs[R_DMACFG] = 0x00020784; 1354c755c943SLuc Michel s->regs[R_IMR] = 0x07ffffff; 1355c755c943SLuc Michel s->regs[R_TXPAUSE] = 0x0000ffff; 1356c755c943SLuc Michel s->regs[R_TXPARTIALSF] = 0x000003ff; 1357c755c943SLuc Michel s->regs[R_RXPARTIALSF] = 0x000003ff; 1358c755c943SLuc Michel s->regs[R_MODID] = s->revision; 1359c755c943SLuc Michel s->regs[R_DESCONF] = 0x02D00111; 1360c755c943SLuc Michel s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1361c755c943SLuc Michel s->regs[R_DESCONF5] = 0x002f2045; 1362c755c943SLuc Michel s->regs[R_DESCONF6] = GEM_DESCONF6_64B_MASK; 1363c755c943SLuc Michel s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1364c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1365726a2a95SEdgar E. Iglesias 1366726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1367726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1368c755c943SLuc Michel s->regs[R_DESCONF6] |= queues_mask; 1369726a2a95SEdgar E. Iglesias } 137049ab747fSPaolo Bonzini 1371afb4c51fSSebastian Huber /* Set MAC address */ 1372afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1373c755c943SLuc Michel s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1374c755c943SLuc Michel s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1375afb4c51fSSebastian Huber 137664eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 137764eb9301SPeter Crosthwaite s->sar_active[i] = false; 137864eb9301SPeter Crosthwaite } 137964eb9301SPeter Crosthwaite 138049ab747fSPaolo Bonzini gem_phy_reset(s); 138149ab747fSPaolo Bonzini 138249ab747fSPaolo Bonzini gem_update_int_status(s); 138349ab747fSPaolo Bonzini } 138449ab747fSPaolo Bonzini 1385448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 138649ab747fSPaolo Bonzini { 138749ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 138849ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 138949ab747fSPaolo Bonzini } 139049ab747fSPaolo Bonzini 1391448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 139249ab747fSPaolo Bonzini { 139349ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 139449ab747fSPaolo Bonzini 139549ab747fSPaolo Bonzini switch (reg_num) { 139649ab747fSPaolo Bonzini case PHY_REG_CONTROL: 139749ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 139849ab747fSPaolo Bonzini /* Phy reset */ 139949ab747fSPaolo Bonzini gem_phy_reset(s); 140049ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 140149ab747fSPaolo Bonzini s->phy_loop = 0; 140249ab747fSPaolo Bonzini } 140349ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 140449ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 14056623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 140649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 140749ab747fSPaolo Bonzini } 140849ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 140949ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 141049ab747fSPaolo Bonzini s->phy_loop = 1; 141149ab747fSPaolo Bonzini } else { 141249ab747fSPaolo Bonzini s->phy_loop = 0; 141349ab747fSPaolo Bonzini } 141449ab747fSPaolo Bonzini break; 141549ab747fSPaolo Bonzini } 141649ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 141749ab747fSPaolo Bonzini } 141849ab747fSPaolo Bonzini 141949ab747fSPaolo Bonzini /* 142049ab747fSPaolo Bonzini * gem_read32: 142149ab747fSPaolo Bonzini * Read a GEM register. 142249ab747fSPaolo Bonzini */ 142349ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 142449ab747fSPaolo Bonzini { 1425448f19e2SPeter Crosthwaite CadenceGEMState *s; 142649ab747fSPaolo Bonzini uint32_t retval; 14273d558330SMarkus Armbruster s = opaque; 142849ab747fSPaolo Bonzini 142949ab747fSPaolo Bonzini offset >>= 2; 143049ab747fSPaolo Bonzini retval = s->regs[offset]; 143149ab747fSPaolo Bonzini 143249ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 143349ab747fSPaolo Bonzini 143449ab747fSPaolo Bonzini switch (offset) { 1435c755c943SLuc Michel case R_ISR: 143667101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1437596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 143849ab747fSPaolo Bonzini break; 1439c755c943SLuc Michel case R_PHYMNTNC: 144049ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 144149ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 144249ab747fSPaolo Bonzini 144349ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1444dfc38879SBin Meng if (phy_addr == s->phy_addr) { 144549ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 144649ab747fSPaolo Bonzini retval &= 0xFFFF0000; 144749ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 144849ab747fSPaolo Bonzini } else { 144949ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 145049ab747fSPaolo Bonzini } 145149ab747fSPaolo Bonzini } 145249ab747fSPaolo Bonzini break; 145349ab747fSPaolo Bonzini } 145449ab747fSPaolo Bonzini 145549ab747fSPaolo Bonzini /* Squash read to clear bits */ 145649ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 145749ab747fSPaolo Bonzini 145849ab747fSPaolo Bonzini /* Do not provide write only bits */ 145949ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 146049ab747fSPaolo Bonzini 146149ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 146267101725SAlistair Francis gem_update_int_status(s); 146349ab747fSPaolo Bonzini return retval; 146449ab747fSPaolo Bonzini } 146549ab747fSPaolo Bonzini 146649ab747fSPaolo Bonzini /* 146749ab747fSPaolo Bonzini * gem_write32: 146849ab747fSPaolo Bonzini * Write a GEM register. 146949ab747fSPaolo Bonzini */ 147049ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 147149ab747fSPaolo Bonzini unsigned size) 147249ab747fSPaolo Bonzini { 1473448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 147449ab747fSPaolo Bonzini uint32_t readonly; 147567101725SAlistair Francis int i; 147649ab747fSPaolo Bonzini 147749ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 147849ab747fSPaolo Bonzini offset >>= 2; 147949ab747fSPaolo Bonzini 148049ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 148149ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1482e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1483e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 148449ab747fSPaolo Bonzini 148549ab747fSPaolo Bonzini /* Copy register write to backing store */ 1486e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1487e2314fdaSPeter Crosthwaite 1488e2314fdaSPeter Crosthwaite /* do w1c */ 1489e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 149049ab747fSPaolo Bonzini 149149ab747fSPaolo Bonzini /* Handle register write side effects */ 149249ab747fSPaolo Bonzini switch (offset) { 1493c755c943SLuc Michel case R_NWCTRL: 149406c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 149567101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 149667101725SAlistair Francis gem_get_rx_desc(s, i); 149767101725SAlistair Francis } 149806c2fe95SPeter Crosthwaite } 149949ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 150049ab747fSPaolo Bonzini gem_transmit(s); 150149ab747fSPaolo Bonzini } 150249ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 150349ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 150467101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 150596ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 150667101725SAlistair Francis } 150749ab747fSPaolo Bonzini } 15088202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 150949ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 151049ab747fSPaolo Bonzini } 151149ab747fSPaolo Bonzini break; 151249ab747fSPaolo Bonzini 1513c755c943SLuc Michel case R_TXSTATUS: 151449ab747fSPaolo Bonzini gem_update_int_status(s); 151549ab747fSPaolo Bonzini break; 1516c755c943SLuc Michel case R_RXQBASE: 15172bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 151849ab747fSPaolo Bonzini break; 1519c755c943SLuc Michel case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1520c755c943SLuc Michel s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 152167101725SAlistair Francis break; 1522c755c943SLuc Michel case R_TXQBASE: 15232bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 152449ab747fSPaolo Bonzini break; 1525c755c943SLuc Michel case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1526c755c943SLuc Michel s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 152767101725SAlistair Francis break; 1528c755c943SLuc Michel case R_RXSTATUS: 152949ab747fSPaolo Bonzini gem_update_int_status(s); 153049ab747fSPaolo Bonzini break; 1531c755c943SLuc Michel case R_IER: 1532c755c943SLuc Michel s->regs[R_IMR] &= ~val; 153349ab747fSPaolo Bonzini gem_update_int_status(s); 153449ab747fSPaolo Bonzini break; 1535c755c943SLuc Michel case R_JUMBO_MAX_LEN: 1536c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 15377ca151c3SSai Pavan Boddu break; 1538c755c943SLuc Michel case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1539c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 154067101725SAlistair Francis gem_update_int_status(s); 154167101725SAlistair Francis break; 1542c755c943SLuc Michel case R_IDR: 1543c755c943SLuc Michel s->regs[R_IMR] |= val; 154449ab747fSPaolo Bonzini gem_update_int_status(s); 154549ab747fSPaolo Bonzini break; 1546c755c943SLuc Michel case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1547c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 154867101725SAlistair Francis gem_update_int_status(s); 154967101725SAlistair Francis break; 1550c755c943SLuc Michel case R_SPADDR1LO: 1551c755c943SLuc Michel case R_SPADDR2LO: 1552c755c943SLuc Michel case R_SPADDR3LO: 1553c755c943SLuc Michel case R_SPADDR4LO: 1554c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 155564eb9301SPeter Crosthwaite break; 1556c755c943SLuc Michel case R_SPADDR1HI: 1557c755c943SLuc Michel case R_SPADDR2HI: 1558c755c943SLuc Michel case R_SPADDR3HI: 1559c755c943SLuc Michel case R_SPADDR4HI: 1560c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 156164eb9301SPeter Crosthwaite break; 1562c755c943SLuc Michel case R_PHYMNTNC: 156349ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 156449ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 156549ab747fSPaolo Bonzini 156649ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1567dfc38879SBin Meng if (phy_addr == s->phy_addr) { 156849ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 156949ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 157049ab747fSPaolo Bonzini } 157149ab747fSPaolo Bonzini } 157249ab747fSPaolo Bonzini break; 157349ab747fSPaolo Bonzini } 157449ab747fSPaolo Bonzini 157549ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 157649ab747fSPaolo Bonzini } 157749ab747fSPaolo Bonzini 157849ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 157949ab747fSPaolo Bonzini .read = gem_read, 158049ab747fSPaolo Bonzini .write = gem_write, 158149ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 158249ab747fSPaolo Bonzini }; 158349ab747fSPaolo Bonzini 158449ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 158549ab747fSPaolo Bonzini { 158667101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 158767101725SAlistair Francis 158849ab747fSPaolo Bonzini DB_PRINT("\n"); 158967101725SAlistair Francis phy_update_link(s); 159067101725SAlistair Francis gem_update_int_status(s); 159149ab747fSPaolo Bonzini } 159249ab747fSPaolo Bonzini 159349ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1594f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 159549ab747fSPaolo Bonzini .size = sizeof(NICState), 159649ab747fSPaolo Bonzini .can_receive = gem_can_receive, 159749ab747fSPaolo Bonzini .receive = gem_receive, 159849ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 159949ab747fSPaolo Bonzini }; 160049ab747fSPaolo Bonzini 1601bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 160249ab747fSPaolo Bonzini { 1603448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 160467101725SAlistair Francis int i; 160549ab747fSPaolo Bonzini 160684aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 160784aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 160884aec8efSEdgar E. Iglesias 16092bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 16102bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 16112bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 16122bf57f73SAlistair Francis s->num_priority_queues); 16132bf57f73SAlistair Francis return; 1614e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1615e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1616e8e49943SAlistair Francis s->num_type1_screeners); 1617e8e49943SAlistair Francis return; 1618e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1619e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1620e8e49943SAlistair Francis s->num_type2_screeners); 1621e8e49943SAlistair Francis return; 16222bf57f73SAlistair Francis } 16232bf57f73SAlistair Francis 162467101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 162567101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 162667101725SAlistair Francis } 1627bcb39a65SAlistair Francis 1628bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1629bcb39a65SAlistair Francis 1630bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1631bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 16327ca151c3SSai Pavan Boddu 16337ca151c3SSai Pavan Boddu if (s->jumbo_max_len > MAX_FRAME_SIZE) { 16347ca151c3SSai Pavan Boddu error_setg(errp, "jumbo-max-len is greater than %d", 16357ca151c3SSai Pavan Boddu MAX_FRAME_SIZE); 16367ca151c3SSai Pavan Boddu return; 16377ca151c3SSai Pavan Boddu } 1638bcb39a65SAlistair Francis } 1639bcb39a65SAlistair Francis 1640bcb39a65SAlistair Francis static void gem_init(Object *obj) 1641bcb39a65SAlistair Francis { 1642bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1643bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1644bcb39a65SAlistair Francis 164549ab747fSPaolo Bonzini DB_PRINT("\n"); 164649ab747fSPaolo Bonzini 164749ab747fSPaolo Bonzini gem_init_register_masks(s); 1648eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1649eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 165049ab747fSPaolo Bonzini 1651bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 165249ab747fSPaolo Bonzini } 165349ab747fSPaolo Bonzini 165449ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 165549ab747fSPaolo Bonzini .name = "cadence_gem", 1656e8e49943SAlistair Francis .version_id = 4, 1657e8e49943SAlistair Francis .minimum_version_id = 4, 165849ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1659448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1660448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1661448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 16622bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 16632bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 16642bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 16652bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1666448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 166717cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 166849ab747fSPaolo Bonzini } 166949ab747fSPaolo Bonzini }; 167049ab747fSPaolo Bonzini 167149ab747fSPaolo Bonzini static Property gem_properties[] = { 1672448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1673a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1674a5517666SAlistair Francis GEM_MODID_VALUE), 167564ac1363SBin Meng DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 16762bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 16772bf57f73SAlistair Francis num_priority_queues, 1), 1678e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1679e8e49943SAlistair Francis num_type1_screeners, 4), 1680e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1681e8e49943SAlistair Francis num_type2_screeners, 4), 16827ca151c3SSai Pavan Boddu DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 16837ca151c3SSai Pavan Boddu jumbo_max_len, 10240), 168408d45942SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 168508d45942SPhilippe Mathieu-Daudé TYPE_MEMORY_REGION, MemoryRegion *), 168649ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 168749ab747fSPaolo Bonzini }; 168849ab747fSPaolo Bonzini 168949ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 169049ab747fSPaolo Bonzini { 169149ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 169249ab747fSPaolo Bonzini 1693bcb39a65SAlistair Francis dc->realize = gem_realize; 16944f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 169549ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 169649ab747fSPaolo Bonzini dc->reset = gem_reset; 169749ab747fSPaolo Bonzini } 169849ab747fSPaolo Bonzini 169949ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1700318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 170149ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1702448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1703bcb39a65SAlistair Francis .instance_init = gem_init, 1704318643beSAndreas Färber .class_init = gem_class_init, 170549ab747fSPaolo Bonzini }; 170649ab747fSPaolo Bonzini 170749ab747fSPaolo Bonzini static void gem_register_types(void) 170849ab747fSPaolo Bonzini { 170949ab747fSPaolo Bonzini type_register_static(&gem_info); 171049ab747fSPaolo Bonzini } 171149ab747fSPaolo Bonzini 171249ab747fSPaolo Bonzini type_init(gem_register_types) 1713