149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31c755c943SLuc Michel #include "hw/registerfields.h" 32d6454270SMarkus Armbruster #include "migration/vmstate.h" 332bf57f73SAlistair Francis #include "qapi/error.h" 34e8e49943SAlistair Francis #include "qemu/log.h" 350b8fa32fSMarkus Armbruster #include "qemu/module.h" 3684aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3749ab747fSPaolo Bonzini #include "net/checksum.h" 38fbc14a09STong Ho #include "net/eth.h" 3949ab747fSPaolo Bonzini 406fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 4149ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 426fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 436fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 446fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 456fe7661dSSai Pavan Boddu } \ 462562755eSEric Blake } while (0) 4749ab747fSPaolo Bonzini 48c755c943SLuc Michel REG32(NWCTRL, 0x0) /* Network Control reg */ 49bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK , 0, 1) 50bd8a922dSLuc Michel FIELD(NWCTRL, LOOPBACK_LOCAL , 1, 1) 51bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_RECEIVE, 2, 1) 52bd8a922dSLuc Michel FIELD(NWCTRL, ENABLE_TRANSMIT, 3, 1) 53bd8a922dSLuc Michel FIELD(NWCTRL, MAN_PORT_EN , 4, 1) 54bd8a922dSLuc Michel FIELD(NWCTRL, CLEAR_ALL_STATS_REGS , 5, 1) 55bd8a922dSLuc Michel FIELD(NWCTRL, INC_ALL_STATS_REGS, 6, 1) 56bd8a922dSLuc Michel FIELD(NWCTRL, STATS_WRITE_EN, 7, 1) 57bd8a922dSLuc Michel FIELD(NWCTRL, BACK_PRESSURE, 8, 1) 58bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_START , 9, 1) 59bd8a922dSLuc Michel FIELD(NWCTRL, TRANSMIT_HALT, 10, 1) 60bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_RE, 11, 1) 61bd8a922dSLuc Michel FIELD(NWCTRL, TX_PAUSE_FRAME_ZE, 12, 1) 62bd8a922dSLuc Michel FIELD(NWCTRL, STATS_TAKE_SNAP, 13, 1) 63bd8a922dSLuc Michel FIELD(NWCTRL, STATS_READ_SNAP, 14, 1) 64bd8a922dSLuc Michel FIELD(NWCTRL, STORE_RX_TS, 15, 1) 65bd8a922dSLuc Michel FIELD(NWCTRL, PFC_ENABLE, 16, 1) 66bd8a922dSLuc Michel FIELD(NWCTRL, PFC_PRIO_BASED, 17, 1) 67bd8a922dSLuc Michel FIELD(NWCTRL, FLUSH_RX_PKT_PCLK , 18, 1) 68bd8a922dSLuc Michel FIELD(NWCTRL, TX_LPI_EN, 19, 1) 69bd8a922dSLuc Michel FIELD(NWCTRL, PTP_UNICAST_ENA, 20, 1) 70bd8a922dSLuc Michel FIELD(NWCTRL, ALT_SGMII_MODE, 21, 1) 71bd8a922dSLuc Michel FIELD(NWCTRL, STORE_UDP_OFFSET, 22, 1) 72bd8a922dSLuc Michel FIELD(NWCTRL, EXT_TSU_PORT_EN, 23, 1) 73bd8a922dSLuc Michel FIELD(NWCTRL, ONE_STEP_SYNC_MO, 24, 1) 74bd8a922dSLuc Michel FIELD(NWCTRL, PFC_CTRL , 25, 1) 75bd8a922dSLuc Michel FIELD(NWCTRL, EXT_RXQ_SEL_EN , 26, 1) 76bd8a922dSLuc Michel FIELD(NWCTRL, OSS_CORRECTION_FIELD, 27, 1) 77bd8a922dSLuc Michel FIELD(NWCTRL, SEL_MII_ON_RGMII, 28, 1) 78bd8a922dSLuc Michel FIELD(NWCTRL, TWO_PT_FIVE_GIG, 29, 1) 79bd8a922dSLuc Michel FIELD(NWCTRL, IFG_EATS_QAV_CREDIT, 30, 1) 80bd8a922dSLuc Michel 81c755c943SLuc Michel REG32(NWCFG, 0x4) /* Network Config reg */ 8287a49c3fSLuc Michel FIELD(NWCFG, SPEED, 0, 1) 8387a49c3fSLuc Michel FIELD(NWCFG, FULL_DUPLEX, 1, 1) 8487a49c3fSLuc Michel FIELD(NWCFG, DISCARD_NON_VLAN_FRAMES, 2, 1) 8587a49c3fSLuc Michel FIELD(NWCFG, JUMBO_FRAMES, 3, 1) 8687a49c3fSLuc Michel FIELD(NWCFG, PROMISC, 4, 1) 8787a49c3fSLuc Michel FIELD(NWCFG, NO_BROADCAST, 5, 1) 8887a49c3fSLuc Michel FIELD(NWCFG, MULTICAST_HASH_EN, 6, 1) 8987a49c3fSLuc Michel FIELD(NWCFG, UNICAST_HASH_EN, 7, 1) 9087a49c3fSLuc Michel FIELD(NWCFG, RECV_1536_BYTE_FRAMES, 8, 1) 9187a49c3fSLuc Michel FIELD(NWCFG, EXTERNAL_ADDR_MATCH_EN, 9, 1) 9287a49c3fSLuc Michel FIELD(NWCFG, GIGABIT_MODE_ENABLE, 10, 1) 9387a49c3fSLuc Michel FIELD(NWCFG, PCS_SELECT, 11, 1) 9487a49c3fSLuc Michel FIELD(NWCFG, RETRY_TEST, 12, 1) 9587a49c3fSLuc Michel FIELD(NWCFG, PAUSE_ENABLE, 13, 1) 9687a49c3fSLuc Michel FIELD(NWCFG, RECV_BUF_OFFSET, 14, 2) 9787a49c3fSLuc Michel FIELD(NWCFG, LEN_ERR_DISCARD, 16, 1) 9887a49c3fSLuc Michel FIELD(NWCFG, FCS_REMOVE, 17, 1) 9987a49c3fSLuc Michel FIELD(NWCFG, MDC_CLOCK_DIV, 18, 3) 10087a49c3fSLuc Michel FIELD(NWCFG, DATA_BUS_WIDTH, 21, 2) 10187a49c3fSLuc Michel FIELD(NWCFG, DISABLE_COPY_PAUSE_FRAMES, 23, 1) 10287a49c3fSLuc Michel FIELD(NWCFG, RECV_CSUM_OFFLOAD_EN, 24, 1) 10387a49c3fSLuc Michel FIELD(NWCFG, EN_HALF_DUPLEX_RX, 25, 1) 10487a49c3fSLuc Michel FIELD(NWCFG, IGNORE_RX_FCS, 26, 1) 10587a49c3fSLuc Michel FIELD(NWCFG, SGMII_MODE_ENABLE, 27, 1) 10687a49c3fSLuc Michel FIELD(NWCFG, IPG_STRETCH_ENABLE, 28, 1) 10787a49c3fSLuc Michel FIELD(NWCFG, NSP_ACCEPT, 29, 1) 10887a49c3fSLuc Michel FIELD(NWCFG, IGNORE_IPG_RX_ER, 30, 1) 10987a49c3fSLuc Michel FIELD(NWCFG, UNI_DIRECTION_ENABLE, 31, 1) 11087a49c3fSLuc Michel 111c755c943SLuc Michel REG32(NWSTATUS, 0x8) /* Network Status reg */ 112c755c943SLuc Michel REG32(USERIO, 0xc) /* User IO reg */ 11301f9175dSLuc Michel 114c755c943SLuc Michel REG32(DMACFG, 0x10) /* DMA Control reg */ 11501f9175dSLuc Michel FIELD(DMACFG, SEND_BCAST_TO_ALL_QS, 31, 1) 11601f9175dSLuc Michel FIELD(DMACFG, DMA_ADDR_BUS_WIDTH, 30, 1) 11701f9175dSLuc Michel FIELD(DMACFG, TX_BD_EXT_MODE_EN , 29, 1) 11801f9175dSLuc Michel FIELD(DMACFG, RX_BD_EXT_MODE_EN , 28, 1) 11901f9175dSLuc Michel FIELD(DMACFG, FORCE_MAX_AMBA_BURST_TX, 26, 1) 12001f9175dSLuc Michel FIELD(DMACFG, FORCE_MAX_AMBA_BURST_RX, 25, 1) 12101f9175dSLuc Michel FIELD(DMACFG, FORCE_DISCARD_ON_ERR, 24, 1) 12201f9175dSLuc Michel FIELD(DMACFG, RX_BUF_SIZE, 16, 8) 12301f9175dSLuc Michel FIELD(DMACFG, CRC_ERROR_REPORT, 13, 1) 12401f9175dSLuc Michel FIELD(DMACFG, INF_LAST_DBUF_SIZE_EN, 12, 1) 12501f9175dSLuc Michel FIELD(DMACFG, TX_PBUF_CSUM_OFFLOAD, 11, 1) 12601f9175dSLuc Michel FIELD(DMACFG, TX_PBUF_SIZE, 10, 1) 12701f9175dSLuc Michel FIELD(DMACFG, RX_PBUF_SIZE, 8, 2) 12801f9175dSLuc Michel FIELD(DMACFG, ENDIAN_SWAP_PACKET, 7, 1) 12901f9175dSLuc Michel FIELD(DMACFG, ENDIAN_SWAP_MGNT, 6, 1) 13001f9175dSLuc Michel FIELD(DMACFG, HDR_DATA_SPLIT_EN, 5, 1) 13101f9175dSLuc Michel FIELD(DMACFG, AMBA_BURST_LEN , 0, 5) 13201f9175dSLuc Michel #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 13301f9175dSLuc Michel 134c755c943SLuc Michel REG32(TXSTATUS, 0x14) /* TX Status reg */ 135466da857SLuc Michel FIELD(TXSTATUS, TX_USED_BIT_READ_MIDFRAME, 12, 1) 136466da857SLuc Michel FIELD(TXSTATUS, TX_FRAME_TOO_LARGE, 11, 1) 137466da857SLuc Michel FIELD(TXSTATUS, TX_DMA_LOCKUP, 10, 1) 138466da857SLuc Michel FIELD(TXSTATUS, TX_MAC_LOCKUP, 9, 1) 139466da857SLuc Michel FIELD(TXSTATUS, RESP_NOT_OK, 8, 1) 140466da857SLuc Michel FIELD(TXSTATUS, LATE_COLLISION, 7, 1) 141466da857SLuc Michel FIELD(TXSTATUS, TRANSMIT_UNDER_RUN, 6, 1) 142466da857SLuc Michel FIELD(TXSTATUS, TRANSMIT_COMPLETE, 5, 1) 143466da857SLuc Michel FIELD(TXSTATUS, AMBA_ERROR, 4, 1) 144466da857SLuc Michel FIELD(TXSTATUS, TRANSMIT_GO, 3, 1) 145466da857SLuc Michel FIELD(TXSTATUS, RETRY_LIMIT, 2, 1) 146466da857SLuc Michel FIELD(TXSTATUS, COLLISION, 1, 1) 147466da857SLuc Michel FIELD(TXSTATUS, USED_BIT_READ, 0, 1) 148466da857SLuc Michel 149c755c943SLuc Michel REG32(RXQBASE, 0x18) /* RX Q Base address reg */ 150c755c943SLuc Michel REG32(TXQBASE, 0x1c) /* TX Q Base address reg */ 151c755c943SLuc Michel REG32(RXSTATUS, 0x20) /* RX Status reg */ 152466da857SLuc Michel FIELD(RXSTATUS, RX_DMA_LOCKUP, 5, 1) 153466da857SLuc Michel FIELD(RXSTATUS, RX_MAC_LOCKUP, 4, 1) 154466da857SLuc Michel FIELD(RXSTATUS, RESP_NOT_OK, 3, 1) 155466da857SLuc Michel FIELD(RXSTATUS, RECEIVE_OVERRUN, 2, 1) 156466da857SLuc Michel FIELD(RXSTATUS, FRAME_RECEIVED, 1, 1) 157466da857SLuc Michel FIELD(RXSTATUS, BUF_NOT_AVAILABLE, 0, 1) 158466da857SLuc Michel 159c755c943SLuc Michel REG32(ISR, 0x24) /* Interrupt Status reg */ 160987e8060SLuc Michel FIELD(ISR, TX_LOCKUP, 31, 1) 161987e8060SLuc Michel FIELD(ISR, RX_LOCKUP, 30, 1) 162987e8060SLuc Michel FIELD(ISR, TSU_TIMER, 29, 1) 163987e8060SLuc Michel FIELD(ISR, WOL, 28, 1) 164987e8060SLuc Michel FIELD(ISR, RECV_LPI, 27, 1) 165987e8060SLuc Michel FIELD(ISR, TSU_SEC_INCR, 26, 1) 166987e8060SLuc Michel FIELD(ISR, PTP_PDELAY_RESP_XMIT, 25, 1) 167987e8060SLuc Michel FIELD(ISR, PTP_PDELAY_REQ_XMIT, 24, 1) 168987e8060SLuc Michel FIELD(ISR, PTP_PDELAY_RESP_RECV, 23, 1) 169987e8060SLuc Michel FIELD(ISR, PTP_PDELAY_REQ_RECV, 22, 1) 170987e8060SLuc Michel FIELD(ISR, PTP_SYNC_XMIT, 21, 1) 171987e8060SLuc Michel FIELD(ISR, PTP_DELAY_REQ_XMIT, 20, 1) 172987e8060SLuc Michel FIELD(ISR, PTP_SYNC_RECV, 19, 1) 173987e8060SLuc Michel FIELD(ISR, PTP_DELAY_REQ_RECV, 18, 1) 174987e8060SLuc Michel FIELD(ISR, PCS_LP_PAGE_RECV, 17, 1) 175987e8060SLuc Michel FIELD(ISR, PCS_AN_COMPLETE, 16, 1) 176987e8060SLuc Michel FIELD(ISR, EXT_IRQ, 15, 1) 177987e8060SLuc Michel FIELD(ISR, PAUSE_FRAME_XMIT, 14, 1) 178987e8060SLuc Michel FIELD(ISR, PAUSE_TIME_ELAPSED, 13, 1) 179987e8060SLuc Michel FIELD(ISR, PAUSE_FRAME_RECV, 12, 1) 180987e8060SLuc Michel FIELD(ISR, RESP_NOT_OK, 11, 1) 181987e8060SLuc Michel FIELD(ISR, RECV_OVERRUN, 10, 1) 182987e8060SLuc Michel FIELD(ISR, LINK_CHANGE, 9, 1) 183987e8060SLuc Michel FIELD(ISR, USXGMII_INT, 8, 1) 184987e8060SLuc Michel FIELD(ISR, XMIT_COMPLETE, 7, 1) 185987e8060SLuc Michel FIELD(ISR, AMBA_ERROR, 6, 1) 186987e8060SLuc Michel FIELD(ISR, RETRY_EXCEEDED, 5, 1) 187987e8060SLuc Michel FIELD(ISR, XMIT_UNDER_RUN, 4, 1) 188987e8060SLuc Michel FIELD(ISR, TX_USED, 3, 1) 189987e8060SLuc Michel FIELD(ISR, RX_USED, 2, 1) 190987e8060SLuc Michel FIELD(ISR, RECV_COMPLETE, 1, 1) 191987e8060SLuc Michel FIELD(ISR, MGNT_FRAME_SENT, 0, 1) 192c755c943SLuc Michel REG32(IER, 0x28) /* Interrupt Enable reg */ 193c755c943SLuc Michel REG32(IDR, 0x2c) /* Interrupt Disable reg */ 194c755c943SLuc Michel REG32(IMR, 0x30) /* Interrupt Mask reg */ 195987e8060SLuc Michel 196c755c943SLuc Michel REG32(PHYMNTNC, 0x34) /* Phy Maintenance reg */ 197c755c943SLuc Michel REG32(RXPAUSE, 0x38) /* RX Pause Time reg */ 198c755c943SLuc Michel REG32(TXPAUSE, 0x3c) /* TX Pause Time reg */ 199c755c943SLuc Michel REG32(TXPARTIALSF, 0x40) /* TX Partial Store and Forward */ 200c755c943SLuc Michel REG32(RXPARTIALSF, 0x44) /* RX Partial Store and Forward */ 201c755c943SLuc Michel REG32(JUMBO_MAX_LEN, 0x48) /* Max Jumbo Frame Size */ 202c755c943SLuc Michel REG32(HASHLO, 0x80) /* Hash Low address reg */ 203c755c943SLuc Michel REG32(HASHHI, 0x84) /* Hash High address reg */ 204c755c943SLuc Michel REG32(SPADDR1LO, 0x88) /* Specific addr 1 low reg */ 205c755c943SLuc Michel REG32(SPADDR1HI, 0x8c) /* Specific addr 1 high reg */ 206c755c943SLuc Michel REG32(SPADDR2LO, 0x90) /* Specific addr 2 low reg */ 207c755c943SLuc Michel REG32(SPADDR2HI, 0x94) /* Specific addr 2 high reg */ 208c755c943SLuc Michel REG32(SPADDR3LO, 0x98) /* Specific addr 3 low reg */ 209c755c943SLuc Michel REG32(SPADDR3HI, 0x9c) /* Specific addr 3 high reg */ 210c755c943SLuc Michel REG32(SPADDR4LO, 0xa0) /* Specific addr 4 low reg */ 211c755c943SLuc Michel REG32(SPADDR4HI, 0xa4) /* Specific addr 4 high reg */ 212c755c943SLuc Michel REG32(TIDMATCH1, 0xa8) /* Type ID1 Match reg */ 213c755c943SLuc Michel REG32(TIDMATCH2, 0xac) /* Type ID2 Match reg */ 214c755c943SLuc Michel REG32(TIDMATCH3, 0xb0) /* Type ID3 Match reg */ 215c755c943SLuc Michel REG32(TIDMATCH4, 0xb4) /* Type ID4 Match reg */ 216c755c943SLuc Michel REG32(WOLAN, 0xb8) /* Wake on LAN reg */ 217c755c943SLuc Michel REG32(IPGSTRETCH, 0xbc) /* IPG Stretch reg */ 218c755c943SLuc Michel REG32(SVLAN, 0xc0) /* Stacked VLAN reg */ 219c755c943SLuc Michel REG32(MODID, 0xfc) /* Module ID reg */ 220c755c943SLuc Michel REG32(OCTTXLO, 0x100) /* Octects transmitted Low reg */ 221c755c943SLuc Michel REG32(OCTTXHI, 0x104) /* Octects transmitted High reg */ 222c755c943SLuc Michel REG32(TXCNT, 0x108) /* Error-free Frames transmitted */ 223c755c943SLuc Michel REG32(TXBCNT, 0x10c) /* Error-free Broadcast Frames */ 224c755c943SLuc Michel REG32(TXMCNT, 0x110) /* Error-free Multicast Frame */ 225c755c943SLuc Michel REG32(TXPAUSECNT, 0x114) /* Pause Frames Transmitted */ 226c755c943SLuc Michel REG32(TX64CNT, 0x118) /* Error-free 64 TX */ 227c755c943SLuc Michel REG32(TX65CNT, 0x11c) /* Error-free 65-127 TX */ 228c755c943SLuc Michel REG32(TX128CNT, 0x120) /* Error-free 128-255 TX */ 229c755c943SLuc Michel REG32(TX256CNT, 0x124) /* Error-free 256-511 */ 230c755c943SLuc Michel REG32(TX512CNT, 0x128) /* Error-free 512-1023 TX */ 231c755c943SLuc Michel REG32(TX1024CNT, 0x12c) /* Error-free 1024-1518 TX */ 232c755c943SLuc Michel REG32(TX1519CNT, 0x130) /* Error-free larger than 1519 TX */ 233c755c943SLuc Michel REG32(TXURUNCNT, 0x134) /* TX under run error counter */ 234c755c943SLuc Michel REG32(SINGLECOLLCNT, 0x138) /* Single Collision Frames */ 235c755c943SLuc Michel REG32(MULTCOLLCNT, 0x13c) /* Multiple Collision Frames */ 236c755c943SLuc Michel REG32(EXCESSCOLLCNT, 0x140) /* Excessive Collision Frames */ 237c755c943SLuc Michel REG32(LATECOLLCNT, 0x144) /* Late Collision Frames */ 238c755c943SLuc Michel REG32(DEFERTXCNT, 0x148) /* Deferred Transmission Frames */ 239c755c943SLuc Michel REG32(CSENSECNT, 0x14c) /* Carrier Sense Error Counter */ 240c755c943SLuc Michel REG32(OCTRXLO, 0x150) /* Octects Received register Low */ 241c755c943SLuc Michel REG32(OCTRXHI, 0x154) /* Octects Received register High */ 242c755c943SLuc Michel REG32(RXCNT, 0x158) /* Error-free Frames Received */ 243c755c943SLuc Michel REG32(RXBROADCNT, 0x15c) /* Error-free Broadcast Frames RX */ 244c755c943SLuc Michel REG32(RXMULTICNT, 0x160) /* Error-free Multicast Frames RX */ 245c755c943SLuc Michel REG32(RXPAUSECNT, 0x164) /* Pause Frames Received Counter */ 246c755c943SLuc Michel REG32(RX64CNT, 0x168) /* Error-free 64 byte Frames RX */ 247c755c943SLuc Michel REG32(RX65CNT, 0x16c) /* Error-free 65-127B Frames RX */ 248c755c943SLuc Michel REG32(RX128CNT, 0x170) /* Error-free 128-255B Frames RX */ 249c755c943SLuc Michel REG32(RX256CNT, 0x174) /* Error-free 256-512B Frames RX */ 250c755c943SLuc Michel REG32(RX512CNT, 0x178) /* Error-free 512-1023B Frames RX */ 251c755c943SLuc Michel REG32(RX1024CNT, 0x17c) /* Error-free 1024-1518B Frames RX */ 252c755c943SLuc Michel REG32(RX1519CNT, 0x180) /* Error-free 1519-max Frames RX */ 253c755c943SLuc Michel REG32(RXUNDERCNT, 0x184) /* Undersize Frames Received */ 254c755c943SLuc Michel REG32(RXOVERCNT, 0x188) /* Oversize Frames Received */ 255c755c943SLuc Michel REG32(RXJABCNT, 0x18c) /* Jabbers Received Counter */ 256c755c943SLuc Michel REG32(RXFCSCNT, 0x190) /* Frame Check seq. Error Counter */ 257c755c943SLuc Michel REG32(RXLENERRCNT, 0x194) /* Length Field Error Counter */ 258c755c943SLuc Michel REG32(RXSYMERRCNT, 0x198) /* Symbol Error Counter */ 259c755c943SLuc Michel REG32(RXALIGNERRCNT, 0x19c) /* Alignment Error Counter */ 260c755c943SLuc Michel REG32(RXRSCERRCNT, 0x1a0) /* Receive Resource Error Counter */ 261c755c943SLuc Michel REG32(RXORUNCNT, 0x1a4) /* Receive Overrun Counter */ 262c755c943SLuc Michel REG32(RXIPCSERRCNT, 0x1a8) /* IP header Checksum Err Counter */ 263c755c943SLuc Michel REG32(RXTCPCCNT, 0x1ac) /* TCP Checksum Error Counter */ 264c755c943SLuc Michel REG32(RXUDPCCNT, 0x1b0) /* UDP Checksum Error Counter */ 26549ab747fSPaolo Bonzini 266c755c943SLuc Michel REG32(1588S, 0x1d0) /* 1588 Timer Seconds */ 267c755c943SLuc Michel REG32(1588NS, 0x1d4) /* 1588 Timer Nanoseconds */ 268c755c943SLuc Michel REG32(1588ADJ, 0x1d8) /* 1588 Timer Adjust */ 269c755c943SLuc Michel REG32(1588INC, 0x1dc) /* 1588 Timer Increment */ 270c755c943SLuc Michel REG32(PTPETXS, 0x1e0) /* PTP Event Frame Transmitted (s) */ 271c755c943SLuc Michel REG32(PTPETXNS, 0x1e4) /* PTP Event Frame Transmitted (ns) */ 272c755c943SLuc Michel REG32(PTPERXS, 0x1e8) /* PTP Event Frame Received (s) */ 273c755c943SLuc Michel REG32(PTPERXNS, 0x1ec) /* PTP Event Frame Received (ns) */ 274c755c943SLuc Michel REG32(PTPPTXS, 0x1e0) /* PTP Peer Frame Transmitted (s) */ 275c755c943SLuc Michel REG32(PTPPTXNS, 0x1e4) /* PTP Peer Frame Transmitted (ns) */ 276c755c943SLuc Michel REG32(PTPPRXS, 0x1e8) /* PTP Peer Frame Received (s) */ 277c755c943SLuc Michel REG32(PTPPRXNS, 0x1ec) /* PTP Peer Frame Received (ns) */ 27849ab747fSPaolo Bonzini 27949ab747fSPaolo Bonzini /* Design Configuration Registers */ 280c755c943SLuc Michel REG32(DESCONF, 0x280) 281c755c943SLuc Michel REG32(DESCONF2, 0x284) 282c755c943SLuc Michel REG32(DESCONF3, 0x288) 283c755c943SLuc Michel REG32(DESCONF4, 0x28c) 284c755c943SLuc Michel REG32(DESCONF5, 0x290) 285c755c943SLuc Michel REG32(DESCONF6, 0x294) 286ce077875SLuc Michel FIELD(DESCONF6, DMA_ADDR_64B, 23, 1) 287c755c943SLuc Michel REG32(DESCONF7, 0x298) 28849ab747fSPaolo Bonzini 289c755c943SLuc Michel REG32(INT_Q1_STATUS, 0x400) 290c755c943SLuc Michel REG32(INT_Q1_MASK, 0x640) 29167101725SAlistair Francis 292c755c943SLuc Michel REG32(TRANSMIT_Q1_PTR, 0x440) 293c755c943SLuc Michel REG32(TRANSMIT_Q7_PTR, 0x458) 29467101725SAlistair Francis 295c755c943SLuc Michel REG32(RECEIVE_Q1_PTR, 0x480) 296c755c943SLuc Michel REG32(RECEIVE_Q7_PTR, 0x498) 29767101725SAlistair Francis 298c755c943SLuc Michel REG32(TBQPH, 0x4c8) 299c755c943SLuc Michel REG32(RBQPH, 0x4d4) 300357aa013SEdgar E. Iglesias 301c755c943SLuc Michel REG32(INT_Q1_ENABLE, 0x600) 302c755c943SLuc Michel REG32(INT_Q7_ENABLE, 0x618) 30367101725SAlistair Francis 304c755c943SLuc Michel REG32(INT_Q1_DISABLE, 0x620) 305c755c943SLuc Michel REG32(INT_Q7_DISABLE, 0x638) 30667101725SAlistair Francis 307c755c943SLuc Michel REG32(SCREENING_TYPE1_REG0, 0x500) 308b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, QUEUE_NUM, 0, 4) 309b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_MATCH, 4, 8) 310b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH, 12, 16) 311b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DSTC_ENABLE, 28, 1) 312b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN, 29, 1) 313b46b526cSLuc Michel FIELD(SCREENING_TYPE1_REG0, DROP_ON_MATCH, 30, 1) 314e8e49943SAlistair Francis 315c755c943SLuc Michel REG32(SCREENING_TYPE2_REG0, 0x540) 316b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, QUEUE_NUM, 0, 4) 317b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_PRIORITY, 4, 3) 318b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, VLAN_ENABLE, 8, 1) 319b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_REG_INDEX, 9, 3) 320b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE, 12, 1) 321b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A, 13, 5) 322b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_A_ENABLE, 18, 1) 323b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B, 19, 5) 324b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_B_ENABLE, 24, 1) 325b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C, 25, 5) 326b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, COMPARE_C_ENABLE, 30, 1) 327b46b526cSLuc Michel FIELD(SCREENING_TYPE2_REG0, DROP_ON_MATCH, 31, 1) 328e8e49943SAlistair Francis 329c755c943SLuc Michel REG32(SCREENING_TYPE2_ETHERTYPE_REG0, 0x6e0) 330e8e49943SAlistair Francis 331b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_0, 0x700) 332b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, MASK_VALUE, 0, 16) 333b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE, 16, 16) 334b46b526cSLuc Michel 335b46b526cSLuc Michel REG32(TYPE2_COMPARE_0_WORD_1, 0x704) 336b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE, 0, 7) 337b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET, 7, 2) 338b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, DISABLE_MASK, 9, 1) 339b46b526cSLuc Michel FIELD(TYPE2_COMPARE_0_WORD_1, COMPARE_VLAN_ID, 10, 1) 340e8e49943SAlistair Francis 34149ab747fSPaolo Bonzini /*****************************************/ 34249ab747fSPaolo Bonzini 34349ab747fSPaolo Bonzini 34449ab747fSPaolo Bonzini 34549ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 34649ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 34749ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 34849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 34949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 35049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 35149ab747fSPaolo Bonzini 35249ab747fSPaolo Bonzini /* Marvell PHY definitions */ 353dfc38879SBin Meng #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 35449ab747fSPaolo Bonzini 35549ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 35649ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 35749ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 35849ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 35949ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 36049ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 36149ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 36249ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 36349ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 36449ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 36549ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 36649ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 36749ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 36849ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 36949ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 37049ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 37149ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 37249ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 37349ab747fSPaolo Bonzini #define PHY_REG_EACD 22 37449ab747fSPaolo Bonzini #define PHY_REG_LED 24 37549ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 37649ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 37749ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 37849ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 37949ab747fSPaolo Bonzini 38049ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 38149ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 38249ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 3836623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 38449ab747fSPaolo Bonzini 38549ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 38649ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 38749ab747fSPaolo Bonzini 38849ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 38949ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 39049ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 39149ab747fSPaolo Bonzini 39249ab747fSPaolo Bonzini /***********************************************************************/ 39363af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 39463af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 39563af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 39663af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 39763af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 39863af1e0cSPeter Crosthwaite 39963af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 40049ab747fSPaolo Bonzini 40149ab747fSPaolo Bonzini /***********************************************************************/ 40249ab747fSPaolo Bonzini 40349ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 40449ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 40549ab747fSPaolo Bonzini 40649ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 40749ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 40849ab747fSPaolo Bonzini 40949ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 41049ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 41149ab747fSPaolo Bonzini 41263af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 41363af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 414a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 41563af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 41663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 41763af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 41863af1e0cSPeter Crosthwaite 41949ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 42049ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 42149ab747fSPaolo Bonzini 422a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 423a5517666SAlistair Francis 424e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 42549ab747fSPaolo Bonzini { 426e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 427e48fdd9dSEdgar E. Iglesias 42801f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 429e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 430e48fdd9dSEdgar E. Iglesias } 431e48fdd9dSEdgar E. Iglesias return ret; 43249ab747fSPaolo Bonzini } 43349ab747fSPaolo Bonzini 434f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 43549ab747fSPaolo Bonzini { 43649ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 43749ab747fSPaolo Bonzini } 43849ab747fSPaolo Bonzini 439f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 44049ab747fSPaolo Bonzini { 44149ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 44249ab747fSPaolo Bonzini } 44349ab747fSPaolo Bonzini 444f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 44549ab747fSPaolo Bonzini { 44649ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 44749ab747fSPaolo Bonzini } 44849ab747fSPaolo Bonzini 449f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 45049ab747fSPaolo Bonzini { 45149ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 45249ab747fSPaolo Bonzini } 45349ab747fSPaolo Bonzini 454f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 45549ab747fSPaolo Bonzini { 45649ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 45749ab747fSPaolo Bonzini } 45849ab747fSPaolo Bonzini 459f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 46049ab747fSPaolo Bonzini { 46167101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 46249ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 46349ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 46449ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 46549ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 46649ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 46749ab747fSPaolo Bonzini } 46849ab747fSPaolo Bonzini 469e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 47049ab747fSPaolo Bonzini { 471e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 472e48fdd9dSEdgar E. Iglesias 47301f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 474e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 475e48fdd9dSEdgar E. Iglesias } 476e48fdd9dSEdgar E. Iglesias return ret; 477e48fdd9dSEdgar E. Iglesias } 478e48fdd9dSEdgar E. Iglesias 479e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 480e48fdd9dSEdgar E. Iglesias { 481e48fdd9dSEdgar E. Iglesias int ret = 2; 482e48fdd9dSEdgar E. Iglesias 48301f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 484e48fdd9dSEdgar E. Iglesias ret += 2; 485e48fdd9dSEdgar E. Iglesias } 48601f9175dSLuc Michel if (s->regs[R_DMACFG] & (rx_n_tx ? R_DMACFG_RX_BD_EXT_MODE_EN_MASK 48701f9175dSLuc Michel : R_DMACFG_TX_BD_EXT_MODE_EN_MASK)) { 488e48fdd9dSEdgar E. Iglesias ret += 2; 489e48fdd9dSEdgar E. Iglesias } 490e48fdd9dSEdgar E. Iglesias 491e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 492e48fdd9dSEdgar E. Iglesias return ret; 49349ab747fSPaolo Bonzini } 49449ab747fSPaolo Bonzini 495f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 49649ab747fSPaolo Bonzini { 49749ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 49849ab747fSPaolo Bonzini } 49949ab747fSPaolo Bonzini 500f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 50149ab747fSPaolo Bonzini { 50249ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 50349ab747fSPaolo Bonzini } 50449ab747fSPaolo Bonzini 505f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 50649ab747fSPaolo Bonzini { 50749ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 50849ab747fSPaolo Bonzini } 50949ab747fSPaolo Bonzini 510f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 51149ab747fSPaolo Bonzini { 51249ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 51349ab747fSPaolo Bonzini } 51449ab747fSPaolo Bonzini 51559ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 51659ab136aSRamon Fried { 51759ab136aSRamon Fried desc[1] = 0; 51859ab136aSRamon Fried } 51959ab136aSRamon Fried 520f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 52149ab747fSPaolo Bonzini { 52249ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 52349ab747fSPaolo Bonzini } 52449ab747fSPaolo Bonzini 525f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 52649ab747fSPaolo Bonzini { 52749ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 52849ab747fSPaolo Bonzini desc[1] |= len; 52949ab747fSPaolo Bonzini } 53049ab747fSPaolo Bonzini 531f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 53263af1e0cSPeter Crosthwaite { 53363af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 53463af1e0cSPeter Crosthwaite } 53563af1e0cSPeter Crosthwaite 536f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 53763af1e0cSPeter Crosthwaite { 53863af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 53963af1e0cSPeter Crosthwaite } 54063af1e0cSPeter Crosthwaite 541f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 54263af1e0cSPeter Crosthwaite { 54363af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 54463af1e0cSPeter Crosthwaite } 54563af1e0cSPeter Crosthwaite 546f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 54763af1e0cSPeter Crosthwaite { 54863af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 54963af1e0cSPeter Crosthwaite sar_idx); 550a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 55163af1e0cSPeter Crosthwaite } 55263af1e0cSPeter Crosthwaite 55349ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 5546a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 55549ab747fSPaolo Bonzini 5567ca151c3SSai Pavan Boddu static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 5577ca151c3SSai Pavan Boddu { 5587ca151c3SSai Pavan Boddu uint32_t size; 55987a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, JUMBO_FRAMES)) { 560c755c943SLuc Michel size = s->regs[R_JUMBO_MAX_LEN]; 5617ca151c3SSai Pavan Boddu if (size > s->jumbo_max_len) { 5627ca151c3SSai Pavan Boddu size = s->jumbo_max_len; 5637ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 5647ca151c3SSai Pavan Boddu " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 5657ca151c3SSai Pavan Boddu } 5667ca151c3SSai Pavan Boddu } else if (tx) { 5677ca151c3SSai Pavan Boddu size = 1518; 5687ca151c3SSai Pavan Boddu } else { 56987a49c3fSLuc Michel size = FIELD_EX32(s->regs[R_NWCFG], 57087a49c3fSLuc Michel NWCFG, RECV_1536_BYTE_FRAMES) ? 1538 : 1518; 5717ca151c3SSai Pavan Boddu } 5727ca151c3SSai Pavan Boddu return size; 5737ca151c3SSai Pavan Boddu } 5747ca151c3SSai Pavan Boddu 57568dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 57668dbee3bSSai Pavan Boddu { 57768dbee3bSSai Pavan Boddu if (q == 0) { 578c755c943SLuc Michel s->regs[R_ISR] |= flag & ~(s->regs[R_IMR]); 57968dbee3bSSai Pavan Boddu } else { 580c755c943SLuc Michel s->regs[R_INT_Q1_STATUS + q - 1] |= flag & 581c755c943SLuc Michel ~(s->regs[R_INT_Q1_MASK + q - 1]); 58268dbee3bSSai Pavan Boddu } 58368dbee3bSSai Pavan Boddu } 58468dbee3bSSai Pavan Boddu 58549ab747fSPaolo Bonzini /* 58649ab747fSPaolo Bonzini * gem_init_register_masks: 58749ab747fSPaolo Bonzini * One time initialization. 58849ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 58949ab747fSPaolo Bonzini */ 590448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 59149ab747fSPaolo Bonzini { 5924c70e32fSSai Pavan Boddu unsigned int i; 59349ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 59449ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 595c755c943SLuc Michel s->regs_ro[R_NWCTRL] = 0xFFF80000; 596c755c943SLuc Michel s->regs_ro[R_NWSTATUS] = 0xFFFFFFFF; 597c755c943SLuc Michel s->regs_ro[R_DMACFG] = 0x8E00F000; 598c755c943SLuc Michel s->regs_ro[R_TXSTATUS] = 0xFFFFFE08; 599c755c943SLuc Michel s->regs_ro[R_RXQBASE] = 0x00000003; 600c755c943SLuc Michel s->regs_ro[R_TXQBASE] = 0x00000003; 601c755c943SLuc Michel s->regs_ro[R_RXSTATUS] = 0xFFFFFFF0; 602c755c943SLuc Michel s->regs_ro[R_ISR] = 0xFFFFFFFF; 603c755c943SLuc Michel s->regs_ro[R_IMR] = 0xFFFFFFFF; 604c755c943SLuc Michel s->regs_ro[R_MODID] = 0xFFFFFFFF; 6054c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 606c755c943SLuc Michel s->regs_ro[R_INT_Q1_STATUS + i] = 0xFFFFFFFF; 607c755c943SLuc Michel s->regs_ro[R_INT_Q1_ENABLE + i] = 0xFFFFF319; 608c755c943SLuc Michel s->regs_ro[R_INT_Q1_DISABLE + i] = 0xFFFFF319; 609c755c943SLuc Michel s->regs_ro[R_INT_Q1_MASK + i] = 0xFFFFFFFF; 6104c70e32fSSai Pavan Boddu } 61149ab747fSPaolo Bonzini 61249ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 61349ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 614c755c943SLuc Michel s->regs_rtc[R_ISR] = 0xFFFFFFFF; 6154c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 616c755c943SLuc Michel s->regs_rtc[R_INT_Q1_STATUS + i] = 0x00000CE6; 6174c70e32fSSai Pavan Boddu } 61849ab747fSPaolo Bonzini 61949ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 62049ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 621c755c943SLuc Michel s->regs_w1c[R_TXSTATUS] = 0x000001F7; 622c755c943SLuc Michel s->regs_w1c[R_RXSTATUS] = 0x0000000F; 62349ab747fSPaolo Bonzini 62449ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 62549ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 626c755c943SLuc Michel s->regs_wo[R_NWCTRL] = 0x00073E60; 627c755c943SLuc Michel s->regs_wo[R_IER] = 0x07FFFFFF; 628c755c943SLuc Michel s->regs_wo[R_IDR] = 0x07FFFFFF; 6294c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 630c755c943SLuc Michel s->regs_wo[R_INT_Q1_ENABLE + i] = 0x00000CE6; 631c755c943SLuc Michel s->regs_wo[R_INT_Q1_DISABLE + i] = 0x00000CE6; 6324c70e32fSSai Pavan Boddu } 63349ab747fSPaolo Bonzini } 63449ab747fSPaolo Bonzini 63549ab747fSPaolo Bonzini /* 63649ab747fSPaolo Bonzini * phy_update_link: 63749ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 63849ab747fSPaolo Bonzini */ 639448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 64049ab747fSPaolo Bonzini { 64149ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 64249ab747fSPaolo Bonzini 64349ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 64449ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 64549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 64649ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 64749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 64849ab747fSPaolo Bonzini } else { 64949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 65049ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 65149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 65249ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 65349ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 65449ab747fSPaolo Bonzini } 65549ab747fSPaolo Bonzini } 65649ab747fSPaolo Bonzini 657b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 65849ab747fSPaolo Bonzini { 659448f19e2SPeter Crosthwaite CadenceGEMState *s; 66067101725SAlistair Francis int i; 66149ab747fSPaolo Bonzini 66249ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 66349ab747fSPaolo Bonzini 66449ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 665bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_RECEIVE)) { 6663ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 6673ae5725fSPeter Crosthwaite s->can_rx_state = 1; 6683ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 6693ae5725fSPeter Crosthwaite } 670b8c4b67eSPhilippe Mathieu-Daudé return false; 67149ab747fSPaolo Bonzini } 67249ab747fSPaolo Bonzini 67367101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 674dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 675dacc0566SAlistair Francis break; 676dacc0566SAlistair Francis } 677dacc0566SAlistair Francis }; 678dacc0566SAlistair Francis 679dacc0566SAlistair Francis if (i == s->num_priority_queues) { 6808202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 6818202aa53SPeter Crosthwaite s->can_rx_state = 2; 682dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 6838202aa53SPeter Crosthwaite } 684b8c4b67eSPhilippe Mathieu-Daudé return false; 6858202aa53SPeter Crosthwaite } 6868202aa53SPeter Crosthwaite 6873ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 6883ae5725fSPeter Crosthwaite s->can_rx_state = 0; 68967101725SAlistair Francis DB_PRINT("can receive\n"); 6903ae5725fSPeter Crosthwaite } 691b8c4b67eSPhilippe Mathieu-Daudé return true; 69249ab747fSPaolo Bonzini } 69349ab747fSPaolo Bonzini 69449ab747fSPaolo Bonzini /* 69549ab747fSPaolo Bonzini * gem_update_int_status: 69649ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 69749ab747fSPaolo Bonzini */ 698448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 69949ab747fSPaolo Bonzini { 70067101725SAlistair Francis int i; 70167101725SAlistair Francis 702c755c943SLuc Michel qemu_set_irq(s->irq[0], !!s->regs[R_ISR]); 703596b6f51SAlistair Francis 70486a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 705c755c943SLuc Michel qemu_set_irq(s->irq[i], !!s->regs[R_INT_Q1_STATUS + i - 1]); 70649ab747fSPaolo Bonzini } 70749ab747fSPaolo Bonzini } 70849ab747fSPaolo Bonzini 70949ab747fSPaolo Bonzini /* 71049ab747fSPaolo Bonzini * gem_receive_updatestats: 71149ab747fSPaolo Bonzini * Increment receive statistics. 71249ab747fSPaolo Bonzini */ 713448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 71449ab747fSPaolo Bonzini unsigned bytes) 71549ab747fSPaolo Bonzini { 71649ab747fSPaolo Bonzini uint64_t octets; 71749ab747fSPaolo Bonzini 71849ab747fSPaolo Bonzini /* Total octets (bytes) received */ 719c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTRXLO]) << 32) | 720c755c943SLuc Michel s->regs[R_OCTRXHI]; 72149ab747fSPaolo Bonzini octets += bytes; 722c755c943SLuc Michel s->regs[R_OCTRXLO] = octets >> 32; 723c755c943SLuc Michel s->regs[R_OCTRXHI] = octets; 72449ab747fSPaolo Bonzini 72549ab747fSPaolo Bonzini /* Error-free Frames received */ 726c755c943SLuc Michel s->regs[R_RXCNT]++; 72749ab747fSPaolo Bonzini 72849ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 72949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 730c755c943SLuc Michel s->regs[R_RXBROADCNT]++; 73149ab747fSPaolo Bonzini } 73249ab747fSPaolo Bonzini 73349ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 73449ab747fSPaolo Bonzini if (packet[0] == 0x01) { 735c755c943SLuc Michel s->regs[R_RXMULTICNT]++; 73649ab747fSPaolo Bonzini } 73749ab747fSPaolo Bonzini 73849ab747fSPaolo Bonzini if (bytes <= 64) { 739c755c943SLuc Michel s->regs[R_RX64CNT]++; 74049ab747fSPaolo Bonzini } else if (bytes <= 127) { 741c755c943SLuc Michel s->regs[R_RX65CNT]++; 74249ab747fSPaolo Bonzini } else if (bytes <= 255) { 743c755c943SLuc Michel s->regs[R_RX128CNT]++; 74449ab747fSPaolo Bonzini } else if (bytes <= 511) { 745c755c943SLuc Michel s->regs[R_RX256CNT]++; 74649ab747fSPaolo Bonzini } else if (bytes <= 1023) { 747c755c943SLuc Michel s->regs[R_RX512CNT]++; 74849ab747fSPaolo Bonzini } else if (bytes <= 1518) { 749c755c943SLuc Michel s->regs[R_RX1024CNT]++; 75049ab747fSPaolo Bonzini } else { 751c755c943SLuc Michel s->regs[R_RX1519CNT]++; 75249ab747fSPaolo Bonzini } 75349ab747fSPaolo Bonzini } 75449ab747fSPaolo Bonzini 75549ab747fSPaolo Bonzini /* 75649ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 75749ab747fSPaolo Bonzini */ 75849ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 75949ab747fSPaolo Bonzini { 76049ab747fSPaolo Bonzini unsigned byte; 76149ab747fSPaolo Bonzini 76249ab747fSPaolo Bonzini byte = mac[bit / 8]; 76349ab747fSPaolo Bonzini byte >>= (bit & 0x7); 76449ab747fSPaolo Bonzini byte &= 1; 76549ab747fSPaolo Bonzini 76649ab747fSPaolo Bonzini return byte; 76749ab747fSPaolo Bonzini } 76849ab747fSPaolo Bonzini 76949ab747fSPaolo Bonzini /* 77049ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 77149ab747fSPaolo Bonzini */ 77249ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 77349ab747fSPaolo Bonzini { 77449ab747fSPaolo Bonzini int index_bit, mac_bit; 77549ab747fSPaolo Bonzini unsigned hash_index; 77649ab747fSPaolo Bonzini 77749ab747fSPaolo Bonzini hash_index = 0; 77849ab747fSPaolo Bonzini mac_bit = 5; 77949ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 78049ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 78149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 78249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 78349ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 78449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 78549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 78649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 78749ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 78849ab747fSPaolo Bonzini mac_bit--; 78949ab747fSPaolo Bonzini } 79049ab747fSPaolo Bonzini 79149ab747fSPaolo Bonzini return hash_index; 79249ab747fSPaolo Bonzini } 79349ab747fSPaolo Bonzini 79449ab747fSPaolo Bonzini /* 79549ab747fSPaolo Bonzini * gem_mac_address_filter: 79649ab747fSPaolo Bonzini * Accept or reject this destination address? 79749ab747fSPaolo Bonzini * Returns: 79849ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 79963af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 80063af1e0cSPeter Crosthwaite * others for various other modes of accept: 80163af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 80263af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 80349ab747fSPaolo Bonzini */ 804448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 80549ab747fSPaolo Bonzini { 80649ab747fSPaolo Bonzini uint8_t *gem_spaddr; 807fbc14a09STong Ho int i, is_mc; 80849ab747fSPaolo Bonzini 80949ab747fSPaolo Bonzini /* Promiscuous mode? */ 81087a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, PROMISC)) { 81163af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 81249ab747fSPaolo Bonzini } 81349ab747fSPaolo Bonzini 81449ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 81549ab747fSPaolo Bonzini /* Reject broadcast packets? */ 81687a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, NO_BROADCAST)) { 81749ab747fSPaolo Bonzini return GEM_RX_REJECT; 81849ab747fSPaolo Bonzini } 81963af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 82049ab747fSPaolo Bonzini } 82149ab747fSPaolo Bonzini 82249ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 823fbc14a09STong Ho is_mc = is_multicast_ether_addr(packet); 82487a49c3fSLuc Michel if ((is_mc && (FIELD_EX32(s->regs[R_NWCFG], NWCFG, MULTICAST_HASH_EN))) || 82587a49c3fSLuc Michel (!is_mc && FIELD_EX32(s->regs[R_NWCFG], NWCFG, UNICAST_HASH_EN))) { 826fbc14a09STong Ho uint64_t buckets; 82749ab747fSPaolo Bonzini unsigned hash_index; 82849ab747fSPaolo Bonzini 82949ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 830c755c943SLuc Michel buckets = ((uint64_t)s->regs[R_HASHHI] << 32) | s->regs[R_HASHLO]; 831fbc14a09STong Ho if ((buckets >> hash_index) & 1) { 832fbc14a09STong Ho return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 833fbc14a09STong Ho : GEM_RX_UNICAST_HASH_ACCEPT; 83449ab747fSPaolo Bonzini } 83549ab747fSPaolo Bonzini } 83649ab747fSPaolo Bonzini 83749ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 838c755c943SLuc Michel gem_spaddr = (uint8_t *)&(s->regs[R_SPADDR1LO]); 83963af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 84064eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 84163af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 84249ab747fSPaolo Bonzini } 84349ab747fSPaolo Bonzini } 84449ab747fSPaolo Bonzini 84549ab747fSPaolo Bonzini /* No address match; reject the packet */ 84649ab747fSPaolo Bonzini return GEM_RX_REJECT; 84749ab747fSPaolo Bonzini } 84849ab747fSPaolo Bonzini 849e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 850e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 851e8e49943SAlistair Francis unsigned rxbufsize) 852e8e49943SAlistair Francis { 853e8e49943SAlistair Francis uint32_t reg; 854e8e49943SAlistair Francis bool matched, mismatched; 855e8e49943SAlistair Francis int i, j; 856e8e49943SAlistair Francis 857e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 858c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE1_REG0 + i]; 859e8e49943SAlistair Francis matched = false; 860e8e49943SAlistair Francis mismatched = false; 861e8e49943SAlistair Francis 862e8e49943SAlistair Francis /* Screening is based on UDP Port */ 863b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH_EN)) { 864e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 865b46b526cSLuc Michel if (udp_port == FIELD_EX32(reg, SCREENING_TYPE1_REG0, UDP_PORT_MATCH)) { 866e8e49943SAlistair Francis matched = true; 867e8e49943SAlistair Francis } else { 868e8e49943SAlistair Francis mismatched = true; 869e8e49943SAlistair Francis } 870e8e49943SAlistair Francis } 871e8e49943SAlistair Francis 872e8e49943SAlistair Francis /* Screening is based on DS/TC */ 873b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_ENABLE)) { 874e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 875b46b526cSLuc Michel if (dscp == FIELD_EX32(reg, SCREENING_TYPE1_REG0, DSTC_MATCH)) { 876e8e49943SAlistair Francis matched = true; 877e8e49943SAlistair Francis } else { 878e8e49943SAlistair Francis mismatched = true; 879e8e49943SAlistair Francis } 880e8e49943SAlistair Francis } 881e8e49943SAlistair Francis 882e8e49943SAlistair Francis if (matched && !mismatched) { 883b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE1_REG0, QUEUE_NUM); 884e8e49943SAlistair Francis } 885e8e49943SAlistair Francis } 886e8e49943SAlistair Francis 887e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 888c755c943SLuc Michel reg = s->regs[R_SCREENING_TYPE2_REG0 + i]; 889e8e49943SAlistair Francis matched = false; 890e8e49943SAlistair Francis mismatched = false; 891e8e49943SAlistair Francis 892b46b526cSLuc Michel if (FIELD_EX32(reg, SCREENING_TYPE2_REG0, ETHERTYPE_ENABLE)) { 893e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 894b46b526cSLuc Michel int et_idx = FIELD_EX32(reg, SCREENING_TYPE2_REG0, 895b46b526cSLuc Michel ETHERTYPE_REG_INDEX); 896e8e49943SAlistair Francis 897e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 898e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 899e8e49943SAlistair Francis "register index: %d\n", et_idx); 900e8e49943SAlistair Francis } 901c755c943SLuc Michel if (type == s->regs[R_SCREENING_TYPE2_ETHERTYPE_REG0 + 902e8e49943SAlistair Francis et_idx]) { 903e8e49943SAlistair Francis matched = true; 904e8e49943SAlistair Francis } else { 905e8e49943SAlistair Francis mismatched = true; 906e8e49943SAlistair Francis } 907e8e49943SAlistair Francis } 908e8e49943SAlistair Francis 909e8e49943SAlistair Francis /* Compare A, B, C */ 910e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 911b46b526cSLuc Michel uint32_t cr0, cr1, mask, compare; 912e8e49943SAlistair Francis uint16_t rx_cmp; 913e8e49943SAlistair Francis int offset; 914b46b526cSLuc Michel int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, 915b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); 916e8e49943SAlistair Francis 917b46b526cSLuc Michel if (!extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_SHIFT + j * 6, 918b46b526cSLuc Michel R_SCREENING_TYPE2_REG0_COMPARE_A_ENABLE_LENGTH)) { 919e8e49943SAlistair Francis continue; 920e8e49943SAlistair Francis } 921b46b526cSLuc Michel 922e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 923e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 924e8e49943SAlistair Francis "register index: %d\n", cr_idx); 925e8e49943SAlistair Francis } 926e8e49943SAlistair Francis 927c755c943SLuc Michel cr0 = s->regs[R_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 928b46b526cSLuc Michel cr1 = s->regs[R_TYPE2_COMPARE_0_WORD_1 + cr_idx * 2]; 929b46b526cSLuc Michel offset = FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, OFFSET_VALUE); 930e8e49943SAlistair Francis 931b46b526cSLuc Michel switch (FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, COMPARE_OFFSET)) { 932e8e49943SAlistair Francis case 3: /* Skip UDP header */ 933e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 934e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 935e8e49943SAlistair Francis offset += 8; 936e8e49943SAlistair Francis /* Fallthrough */ 937e8e49943SAlistair Francis case 2: /* skip the IP header */ 938e8e49943SAlistair Francis offset += 20; 939e8e49943SAlistair Francis /* Fallthrough */ 940e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 941e8e49943SAlistair Francis offset += 14; 942e8e49943SAlistair Francis break; 943e8e49943SAlistair Francis case 0: 944e8e49943SAlistair Francis /* Offset from start of frame */ 945e8e49943SAlistair Francis break; 946e8e49943SAlistair Francis } 947e8e49943SAlistair Francis 948e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 949b46b526cSLuc Michel mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); 950b46b526cSLuc Michel compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); 951e8e49943SAlistair Francis 952b46b526cSLuc Michel if ((rx_cmp & mask) == (compare & mask)) { 953e8e49943SAlistair Francis matched = true; 954e8e49943SAlistair Francis } else { 955e8e49943SAlistair Francis mismatched = true; 956e8e49943SAlistair Francis } 957e8e49943SAlistair Francis } 958e8e49943SAlistair Francis 959e8e49943SAlistair Francis if (matched && !mismatched) { 960b46b526cSLuc Michel return FIELD_EX32(reg, SCREENING_TYPE2_REG0, QUEUE_NUM); 961e8e49943SAlistair Francis } 962e8e49943SAlistair Francis } 963e8e49943SAlistair Francis 964e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 965e8e49943SAlistair Francis return 0; 966e8e49943SAlistair Francis } 967e8e49943SAlistair Francis 96896ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 96996ea126aSSai Pavan Boddu { 97096ea126aSSai Pavan Boddu uint32_t base_addr = 0; 97196ea126aSSai Pavan Boddu 97296ea126aSSai Pavan Boddu switch (q) { 97396ea126aSSai Pavan Boddu case 0: 974c755c943SLuc Michel base_addr = s->regs[tx ? R_TXQBASE : R_RXQBASE]; 97596ea126aSSai Pavan Boddu break; 97696ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 977c755c943SLuc Michel base_addr = s->regs[(tx ? R_TRANSMIT_Q1_PTR : 978c755c943SLuc Michel R_RECEIVE_Q1_PTR) + q - 1]; 97996ea126aSSai Pavan Boddu break; 98096ea126aSSai Pavan Boddu default: 98196ea126aSSai Pavan Boddu g_assert_not_reached(); 98296ea126aSSai Pavan Boddu }; 98396ea126aSSai Pavan Boddu 98496ea126aSSai Pavan Boddu return base_addr; 98596ea126aSSai Pavan Boddu } 98696ea126aSSai Pavan Boddu 98796ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 98896ea126aSSai Pavan Boddu { 98996ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 99096ea126aSSai Pavan Boddu } 99196ea126aSSai Pavan Boddu 99296ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 99396ea126aSSai Pavan Boddu { 99496ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 99596ea126aSSai Pavan Boddu } 99696ea126aSSai Pavan Boddu 997357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 998357aa013SEdgar E. Iglesias { 999357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 1000357aa013SEdgar E. Iglesias 100101f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 1002c755c943SLuc Michel desc_addr = s->regs[tx ? R_TBQPH : R_RBQPH]; 1003357aa013SEdgar E. Iglesias } 1004357aa013SEdgar E. Iglesias desc_addr <<= 32; 1005357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 1006357aa013SEdgar E. Iglesias return desc_addr; 1007357aa013SEdgar E. Iglesias } 1008357aa013SEdgar E. Iglesias 1009357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 1010357aa013SEdgar E. Iglesias { 1011357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 1012357aa013SEdgar E. Iglesias } 1013357aa013SEdgar E. Iglesias 1014357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 1015357aa013SEdgar E. Iglesias { 1016357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 1017357aa013SEdgar E. Iglesias } 1018357aa013SEdgar E. Iglesias 101967101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 102006c2fe95SPeter Crosthwaite { 1021357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 1022357aa013SEdgar E. Iglesias 1023357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 1024357aa013SEdgar E. Iglesias 102506c2fe95SPeter Crosthwaite /* read current descriptor */ 1026357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1027b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1028e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 102906c2fe95SPeter Crosthwaite 103006c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 103167101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 1032357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 1033466da857SLuc Michel s->regs[R_RXSTATUS] |= R_RXSTATUS_BUF_NOT_AVAILABLE_MASK; 1034987e8060SLuc Michel gem_set_isr(s, q, R_ISR_RX_USED_MASK); 103506c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 103606c2fe95SPeter Crosthwaite gem_update_int_status(s); 103706c2fe95SPeter Crosthwaite } 103806c2fe95SPeter Crosthwaite } 103906c2fe95SPeter Crosthwaite 104049ab747fSPaolo Bonzini /* 104149ab747fSPaolo Bonzini * gem_receive: 104249ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 104349ab747fSPaolo Bonzini */ 104449ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 104549ab747fSPaolo Bonzini { 104624d62fd5SSai Pavan Boddu CadenceGEMState *s = qemu_get_nic_opaque(nc); 104749ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 104849ab747fSPaolo Bonzini unsigned rxbuf_offset; 104949ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 10503b2c97f9SEdgar E. Iglesias bool first_desc = true; 105163af1e0cSPeter Crosthwaite int maf; 10522bf57f73SAlistair Francis int q = 0; 105349ab747fSPaolo Bonzini 105449ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 105563af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 105663af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 10572431f4f1SMichael Tokarev return size; /* no, drop silently b/c it's not an error */ 105849ab747fSPaolo Bonzini } 105949ab747fSPaolo Bonzini 106049ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 106187a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, LEN_ERR_DISCARD)) { 106249ab747fSPaolo Bonzini unsigned type_len; 106349ab747fSPaolo Bonzini 106449ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 106549ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 106649ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 106749ab747fSPaolo Bonzini if (type_len < 0x600) { 106849ab747fSPaolo Bonzini if (size < type_len) { 106949ab747fSPaolo Bonzini /* discard */ 107049ab747fSPaolo Bonzini return -1; 107149ab747fSPaolo Bonzini } 107249ab747fSPaolo Bonzini } 107349ab747fSPaolo Bonzini } 107449ab747fSPaolo Bonzini 107549ab747fSPaolo Bonzini /* 107649ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 107749ab747fSPaolo Bonzini */ 107887a49c3fSLuc Michel rxbuf_offset = FIELD_EX32(s->regs[R_NWCFG], NWCFG, RECV_BUF_OFFSET); 107949ab747fSPaolo Bonzini 108049ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 108149ab747fSPaolo Bonzini * buffers needed to hold this packet. 108249ab747fSPaolo Bonzini */ 108301f9175dSLuc Michel rxbufsize = FIELD_EX32(s->regs[R_DMACFG], DMACFG, RX_BUF_SIZE); 108401f9175dSLuc Michel rxbufsize *= GEM_DMACFG_RBUFSZ_MUL; 108501f9175dSLuc Michel 108649ab747fSPaolo Bonzini bytes_to_copy = size; 108749ab747fSPaolo Bonzini 1088f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 1089f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 1090f265ae8cSAlistair Francis */ 1091f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 1092f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 1093f265ae8cSAlistair Francis } 1094f265ae8cSAlistair Francis 1095191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 1096191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 1097191946c5SPeter Crosthwaite * not FCS stripping 1098191946c5SPeter Crosthwaite */ 1099191946c5SPeter Crosthwaite if (size < 60) { 1100191946c5SPeter Crosthwaite size = 60; 1101191946c5SPeter Crosthwaite } 1102191946c5SPeter Crosthwaite 110349ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 110487a49c3fSLuc Michel if (FIELD_EX32(s->regs[R_NWCFG], NWCFG, FCS_REMOVE)) { 110549ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 110649ab747fSPaolo Bonzini } else { 110749ab747fSPaolo Bonzini unsigned crc_val; 110849ab747fSPaolo Bonzini 110924d62fd5SSai Pavan Boddu if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 111024d62fd5SSai Pavan Boddu size = MAX_FRAME_SIZE - sizeof(crc_val); 1111244381ecSPrasad J Pandit } 1112244381ecSPrasad J Pandit bytes_to_copy = size; 111349ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 11143048ed6aSPeter Crosthwaite * We must try and calculate one. 111549ab747fSPaolo Bonzini */ 111649ab747fSPaolo Bonzini 111724d62fd5SSai Pavan Boddu memcpy(s->rx_packet, buf, size); 111824d62fd5SSai Pavan Boddu memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 111924d62fd5SSai Pavan Boddu rxbuf_ptr = s->rx_packet; 112024d62fd5SSai Pavan Boddu crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 112124d62fd5SSai Pavan Boddu memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 112249ab747fSPaolo Bonzini 112349ab747fSPaolo Bonzini bytes_to_copy += 4; 112449ab747fSPaolo Bonzini size += 4; 112549ab747fSPaolo Bonzini } 112649ab747fSPaolo Bonzini 11276fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 112849ab747fSPaolo Bonzini 1129b12227afSStefan Weil /* Find which queue we are targeting */ 1130e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1131e8e49943SAlistair Francis 11327ca151c3SSai Pavan Boddu if (size > gem_get_max_buf_len(s, false)) { 11337ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 1134987e8060SLuc Michel gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK); 11357ca151c3SSai Pavan Boddu return -1; 11367ca151c3SSai Pavan Boddu } 11377ca151c3SSai Pavan Boddu 11387cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1139357aa013SEdgar E. Iglesias hwaddr desc_addr; 1140357aa013SEdgar E. Iglesias 114106c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 114206c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 114349ab747fSPaolo Bonzini return -1; 114449ab747fSPaolo Bonzini } 114549ab747fSPaolo Bonzini 11466fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1147dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1148dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 114949ab747fSPaolo Bonzini 115049ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 115184aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 11522bf57f73SAlistair Francis rxbuf_offset, 115384aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1154e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 115549ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 115630570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 11573b2c97f9SEdgar E. Iglesias 115859ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 115959ab136aSRamon Fried 11603b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 11613b2c97f9SEdgar E. Iglesias if (first_desc) { 11622bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 11633b2c97f9SEdgar E. Iglesias first_desc = false; 11643b2c97f9SEdgar E. Iglesias } 11653b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 11662bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 11672bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 11683b2c97f9SEdgar E. Iglesias } 11692bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 117063af1e0cSPeter Crosthwaite 117163af1e0cSPeter Crosthwaite switch (maf) { 117263af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 117363af1e0cSPeter Crosthwaite break; 117463af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 11752bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 117663af1e0cSPeter Crosthwaite break; 117763af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 11782bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 117963af1e0cSPeter Crosthwaite break; 118063af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 11812bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 118263af1e0cSPeter Crosthwaite break; 118363af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 118463af1e0cSPeter Crosthwaite abort(); 118563af1e0cSPeter Crosthwaite default: /* SAR */ 11862bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 118763af1e0cSPeter Crosthwaite } 118863af1e0cSPeter Crosthwaite 11893b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1190357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1191b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1192b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1193e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 11943b2c97f9SEdgar E. Iglesias 119549ab747fSPaolo Bonzini /* Next descriptor */ 11962bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 119749ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 119896ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 119949ab747fSPaolo Bonzini } else { 120049ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1201e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 120249ab747fSPaolo Bonzini } 120367101725SAlistair Francis 120467101725SAlistair Francis gem_get_rx_desc(s, q); 12057cfd65e4SPeter Crosthwaite } 120649ab747fSPaolo Bonzini 120749ab747fSPaolo Bonzini /* Count it */ 120849ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 120949ab747fSPaolo Bonzini 1210466da857SLuc Michel s->regs[R_RXSTATUS] |= R_RXSTATUS_FRAME_RECEIVED_MASK; 1211987e8060SLuc Michel gem_set_isr(s, q, R_ISR_RECV_COMPLETE_MASK); 121249ab747fSPaolo Bonzini 121349ab747fSPaolo Bonzini /* Handle interrupt consequences */ 121449ab747fSPaolo Bonzini gem_update_int_status(s); 121549ab747fSPaolo Bonzini 121649ab747fSPaolo Bonzini return size; 121749ab747fSPaolo Bonzini } 121849ab747fSPaolo Bonzini 121949ab747fSPaolo Bonzini /* 122049ab747fSPaolo Bonzini * gem_transmit_updatestats: 122149ab747fSPaolo Bonzini * Increment transmit statistics. 122249ab747fSPaolo Bonzini */ 1223448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 122449ab747fSPaolo Bonzini unsigned bytes) 122549ab747fSPaolo Bonzini { 122649ab747fSPaolo Bonzini uint64_t octets; 122749ab747fSPaolo Bonzini 122849ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 1229c755c943SLuc Michel octets = ((uint64_t)(s->regs[R_OCTTXLO]) << 32) | 1230c755c943SLuc Michel s->regs[R_OCTTXHI]; 123149ab747fSPaolo Bonzini octets += bytes; 1232c755c943SLuc Michel s->regs[R_OCTTXLO] = octets >> 32; 1233c755c943SLuc Michel s->regs[R_OCTTXHI] = octets; 123449ab747fSPaolo Bonzini 123549ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 1236c755c943SLuc Michel s->regs[R_TXCNT]++; 123749ab747fSPaolo Bonzini 123849ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 123949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 1240c755c943SLuc Michel s->regs[R_TXBCNT]++; 124149ab747fSPaolo Bonzini } 124249ab747fSPaolo Bonzini 124349ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 124449ab747fSPaolo Bonzini if (packet[0] == 0x01) { 1245c755c943SLuc Michel s->regs[R_TXMCNT]++; 124649ab747fSPaolo Bonzini } 124749ab747fSPaolo Bonzini 124849ab747fSPaolo Bonzini if (bytes <= 64) { 1249c755c943SLuc Michel s->regs[R_TX64CNT]++; 125049ab747fSPaolo Bonzini } else if (bytes <= 127) { 1251c755c943SLuc Michel s->regs[R_TX65CNT]++; 125249ab747fSPaolo Bonzini } else if (bytes <= 255) { 1253c755c943SLuc Michel s->regs[R_TX128CNT]++; 125449ab747fSPaolo Bonzini } else if (bytes <= 511) { 1255c755c943SLuc Michel s->regs[R_TX256CNT]++; 125649ab747fSPaolo Bonzini } else if (bytes <= 1023) { 1257c755c943SLuc Michel s->regs[R_TX512CNT]++; 125849ab747fSPaolo Bonzini } else if (bytes <= 1518) { 1259c755c943SLuc Michel s->regs[R_TX1024CNT]++; 126049ab747fSPaolo Bonzini } else { 1261c755c943SLuc Michel s->regs[R_TX1519CNT]++; 126249ab747fSPaolo Bonzini } 126349ab747fSPaolo Bonzini } 126449ab747fSPaolo Bonzini 126549ab747fSPaolo Bonzini /* 126649ab747fSPaolo Bonzini * gem_transmit: 126749ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 126849ab747fSPaolo Bonzini */ 1269448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 127049ab747fSPaolo Bonzini { 12718568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 127249ab747fSPaolo Bonzini hwaddr packet_desc_addr; 127349ab747fSPaolo Bonzini uint8_t *p; 127449ab747fSPaolo Bonzini unsigned total_bytes; 12752bf57f73SAlistair Francis int q = 0; 127649ab747fSPaolo Bonzini 127749ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1278bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 127949ab747fSPaolo Bonzini return; 128049ab747fSPaolo Bonzini } 128149ab747fSPaolo Bonzini 128249ab747fSPaolo Bonzini DB_PRINT("\n"); 128349ab747fSPaolo Bonzini 12843048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 128549ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 128649ab747fSPaolo Bonzini * one contiguous buffer first. 128749ab747fSPaolo Bonzini */ 128824d62fd5SSai Pavan Boddu p = s->tx_packet; 128949ab747fSPaolo Bonzini total_bytes = 0; 129049ab747fSPaolo Bonzini 129167101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 129249ab747fSPaolo Bonzini /* read current descriptor */ 1293357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1294fa15286aSPeter Crosthwaite 1295fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 129684aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1297b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1298e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 129949ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 130049ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 130149ab747fSPaolo Bonzini 130249ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 1303bd8a922dSLuc Michel if (!FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, ENABLE_TRANSMIT)) { 130449ab747fSPaolo Bonzini return; 130549ab747fSPaolo Bonzini } 130667101725SAlistair Francis print_gem_tx_desc(desc, q); 130749ab747fSPaolo Bonzini 130849ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 130949ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 131049ab747fSPaolo Bonzini */ 1311e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 131249ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 13136fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 13146fe7661dSSai Pavan Boddu packet_desc_addr); 131549ab747fSPaolo Bonzini break; 131649ab747fSPaolo Bonzini } 131749ab747fSPaolo Bonzini 13187ca151c3SSai Pavan Boddu if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 131924d62fd5SSai Pavan Boddu (p - s->tx_packet)) { 13207ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 13217ca151c3SSai Pavan Boddu HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1322dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 13237ca151c3SSai Pavan Boddu gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 1324987e8060SLuc Michel gem_set_isr(s, q, R_ISR_AMBA_ERROR_MASK); 1325d7f05365SMichael S. Tsirkin break; 1326d7f05365SMichael S. Tsirkin } 1327d7f05365SMichael S. Tsirkin 132877524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 132977524d11SAlistair Francis * contig buffer. 133049ab747fSPaolo Bonzini */ 133184aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 133284aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 133384aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 133449ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 133549ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 133649ab747fSPaolo Bonzini 133749ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 133849ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 13398568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1340357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 13416ab57a6bSPeter Crosthwaite 134249ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 134349ab747fSPaolo Bonzini * the processor. 134449ab747fSPaolo Bonzini */ 1345357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1346b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 13476ab57a6bSPeter Crosthwaite sizeof(desc_first)); 13486ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1349357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1350b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 13516ab57a6bSPeter Crosthwaite sizeof(desc_first)); 13523048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 135349ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 135496ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 135549ab747fSPaolo Bonzini } else { 1356e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1357e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 135849ab747fSPaolo Bonzini } 13592bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 136049ab747fSPaolo Bonzini 1361466da857SLuc Michel s->regs[R_TXSTATUS] |= R_TXSTATUS_TRANSMIT_COMPLETE_MASK; 1362987e8060SLuc Michel gem_set_isr(s, q, R_ISR_XMIT_COMPLETE_MASK); 136367101725SAlistair Francis 136449ab747fSPaolo Bonzini /* Handle interrupt consequences */ 136549ab747fSPaolo Bonzini gem_update_int_status(s); 136649ab747fSPaolo Bonzini 136749ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 136801f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, TX_PBUF_CSUM_OFFLOAD)) { 1369f5746335SBin Meng net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 137049ab747fSPaolo Bonzini } 137149ab747fSPaolo Bonzini 137249ab747fSPaolo Bonzini /* Update MAC statistics */ 137324d62fd5SSai Pavan Boddu gem_transmit_updatestats(s, s->tx_packet, total_bytes); 137449ab747fSPaolo Bonzini 137549ab747fSPaolo Bonzini /* Send the packet somewhere */ 1376bd8a922dSLuc Michel if (s->phy_loop || FIELD_EX32(s->regs[R_NWCTRL], NWCTRL, 1377bd8a922dSLuc Michel LOOPBACK_LOCAL)) { 1378e73adfbeSAlexander Bulekov qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 137977524d11SAlistair Francis total_bytes); 138049ab747fSPaolo Bonzini } else { 138124d62fd5SSai Pavan Boddu qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 138249ab747fSPaolo Bonzini total_bytes); 138349ab747fSPaolo Bonzini } 138449ab747fSPaolo Bonzini 138549ab747fSPaolo Bonzini /* Prepare for next packet */ 138624d62fd5SSai Pavan Boddu p = s->tx_packet; 138749ab747fSPaolo Bonzini total_bytes = 0; 138849ab747fSPaolo Bonzini } 138949ab747fSPaolo Bonzini 139049ab747fSPaolo Bonzini /* read next descriptor */ 139149ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 139201f9175dSLuc Michel if (FIELD_EX32(s->regs[R_DMACFG], DMACFG, DMA_ADDR_BUS_WIDTH)) { 1393c755c943SLuc Michel packet_desc_addr = s->regs[R_TBQPH]; 1394f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1395f1e7cb13SRamon Fried } else { 1396f1e7cb13SRamon Fried packet_desc_addr = 0; 1397f1e7cb13SRamon Fried } 139896ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 139949ab747fSPaolo Bonzini } else { 1400e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 140149ab747fSPaolo Bonzini } 1402fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 140384aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1404b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1405e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 140649ab747fSPaolo Bonzini } 140749ab747fSPaolo Bonzini 140849ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 1409466da857SLuc Michel s->regs[R_TXSTATUS] |= R_TXSTATUS_USED_BIT_READ_MASK; 141068dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 141168dbee3bSSai Pavan Boddu if (q == 0) { 1412987e8060SLuc Michel gem_set_isr(s, 0, R_ISR_TX_USED_MASK); 141368dbee3bSSai Pavan Boddu } 141449ab747fSPaolo Bonzini gem_update_int_status(s); 141549ab747fSPaolo Bonzini } 141649ab747fSPaolo Bonzini } 141767101725SAlistair Francis } 141849ab747fSPaolo Bonzini 1419448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 142049ab747fSPaolo Bonzini { 142149ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 142249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 142349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 142449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 142549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 142649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 142749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 142849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 142949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 143049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 143149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 143249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 143349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 143449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 14357777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 143649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 143749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 143849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 143949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 144049ab747fSPaolo Bonzini 144149ab747fSPaolo Bonzini phy_update_link(s); 144249ab747fSPaolo Bonzini } 144349ab747fSPaolo Bonzini 144449ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 144549ab747fSPaolo Bonzini { 144664eb9301SPeter Crosthwaite int i; 1447448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1448afb4c51fSSebastian Huber const uint8_t *a; 1449726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 145049ab747fSPaolo Bonzini 145149ab747fSPaolo Bonzini DB_PRINT("\n"); 145249ab747fSPaolo Bonzini 145349ab747fSPaolo Bonzini /* Set post reset register values */ 145449ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 1455c755c943SLuc Michel s->regs[R_NWCFG] = 0x00080000; 1456c755c943SLuc Michel s->regs[R_NWSTATUS] = 0x00000006; 1457c755c943SLuc Michel s->regs[R_DMACFG] = 0x00020784; 1458c755c943SLuc Michel s->regs[R_IMR] = 0x07ffffff; 1459c755c943SLuc Michel s->regs[R_TXPAUSE] = 0x0000ffff; 1460c755c943SLuc Michel s->regs[R_TXPARTIALSF] = 0x000003ff; 1461c755c943SLuc Michel s->regs[R_RXPARTIALSF] = 0x000003ff; 1462c755c943SLuc Michel s->regs[R_MODID] = s->revision; 1463c755c943SLuc Michel s->regs[R_DESCONF] = 0x02D00111; 1464c755c943SLuc Michel s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1465c755c943SLuc Michel s->regs[R_DESCONF5] = 0x002f2045; 1466ce077875SLuc Michel s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK; 1467c755c943SLuc Michel s->regs[R_INT_Q1_MASK] = 0x00000CE6; 1468c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = s->jumbo_max_len; 1469726a2a95SEdgar E. Iglesias 1470726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1471726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1472c755c943SLuc Michel s->regs[R_DESCONF6] |= queues_mask; 1473726a2a95SEdgar E. Iglesias } 147449ab747fSPaolo Bonzini 1475afb4c51fSSebastian Huber /* Set MAC address */ 1476afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1477c755c943SLuc Michel s->regs[R_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1478c755c943SLuc Michel s->regs[R_SPADDR1HI] = a[4] | (a[5] << 8); 1479afb4c51fSSebastian Huber 148064eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 148164eb9301SPeter Crosthwaite s->sar_active[i] = false; 148264eb9301SPeter Crosthwaite } 148364eb9301SPeter Crosthwaite 148449ab747fSPaolo Bonzini gem_phy_reset(s); 148549ab747fSPaolo Bonzini 148649ab747fSPaolo Bonzini gem_update_int_status(s); 148749ab747fSPaolo Bonzini } 148849ab747fSPaolo Bonzini 1489448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 149049ab747fSPaolo Bonzini { 149149ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 149249ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 149349ab747fSPaolo Bonzini } 149449ab747fSPaolo Bonzini 1495448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 149649ab747fSPaolo Bonzini { 149749ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 149849ab747fSPaolo Bonzini 149949ab747fSPaolo Bonzini switch (reg_num) { 150049ab747fSPaolo Bonzini case PHY_REG_CONTROL: 150149ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 150249ab747fSPaolo Bonzini /* Phy reset */ 150349ab747fSPaolo Bonzini gem_phy_reset(s); 150449ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 150549ab747fSPaolo Bonzini s->phy_loop = 0; 150649ab747fSPaolo Bonzini } 150749ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 150849ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 15096623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 151049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 151149ab747fSPaolo Bonzini } 151249ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 151349ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 151449ab747fSPaolo Bonzini s->phy_loop = 1; 151549ab747fSPaolo Bonzini } else { 151649ab747fSPaolo Bonzini s->phy_loop = 0; 151749ab747fSPaolo Bonzini } 151849ab747fSPaolo Bonzini break; 151949ab747fSPaolo Bonzini } 152049ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 152149ab747fSPaolo Bonzini } 152249ab747fSPaolo Bonzini 152349ab747fSPaolo Bonzini /* 152449ab747fSPaolo Bonzini * gem_read32: 152549ab747fSPaolo Bonzini * Read a GEM register. 152649ab747fSPaolo Bonzini */ 152749ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 152849ab747fSPaolo Bonzini { 1529448f19e2SPeter Crosthwaite CadenceGEMState *s; 153049ab747fSPaolo Bonzini uint32_t retval; 15313d558330SMarkus Armbruster s = opaque; 153249ab747fSPaolo Bonzini 153349ab747fSPaolo Bonzini offset >>= 2; 153449ab747fSPaolo Bonzini retval = s->regs[offset]; 153549ab747fSPaolo Bonzini 153649ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 153749ab747fSPaolo Bonzini 153849ab747fSPaolo Bonzini switch (offset) { 1539c755c943SLuc Michel case R_ISR: 154067101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1541596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 154249ab747fSPaolo Bonzini break; 1543c755c943SLuc Michel case R_PHYMNTNC: 154449ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 154549ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 154649ab747fSPaolo Bonzini 154749ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1548dfc38879SBin Meng if (phy_addr == s->phy_addr) { 154949ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 155049ab747fSPaolo Bonzini retval &= 0xFFFF0000; 155149ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 155249ab747fSPaolo Bonzini } else { 155349ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 155449ab747fSPaolo Bonzini } 155549ab747fSPaolo Bonzini } 155649ab747fSPaolo Bonzini break; 155749ab747fSPaolo Bonzini } 155849ab747fSPaolo Bonzini 155949ab747fSPaolo Bonzini /* Squash read to clear bits */ 156049ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 156149ab747fSPaolo Bonzini 156249ab747fSPaolo Bonzini /* Do not provide write only bits */ 156349ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 156449ab747fSPaolo Bonzini 156549ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 156667101725SAlistair Francis gem_update_int_status(s); 156749ab747fSPaolo Bonzini return retval; 156849ab747fSPaolo Bonzini } 156949ab747fSPaolo Bonzini 157049ab747fSPaolo Bonzini /* 157149ab747fSPaolo Bonzini * gem_write32: 157249ab747fSPaolo Bonzini * Write a GEM register. 157349ab747fSPaolo Bonzini */ 157449ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 157549ab747fSPaolo Bonzini unsigned size) 157649ab747fSPaolo Bonzini { 1577448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 157849ab747fSPaolo Bonzini uint32_t readonly; 157967101725SAlistair Francis int i; 158049ab747fSPaolo Bonzini 158149ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 158249ab747fSPaolo Bonzini offset >>= 2; 158349ab747fSPaolo Bonzini 158449ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 158549ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1586e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1587e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 158849ab747fSPaolo Bonzini 158949ab747fSPaolo Bonzini /* Copy register write to backing store */ 1590e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1591e2314fdaSPeter Crosthwaite 1592e2314fdaSPeter Crosthwaite /* do w1c */ 1593e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 159449ab747fSPaolo Bonzini 159549ab747fSPaolo Bonzini /* Handle register write side effects */ 159649ab747fSPaolo Bonzini switch (offset) { 1597c755c943SLuc Michel case R_NWCTRL: 1598bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, ENABLE_RECEIVE)) { 159967101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 160067101725SAlistair Francis gem_get_rx_desc(s, i); 160167101725SAlistair Francis } 160206c2fe95SPeter Crosthwaite } 1603bd8a922dSLuc Michel if (FIELD_EX32(val, NWCTRL, TRANSMIT_START)) { 160449ab747fSPaolo Bonzini gem_transmit(s); 160549ab747fSPaolo Bonzini } 1606bd8a922dSLuc Michel if (!(FIELD_EX32(val, NWCTRL, ENABLE_TRANSMIT))) { 160749ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 160867101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 160996ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 161067101725SAlistair Francis } 161149ab747fSPaolo Bonzini } 16128202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 161349ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 161449ab747fSPaolo Bonzini } 161549ab747fSPaolo Bonzini break; 161649ab747fSPaolo Bonzini 1617c755c943SLuc Michel case R_TXSTATUS: 161849ab747fSPaolo Bonzini gem_update_int_status(s); 161949ab747fSPaolo Bonzini break; 1620c755c943SLuc Michel case R_RXQBASE: 16212bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 162249ab747fSPaolo Bonzini break; 1623c755c943SLuc Michel case R_RECEIVE_Q1_PTR ... R_RECEIVE_Q7_PTR: 1624c755c943SLuc Michel s->rx_desc_addr[offset - R_RECEIVE_Q1_PTR + 1] = val; 162567101725SAlistair Francis break; 1626c755c943SLuc Michel case R_TXQBASE: 16272bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 162849ab747fSPaolo Bonzini break; 1629c755c943SLuc Michel case R_TRANSMIT_Q1_PTR ... R_TRANSMIT_Q7_PTR: 1630c755c943SLuc Michel s->tx_desc_addr[offset - R_TRANSMIT_Q1_PTR + 1] = val; 163167101725SAlistair Francis break; 1632c755c943SLuc Michel case R_RXSTATUS: 163349ab747fSPaolo Bonzini gem_update_int_status(s); 163449ab747fSPaolo Bonzini break; 1635c755c943SLuc Michel case R_IER: 1636c755c943SLuc Michel s->regs[R_IMR] &= ~val; 163749ab747fSPaolo Bonzini gem_update_int_status(s); 163849ab747fSPaolo Bonzini break; 1639c755c943SLuc Michel case R_JUMBO_MAX_LEN: 1640c755c943SLuc Michel s->regs[R_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 16417ca151c3SSai Pavan Boddu break; 1642c755c943SLuc Michel case R_INT_Q1_ENABLE ... R_INT_Q7_ENABLE: 1643c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_ENABLE] &= ~val; 164467101725SAlistair Francis gem_update_int_status(s); 164567101725SAlistair Francis break; 1646c755c943SLuc Michel case R_IDR: 1647c755c943SLuc Michel s->regs[R_IMR] |= val; 164849ab747fSPaolo Bonzini gem_update_int_status(s); 164949ab747fSPaolo Bonzini break; 1650c755c943SLuc Michel case R_INT_Q1_DISABLE ... R_INT_Q7_DISABLE: 1651c755c943SLuc Michel s->regs[R_INT_Q1_MASK + offset - R_INT_Q1_DISABLE] |= val; 165267101725SAlistair Francis gem_update_int_status(s); 165367101725SAlistair Francis break; 1654c755c943SLuc Michel case R_SPADDR1LO: 1655c755c943SLuc Michel case R_SPADDR2LO: 1656c755c943SLuc Michel case R_SPADDR3LO: 1657c755c943SLuc Michel case R_SPADDR4LO: 1658c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1LO) / 2] = false; 165964eb9301SPeter Crosthwaite break; 1660c755c943SLuc Michel case R_SPADDR1HI: 1661c755c943SLuc Michel case R_SPADDR2HI: 1662c755c943SLuc Michel case R_SPADDR3HI: 1663c755c943SLuc Michel case R_SPADDR4HI: 1664c755c943SLuc Michel s->sar_active[(offset - R_SPADDR1HI) / 2] = true; 166564eb9301SPeter Crosthwaite break; 1666c755c943SLuc Michel case R_PHYMNTNC: 166749ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 166849ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 166949ab747fSPaolo Bonzini 167049ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1671dfc38879SBin Meng if (phy_addr == s->phy_addr) { 167249ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 167349ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 167449ab747fSPaolo Bonzini } 167549ab747fSPaolo Bonzini } 167649ab747fSPaolo Bonzini break; 167749ab747fSPaolo Bonzini } 167849ab747fSPaolo Bonzini 167949ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 168049ab747fSPaolo Bonzini } 168149ab747fSPaolo Bonzini 168249ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 168349ab747fSPaolo Bonzini .read = gem_read, 168449ab747fSPaolo Bonzini .write = gem_write, 168549ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 168649ab747fSPaolo Bonzini }; 168749ab747fSPaolo Bonzini 168849ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 168949ab747fSPaolo Bonzini { 169067101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 169167101725SAlistair Francis 169249ab747fSPaolo Bonzini DB_PRINT("\n"); 169367101725SAlistair Francis phy_update_link(s); 169467101725SAlistair Francis gem_update_int_status(s); 169549ab747fSPaolo Bonzini } 169649ab747fSPaolo Bonzini 169749ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1698f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 169949ab747fSPaolo Bonzini .size = sizeof(NICState), 170049ab747fSPaolo Bonzini .can_receive = gem_can_receive, 170149ab747fSPaolo Bonzini .receive = gem_receive, 170249ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 170349ab747fSPaolo Bonzini }; 170449ab747fSPaolo Bonzini 1705bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 170649ab747fSPaolo Bonzini { 1707448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 170867101725SAlistair Francis int i; 170949ab747fSPaolo Bonzini 171084aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 171184aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 171284aec8efSEdgar E. Iglesias 17132bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 17142bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 17152bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 17162bf57f73SAlistair Francis s->num_priority_queues); 17172bf57f73SAlistair Francis return; 1718e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1719e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1720e8e49943SAlistair Francis s->num_type1_screeners); 1721e8e49943SAlistair Francis return; 1722e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1723e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1724e8e49943SAlistair Francis s->num_type2_screeners); 1725e8e49943SAlistair Francis return; 17262bf57f73SAlistair Francis } 17272bf57f73SAlistair Francis 172867101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 172967101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 173067101725SAlistair Francis } 1731bcb39a65SAlistair Francis 1732bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1733bcb39a65SAlistair Francis 1734bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1735bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 17367ca151c3SSai Pavan Boddu 17377ca151c3SSai Pavan Boddu if (s->jumbo_max_len > MAX_FRAME_SIZE) { 17387ca151c3SSai Pavan Boddu error_setg(errp, "jumbo-max-len is greater than %d", 17397ca151c3SSai Pavan Boddu MAX_FRAME_SIZE); 17407ca151c3SSai Pavan Boddu return; 17417ca151c3SSai Pavan Boddu } 1742bcb39a65SAlistair Francis } 1743bcb39a65SAlistair Francis 1744bcb39a65SAlistair Francis static void gem_init(Object *obj) 1745bcb39a65SAlistair Francis { 1746bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1747bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1748bcb39a65SAlistair Francis 174949ab747fSPaolo Bonzini DB_PRINT("\n"); 175049ab747fSPaolo Bonzini 175149ab747fSPaolo Bonzini gem_init_register_masks(s); 1752eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1753eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 175449ab747fSPaolo Bonzini 1755bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 175649ab747fSPaolo Bonzini } 175749ab747fSPaolo Bonzini 175849ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 175949ab747fSPaolo Bonzini .name = "cadence_gem", 1760e8e49943SAlistair Francis .version_id = 4, 1761e8e49943SAlistair Francis .minimum_version_id = 4, 176249ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1763448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1764448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1765448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 17662bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 17672bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 17682bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 17692bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1770448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 177117cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 177249ab747fSPaolo Bonzini } 177349ab747fSPaolo Bonzini }; 177449ab747fSPaolo Bonzini 177549ab747fSPaolo Bonzini static Property gem_properties[] = { 1776448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1777a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1778a5517666SAlistair Francis GEM_MODID_VALUE), 177964ac1363SBin Meng DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 17802bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 17812bf57f73SAlistair Francis num_priority_queues, 1), 1782e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1783e8e49943SAlistair Francis num_type1_screeners, 4), 1784e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1785e8e49943SAlistair Francis num_type2_screeners, 4), 17867ca151c3SSai Pavan Boddu DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 17877ca151c3SSai Pavan Boddu jumbo_max_len, 10240), 178808d45942SPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, 178908d45942SPhilippe Mathieu-Daudé TYPE_MEMORY_REGION, MemoryRegion *), 179049ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 179149ab747fSPaolo Bonzini }; 179249ab747fSPaolo Bonzini 179349ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 179449ab747fSPaolo Bonzini { 179549ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 179649ab747fSPaolo Bonzini 1797bcb39a65SAlistair Francis dc->realize = gem_realize; 17984f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 179949ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 180049ab747fSPaolo Bonzini dc->reset = gem_reset; 180149ab747fSPaolo Bonzini } 180249ab747fSPaolo Bonzini 180349ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1804318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 180549ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1806448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1807bcb39a65SAlistair Francis .instance_init = gem_init, 1808318643beSAndreas Färber .class_init = gem_class_init, 180949ab747fSPaolo Bonzini }; 181049ab747fSPaolo Bonzini 181149ab747fSPaolo Bonzini static void gem_register_types(void) 181249ab747fSPaolo Bonzini { 181349ab747fSPaolo Bonzini type_register_static(&gem_info); 181449ab747fSPaolo Bonzini } 181549ab747fSPaolo Bonzini 181649ab747fSPaolo Bonzini type_init(gem_register_types) 1817