149ab747fSPaolo Bonzini /* 2116d5546SPeter Crosthwaite * QEMU Cadence GEM emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Xilinx, Inc. 549ab747fSPaolo Bonzini * 649ab747fSPaolo Bonzini * Permission is hereby granted, free of charge, to any person obtaining a copy 749ab747fSPaolo Bonzini * of this software and associated documentation files (the "Software"), to deal 849ab747fSPaolo Bonzini * in the Software without restriction, including without limitation the rights 949ab747fSPaolo Bonzini * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 1049ab747fSPaolo Bonzini * copies of the Software, and to permit persons to whom the Software is 1149ab747fSPaolo Bonzini * furnished to do so, subject to the following conditions: 1249ab747fSPaolo Bonzini * 1349ab747fSPaolo Bonzini * The above copyright notice and this permission notice shall be included in 1449ab747fSPaolo Bonzini * all copies or substantial portions of the Software. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1749ab747fSPaolo Bonzini * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1849ab747fSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1949ab747fSPaolo Bonzini * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2049ab747fSPaolo Bonzini * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2149ab747fSPaolo Bonzini * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 2249ab747fSPaolo Bonzini * THE SOFTWARE. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 258ef94f0bSPeter Maydell #include "qemu/osdep.h" 2649ab747fSPaolo Bonzini #include <zlib.h> /* For crc32 */ 2749ab747fSPaolo Bonzini 2864552b6bSMarkus Armbruster #include "hw/irq.h" 29f49856d4SPeter Crosthwaite #include "hw/net/cadence_gem.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 31d6454270SMarkus Armbruster #include "migration/vmstate.h" 322bf57f73SAlistair Francis #include "qapi/error.h" 33e8e49943SAlistair Francis #include "qemu/log.h" 340b8fa32fSMarkus Armbruster #include "qemu/module.h" 3584aec8efSEdgar E. Iglesias #include "sysemu/dma.h" 3649ab747fSPaolo Bonzini #include "net/checksum.h" 37fbc14a09STong Ho #include "net/eth.h" 3849ab747fSPaolo Bonzini 396fe7661dSSai Pavan Boddu #define CADENCE_GEM_ERR_DEBUG 0 4049ab747fSPaolo Bonzini #define DB_PRINT(...) do {\ 416fe7661dSSai Pavan Boddu if (CADENCE_GEM_ERR_DEBUG) { \ 426fe7661dSSai Pavan Boddu qemu_log(": %s: ", __func__); \ 436fe7661dSSai Pavan Boddu qemu_log(__VA_ARGS__); \ 446fe7661dSSai Pavan Boddu } \ 452562755eSEric Blake } while (0) 4649ab747fSPaolo Bonzini 4749ab747fSPaolo Bonzini #define GEM_NWCTRL (0x00000000 / 4) /* Network Control reg */ 4849ab747fSPaolo Bonzini #define GEM_NWCFG (0x00000004 / 4) /* Network Config reg */ 4949ab747fSPaolo Bonzini #define GEM_NWSTATUS (0x00000008 / 4) /* Network Status reg */ 5049ab747fSPaolo Bonzini #define GEM_USERIO (0x0000000C / 4) /* User IO reg */ 5149ab747fSPaolo Bonzini #define GEM_DMACFG (0x00000010 / 4) /* DMA Control reg */ 5249ab747fSPaolo Bonzini #define GEM_TXSTATUS (0x00000014 / 4) /* TX Status reg */ 5349ab747fSPaolo Bonzini #define GEM_RXQBASE (0x00000018 / 4) /* RX Q Base address reg */ 5449ab747fSPaolo Bonzini #define GEM_TXQBASE (0x0000001C / 4) /* TX Q Base address reg */ 5549ab747fSPaolo Bonzini #define GEM_RXSTATUS (0x00000020 / 4) /* RX Status reg */ 5649ab747fSPaolo Bonzini #define GEM_ISR (0x00000024 / 4) /* Interrupt Status reg */ 5749ab747fSPaolo Bonzini #define GEM_IER (0x00000028 / 4) /* Interrupt Enable reg */ 5849ab747fSPaolo Bonzini #define GEM_IDR (0x0000002C / 4) /* Interrupt Disable reg */ 5949ab747fSPaolo Bonzini #define GEM_IMR (0x00000030 / 4) /* Interrupt Mask reg */ 603048ed6aSPeter Crosthwaite #define GEM_PHYMNTNC (0x00000034 / 4) /* Phy Maintenance reg */ 6149ab747fSPaolo Bonzini #define GEM_RXPAUSE (0x00000038 / 4) /* RX Pause Time reg */ 6249ab747fSPaolo Bonzini #define GEM_TXPAUSE (0x0000003C / 4) /* TX Pause Time reg */ 6349ab747fSPaolo Bonzini #define GEM_TXPARTIALSF (0x00000040 / 4) /* TX Partial Store and Forward */ 6449ab747fSPaolo Bonzini #define GEM_RXPARTIALSF (0x00000044 / 4) /* RX Partial Store and Forward */ 657ca151c3SSai Pavan Boddu #define GEM_JUMBO_MAX_LEN (0x00000048 / 4) /* Max Jumbo Frame Size */ 6649ab747fSPaolo Bonzini #define GEM_HASHLO (0x00000080 / 4) /* Hash Low address reg */ 6749ab747fSPaolo Bonzini #define GEM_HASHHI (0x00000084 / 4) /* Hash High address reg */ 6849ab747fSPaolo Bonzini #define GEM_SPADDR1LO (0x00000088 / 4) /* Specific addr 1 low reg */ 6949ab747fSPaolo Bonzini #define GEM_SPADDR1HI (0x0000008C / 4) /* Specific addr 1 high reg */ 7049ab747fSPaolo Bonzini #define GEM_SPADDR2LO (0x00000090 / 4) /* Specific addr 2 low reg */ 7149ab747fSPaolo Bonzini #define GEM_SPADDR2HI (0x00000094 / 4) /* Specific addr 2 high reg */ 7249ab747fSPaolo Bonzini #define GEM_SPADDR3LO (0x00000098 / 4) /* Specific addr 3 low reg */ 7349ab747fSPaolo Bonzini #define GEM_SPADDR3HI (0x0000009C / 4) /* Specific addr 3 high reg */ 7449ab747fSPaolo Bonzini #define GEM_SPADDR4LO (0x000000A0 / 4) /* Specific addr 4 low reg */ 7549ab747fSPaolo Bonzini #define GEM_SPADDR4HI (0x000000A4 / 4) /* Specific addr 4 high reg */ 7649ab747fSPaolo Bonzini #define GEM_TIDMATCH1 (0x000000A8 / 4) /* Type ID1 Match reg */ 7749ab747fSPaolo Bonzini #define GEM_TIDMATCH2 (0x000000AC / 4) /* Type ID2 Match reg */ 7849ab747fSPaolo Bonzini #define GEM_TIDMATCH3 (0x000000B0 / 4) /* Type ID3 Match reg */ 7949ab747fSPaolo Bonzini #define GEM_TIDMATCH4 (0x000000B4 / 4) /* Type ID4 Match reg */ 8049ab747fSPaolo Bonzini #define GEM_WOLAN (0x000000B8 / 4) /* Wake on LAN reg */ 8149ab747fSPaolo Bonzini #define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */ 8249ab747fSPaolo Bonzini #define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */ 8349ab747fSPaolo Bonzini #define GEM_MODID (0x000000FC / 4) /* Module ID reg */ 8449ab747fSPaolo Bonzini #define GEM_OCTTXLO (0x00000100 / 4) /* Octects transmitted Low reg */ 8549ab747fSPaolo Bonzini #define GEM_OCTTXHI (0x00000104 / 4) /* Octects transmitted High reg */ 8649ab747fSPaolo Bonzini #define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitted */ 8749ab747fSPaolo Bonzini #define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames */ 8849ab747fSPaolo Bonzini #define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */ 8949ab747fSPaolo Bonzini #define GEM_TXPAUSECNT (0x00000114 / 4) /* Pause Frames Transmitted */ 9049ab747fSPaolo Bonzini #define GEM_TX64CNT (0x00000118 / 4) /* Error-free 64 TX */ 9149ab747fSPaolo Bonzini #define GEM_TX65CNT (0x0000011C / 4) /* Error-free 65-127 TX */ 9249ab747fSPaolo Bonzini #define GEM_TX128CNT (0x00000120 / 4) /* Error-free 128-255 TX */ 9349ab747fSPaolo Bonzini #define GEM_TX256CNT (0x00000124 / 4) /* Error-free 256-511 */ 9449ab747fSPaolo Bonzini #define GEM_TX512CNT (0x00000128 / 4) /* Error-free 512-1023 TX */ 9549ab747fSPaolo Bonzini #define GEM_TX1024CNT (0x0000012C / 4) /* Error-free 1024-1518 TX */ 9649ab747fSPaolo Bonzini #define GEM_TX1519CNT (0x00000130 / 4) /* Error-free larger than 1519 TX */ 9749ab747fSPaolo Bonzini #define GEM_TXURUNCNT (0x00000134 / 4) /* TX under run error counter */ 9849ab747fSPaolo Bonzini #define GEM_SINGLECOLLCNT (0x00000138 / 4) /* Single Collision Frames */ 9949ab747fSPaolo Bonzini #define GEM_MULTCOLLCNT (0x0000013C / 4) /* Multiple Collision Frames */ 10049ab747fSPaolo Bonzini #define GEM_EXCESSCOLLCNT (0x00000140 / 4) /* Excessive Collision Frames */ 10149ab747fSPaolo Bonzini #define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */ 10249ab747fSPaolo Bonzini #define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames */ 10349ab747fSPaolo Bonzini #define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter */ 10449ab747fSPaolo Bonzini #define GEM_OCTRXLO (0x00000150 / 4) /* Octects Received register Low */ 10549ab747fSPaolo Bonzini #define GEM_OCTRXHI (0x00000154 / 4) /* Octects Received register High */ 10649ab747fSPaolo Bonzini #define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */ 10749ab747fSPaolo Bonzini #define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames RX */ 10849ab747fSPaolo Bonzini #define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames RX */ 10949ab747fSPaolo Bonzini #define GEM_RXPAUSECNT (0x00000164 / 4) /* Pause Frames Received Counter */ 11049ab747fSPaolo Bonzini #define GEM_RX64CNT (0x00000168 / 4) /* Error-free 64 byte Frames RX */ 11149ab747fSPaolo Bonzini #define GEM_RX65CNT (0x0000016C / 4) /* Error-free 65-127B Frames RX */ 11249ab747fSPaolo Bonzini #define GEM_RX128CNT (0x00000170 / 4) /* Error-free 128-255B Frames RX */ 11349ab747fSPaolo Bonzini #define GEM_RX256CNT (0x00000174 / 4) /* Error-free 256-512B Frames RX */ 11449ab747fSPaolo Bonzini #define GEM_RX512CNT (0x00000178 / 4) /* Error-free 512-1023B Frames RX */ 11549ab747fSPaolo Bonzini #define GEM_RX1024CNT (0x0000017C / 4) /* Error-free 1024-1518B Frames RX */ 11649ab747fSPaolo Bonzini #define GEM_RX1519CNT (0x00000180 / 4) /* Error-free 1519-max Frames RX */ 11749ab747fSPaolo Bonzini #define GEM_RXUNDERCNT (0x00000184 / 4) /* Undersize Frames Received */ 11849ab747fSPaolo Bonzini #define GEM_RXOVERCNT (0x00000188 / 4) /* Oversize Frames Received */ 11949ab747fSPaolo Bonzini #define GEM_RXJABCNT (0x0000018C / 4) /* Jabbers Received Counter */ 12049ab747fSPaolo Bonzini #define GEM_RXFCSCNT (0x00000190 / 4) /* Frame Check seq. Error Counter */ 12149ab747fSPaolo Bonzini #define GEM_RXLENERRCNT (0x00000194 / 4) /* Length Field Error Counter */ 12249ab747fSPaolo Bonzini #define GEM_RXSYMERRCNT (0x00000198 / 4) /* Symbol Error Counter */ 12349ab747fSPaolo Bonzini #define GEM_RXALIGNERRCNT (0x0000019C / 4) /* Alignment Error Counter */ 12449ab747fSPaolo Bonzini #define GEM_RXRSCERRCNT (0x000001A0 / 4) /* Receive Resource Error Counter */ 12549ab747fSPaolo Bonzini #define GEM_RXORUNCNT (0x000001A4 / 4) /* Receive Overrun Counter */ 12688dba7edSSai Pavan Boddu #define GEM_RXIPCSERRCNT (0x000001A8 / 4) /* IP header Checksum Err Counter */ 12749ab747fSPaolo Bonzini #define GEM_RXTCPCCNT (0x000001AC / 4) /* TCP Checksum Error Counter */ 12849ab747fSPaolo Bonzini #define GEM_RXUDPCCNT (0x000001B0 / 4) /* UDP Checksum Error Counter */ 12949ab747fSPaolo Bonzini 13049ab747fSPaolo Bonzini #define GEM_1588S (0x000001D0 / 4) /* 1588 Timer Seconds */ 13149ab747fSPaolo Bonzini #define GEM_1588NS (0x000001D4 / 4) /* 1588 Timer Nanoseconds */ 13249ab747fSPaolo Bonzini #define GEM_1588ADJ (0x000001D8 / 4) /* 1588 Timer Adjust */ 13349ab747fSPaolo Bonzini #define GEM_1588INC (0x000001DC / 4) /* 1588 Timer Increment */ 13449ab747fSPaolo Bonzini #define GEM_PTPETXS (0x000001E0 / 4) /* PTP Event Frame Transmitted (s) */ 13588dba7edSSai Pavan Boddu #define GEM_PTPETXNS (0x000001E4 / 4) /* 13688dba7edSSai Pavan Boddu * PTP Event Frame Transmitted (ns) 13788dba7edSSai Pavan Boddu */ 13849ab747fSPaolo Bonzini #define GEM_PTPERXS (0x000001E8 / 4) /* PTP Event Frame Received (s) */ 13949ab747fSPaolo Bonzini #define GEM_PTPERXNS (0x000001EC / 4) /* PTP Event Frame Received (ns) */ 14049ab747fSPaolo Bonzini #define GEM_PTPPTXS (0x000001E0 / 4) /* PTP Peer Frame Transmitted (s) */ 14149ab747fSPaolo Bonzini #define GEM_PTPPTXNS (0x000001E4 / 4) /* PTP Peer Frame Transmitted (ns) */ 14249ab747fSPaolo Bonzini #define GEM_PTPPRXS (0x000001E8 / 4) /* PTP Peer Frame Received (s) */ 14349ab747fSPaolo Bonzini #define GEM_PTPPRXNS (0x000001EC / 4) /* PTP Peer Frame Received (ns) */ 14449ab747fSPaolo Bonzini 14549ab747fSPaolo Bonzini /* Design Configuration Registers */ 14649ab747fSPaolo Bonzini #define GEM_DESCONF (0x00000280 / 4) 14749ab747fSPaolo Bonzini #define GEM_DESCONF2 (0x00000284 / 4) 14849ab747fSPaolo Bonzini #define GEM_DESCONF3 (0x00000288 / 4) 14949ab747fSPaolo Bonzini #define GEM_DESCONF4 (0x0000028C / 4) 15049ab747fSPaolo Bonzini #define GEM_DESCONF5 (0x00000290 / 4) 15149ab747fSPaolo Bonzini #define GEM_DESCONF6 (0x00000294 / 4) 152e2c0c4eeSEdgar E. Iglesias #define GEM_DESCONF6_64B_MASK (1U << 23) 15349ab747fSPaolo Bonzini #define GEM_DESCONF7 (0x00000298 / 4) 15449ab747fSPaolo Bonzini 15567101725SAlistair Francis #define GEM_INT_Q1_STATUS (0x00000400 / 4) 15667101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 15767101725SAlistair Francis 15867101725SAlistair Francis #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4) 15979b2ac8fSAlistair Francis #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6) 16067101725SAlistair Francis 16167101725SAlistair Francis #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) 16279b2ac8fSAlistair Francis #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) 16367101725SAlistair Francis 164357aa013SEdgar E. Iglesias #define GEM_TBQPH (0x000004C8 / 4) 165357aa013SEdgar E. Iglesias #define GEM_RBQPH (0x000004D4 / 4) 166357aa013SEdgar E. Iglesias 16767101725SAlistair Francis #define GEM_INT_Q1_ENABLE (0x00000600 / 4) 16867101725SAlistair Francis #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) 16967101725SAlistair Francis 17067101725SAlistair Francis #define GEM_INT_Q1_DISABLE (0x00000620 / 4) 17167101725SAlistair Francis #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6) 17267101725SAlistair Francis 17367101725SAlistair Francis #define GEM_INT_Q1_MASK (0x00000640 / 4) 17467101725SAlistair Francis #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6) 17567101725SAlistair Francis 176e8e49943SAlistair Francis #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4) 177e8e49943SAlistair Francis 178e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29) 179e8e49943SAlistair Francis #define GEM_ST1R_DSTC_ENABLE (1 << 28) 180e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12) 181e8e49943SAlistair Francis #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1) 182e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_SHIFT (4) 183e8e49943SAlistair Francis #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1) 184e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_SHIFT (0) 185e8e49943SAlistair Francis #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1) 186e8e49943SAlistair Francis 187e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4) 188e8e49943SAlistair Francis 189e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18) 190e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_A_SHIFT (13) 191e8e49943SAlistair Francis #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1) 192e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12) 193e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9) 194e8e49943SAlistair Francis #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \ 195e8e49943SAlistair Francis + 1) 196e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_SHIFT (0) 197e8e49943SAlistair Francis #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1) 198e8e49943SAlistair Francis 199e8e49943SAlistair Francis #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4) 200e8e49943SAlistair Francis #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4) 201e8e49943SAlistair Francis 202e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7) 203e8e49943SAlistair Francis #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1) 204e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0) 205e8e49943SAlistair Francis #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1) 206e8e49943SAlistair Francis 20749ab747fSPaolo Bonzini /*****************************************/ 20849ab747fSPaolo Bonzini #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 20949ab747fSPaolo Bonzini #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 21049ab747fSPaolo Bonzini #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 21149ab747fSPaolo Bonzini #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 21249ab747fSPaolo Bonzini 21349ab747fSPaolo Bonzini #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 2143048ed6aSPeter Crosthwaite #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */ 21549ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 21649ab747fSPaolo Bonzini #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 2177ca151c3SSai Pavan Boddu #define GEM_NWCFG_RCV_1538 0x00000100 /* Receive 1538 bytes frame */ 21849ab747fSPaolo Bonzini #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 21949ab747fSPaolo Bonzini #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 22049ab747fSPaolo Bonzini #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 22149ab747fSPaolo Bonzini #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 2227ca151c3SSai Pavan Boddu #define GEM_NWCFG_JUMBO_FRAME 0x00000008 /* Jumbo Frames enable */ 22349ab747fSPaolo Bonzini 224e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_ADDR_64B (1U << 30) 225e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_TX_BD_EXT (1U << 29) 226e48fdd9dSEdgar E. Iglesias #define GEM_DMACFG_RX_BD_EXT (1U << 28) 2272801339fSSai Pavan Boddu #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ 22849ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 22949ab747fSPaolo Bonzini #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 23049ab747fSPaolo Bonzini #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 23149ab747fSPaolo Bonzini 23249ab747fSPaolo Bonzini #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 23349ab747fSPaolo Bonzini #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 23449ab747fSPaolo Bonzini 23549ab747fSPaolo Bonzini #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 23649ab747fSPaolo Bonzini #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 23749ab747fSPaolo Bonzini 23849ab747fSPaolo Bonzini /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 23949ab747fSPaolo Bonzini #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 2407ca151c3SSai Pavan Boddu #define GEM_INT_AMBA_ERR 0x00000040 24149ab747fSPaolo Bonzini #define GEM_INT_TXUSED 0x00000008 24249ab747fSPaolo Bonzini #define GEM_INT_RXUSED 0x00000004 24349ab747fSPaolo Bonzini #define GEM_INT_RXCMPL 0x00000002 24449ab747fSPaolo Bonzini 24549ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 24649ab747fSPaolo Bonzini #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 24749ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 24849ab747fSPaolo Bonzini #define GEM_PHYMNTNC_ADDR_SHFT 23 24949ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 25049ab747fSPaolo Bonzini #define GEM_PHYMNTNC_REG_SHIFT 18 25149ab747fSPaolo Bonzini 25249ab747fSPaolo Bonzini /* Marvell PHY definitions */ 253dfc38879SBin Meng #define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ 25449ab747fSPaolo Bonzini 25549ab747fSPaolo Bonzini #define PHY_REG_CONTROL 0 25649ab747fSPaolo Bonzini #define PHY_REG_STATUS 1 25749ab747fSPaolo Bonzini #define PHY_REG_PHYID1 2 25849ab747fSPaolo Bonzini #define PHY_REG_PHYID2 3 25949ab747fSPaolo Bonzini #define PHY_REG_ANEGADV 4 26049ab747fSPaolo Bonzini #define PHY_REG_LINKPABIL 5 26149ab747fSPaolo Bonzini #define PHY_REG_ANEGEXP 6 26249ab747fSPaolo Bonzini #define PHY_REG_NEXTP 7 26349ab747fSPaolo Bonzini #define PHY_REG_LINKPNEXTP 8 26449ab747fSPaolo Bonzini #define PHY_REG_100BTCTRL 9 26549ab747fSPaolo Bonzini #define PHY_REG_1000BTSTAT 10 26649ab747fSPaolo Bonzini #define PHY_REG_EXTSTAT 15 26749ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_CTL 16 26849ab747fSPaolo Bonzini #define PHY_REG_PHYSPCFC_ST 17 26949ab747fSPaolo Bonzini #define PHY_REG_INT_EN 18 27049ab747fSPaolo Bonzini #define PHY_REG_INT_ST 19 27149ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL 20 27249ab747fSPaolo Bonzini #define PHY_REG_RXERR 21 27349ab747fSPaolo Bonzini #define PHY_REG_EACD 22 27449ab747fSPaolo Bonzini #define PHY_REG_LED 24 27549ab747fSPaolo Bonzini #define PHY_REG_LED_OVRD 25 27649ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_CTL2 26 27749ab747fSPaolo Bonzini #define PHY_REG_EXT_PHYSPCFC_ST 27 27849ab747fSPaolo Bonzini #define PHY_REG_CABLE_DIAG 28 27949ab747fSPaolo Bonzini 28049ab747fSPaolo Bonzini #define PHY_REG_CONTROL_RST 0x8000 28149ab747fSPaolo Bonzini #define PHY_REG_CONTROL_LOOP 0x4000 28249ab747fSPaolo Bonzini #define PHY_REG_CONTROL_ANEG 0x1000 2836623d214SLinus Ziegert #define PHY_REG_CONTROL_ANRESTART 0x0200 28449ab747fSPaolo Bonzini 28549ab747fSPaolo Bonzini #define PHY_REG_STATUS_LINK 0x0004 28649ab747fSPaolo Bonzini #define PHY_REG_STATUS_ANEGCMPL 0x0020 28749ab747fSPaolo Bonzini 28849ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ANEGCMPL 0x0800 28949ab747fSPaolo Bonzini #define PHY_REG_INT_ST_LINKC 0x0400 29049ab747fSPaolo Bonzini #define PHY_REG_INT_ST_ENERGY 0x0010 29149ab747fSPaolo Bonzini 29249ab747fSPaolo Bonzini /***********************************************************************/ 29363af1e0cSPeter Crosthwaite #define GEM_RX_REJECT (-1) 29463af1e0cSPeter Crosthwaite #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 29563af1e0cSPeter Crosthwaite #define GEM_RX_BROADCAST_ACCEPT (-3) 29663af1e0cSPeter Crosthwaite #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 29763af1e0cSPeter Crosthwaite #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 29863af1e0cSPeter Crosthwaite 29963af1e0cSPeter Crosthwaite #define GEM_RX_SAR_ACCEPT 0 30049ab747fSPaolo Bonzini 30149ab747fSPaolo Bonzini /***********************************************************************/ 30249ab747fSPaolo Bonzini 30349ab747fSPaolo Bonzini #define DESC_1_USED 0x80000000 30449ab747fSPaolo Bonzini #define DESC_1_LENGTH 0x00001FFF 30549ab747fSPaolo Bonzini 30649ab747fSPaolo Bonzini #define DESC_1_TX_WRAP 0x40000000 30749ab747fSPaolo Bonzini #define DESC_1_TX_LAST 0x00008000 30849ab747fSPaolo Bonzini 30949ab747fSPaolo Bonzini #define DESC_0_RX_WRAP 0x00000002 31049ab747fSPaolo Bonzini #define DESC_0_RX_OWNERSHIP 0x00000001 31149ab747fSPaolo Bonzini 31263af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_SHIFT 25 31363af1e0cSPeter Crosthwaite #define R_DESC_1_RX_SAR_LENGTH 2 314a03f7429SPeter Crosthwaite #define R_DESC_1_RX_SAR_MATCH (1 << 27) 31563af1e0cSPeter Crosthwaite #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 31663af1e0cSPeter Crosthwaite #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 31763af1e0cSPeter Crosthwaite #define R_DESC_1_RX_BROADCAST (1 << 31) 31863af1e0cSPeter Crosthwaite 31949ab747fSPaolo Bonzini #define DESC_1_RX_SOF 0x00004000 32049ab747fSPaolo Bonzini #define DESC_1_RX_EOF 0x00008000 32149ab747fSPaolo Bonzini 322a5517666SAlistair Francis #define GEM_MODID_VALUE 0x00020118 323a5517666SAlistair Francis 324e48fdd9dSEdgar E. Iglesias static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 32549ab747fSPaolo Bonzini { 326e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0]; 327e48fdd9dSEdgar E. Iglesias 328e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 329e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 330e48fdd9dSEdgar E. Iglesias } 331e48fdd9dSEdgar E. Iglesias return ret; 33249ab747fSPaolo Bonzini } 33349ab747fSPaolo Bonzini 334f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_used(uint32_t *desc) 33549ab747fSPaolo Bonzini { 33649ab747fSPaolo Bonzini return (desc[1] & DESC_1_USED) ? 1 : 0; 33749ab747fSPaolo Bonzini } 33849ab747fSPaolo Bonzini 339f0236182SEdgar E. Iglesias static inline void tx_desc_set_used(uint32_t *desc) 34049ab747fSPaolo Bonzini { 34149ab747fSPaolo Bonzini desc[1] |= DESC_1_USED; 34249ab747fSPaolo Bonzini } 34349ab747fSPaolo Bonzini 344f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_wrap(uint32_t *desc) 34549ab747fSPaolo Bonzini { 34649ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 34749ab747fSPaolo Bonzini } 34849ab747fSPaolo Bonzini 349f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_last(uint32_t *desc) 35049ab747fSPaolo Bonzini { 35149ab747fSPaolo Bonzini return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 35249ab747fSPaolo Bonzini } 35349ab747fSPaolo Bonzini 354f0236182SEdgar E. Iglesias static inline unsigned tx_desc_get_length(uint32_t *desc) 35549ab747fSPaolo Bonzini { 35649ab747fSPaolo Bonzini return desc[1] & DESC_1_LENGTH; 35749ab747fSPaolo Bonzini } 35849ab747fSPaolo Bonzini 359f0236182SEdgar E. Iglesias static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) 36049ab747fSPaolo Bonzini { 36167101725SAlistair Francis DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); 36249ab747fSPaolo Bonzini DB_PRINT("bufaddr: 0x%08x\n", *desc); 36349ab747fSPaolo Bonzini DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 36449ab747fSPaolo Bonzini DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 36549ab747fSPaolo Bonzini DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 36649ab747fSPaolo Bonzini DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 36749ab747fSPaolo Bonzini } 36849ab747fSPaolo Bonzini 369e48fdd9dSEdgar E. Iglesias static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) 37049ab747fSPaolo Bonzini { 371e48fdd9dSEdgar E. Iglesias uint64_t ret = desc[0] & ~0x3UL; 372e48fdd9dSEdgar E. Iglesias 373e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 374e48fdd9dSEdgar E. Iglesias ret |= (uint64_t)desc[2] << 32; 375e48fdd9dSEdgar E. Iglesias } 376e48fdd9dSEdgar E. Iglesias return ret; 377e48fdd9dSEdgar E. Iglesias } 378e48fdd9dSEdgar E. Iglesias 379e48fdd9dSEdgar E. Iglesias static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) 380e48fdd9dSEdgar E. Iglesias { 381e48fdd9dSEdgar E. Iglesias int ret = 2; 382e48fdd9dSEdgar E. Iglesias 383e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 384e48fdd9dSEdgar E. Iglesias ret += 2; 385e48fdd9dSEdgar E. Iglesias } 386e48fdd9dSEdgar E. Iglesias if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT 387e48fdd9dSEdgar E. Iglesias : GEM_DMACFG_TX_BD_EXT)) { 388e48fdd9dSEdgar E. Iglesias ret += 2; 389e48fdd9dSEdgar E. Iglesias } 390e48fdd9dSEdgar E. Iglesias 391e48fdd9dSEdgar E. Iglesias assert(ret <= DESC_MAX_NUM_WORDS); 392e48fdd9dSEdgar E. Iglesias return ret; 39349ab747fSPaolo Bonzini } 39449ab747fSPaolo Bonzini 395f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_wrap(uint32_t *desc) 39649ab747fSPaolo Bonzini { 39749ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 39849ab747fSPaolo Bonzini } 39949ab747fSPaolo Bonzini 400f0236182SEdgar E. Iglesias static inline unsigned rx_desc_get_ownership(uint32_t *desc) 40149ab747fSPaolo Bonzini { 40249ab747fSPaolo Bonzini return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 40349ab747fSPaolo Bonzini } 40449ab747fSPaolo Bonzini 405f0236182SEdgar E. Iglesias static inline void rx_desc_set_ownership(uint32_t *desc) 40649ab747fSPaolo Bonzini { 40749ab747fSPaolo Bonzini desc[0] |= DESC_0_RX_OWNERSHIP; 40849ab747fSPaolo Bonzini } 40949ab747fSPaolo Bonzini 410f0236182SEdgar E. Iglesias static inline void rx_desc_set_sof(uint32_t *desc) 41149ab747fSPaolo Bonzini { 41249ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_SOF; 41349ab747fSPaolo Bonzini } 41449ab747fSPaolo Bonzini 41559ab136aSRamon Fried static inline void rx_desc_clear_control(uint32_t *desc) 41659ab136aSRamon Fried { 41759ab136aSRamon Fried desc[1] = 0; 41859ab136aSRamon Fried } 41959ab136aSRamon Fried 420f0236182SEdgar E. Iglesias static inline void rx_desc_set_eof(uint32_t *desc) 42149ab747fSPaolo Bonzini { 42249ab747fSPaolo Bonzini desc[1] |= DESC_1_RX_EOF; 42349ab747fSPaolo Bonzini } 42449ab747fSPaolo Bonzini 425f0236182SEdgar E. Iglesias static inline void rx_desc_set_length(uint32_t *desc, unsigned len) 42649ab747fSPaolo Bonzini { 42749ab747fSPaolo Bonzini desc[1] &= ~DESC_1_LENGTH; 42849ab747fSPaolo Bonzini desc[1] |= len; 42949ab747fSPaolo Bonzini } 43049ab747fSPaolo Bonzini 431f0236182SEdgar E. Iglesias static inline void rx_desc_set_broadcast(uint32_t *desc) 43263af1e0cSPeter Crosthwaite { 43363af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_BROADCAST; 43463af1e0cSPeter Crosthwaite } 43563af1e0cSPeter Crosthwaite 436f0236182SEdgar E. Iglesias static inline void rx_desc_set_unicast_hash(uint32_t *desc) 43763af1e0cSPeter Crosthwaite { 43863af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_UNICAST_HASH; 43963af1e0cSPeter Crosthwaite } 44063af1e0cSPeter Crosthwaite 441f0236182SEdgar E. Iglesias static inline void rx_desc_set_multicast_hash(uint32_t *desc) 44263af1e0cSPeter Crosthwaite { 44363af1e0cSPeter Crosthwaite desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 44463af1e0cSPeter Crosthwaite } 44563af1e0cSPeter Crosthwaite 446f0236182SEdgar E. Iglesias static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) 44763af1e0cSPeter Crosthwaite { 44863af1e0cSPeter Crosthwaite desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 44963af1e0cSPeter Crosthwaite sar_idx); 450a03f7429SPeter Crosthwaite desc[1] |= R_DESC_1_RX_SAR_MATCH; 45163af1e0cSPeter Crosthwaite } 45263af1e0cSPeter Crosthwaite 45349ab747fSPaolo Bonzini /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 4546a0a70b0SStefan Weil static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 45549ab747fSPaolo Bonzini 4567ca151c3SSai Pavan Boddu static uint32_t gem_get_max_buf_len(CadenceGEMState *s, bool tx) 4577ca151c3SSai Pavan Boddu { 4587ca151c3SSai Pavan Boddu uint32_t size; 4597ca151c3SSai Pavan Boddu if (s->regs[GEM_NWCFG] & GEM_NWCFG_JUMBO_FRAME) { 4607ca151c3SSai Pavan Boddu size = s->regs[GEM_JUMBO_MAX_LEN]; 4617ca151c3SSai Pavan Boddu if (size > s->jumbo_max_len) { 4627ca151c3SSai Pavan Boddu size = s->jumbo_max_len; 4637ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "GEM_JUMBO_MAX_LEN reg cannot be" 4647ca151c3SSai Pavan Boddu " greater than 0x%" PRIx32 "\n", s->jumbo_max_len); 4657ca151c3SSai Pavan Boddu } 4667ca151c3SSai Pavan Boddu } else if (tx) { 4677ca151c3SSai Pavan Boddu size = 1518; 4687ca151c3SSai Pavan Boddu } else { 4697ca151c3SSai Pavan Boddu size = s->regs[GEM_NWCFG] & GEM_NWCFG_RCV_1538 ? 1538 : 1518; 4707ca151c3SSai Pavan Boddu } 4717ca151c3SSai Pavan Boddu return size; 4727ca151c3SSai Pavan Boddu } 4737ca151c3SSai Pavan Boddu 47468dbee3bSSai Pavan Boddu static void gem_set_isr(CadenceGEMState *s, int q, uint32_t flag) 47568dbee3bSSai Pavan Boddu { 47668dbee3bSSai Pavan Boddu if (q == 0) { 47768dbee3bSSai Pavan Boddu s->regs[GEM_ISR] |= flag & ~(s->regs[GEM_IMR]); 47868dbee3bSSai Pavan Boddu } else { 47968dbee3bSSai Pavan Boddu s->regs[GEM_INT_Q1_STATUS + q - 1] |= flag & 48068dbee3bSSai Pavan Boddu ~(s->regs[GEM_INT_Q1_MASK + q - 1]); 48168dbee3bSSai Pavan Boddu } 48268dbee3bSSai Pavan Boddu } 48368dbee3bSSai Pavan Boddu 48449ab747fSPaolo Bonzini /* 48549ab747fSPaolo Bonzini * gem_init_register_masks: 48649ab747fSPaolo Bonzini * One time initialization. 48749ab747fSPaolo Bonzini * Set masks to identify which register bits have magical clear properties 48849ab747fSPaolo Bonzini */ 489448f19e2SPeter Crosthwaite static void gem_init_register_masks(CadenceGEMState *s) 49049ab747fSPaolo Bonzini { 4914c70e32fSSai Pavan Boddu unsigned int i; 49249ab747fSPaolo Bonzini /* Mask of register bits which are read only */ 49349ab747fSPaolo Bonzini memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 49449ab747fSPaolo Bonzini s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 49549ab747fSPaolo Bonzini s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 496e48fdd9dSEdgar E. Iglesias s->regs_ro[GEM_DMACFG] = 0x8E00F000; 49749ab747fSPaolo Bonzini s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 49849ab747fSPaolo Bonzini s->regs_ro[GEM_RXQBASE] = 0x00000003; 49949ab747fSPaolo Bonzini s->regs_ro[GEM_TXQBASE] = 0x00000003; 50049ab747fSPaolo Bonzini s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 50149ab747fSPaolo Bonzini s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 50249ab747fSPaolo Bonzini s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 50349ab747fSPaolo Bonzini s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 5044c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 5054c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_STATUS + i] = 0xFFFFFFFF; 5064c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xFFFFF319; 5074c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xFFFFF319; 5084c70e32fSSai Pavan Boddu s->regs_ro[GEM_INT_Q1_MASK + i] = 0xFFFFFFFF; 5094c70e32fSSai Pavan Boddu } 51049ab747fSPaolo Bonzini 51149ab747fSPaolo Bonzini /* Mask of register bits which are clear on read */ 51249ab747fSPaolo Bonzini memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 51349ab747fSPaolo Bonzini s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 5144c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 5154c70e32fSSai Pavan Boddu s->regs_rtc[GEM_INT_Q1_STATUS + i] = 0x00000CE6; 5164c70e32fSSai Pavan Boddu } 51749ab747fSPaolo Bonzini 51849ab747fSPaolo Bonzini /* Mask of register bits which are write 1 to clear */ 51949ab747fSPaolo Bonzini memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 52049ab747fSPaolo Bonzini s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 52149ab747fSPaolo Bonzini s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 52249ab747fSPaolo Bonzini 52349ab747fSPaolo Bonzini /* Mask of register bits which are write only */ 52449ab747fSPaolo Bonzini memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 52549ab747fSPaolo Bonzini s->regs_wo[GEM_NWCTRL] = 0x00073E60; 52649ab747fSPaolo Bonzini s->regs_wo[GEM_IER] = 0x07FFFFFF; 52749ab747fSPaolo Bonzini s->regs_wo[GEM_IDR] = 0x07FFFFFF; 5284c70e32fSSai Pavan Boddu for (i = 0; i < s->num_priority_queues; i++) { 5294c70e32fSSai Pavan Boddu s->regs_wo[GEM_INT_Q1_ENABLE + i] = 0x00000CE6; 5304c70e32fSSai Pavan Boddu s->regs_wo[GEM_INT_Q1_DISABLE + i] = 0x00000CE6; 5314c70e32fSSai Pavan Boddu } 53249ab747fSPaolo Bonzini } 53349ab747fSPaolo Bonzini 53449ab747fSPaolo Bonzini /* 53549ab747fSPaolo Bonzini * phy_update_link: 53649ab747fSPaolo Bonzini * Make the emulated PHY link state match the QEMU "interface" state. 53749ab747fSPaolo Bonzini */ 538448f19e2SPeter Crosthwaite static void phy_update_link(CadenceGEMState *s) 53949ab747fSPaolo Bonzini { 54049ab747fSPaolo Bonzini DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 54149ab747fSPaolo Bonzini 54249ab747fSPaolo Bonzini /* Autonegotiation status mirrors link status. */ 54349ab747fSPaolo Bonzini if (qemu_get_queue(s->nic)->link_down) { 54449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 54549ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 54649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 54749ab747fSPaolo Bonzini } else { 54849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 54949ab747fSPaolo Bonzini PHY_REG_STATUS_LINK); 55049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 55149ab747fSPaolo Bonzini PHY_REG_INT_ST_ANEGCMPL | 55249ab747fSPaolo Bonzini PHY_REG_INT_ST_ENERGY); 55349ab747fSPaolo Bonzini } 55449ab747fSPaolo Bonzini } 55549ab747fSPaolo Bonzini 556b8c4b67eSPhilippe Mathieu-Daudé static bool gem_can_receive(NetClientState *nc) 55749ab747fSPaolo Bonzini { 558448f19e2SPeter Crosthwaite CadenceGEMState *s; 55967101725SAlistair Francis int i; 56049ab747fSPaolo Bonzini 56149ab747fSPaolo Bonzini s = qemu_get_nic_opaque(nc); 56249ab747fSPaolo Bonzini 56349ab747fSPaolo Bonzini /* Do nothing if receive is not enabled. */ 56449ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 5653ae5725fSPeter Crosthwaite if (s->can_rx_state != 1) { 5663ae5725fSPeter Crosthwaite s->can_rx_state = 1; 5673ae5725fSPeter Crosthwaite DB_PRINT("can't receive - no enable\n"); 5683ae5725fSPeter Crosthwaite } 569b8c4b67eSPhilippe Mathieu-Daudé return false; 57049ab747fSPaolo Bonzini } 57149ab747fSPaolo Bonzini 57267101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 573dacc0566SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[i]) != 1) { 574dacc0566SAlistair Francis break; 575dacc0566SAlistair Francis } 576dacc0566SAlistair Francis }; 577dacc0566SAlistair Francis 578dacc0566SAlistair Francis if (i == s->num_priority_queues) { 5798202aa53SPeter Crosthwaite if (s->can_rx_state != 2) { 5808202aa53SPeter Crosthwaite s->can_rx_state = 2; 581dacc0566SAlistair Francis DB_PRINT("can't receive - all the buffer descriptors are busy\n"); 5828202aa53SPeter Crosthwaite } 583b8c4b67eSPhilippe Mathieu-Daudé return false; 5848202aa53SPeter Crosthwaite } 5858202aa53SPeter Crosthwaite 5863ae5725fSPeter Crosthwaite if (s->can_rx_state != 0) { 5873ae5725fSPeter Crosthwaite s->can_rx_state = 0; 58867101725SAlistair Francis DB_PRINT("can receive\n"); 5893ae5725fSPeter Crosthwaite } 590b8c4b67eSPhilippe Mathieu-Daudé return true; 59149ab747fSPaolo Bonzini } 59249ab747fSPaolo Bonzini 59349ab747fSPaolo Bonzini /* 59449ab747fSPaolo Bonzini * gem_update_int_status: 59549ab747fSPaolo Bonzini * Raise or lower interrupt based on current status. 59649ab747fSPaolo Bonzini */ 597448f19e2SPeter Crosthwaite static void gem_update_int_status(CadenceGEMState *s) 59849ab747fSPaolo Bonzini { 59967101725SAlistair Francis int i; 60067101725SAlistair Francis 60186a29d4cSSai Pavan Boddu qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]); 602596b6f51SAlistair Francis 60386a29d4cSSai Pavan Boddu for (i = 1; i < s->num_priority_queues; ++i) { 60486a29d4cSSai Pavan Boddu qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]); 60549ab747fSPaolo Bonzini } 60649ab747fSPaolo Bonzini } 60749ab747fSPaolo Bonzini 60849ab747fSPaolo Bonzini /* 60949ab747fSPaolo Bonzini * gem_receive_updatestats: 61049ab747fSPaolo Bonzini * Increment receive statistics. 61149ab747fSPaolo Bonzini */ 612448f19e2SPeter Crosthwaite static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet, 61349ab747fSPaolo Bonzini unsigned bytes) 61449ab747fSPaolo Bonzini { 61549ab747fSPaolo Bonzini uint64_t octets; 61649ab747fSPaolo Bonzini 61749ab747fSPaolo Bonzini /* Total octets (bytes) received */ 61849ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 61949ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI]; 62049ab747fSPaolo Bonzini octets += bytes; 62149ab747fSPaolo Bonzini s->regs[GEM_OCTRXLO] = octets >> 32; 62249ab747fSPaolo Bonzini s->regs[GEM_OCTRXHI] = octets; 62349ab747fSPaolo Bonzini 62449ab747fSPaolo Bonzini /* Error-free Frames received */ 62549ab747fSPaolo Bonzini s->regs[GEM_RXCNT]++; 62649ab747fSPaolo Bonzini 62749ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 62849ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 62949ab747fSPaolo Bonzini s->regs[GEM_RXBROADCNT]++; 63049ab747fSPaolo Bonzini } 63149ab747fSPaolo Bonzini 63249ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 63349ab747fSPaolo Bonzini if (packet[0] == 0x01) { 63449ab747fSPaolo Bonzini s->regs[GEM_RXMULTICNT]++; 63549ab747fSPaolo Bonzini } 63649ab747fSPaolo Bonzini 63749ab747fSPaolo Bonzini if (bytes <= 64) { 63849ab747fSPaolo Bonzini s->regs[GEM_RX64CNT]++; 63949ab747fSPaolo Bonzini } else if (bytes <= 127) { 64049ab747fSPaolo Bonzini s->regs[GEM_RX65CNT]++; 64149ab747fSPaolo Bonzini } else if (bytes <= 255) { 64249ab747fSPaolo Bonzini s->regs[GEM_RX128CNT]++; 64349ab747fSPaolo Bonzini } else if (bytes <= 511) { 64449ab747fSPaolo Bonzini s->regs[GEM_RX256CNT]++; 64549ab747fSPaolo Bonzini } else if (bytes <= 1023) { 64649ab747fSPaolo Bonzini s->regs[GEM_RX512CNT]++; 64749ab747fSPaolo Bonzini } else if (bytes <= 1518) { 64849ab747fSPaolo Bonzini s->regs[GEM_RX1024CNT]++; 64949ab747fSPaolo Bonzini } else { 65049ab747fSPaolo Bonzini s->regs[GEM_RX1519CNT]++; 65149ab747fSPaolo Bonzini } 65249ab747fSPaolo Bonzini } 65349ab747fSPaolo Bonzini 65449ab747fSPaolo Bonzini /* 65549ab747fSPaolo Bonzini * Get the MAC Address bit from the specified position 65649ab747fSPaolo Bonzini */ 65749ab747fSPaolo Bonzini static unsigned get_bit(const uint8_t *mac, unsigned bit) 65849ab747fSPaolo Bonzini { 65949ab747fSPaolo Bonzini unsigned byte; 66049ab747fSPaolo Bonzini 66149ab747fSPaolo Bonzini byte = mac[bit / 8]; 66249ab747fSPaolo Bonzini byte >>= (bit & 0x7); 66349ab747fSPaolo Bonzini byte &= 1; 66449ab747fSPaolo Bonzini 66549ab747fSPaolo Bonzini return byte; 66649ab747fSPaolo Bonzini } 66749ab747fSPaolo Bonzini 66849ab747fSPaolo Bonzini /* 66949ab747fSPaolo Bonzini * Calculate a GEM MAC Address hash index 67049ab747fSPaolo Bonzini */ 67149ab747fSPaolo Bonzini static unsigned calc_mac_hash(const uint8_t *mac) 67249ab747fSPaolo Bonzini { 67349ab747fSPaolo Bonzini int index_bit, mac_bit; 67449ab747fSPaolo Bonzini unsigned hash_index; 67549ab747fSPaolo Bonzini 67649ab747fSPaolo Bonzini hash_index = 0; 67749ab747fSPaolo Bonzini mac_bit = 5; 67849ab747fSPaolo Bonzini for (index_bit = 5; index_bit >= 0; index_bit--) { 67949ab747fSPaolo Bonzini hash_index |= (get_bit(mac, mac_bit) ^ 68049ab747fSPaolo Bonzini get_bit(mac, mac_bit + 6) ^ 68149ab747fSPaolo Bonzini get_bit(mac, mac_bit + 12) ^ 68249ab747fSPaolo Bonzini get_bit(mac, mac_bit + 18) ^ 68349ab747fSPaolo Bonzini get_bit(mac, mac_bit + 24) ^ 68449ab747fSPaolo Bonzini get_bit(mac, mac_bit + 30) ^ 68549ab747fSPaolo Bonzini get_bit(mac, mac_bit + 36) ^ 68649ab747fSPaolo Bonzini get_bit(mac, mac_bit + 42)) << index_bit; 68749ab747fSPaolo Bonzini mac_bit--; 68849ab747fSPaolo Bonzini } 68949ab747fSPaolo Bonzini 69049ab747fSPaolo Bonzini return hash_index; 69149ab747fSPaolo Bonzini } 69249ab747fSPaolo Bonzini 69349ab747fSPaolo Bonzini /* 69449ab747fSPaolo Bonzini * gem_mac_address_filter: 69549ab747fSPaolo Bonzini * Accept or reject this destination address? 69649ab747fSPaolo Bonzini * Returns: 69749ab747fSPaolo Bonzini * GEM_RX_REJECT: reject 69863af1e0cSPeter Crosthwaite * >= 0: Specific address accept (which matched SAR is returned) 69963af1e0cSPeter Crosthwaite * others for various other modes of accept: 70063af1e0cSPeter Crosthwaite * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 70163af1e0cSPeter Crosthwaite * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 70249ab747fSPaolo Bonzini */ 703448f19e2SPeter Crosthwaite static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet) 70449ab747fSPaolo Bonzini { 70549ab747fSPaolo Bonzini uint8_t *gem_spaddr; 706fbc14a09STong Ho int i, is_mc; 70749ab747fSPaolo Bonzini 70849ab747fSPaolo Bonzini /* Promiscuous mode? */ 70949ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 71063af1e0cSPeter Crosthwaite return GEM_RX_PROMISCUOUS_ACCEPT; 71149ab747fSPaolo Bonzini } 71249ab747fSPaolo Bonzini 71349ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 71449ab747fSPaolo Bonzini /* Reject broadcast packets? */ 71549ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 71649ab747fSPaolo Bonzini return GEM_RX_REJECT; 71749ab747fSPaolo Bonzini } 71863af1e0cSPeter Crosthwaite return GEM_RX_BROADCAST_ACCEPT; 71949ab747fSPaolo Bonzini } 72049ab747fSPaolo Bonzini 72149ab747fSPaolo Bonzini /* Accept packets -w- hash match? */ 722fbc14a09STong Ho is_mc = is_multicast_ether_addr(packet); 723fbc14a09STong Ho if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 724fbc14a09STong Ho (!is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 725fbc14a09STong Ho uint64_t buckets; 72649ab747fSPaolo Bonzini unsigned hash_index; 72749ab747fSPaolo Bonzini 72849ab747fSPaolo Bonzini hash_index = calc_mac_hash(packet); 729fbc14a09STong Ho buckets = ((uint64_t)s->regs[GEM_HASHHI] << 32) | s->regs[GEM_HASHLO]; 730fbc14a09STong Ho if ((buckets >> hash_index) & 1) { 731fbc14a09STong Ho return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT 732fbc14a09STong Ho : GEM_RX_UNICAST_HASH_ACCEPT; 73349ab747fSPaolo Bonzini } 73449ab747fSPaolo Bonzini } 73549ab747fSPaolo Bonzini 73649ab747fSPaolo Bonzini /* Check all 4 specific addresses */ 73749ab747fSPaolo Bonzini gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 73863af1e0cSPeter Crosthwaite for (i = 3; i >= 0; i--) { 73964eb9301SPeter Crosthwaite if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 74063af1e0cSPeter Crosthwaite return GEM_RX_SAR_ACCEPT + i; 74149ab747fSPaolo Bonzini } 74249ab747fSPaolo Bonzini } 74349ab747fSPaolo Bonzini 74449ab747fSPaolo Bonzini /* No address match; reject the packet */ 74549ab747fSPaolo Bonzini return GEM_RX_REJECT; 74649ab747fSPaolo Bonzini } 74749ab747fSPaolo Bonzini 748e8e49943SAlistair Francis /* Figure out which queue the received data should be sent to */ 749e8e49943SAlistair Francis static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, 750e8e49943SAlistair Francis unsigned rxbufsize) 751e8e49943SAlistair Francis { 752e8e49943SAlistair Francis uint32_t reg; 753e8e49943SAlistair Francis bool matched, mismatched; 754e8e49943SAlistair Francis int i, j; 755e8e49943SAlistair Francis 756e8e49943SAlistair Francis for (i = 0; i < s->num_type1_screeners; i++) { 757e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i]; 758e8e49943SAlistair Francis matched = false; 759e8e49943SAlistair Francis mismatched = false; 760e8e49943SAlistair Francis 761e8e49943SAlistair Francis /* Screening is based on UDP Port */ 762e8e49943SAlistair Francis if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) { 763e8e49943SAlistair Francis uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23]; 764e8e49943SAlistair Francis if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT, 765e8e49943SAlistair Francis GEM_ST1R_UDP_PORT_MATCH_WIDTH)) { 766e8e49943SAlistair Francis matched = true; 767e8e49943SAlistair Francis } else { 768e8e49943SAlistair Francis mismatched = true; 769e8e49943SAlistair Francis } 770e8e49943SAlistair Francis } 771e8e49943SAlistair Francis 772e8e49943SAlistair Francis /* Screening is based on DS/TC */ 773e8e49943SAlistair Francis if (reg & GEM_ST1R_DSTC_ENABLE) { 774e8e49943SAlistair Francis uint8_t dscp = rxbuf_ptr[14 + 1]; 775e8e49943SAlistair Francis if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT, 776e8e49943SAlistair Francis GEM_ST1R_DSTC_MATCH_WIDTH)) { 777e8e49943SAlistair Francis matched = true; 778e8e49943SAlistair Francis } else { 779e8e49943SAlistair Francis mismatched = true; 780e8e49943SAlistair Francis } 781e8e49943SAlistair Francis } 782e8e49943SAlistair Francis 783e8e49943SAlistair Francis if (matched && !mismatched) { 784e8e49943SAlistair Francis return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH); 785e8e49943SAlistair Francis } 786e8e49943SAlistair Francis } 787e8e49943SAlistair Francis 788e8e49943SAlistair Francis for (i = 0; i < s->num_type2_screeners; i++) { 789e8e49943SAlistair Francis reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i]; 790e8e49943SAlistair Francis matched = false; 791e8e49943SAlistair Francis mismatched = false; 792e8e49943SAlistair Francis 793e8e49943SAlistair Francis if (reg & GEM_ST2R_ETHERTYPE_ENABLE) { 794e8e49943SAlistair Francis uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13]; 795e8e49943SAlistair Francis int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT, 796e8e49943SAlistair Francis GEM_ST2R_ETHERTYPE_INDEX_WIDTH); 797e8e49943SAlistair Francis 798e8e49943SAlistair Francis if (et_idx > s->num_type2_screeners) { 799e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype " 800e8e49943SAlistair Francis "register index: %d\n", et_idx); 801e8e49943SAlistair Francis } 802e8e49943SAlistair Francis if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 + 803e8e49943SAlistair Francis et_idx]) { 804e8e49943SAlistair Francis matched = true; 805e8e49943SAlistair Francis } else { 806e8e49943SAlistair Francis mismatched = true; 807e8e49943SAlistair Francis } 808e8e49943SAlistair Francis } 809e8e49943SAlistair Francis 810e8e49943SAlistair Francis /* Compare A, B, C */ 811e8e49943SAlistair Francis for (j = 0; j < 3; j++) { 812e8e49943SAlistair Francis uint32_t cr0, cr1, mask; 813e8e49943SAlistair Francis uint16_t rx_cmp; 814e8e49943SAlistair Francis int offset; 815e8e49943SAlistair Francis int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6, 816e8e49943SAlistair Francis GEM_ST2R_COMPARE_WIDTH); 817e8e49943SAlistair Francis 818e8e49943SAlistair Francis if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) { 819e8e49943SAlistair Francis continue; 820e8e49943SAlistair Francis } 821e8e49943SAlistair Francis if (cr_idx > s->num_type2_screeners) { 822e8e49943SAlistair Francis qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare " 823e8e49943SAlistair Francis "register index: %d\n", cr_idx); 824e8e49943SAlistair Francis } 825e8e49943SAlistair Francis 826e8e49943SAlistair Francis cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2]; 827e8e49943SAlistair Francis cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1]; 828e8e49943SAlistair Francis offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT, 829e8e49943SAlistair Francis GEM_T2CW1_OFFSET_VALUE_WIDTH); 830e8e49943SAlistair Francis 831e8e49943SAlistair Francis switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT, 832e8e49943SAlistair Francis GEM_T2CW1_COMPARE_OFFSET_WIDTH)) { 833e8e49943SAlistair Francis case 3: /* Skip UDP header */ 834e8e49943SAlistair Francis qemu_log_mask(LOG_UNIMP, "TCP compare offsets" 835e8e49943SAlistair Francis "unimplemented - assuming UDP\n"); 836e8e49943SAlistair Francis offset += 8; 837e8e49943SAlistair Francis /* Fallthrough */ 838e8e49943SAlistair Francis case 2: /* skip the IP header */ 839e8e49943SAlistair Francis offset += 20; 840e8e49943SAlistair Francis /* Fallthrough */ 841e8e49943SAlistair Francis case 1: /* Count from after the ethertype */ 842e8e49943SAlistair Francis offset += 14; 843e8e49943SAlistair Francis break; 844e8e49943SAlistair Francis case 0: 845e8e49943SAlistair Francis /* Offset from start of frame */ 846e8e49943SAlistair Francis break; 847e8e49943SAlistair Francis } 848e8e49943SAlistair Francis 849e8e49943SAlistair Francis rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; 850e8e49943SAlistair Francis mask = extract32(cr0, 0, 16); 851e8e49943SAlistair Francis 852e8e49943SAlistair Francis if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) { 853e8e49943SAlistair Francis matched = true; 854e8e49943SAlistair Francis } else { 855e8e49943SAlistair Francis mismatched = true; 856e8e49943SAlistair Francis } 857e8e49943SAlistair Francis } 858e8e49943SAlistair Francis 859e8e49943SAlistair Francis if (matched && !mismatched) { 860e8e49943SAlistair Francis return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH); 861e8e49943SAlistair Francis } 862e8e49943SAlistair Francis } 863e8e49943SAlistair Francis 864e8e49943SAlistair Francis /* We made it here, assume it's queue 0 */ 865e8e49943SAlistair Francis return 0; 866e8e49943SAlistair Francis } 867e8e49943SAlistair Francis 86896ea126aSSai Pavan Boddu static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q) 86996ea126aSSai Pavan Boddu { 87096ea126aSSai Pavan Boddu uint32_t base_addr = 0; 87196ea126aSSai Pavan Boddu 87296ea126aSSai Pavan Boddu switch (q) { 87396ea126aSSai Pavan Boddu case 0: 87496ea126aSSai Pavan Boddu base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE]; 87596ea126aSSai Pavan Boddu break; 87696ea126aSSai Pavan Boddu case 1 ... (MAX_PRIORITY_QUEUES - 1): 87796ea126aSSai Pavan Boddu base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR : 87896ea126aSSai Pavan Boddu GEM_RECEIVE_Q1_PTR) + q - 1]; 87996ea126aSSai Pavan Boddu break; 88096ea126aSSai Pavan Boddu default: 88196ea126aSSai Pavan Boddu g_assert_not_reached(); 88296ea126aSSai Pavan Boddu }; 88396ea126aSSai Pavan Boddu 88496ea126aSSai Pavan Boddu return base_addr; 88596ea126aSSai Pavan Boddu } 88696ea126aSSai Pavan Boddu 88796ea126aSSai Pavan Boddu static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) 88896ea126aSSai Pavan Boddu { 88996ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, true, q); 89096ea126aSSai Pavan Boddu } 89196ea126aSSai Pavan Boddu 89296ea126aSSai Pavan Boddu static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) 89396ea126aSSai Pavan Boddu { 89496ea126aSSai Pavan Boddu return gem_get_queue_base_addr(s, false, q); 89596ea126aSSai Pavan Boddu } 89696ea126aSSai Pavan Boddu 897357aa013SEdgar E. Iglesias static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) 898357aa013SEdgar E. Iglesias { 899357aa013SEdgar E. Iglesias hwaddr desc_addr = 0; 900357aa013SEdgar E. Iglesias 901357aa013SEdgar E. Iglesias if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 902357aa013SEdgar E. Iglesias desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; 903357aa013SEdgar E. Iglesias } 904357aa013SEdgar E. Iglesias desc_addr <<= 32; 905357aa013SEdgar E. Iglesias desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; 906357aa013SEdgar E. Iglesias return desc_addr; 907357aa013SEdgar E. Iglesias } 908357aa013SEdgar E. Iglesias 909357aa013SEdgar E. Iglesias static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) 910357aa013SEdgar E. Iglesias { 911357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, true, q); 912357aa013SEdgar E. Iglesias } 913357aa013SEdgar E. Iglesias 914357aa013SEdgar E. Iglesias static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) 915357aa013SEdgar E. Iglesias { 916357aa013SEdgar E. Iglesias return gem_get_desc_addr(s, false, q); 917357aa013SEdgar E. Iglesias } 918357aa013SEdgar E. Iglesias 91967101725SAlistair Francis static void gem_get_rx_desc(CadenceGEMState *s, int q) 92006c2fe95SPeter Crosthwaite { 921357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_rx_desc_addr(s, q); 922357aa013SEdgar E. Iglesias 923357aa013SEdgar E. Iglesias DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); 924357aa013SEdgar E. Iglesias 92506c2fe95SPeter Crosthwaite /* read current descriptor */ 926357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 927b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 928e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 92906c2fe95SPeter Crosthwaite 93006c2fe95SPeter Crosthwaite /* Descriptor owned by software ? */ 93167101725SAlistair Francis if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { 932357aa013SEdgar E. Iglesias DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); 93306c2fe95SPeter Crosthwaite s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 93468dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXUSED); 93506c2fe95SPeter Crosthwaite /* Handle interrupt consequences */ 93606c2fe95SPeter Crosthwaite gem_update_int_status(s); 93706c2fe95SPeter Crosthwaite } 93806c2fe95SPeter Crosthwaite } 93906c2fe95SPeter Crosthwaite 94049ab747fSPaolo Bonzini /* 94149ab747fSPaolo Bonzini * gem_receive: 94249ab747fSPaolo Bonzini * Fit a packet handed to us by QEMU into the receive descriptor ring. 94349ab747fSPaolo Bonzini */ 94449ab747fSPaolo Bonzini static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 94549ab747fSPaolo Bonzini { 94624d62fd5SSai Pavan Boddu CadenceGEMState *s = qemu_get_nic_opaque(nc); 94749ab747fSPaolo Bonzini unsigned rxbufsize, bytes_to_copy; 94849ab747fSPaolo Bonzini unsigned rxbuf_offset; 94949ab747fSPaolo Bonzini uint8_t *rxbuf_ptr; 9503b2c97f9SEdgar E. Iglesias bool first_desc = true; 95163af1e0cSPeter Crosthwaite int maf; 9522bf57f73SAlistair Francis int q = 0; 95349ab747fSPaolo Bonzini 95449ab747fSPaolo Bonzini /* Is this destination MAC address "for us" ? */ 95563af1e0cSPeter Crosthwaite maf = gem_mac_address_filter(s, buf); 95663af1e0cSPeter Crosthwaite if (maf == GEM_RX_REJECT) { 957fbc14a09STong Ho return size; /* no, drop siliently b/c it's not an error */ 95849ab747fSPaolo Bonzini } 95949ab747fSPaolo Bonzini 96049ab747fSPaolo Bonzini /* Discard packets with receive length error enabled ? */ 96149ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 96249ab747fSPaolo Bonzini unsigned type_len; 96349ab747fSPaolo Bonzini 96449ab747fSPaolo Bonzini /* Fish the ethertype / length field out of the RX packet */ 96549ab747fSPaolo Bonzini type_len = buf[12] << 8 | buf[13]; 96649ab747fSPaolo Bonzini /* It is a length field, not an ethertype */ 96749ab747fSPaolo Bonzini if (type_len < 0x600) { 96849ab747fSPaolo Bonzini if (size < type_len) { 96949ab747fSPaolo Bonzini /* discard */ 97049ab747fSPaolo Bonzini return -1; 97149ab747fSPaolo Bonzini } 97249ab747fSPaolo Bonzini } 97349ab747fSPaolo Bonzini } 97449ab747fSPaolo Bonzini 97549ab747fSPaolo Bonzini /* 97649ab747fSPaolo Bonzini * Determine configured receive buffer offset (probably 0) 97749ab747fSPaolo Bonzini */ 97849ab747fSPaolo Bonzini rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 97949ab747fSPaolo Bonzini GEM_NWCFG_BUFF_OFST_S; 98049ab747fSPaolo Bonzini 98149ab747fSPaolo Bonzini /* The configure size of each receive buffer. Determines how many 98249ab747fSPaolo Bonzini * buffers needed to hold this packet. 98349ab747fSPaolo Bonzini */ 98449ab747fSPaolo Bonzini rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 98549ab747fSPaolo Bonzini GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 98649ab747fSPaolo Bonzini bytes_to_copy = size; 98749ab747fSPaolo Bonzini 988f265ae8cSAlistair Francis /* Hardware allows a zero value here but warns against it. To avoid QEMU 989f265ae8cSAlistair Francis * indefinite loops we enforce a minimum value here 990f265ae8cSAlistair Francis */ 991f265ae8cSAlistair Francis if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) { 992f265ae8cSAlistair Francis rxbufsize = GEM_DMACFG_RBUFSZ_MUL; 993f265ae8cSAlistair Francis } 994f265ae8cSAlistair Francis 995191946c5SPeter Crosthwaite /* Pad to minimum length. Assume FCS field is stripped, logic 996191946c5SPeter Crosthwaite * below will increment it to the real minimum of 64 when 997191946c5SPeter Crosthwaite * not FCS stripping 998191946c5SPeter Crosthwaite */ 999191946c5SPeter Crosthwaite if (size < 60) { 1000191946c5SPeter Crosthwaite size = 60; 1001191946c5SPeter Crosthwaite } 1002191946c5SPeter Crosthwaite 100349ab747fSPaolo Bonzini /* Strip of FCS field ? (usually yes) */ 100449ab747fSPaolo Bonzini if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 100549ab747fSPaolo Bonzini rxbuf_ptr = (void *)buf; 100649ab747fSPaolo Bonzini } else { 100749ab747fSPaolo Bonzini unsigned crc_val; 100849ab747fSPaolo Bonzini 100924d62fd5SSai Pavan Boddu if (size > MAX_FRAME_SIZE - sizeof(crc_val)) { 101024d62fd5SSai Pavan Boddu size = MAX_FRAME_SIZE - sizeof(crc_val); 1011244381ecSPrasad J Pandit } 1012244381ecSPrasad J Pandit bytes_to_copy = size; 101349ab747fSPaolo Bonzini /* The application wants the FCS field, which QEMU does not provide. 10143048ed6aSPeter Crosthwaite * We must try and calculate one. 101549ab747fSPaolo Bonzini */ 101649ab747fSPaolo Bonzini 101724d62fd5SSai Pavan Boddu memcpy(s->rx_packet, buf, size); 101824d62fd5SSai Pavan Boddu memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size); 101924d62fd5SSai Pavan Boddu rxbuf_ptr = s->rx_packet; 102024d62fd5SSai Pavan Boddu crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60))); 102124d62fd5SSai Pavan Boddu memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val)); 102249ab747fSPaolo Bonzini 102349ab747fSPaolo Bonzini bytes_to_copy += 4; 102449ab747fSPaolo Bonzini size += 4; 102549ab747fSPaolo Bonzini } 102649ab747fSPaolo Bonzini 10276fe7661dSSai Pavan Boddu DB_PRINT("config bufsize: %u packet size: %zd\n", rxbufsize, size); 102849ab747fSPaolo Bonzini 1029b12227afSStefan Weil /* Find which queue we are targeting */ 1030e8e49943SAlistair Francis q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); 1031e8e49943SAlistair Francis 10327ca151c3SSai Pavan Boddu if (size > gem_get_max_buf_len(s, false)) { 10337ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "rx frame too long\n"); 10347ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 10357ca151c3SSai Pavan Boddu return -1; 10367ca151c3SSai Pavan Boddu } 10377ca151c3SSai Pavan Boddu 10387cfd65e4SPeter Crosthwaite while (bytes_to_copy) { 1039357aa013SEdgar E. Iglesias hwaddr desc_addr; 1040357aa013SEdgar E. Iglesias 104106c2fe95SPeter Crosthwaite /* Do nothing if receive is not enabled. */ 104206c2fe95SPeter Crosthwaite if (!gem_can_receive(nc)) { 104349ab747fSPaolo Bonzini return -1; 104449ab747fSPaolo Bonzini } 104549ab747fSPaolo Bonzini 10466fe7661dSSai Pavan Boddu DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n", 1047dda8f185SBin Meng MIN(bytes_to_copy, rxbufsize), 1048dda8f185SBin Meng rx_desc_get_buffer(s, s->rx_desc[q])); 104949ab747fSPaolo Bonzini 105049ab747fSPaolo Bonzini /* Copy packet data to emulated DMA buffer */ 105184aec8efSEdgar E. Iglesias address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + 10522bf57f73SAlistair Francis rxbuf_offset, 105384aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, 1054e48fdd9dSEdgar E. Iglesias MIN(bytes_to_copy, rxbufsize)); 105549ab747fSPaolo Bonzini rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 105630570698SPeter Crosthwaite bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 10573b2c97f9SEdgar E. Iglesias 105859ab136aSRamon Fried rx_desc_clear_control(s->rx_desc[q]); 105959ab136aSRamon Fried 10603b2c97f9SEdgar E. Iglesias /* Update the descriptor. */ 10613b2c97f9SEdgar E. Iglesias if (first_desc) { 10622bf57f73SAlistair Francis rx_desc_set_sof(s->rx_desc[q]); 10633b2c97f9SEdgar E. Iglesias first_desc = false; 10643b2c97f9SEdgar E. Iglesias } 10653b2c97f9SEdgar E. Iglesias if (bytes_to_copy == 0) { 10662bf57f73SAlistair Francis rx_desc_set_eof(s->rx_desc[q]); 10672bf57f73SAlistair Francis rx_desc_set_length(s->rx_desc[q], size); 10683b2c97f9SEdgar E. Iglesias } 10692bf57f73SAlistair Francis rx_desc_set_ownership(s->rx_desc[q]); 107063af1e0cSPeter Crosthwaite 107163af1e0cSPeter Crosthwaite switch (maf) { 107263af1e0cSPeter Crosthwaite case GEM_RX_PROMISCUOUS_ACCEPT: 107363af1e0cSPeter Crosthwaite break; 107463af1e0cSPeter Crosthwaite case GEM_RX_BROADCAST_ACCEPT: 10752bf57f73SAlistair Francis rx_desc_set_broadcast(s->rx_desc[q]); 107663af1e0cSPeter Crosthwaite break; 107763af1e0cSPeter Crosthwaite case GEM_RX_UNICAST_HASH_ACCEPT: 10782bf57f73SAlistair Francis rx_desc_set_unicast_hash(s->rx_desc[q]); 107963af1e0cSPeter Crosthwaite break; 108063af1e0cSPeter Crosthwaite case GEM_RX_MULTICAST_HASH_ACCEPT: 10812bf57f73SAlistair Francis rx_desc_set_multicast_hash(s->rx_desc[q]); 108263af1e0cSPeter Crosthwaite break; 108363af1e0cSPeter Crosthwaite case GEM_RX_REJECT: 108463af1e0cSPeter Crosthwaite abort(); 108563af1e0cSPeter Crosthwaite default: /* SAR */ 10862bf57f73SAlistair Francis rx_desc_set_sar(s->rx_desc[q], maf); 108763af1e0cSPeter Crosthwaite } 108863af1e0cSPeter Crosthwaite 10893b2c97f9SEdgar E. Iglesias /* Descriptor write-back. */ 1090357aa013SEdgar E. Iglesias desc_addr = gem_get_rx_desc_addr(s, q); 1091b7cbebf2SPhilippe Mathieu-Daudé address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, 1092b7cbebf2SPhilippe Mathieu-Daudé s->rx_desc[q], 1093e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, true)); 10943b2c97f9SEdgar E. Iglesias 109549ab747fSPaolo Bonzini /* Next descriptor */ 10962bf57f73SAlistair Francis if (rx_desc_get_wrap(s->rx_desc[q])) { 109749ab747fSPaolo Bonzini DB_PRINT("wrapping RX descriptor list\n"); 109896ea126aSSai Pavan Boddu s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q); 109949ab747fSPaolo Bonzini } else { 110049ab747fSPaolo Bonzini DB_PRINT("incrementing RX descriptor list\n"); 1101e48fdd9dSEdgar E. Iglesias s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); 110249ab747fSPaolo Bonzini } 110367101725SAlistair Francis 110467101725SAlistair Francis gem_get_rx_desc(s, q); 11057cfd65e4SPeter Crosthwaite } 110649ab747fSPaolo Bonzini 110749ab747fSPaolo Bonzini /* Count it */ 110849ab747fSPaolo Bonzini gem_receive_updatestats(s, buf, size); 110949ab747fSPaolo Bonzini 111049ab747fSPaolo Bonzini s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 111168dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_RXCMPL); 111249ab747fSPaolo Bonzini 111349ab747fSPaolo Bonzini /* Handle interrupt consequences */ 111449ab747fSPaolo Bonzini gem_update_int_status(s); 111549ab747fSPaolo Bonzini 111649ab747fSPaolo Bonzini return size; 111749ab747fSPaolo Bonzini } 111849ab747fSPaolo Bonzini 111949ab747fSPaolo Bonzini /* 112049ab747fSPaolo Bonzini * gem_transmit_updatestats: 112149ab747fSPaolo Bonzini * Increment transmit statistics. 112249ab747fSPaolo Bonzini */ 1123448f19e2SPeter Crosthwaite static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, 112449ab747fSPaolo Bonzini unsigned bytes) 112549ab747fSPaolo Bonzini { 112649ab747fSPaolo Bonzini uint64_t octets; 112749ab747fSPaolo Bonzini 112849ab747fSPaolo Bonzini /* Total octets (bytes) transmitted */ 112949ab747fSPaolo Bonzini octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 113049ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI]; 113149ab747fSPaolo Bonzini octets += bytes; 113249ab747fSPaolo Bonzini s->regs[GEM_OCTTXLO] = octets >> 32; 113349ab747fSPaolo Bonzini s->regs[GEM_OCTTXHI] = octets; 113449ab747fSPaolo Bonzini 113549ab747fSPaolo Bonzini /* Error-free Frames transmitted */ 113649ab747fSPaolo Bonzini s->regs[GEM_TXCNT]++; 113749ab747fSPaolo Bonzini 113849ab747fSPaolo Bonzini /* Error-free Broadcast Frames counter */ 113949ab747fSPaolo Bonzini if (!memcmp(packet, broadcast_addr, 6)) { 114049ab747fSPaolo Bonzini s->regs[GEM_TXBCNT]++; 114149ab747fSPaolo Bonzini } 114249ab747fSPaolo Bonzini 114349ab747fSPaolo Bonzini /* Error-free Multicast Frames counter */ 114449ab747fSPaolo Bonzini if (packet[0] == 0x01) { 114549ab747fSPaolo Bonzini s->regs[GEM_TXMCNT]++; 114649ab747fSPaolo Bonzini } 114749ab747fSPaolo Bonzini 114849ab747fSPaolo Bonzini if (bytes <= 64) { 114949ab747fSPaolo Bonzini s->regs[GEM_TX64CNT]++; 115049ab747fSPaolo Bonzini } else if (bytes <= 127) { 115149ab747fSPaolo Bonzini s->regs[GEM_TX65CNT]++; 115249ab747fSPaolo Bonzini } else if (bytes <= 255) { 115349ab747fSPaolo Bonzini s->regs[GEM_TX128CNT]++; 115449ab747fSPaolo Bonzini } else if (bytes <= 511) { 115549ab747fSPaolo Bonzini s->regs[GEM_TX256CNT]++; 115649ab747fSPaolo Bonzini } else if (bytes <= 1023) { 115749ab747fSPaolo Bonzini s->regs[GEM_TX512CNT]++; 115849ab747fSPaolo Bonzini } else if (bytes <= 1518) { 115949ab747fSPaolo Bonzini s->regs[GEM_TX1024CNT]++; 116049ab747fSPaolo Bonzini } else { 116149ab747fSPaolo Bonzini s->regs[GEM_TX1519CNT]++; 116249ab747fSPaolo Bonzini } 116349ab747fSPaolo Bonzini } 116449ab747fSPaolo Bonzini 116549ab747fSPaolo Bonzini /* 116649ab747fSPaolo Bonzini * gem_transmit: 116749ab747fSPaolo Bonzini * Fish packets out of the descriptor ring and feed them to QEMU 116849ab747fSPaolo Bonzini */ 1169448f19e2SPeter Crosthwaite static void gem_transmit(CadenceGEMState *s) 117049ab747fSPaolo Bonzini { 11718568313fSEdgar E. Iglesias uint32_t desc[DESC_MAX_NUM_WORDS]; 117249ab747fSPaolo Bonzini hwaddr packet_desc_addr; 117349ab747fSPaolo Bonzini uint8_t *p; 117449ab747fSPaolo Bonzini unsigned total_bytes; 11752bf57f73SAlistair Francis int q = 0; 117649ab747fSPaolo Bonzini 117749ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 117849ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 117949ab747fSPaolo Bonzini return; 118049ab747fSPaolo Bonzini } 118149ab747fSPaolo Bonzini 118249ab747fSPaolo Bonzini DB_PRINT("\n"); 118349ab747fSPaolo Bonzini 11843048ed6aSPeter Crosthwaite /* The packet we will hand off to QEMU. 118549ab747fSPaolo Bonzini * Packets scattered across multiple descriptors are gathered to this 118649ab747fSPaolo Bonzini * one contiguous buffer first. 118749ab747fSPaolo Bonzini */ 118824d62fd5SSai Pavan Boddu p = s->tx_packet; 118949ab747fSPaolo Bonzini total_bytes = 0; 119049ab747fSPaolo Bonzini 119167101725SAlistair Francis for (q = s->num_priority_queues - 1; q >= 0; q--) { 119249ab747fSPaolo Bonzini /* read current descriptor */ 1193357aa013SEdgar E. Iglesias packet_desc_addr = gem_get_tx_desc_addr(s, q); 1194fa15286aSPeter Crosthwaite 1195fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 119684aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1197b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1198e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 119949ab747fSPaolo Bonzini /* Handle all descriptors owned by hardware */ 120049ab747fSPaolo Bonzini while (tx_desc_get_used(desc) == 0) { 120149ab747fSPaolo Bonzini 120249ab747fSPaolo Bonzini /* Do nothing if transmit is not enabled. */ 120349ab747fSPaolo Bonzini if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 120449ab747fSPaolo Bonzini return; 120549ab747fSPaolo Bonzini } 120667101725SAlistair Francis print_gem_tx_desc(desc, q); 120749ab747fSPaolo Bonzini 120849ab747fSPaolo Bonzini /* The real hardware would eat this (and possibly crash). 120949ab747fSPaolo Bonzini * For QEMU let's lend a helping hand. 121049ab747fSPaolo Bonzini */ 1211e48fdd9dSEdgar E. Iglesias if ((tx_desc_get_buffer(s, desc) == 0) || 121249ab747fSPaolo Bonzini (tx_desc_get_length(desc) == 0)) { 12136fe7661dSSai Pavan Boddu DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n", 12146fe7661dSSai Pavan Boddu packet_desc_addr); 121549ab747fSPaolo Bonzini break; 121649ab747fSPaolo Bonzini } 121749ab747fSPaolo Bonzini 12187ca151c3SSai Pavan Boddu if (tx_desc_get_length(desc) > gem_get_max_buf_len(s, true) - 121924d62fd5SSai Pavan Boddu (p - s->tx_packet)) { 12207ca151c3SSai Pavan Boddu qemu_log_mask(LOG_GUEST_ERROR, "TX descriptor @ 0x%" \ 12217ca151c3SSai Pavan Boddu HWADDR_PRIx " too large: size 0x%x space 0x%zx\n", 1222dda8f185SBin Meng packet_desc_addr, tx_desc_get_length(desc), 12237ca151c3SSai Pavan Boddu gem_get_max_buf_len(s, true) - (p - s->tx_packet)); 12247ca151c3SSai Pavan Boddu gem_set_isr(s, q, GEM_INT_AMBA_ERR); 1225d7f05365SMichael S. Tsirkin break; 1226d7f05365SMichael S. Tsirkin } 1227d7f05365SMichael S. Tsirkin 122877524d11SAlistair Francis /* Gather this fragment of the packet from "dma memory" to our 122977524d11SAlistair Francis * contig buffer. 123049ab747fSPaolo Bonzini */ 123184aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), 123284aec8efSEdgar E. Iglesias MEMTXATTRS_UNSPECIFIED, 123384aec8efSEdgar E. Iglesias p, tx_desc_get_length(desc)); 123449ab747fSPaolo Bonzini p += tx_desc_get_length(desc); 123549ab747fSPaolo Bonzini total_bytes += tx_desc_get_length(desc); 123649ab747fSPaolo Bonzini 123749ab747fSPaolo Bonzini /* Last descriptor for this packet; hand the whole thing off */ 123849ab747fSPaolo Bonzini if (tx_desc_get_last(desc)) { 12398568313fSEdgar E. Iglesias uint32_t desc_first[DESC_MAX_NUM_WORDS]; 1240357aa013SEdgar E. Iglesias hwaddr desc_addr = gem_get_tx_desc_addr(s, q); 12416ab57a6bSPeter Crosthwaite 124249ab747fSPaolo Bonzini /* Modify the 1st descriptor of this packet to be owned by 124349ab747fSPaolo Bonzini * the processor. 124449ab747fSPaolo Bonzini */ 1245357aa013SEdgar E. Iglesias address_space_read(&s->dma_as, desc_addr, 1246b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12476ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12486ab57a6bSPeter Crosthwaite tx_desc_set_used(desc_first); 1249357aa013SEdgar E. Iglesias address_space_write(&s->dma_as, desc_addr, 1250b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc_first, 12516ab57a6bSPeter Crosthwaite sizeof(desc_first)); 12523048ed6aSPeter Crosthwaite /* Advance the hardware current descriptor past this packet */ 125349ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 125496ea126aSSai Pavan Boddu s->tx_desc_addr[q] = gem_get_tx_queue_base_addr(s, q); 125549ab747fSPaolo Bonzini } else { 1256e48fdd9dSEdgar E. Iglesias s->tx_desc_addr[q] = packet_desc_addr + 1257e48fdd9dSEdgar E. Iglesias 4 * gem_get_desc_len(s, false); 125849ab747fSPaolo Bonzini } 12592bf57f73SAlistair Francis DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); 126049ab747fSPaolo Bonzini 126149ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 126268dbee3bSSai Pavan Boddu gem_set_isr(s, q, GEM_INT_TXCMPL); 126367101725SAlistair Francis 126449ab747fSPaolo Bonzini /* Handle interrupt consequences */ 126549ab747fSPaolo Bonzini gem_update_int_status(s); 126649ab747fSPaolo Bonzini 126749ab747fSPaolo Bonzini /* Is checksum offload enabled? */ 126849ab747fSPaolo Bonzini if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 1269f5746335SBin Meng net_checksum_calculate(s->tx_packet, total_bytes, CSUM_ALL); 127049ab747fSPaolo Bonzini } 127149ab747fSPaolo Bonzini 127249ab747fSPaolo Bonzini /* Update MAC statistics */ 127324d62fd5SSai Pavan Boddu gem_transmit_updatestats(s, s->tx_packet, total_bytes); 127449ab747fSPaolo Bonzini 127549ab747fSPaolo Bonzini /* Send the packet somewhere */ 127677524d11SAlistair Francis if (s->phy_loop || (s->regs[GEM_NWCTRL] & 127777524d11SAlistair Francis GEM_NWCTRL_LOCALLOOP)) { 1278*e73adfbeSAlexander Bulekov qemu_receive_packet(qemu_get_queue(s->nic), s->tx_packet, 127977524d11SAlistair Francis total_bytes); 128049ab747fSPaolo Bonzini } else { 128124d62fd5SSai Pavan Boddu qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet, 128249ab747fSPaolo Bonzini total_bytes); 128349ab747fSPaolo Bonzini } 128449ab747fSPaolo Bonzini 128549ab747fSPaolo Bonzini /* Prepare for next packet */ 128624d62fd5SSai Pavan Boddu p = s->tx_packet; 128749ab747fSPaolo Bonzini total_bytes = 0; 128849ab747fSPaolo Bonzini } 128949ab747fSPaolo Bonzini 129049ab747fSPaolo Bonzini /* read next descriptor */ 129149ab747fSPaolo Bonzini if (tx_desc_get_wrap(desc)) { 1292f1e7cb13SRamon Fried 1293f1e7cb13SRamon Fried if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { 1294f1e7cb13SRamon Fried packet_desc_addr = s->regs[GEM_TBQPH]; 1295f1e7cb13SRamon Fried packet_desc_addr <<= 32; 1296f1e7cb13SRamon Fried } else { 1297f1e7cb13SRamon Fried packet_desc_addr = 0; 1298f1e7cb13SRamon Fried } 129996ea126aSSai Pavan Boddu packet_desc_addr |= gem_get_tx_queue_base_addr(s, q); 130049ab747fSPaolo Bonzini } else { 1301e48fdd9dSEdgar E. Iglesias packet_desc_addr += 4 * gem_get_desc_len(s, false); 130249ab747fSPaolo Bonzini } 1303fa15286aSPeter Crosthwaite DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); 130484aec8efSEdgar E. Iglesias address_space_read(&s->dma_as, packet_desc_addr, 1305b7cbebf2SPhilippe Mathieu-Daudé MEMTXATTRS_UNSPECIFIED, desc, 1306e48fdd9dSEdgar E. Iglesias sizeof(uint32_t) * gem_get_desc_len(s, false)); 130749ab747fSPaolo Bonzini } 130849ab747fSPaolo Bonzini 130949ab747fSPaolo Bonzini if (tx_desc_get_used(desc)) { 131049ab747fSPaolo Bonzini s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 131168dbee3bSSai Pavan Boddu /* IRQ TXUSED is defined only for queue 0 */ 131268dbee3bSSai Pavan Boddu if (q == 0) { 131368dbee3bSSai Pavan Boddu gem_set_isr(s, 0, GEM_INT_TXUSED); 131468dbee3bSSai Pavan Boddu } 131549ab747fSPaolo Bonzini gem_update_int_status(s); 131649ab747fSPaolo Bonzini } 131749ab747fSPaolo Bonzini } 131867101725SAlistair Francis } 131949ab747fSPaolo Bonzini 1320448f19e2SPeter Crosthwaite static void gem_phy_reset(CadenceGEMState *s) 132149ab747fSPaolo Bonzini { 132249ab747fSPaolo Bonzini memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 132349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_CONTROL] = 0x1140; 132449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] = 0x7969; 132549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID1] = 0x0141; 132649ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 132749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 132849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 132949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 133049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_NEXTP] = 0x2001; 133149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 133249ab747fSPaolo Bonzini s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 133349ab747fSPaolo Bonzini s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 133449ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 133549ab747fSPaolo Bonzini s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 13367777b7a0SAlistair Francis s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; 133749ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 133849ab747fSPaolo Bonzini s->phy_regs[PHY_REG_LED] = 0x4100; 133949ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 134049ab747fSPaolo Bonzini s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 134149ab747fSPaolo Bonzini 134249ab747fSPaolo Bonzini phy_update_link(s); 134349ab747fSPaolo Bonzini } 134449ab747fSPaolo Bonzini 134549ab747fSPaolo Bonzini static void gem_reset(DeviceState *d) 134649ab747fSPaolo Bonzini { 134764eb9301SPeter Crosthwaite int i; 1348448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(d); 1349afb4c51fSSebastian Huber const uint8_t *a; 1350726a2a95SEdgar E. Iglesias uint32_t queues_mask = 0; 135149ab747fSPaolo Bonzini 135249ab747fSPaolo Bonzini DB_PRINT("\n"); 135349ab747fSPaolo Bonzini 135449ab747fSPaolo Bonzini /* Set post reset register values */ 135549ab747fSPaolo Bonzini memset(&s->regs[0], 0, sizeof(s->regs)); 135649ab747fSPaolo Bonzini s->regs[GEM_NWCFG] = 0x00080000; 135749ab747fSPaolo Bonzini s->regs[GEM_NWSTATUS] = 0x00000006; 135849ab747fSPaolo Bonzini s->regs[GEM_DMACFG] = 0x00020784; 135949ab747fSPaolo Bonzini s->regs[GEM_IMR] = 0x07ffffff; 136049ab747fSPaolo Bonzini s->regs[GEM_TXPAUSE] = 0x0000ffff; 136149ab747fSPaolo Bonzini s->regs[GEM_TXPARTIALSF] = 0x000003ff; 136249ab747fSPaolo Bonzini s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1363a5517666SAlistair Francis s->regs[GEM_MODID] = s->revision; 1364d48cb519SSai Pavan Boddu s->regs[GEM_DESCONF] = 0x02D00111; 13657ca151c3SSai Pavan Boddu s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; 1366b2d43091SEdgar E. Iglesias s->regs[GEM_DESCONF5] = 0x002f2045; 1367e2c0c4eeSEdgar E. Iglesias s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; 136815baf5e2SSai Pavan Boddu s->regs[GEM_INT_Q1_MASK] = 0x00000CE6; 13697ca151c3SSai Pavan Boddu s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len; 1370726a2a95SEdgar E. Iglesias 1371726a2a95SEdgar E. Iglesias if (s->num_priority_queues > 1) { 1372726a2a95SEdgar E. Iglesias queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); 1373726a2a95SEdgar E. Iglesias s->regs[GEM_DESCONF6] |= queues_mask; 1374726a2a95SEdgar E. Iglesias } 137549ab747fSPaolo Bonzini 1376afb4c51fSSebastian Huber /* Set MAC address */ 1377afb4c51fSSebastian Huber a = &s->conf.macaddr.a[0]; 1378afb4c51fSSebastian Huber s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24); 1379afb4c51fSSebastian Huber s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8); 1380afb4c51fSSebastian Huber 138164eb9301SPeter Crosthwaite for (i = 0; i < 4; i++) { 138264eb9301SPeter Crosthwaite s->sar_active[i] = false; 138364eb9301SPeter Crosthwaite } 138464eb9301SPeter Crosthwaite 138549ab747fSPaolo Bonzini gem_phy_reset(s); 138649ab747fSPaolo Bonzini 138749ab747fSPaolo Bonzini gem_update_int_status(s); 138849ab747fSPaolo Bonzini } 138949ab747fSPaolo Bonzini 1390448f19e2SPeter Crosthwaite static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) 139149ab747fSPaolo Bonzini { 139249ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 139349ab747fSPaolo Bonzini return s->phy_regs[reg_num]; 139449ab747fSPaolo Bonzini } 139549ab747fSPaolo Bonzini 1396448f19e2SPeter Crosthwaite static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) 139749ab747fSPaolo Bonzini { 139849ab747fSPaolo Bonzini DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 139949ab747fSPaolo Bonzini 140049ab747fSPaolo Bonzini switch (reg_num) { 140149ab747fSPaolo Bonzini case PHY_REG_CONTROL: 140249ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_RST) { 140349ab747fSPaolo Bonzini /* Phy reset */ 140449ab747fSPaolo Bonzini gem_phy_reset(s); 140549ab747fSPaolo Bonzini val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 140649ab747fSPaolo Bonzini s->phy_loop = 0; 140749ab747fSPaolo Bonzini } 140849ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_ANEG) { 140949ab747fSPaolo Bonzini /* Complete autonegotiation immediately */ 14106623d214SLinus Ziegert val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART); 141149ab747fSPaolo Bonzini s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 141249ab747fSPaolo Bonzini } 141349ab747fSPaolo Bonzini if (val & PHY_REG_CONTROL_LOOP) { 141449ab747fSPaolo Bonzini DB_PRINT("PHY placed in loopback\n"); 141549ab747fSPaolo Bonzini s->phy_loop = 1; 141649ab747fSPaolo Bonzini } else { 141749ab747fSPaolo Bonzini s->phy_loop = 0; 141849ab747fSPaolo Bonzini } 141949ab747fSPaolo Bonzini break; 142049ab747fSPaolo Bonzini } 142149ab747fSPaolo Bonzini s->phy_regs[reg_num] = val; 142249ab747fSPaolo Bonzini } 142349ab747fSPaolo Bonzini 142449ab747fSPaolo Bonzini /* 142549ab747fSPaolo Bonzini * gem_read32: 142649ab747fSPaolo Bonzini * Read a GEM register. 142749ab747fSPaolo Bonzini */ 142849ab747fSPaolo Bonzini static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 142949ab747fSPaolo Bonzini { 1430448f19e2SPeter Crosthwaite CadenceGEMState *s; 143149ab747fSPaolo Bonzini uint32_t retval; 1432448f19e2SPeter Crosthwaite s = (CadenceGEMState *)opaque; 143349ab747fSPaolo Bonzini 143449ab747fSPaolo Bonzini offset >>= 2; 143549ab747fSPaolo Bonzini retval = s->regs[offset]; 143649ab747fSPaolo Bonzini 143749ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 143849ab747fSPaolo Bonzini 143949ab747fSPaolo Bonzini switch (offset) { 144049ab747fSPaolo Bonzini case GEM_ISR: 144167101725SAlistair Francis DB_PRINT("lowering irqs on ISR read\n"); 1442596b6f51SAlistair Francis /* The interrupts get updated at the end of the function. */ 144349ab747fSPaolo Bonzini break; 144449ab747fSPaolo Bonzini case GEM_PHYMNTNC: 144549ab747fSPaolo Bonzini if (retval & GEM_PHYMNTNC_OP_R) { 144649ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 144749ab747fSPaolo Bonzini 144849ab747fSPaolo Bonzini phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1449dfc38879SBin Meng if (phy_addr == s->phy_addr) { 145049ab747fSPaolo Bonzini reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 145149ab747fSPaolo Bonzini retval &= 0xFFFF0000; 145249ab747fSPaolo Bonzini retval |= gem_phy_read(s, reg_num); 145349ab747fSPaolo Bonzini } else { 145449ab747fSPaolo Bonzini retval |= 0xFFFF; /* No device at this address */ 145549ab747fSPaolo Bonzini } 145649ab747fSPaolo Bonzini } 145749ab747fSPaolo Bonzini break; 145849ab747fSPaolo Bonzini } 145949ab747fSPaolo Bonzini 146049ab747fSPaolo Bonzini /* Squash read to clear bits */ 146149ab747fSPaolo Bonzini s->regs[offset] &= ~(s->regs_rtc[offset]); 146249ab747fSPaolo Bonzini 146349ab747fSPaolo Bonzini /* Do not provide write only bits */ 146449ab747fSPaolo Bonzini retval &= ~(s->regs_wo[offset]); 146549ab747fSPaolo Bonzini 146649ab747fSPaolo Bonzini DB_PRINT("0x%08x\n", retval); 146767101725SAlistair Francis gem_update_int_status(s); 146849ab747fSPaolo Bonzini return retval; 146949ab747fSPaolo Bonzini } 147049ab747fSPaolo Bonzini 147149ab747fSPaolo Bonzini /* 147249ab747fSPaolo Bonzini * gem_write32: 147349ab747fSPaolo Bonzini * Write a GEM register. 147449ab747fSPaolo Bonzini */ 147549ab747fSPaolo Bonzini static void gem_write(void *opaque, hwaddr offset, uint64_t val, 147649ab747fSPaolo Bonzini unsigned size) 147749ab747fSPaolo Bonzini { 1478448f19e2SPeter Crosthwaite CadenceGEMState *s = (CadenceGEMState *)opaque; 147949ab747fSPaolo Bonzini uint32_t readonly; 148067101725SAlistair Francis int i; 148149ab747fSPaolo Bonzini 148249ab747fSPaolo Bonzini DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 148349ab747fSPaolo Bonzini offset >>= 2; 148449ab747fSPaolo Bonzini 148549ab747fSPaolo Bonzini /* Squash bits which are read only in write value */ 148649ab747fSPaolo Bonzini val &= ~(s->regs_ro[offset]); 1487e2314fdaSPeter Crosthwaite /* Preserve (only) bits which are read only and wtc in register */ 1488e2314fdaSPeter Crosthwaite readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 148949ab747fSPaolo Bonzini 149049ab747fSPaolo Bonzini /* Copy register write to backing store */ 1491e2314fdaSPeter Crosthwaite s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1492e2314fdaSPeter Crosthwaite 1493e2314fdaSPeter Crosthwaite /* do w1c */ 1494e2314fdaSPeter Crosthwaite s->regs[offset] &= ~(s->regs_w1c[offset] & val); 149549ab747fSPaolo Bonzini 149649ab747fSPaolo Bonzini /* Handle register write side effects */ 149749ab747fSPaolo Bonzini switch (offset) { 149849ab747fSPaolo Bonzini case GEM_NWCTRL: 149906c2fe95SPeter Crosthwaite if (val & GEM_NWCTRL_RXENA) { 150067101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 150167101725SAlistair Francis gem_get_rx_desc(s, i); 150267101725SAlistair Francis } 150306c2fe95SPeter Crosthwaite } 150449ab747fSPaolo Bonzini if (val & GEM_NWCTRL_TXSTART) { 150549ab747fSPaolo Bonzini gem_transmit(s); 150649ab747fSPaolo Bonzini } 150749ab747fSPaolo Bonzini if (!(val & GEM_NWCTRL_TXENA)) { 150849ab747fSPaolo Bonzini /* Reset to start of Q when transmit disabled. */ 150967101725SAlistair Francis for (i = 0; i < s->num_priority_queues; i++) { 151096ea126aSSai Pavan Boddu s->tx_desc_addr[i] = gem_get_tx_queue_base_addr(s, i); 151167101725SAlistair Francis } 151249ab747fSPaolo Bonzini } 15138202aa53SPeter Crosthwaite if (gem_can_receive(qemu_get_queue(s->nic))) { 151449ab747fSPaolo Bonzini qemu_flush_queued_packets(qemu_get_queue(s->nic)); 151549ab747fSPaolo Bonzini } 151649ab747fSPaolo Bonzini break; 151749ab747fSPaolo Bonzini 151849ab747fSPaolo Bonzini case GEM_TXSTATUS: 151949ab747fSPaolo Bonzini gem_update_int_status(s); 152049ab747fSPaolo Bonzini break; 152149ab747fSPaolo Bonzini case GEM_RXQBASE: 15222bf57f73SAlistair Francis s->rx_desc_addr[0] = val; 152349ab747fSPaolo Bonzini break; 152479b2ac8fSAlistair Francis case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR: 152567101725SAlistair Francis s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val; 152667101725SAlistair Francis break; 152749ab747fSPaolo Bonzini case GEM_TXQBASE: 15282bf57f73SAlistair Francis s->tx_desc_addr[0] = val; 152949ab747fSPaolo Bonzini break; 153079b2ac8fSAlistair Francis case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR: 153167101725SAlistair Francis s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val; 153267101725SAlistair Francis break; 153349ab747fSPaolo Bonzini case GEM_RXSTATUS: 153449ab747fSPaolo Bonzini gem_update_int_status(s); 153549ab747fSPaolo Bonzini break; 153649ab747fSPaolo Bonzini case GEM_IER: 153749ab747fSPaolo Bonzini s->regs[GEM_IMR] &= ~val; 153849ab747fSPaolo Bonzini gem_update_int_status(s); 153949ab747fSPaolo Bonzini break; 15407ca151c3SSai Pavan Boddu case GEM_JUMBO_MAX_LEN: 15417ca151c3SSai Pavan Boddu s->regs[GEM_JUMBO_MAX_LEN] = val & MAX_JUMBO_FRAME_SIZE_MASK; 15427ca151c3SSai Pavan Boddu break; 154367101725SAlistair Francis case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE: 154467101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val; 154567101725SAlistair Francis gem_update_int_status(s); 154667101725SAlistair Francis break; 154749ab747fSPaolo Bonzini case GEM_IDR: 154849ab747fSPaolo Bonzini s->regs[GEM_IMR] |= val; 154949ab747fSPaolo Bonzini gem_update_int_status(s); 155049ab747fSPaolo Bonzini break; 155167101725SAlistair Francis case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE: 155267101725SAlistair Francis s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val; 155367101725SAlistair Francis gem_update_int_status(s); 155467101725SAlistair Francis break; 155564eb9301SPeter Crosthwaite case GEM_SPADDR1LO: 155664eb9301SPeter Crosthwaite case GEM_SPADDR2LO: 155764eb9301SPeter Crosthwaite case GEM_SPADDR3LO: 155864eb9301SPeter Crosthwaite case GEM_SPADDR4LO: 155964eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 156064eb9301SPeter Crosthwaite break; 156164eb9301SPeter Crosthwaite case GEM_SPADDR1HI: 156264eb9301SPeter Crosthwaite case GEM_SPADDR2HI: 156364eb9301SPeter Crosthwaite case GEM_SPADDR3HI: 156464eb9301SPeter Crosthwaite case GEM_SPADDR4HI: 156564eb9301SPeter Crosthwaite s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 156664eb9301SPeter Crosthwaite break; 156749ab747fSPaolo Bonzini case GEM_PHYMNTNC: 156849ab747fSPaolo Bonzini if (val & GEM_PHYMNTNC_OP_W) { 156949ab747fSPaolo Bonzini uint32_t phy_addr, reg_num; 157049ab747fSPaolo Bonzini 157149ab747fSPaolo Bonzini phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1572dfc38879SBin Meng if (phy_addr == s->phy_addr) { 157349ab747fSPaolo Bonzini reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 157449ab747fSPaolo Bonzini gem_phy_write(s, reg_num, val); 157549ab747fSPaolo Bonzini } 157649ab747fSPaolo Bonzini } 157749ab747fSPaolo Bonzini break; 157849ab747fSPaolo Bonzini } 157949ab747fSPaolo Bonzini 158049ab747fSPaolo Bonzini DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 158149ab747fSPaolo Bonzini } 158249ab747fSPaolo Bonzini 158349ab747fSPaolo Bonzini static const MemoryRegionOps gem_ops = { 158449ab747fSPaolo Bonzini .read = gem_read, 158549ab747fSPaolo Bonzini .write = gem_write, 158649ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 158749ab747fSPaolo Bonzini }; 158849ab747fSPaolo Bonzini 158949ab747fSPaolo Bonzini static void gem_set_link(NetClientState *nc) 159049ab747fSPaolo Bonzini { 159167101725SAlistair Francis CadenceGEMState *s = qemu_get_nic_opaque(nc); 159267101725SAlistair Francis 159349ab747fSPaolo Bonzini DB_PRINT("\n"); 159467101725SAlistair Francis phy_update_link(s); 159567101725SAlistair Francis gem_update_int_status(s); 159649ab747fSPaolo Bonzini } 159749ab747fSPaolo Bonzini 159849ab747fSPaolo Bonzini static NetClientInfo net_gem_info = { 1599f394b2e2SEric Blake .type = NET_CLIENT_DRIVER_NIC, 160049ab747fSPaolo Bonzini .size = sizeof(NICState), 160149ab747fSPaolo Bonzini .can_receive = gem_can_receive, 160249ab747fSPaolo Bonzini .receive = gem_receive, 160349ab747fSPaolo Bonzini .link_status_changed = gem_set_link, 160449ab747fSPaolo Bonzini }; 160549ab747fSPaolo Bonzini 1606bcb39a65SAlistair Francis static void gem_realize(DeviceState *dev, Error **errp) 160749ab747fSPaolo Bonzini { 1608448f19e2SPeter Crosthwaite CadenceGEMState *s = CADENCE_GEM(dev); 160967101725SAlistair Francis int i; 161049ab747fSPaolo Bonzini 161184aec8efSEdgar E. Iglesias address_space_init(&s->dma_as, 161284aec8efSEdgar E. Iglesias s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); 161384aec8efSEdgar E. Iglesias 16142bf57f73SAlistair Francis if (s->num_priority_queues == 0 || 16152bf57f73SAlistair Francis s->num_priority_queues > MAX_PRIORITY_QUEUES) { 16162bf57f73SAlistair Francis error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, 16172bf57f73SAlistair Francis s->num_priority_queues); 16182bf57f73SAlistair Francis return; 1619e8e49943SAlistair Francis } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) { 1620e8e49943SAlistair Francis error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8, 1621e8e49943SAlistair Francis s->num_type1_screeners); 1622e8e49943SAlistair Francis return; 1623e8e49943SAlistair Francis } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) { 1624e8e49943SAlistair Francis error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8, 1625e8e49943SAlistair Francis s->num_type2_screeners); 1626e8e49943SAlistair Francis return; 16272bf57f73SAlistair Francis } 16282bf57f73SAlistair Francis 162967101725SAlistair Francis for (i = 0; i < s->num_priority_queues; ++i) { 163067101725SAlistair Francis sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 163167101725SAlistair Francis } 1632bcb39a65SAlistair Francis 1633bcb39a65SAlistair Francis qemu_macaddr_default_if_unset(&s->conf.macaddr); 1634bcb39a65SAlistair Francis 1635bcb39a65SAlistair Francis s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1636bcb39a65SAlistair Francis object_get_typename(OBJECT(dev)), dev->id, s); 16377ca151c3SSai Pavan Boddu 16387ca151c3SSai Pavan Boddu if (s->jumbo_max_len > MAX_FRAME_SIZE) { 16397ca151c3SSai Pavan Boddu error_setg(errp, "jumbo-max-len is greater than %d", 16407ca151c3SSai Pavan Boddu MAX_FRAME_SIZE); 16417ca151c3SSai Pavan Boddu return; 16427ca151c3SSai Pavan Boddu } 1643bcb39a65SAlistair Francis } 1644bcb39a65SAlistair Francis 1645bcb39a65SAlistair Francis static void gem_init(Object *obj) 1646bcb39a65SAlistair Francis { 1647bcb39a65SAlistair Francis CadenceGEMState *s = CADENCE_GEM(obj); 1648bcb39a65SAlistair Francis DeviceState *dev = DEVICE(obj); 1649bcb39a65SAlistair Francis 165049ab747fSPaolo Bonzini DB_PRINT("\n"); 165149ab747fSPaolo Bonzini 165249ab747fSPaolo Bonzini gem_init_register_masks(s); 1653eedfac6fSPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1654eedfac6fSPaolo Bonzini "enet", sizeof(s->regs)); 165549ab747fSPaolo Bonzini 1656bcb39a65SAlistair Francis sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); 165784aec8efSEdgar E. Iglesias 165884aec8efSEdgar E. Iglesias object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, 165984aec8efSEdgar E. Iglesias (Object **)&s->dma_mr, 166084aec8efSEdgar E. Iglesias qdev_prop_allow_set_link_before_realize, 1661d2623129SMarkus Armbruster OBJ_PROP_LINK_STRONG); 166249ab747fSPaolo Bonzini } 166349ab747fSPaolo Bonzini 166449ab747fSPaolo Bonzini static const VMStateDescription vmstate_cadence_gem = { 166549ab747fSPaolo Bonzini .name = "cadence_gem", 1666e8e49943SAlistair Francis .version_id = 4, 1667e8e49943SAlistair Francis .minimum_version_id = 4, 166849ab747fSPaolo Bonzini .fields = (VMStateField[]) { 1669448f19e2SPeter Crosthwaite VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG), 1670448f19e2SPeter Crosthwaite VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32), 1671448f19e2SPeter Crosthwaite VMSTATE_UINT8(phy_loop, CadenceGEMState), 16722bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState, 16732bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 16742bf57f73SAlistair Francis VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState, 16752bf57f73SAlistair Francis MAX_PRIORITY_QUEUES), 1676448f19e2SPeter Crosthwaite VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4), 167717cf2c76SPeter Crosthwaite VMSTATE_END_OF_LIST(), 167849ab747fSPaolo Bonzini } 167949ab747fSPaolo Bonzini }; 168049ab747fSPaolo Bonzini 168149ab747fSPaolo Bonzini static Property gem_properties[] = { 1682448f19e2SPeter Crosthwaite DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), 1683a5517666SAlistair Francis DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, 1684a5517666SAlistair Francis GEM_MODID_VALUE), 168564ac1363SBin Meng DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS), 16862bf57f73SAlistair Francis DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, 16872bf57f73SAlistair Francis num_priority_queues, 1), 1688e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, 1689e8e49943SAlistair Francis num_type1_screeners, 4), 1690e8e49943SAlistair Francis DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState, 1691e8e49943SAlistair Francis num_type2_screeners, 4), 16927ca151c3SSai Pavan Boddu DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState, 16937ca151c3SSai Pavan Boddu jumbo_max_len, 10240), 169449ab747fSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 169549ab747fSPaolo Bonzini }; 169649ab747fSPaolo Bonzini 169749ab747fSPaolo Bonzini static void gem_class_init(ObjectClass *klass, void *data) 169849ab747fSPaolo Bonzini { 169949ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 170049ab747fSPaolo Bonzini 1701bcb39a65SAlistair Francis dc->realize = gem_realize; 17024f67d30bSMarc-André Lureau device_class_set_props(dc, gem_properties); 170349ab747fSPaolo Bonzini dc->vmsd = &vmstate_cadence_gem; 170449ab747fSPaolo Bonzini dc->reset = gem_reset; 170549ab747fSPaolo Bonzini } 170649ab747fSPaolo Bonzini 170749ab747fSPaolo Bonzini static const TypeInfo gem_info = { 1708318643beSAndreas Färber .name = TYPE_CADENCE_GEM, 170949ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 1710448f19e2SPeter Crosthwaite .instance_size = sizeof(CadenceGEMState), 1711bcb39a65SAlistair Francis .instance_init = gem_init, 1712318643beSAndreas Färber .class_init = gem_class_init, 171349ab747fSPaolo Bonzini }; 171449ab747fSPaolo Bonzini 171549ab747fSPaolo Bonzini static void gem_register_types(void) 171649ab747fSPaolo Bonzini { 171749ab747fSPaolo Bonzini type_register_static(&gem_info); 171849ab747fSPaolo Bonzini } 171949ab747fSPaolo Bonzini 172049ab747fSPaolo Bonzini type_init(gem_register_types) 1721