1 /* 2 * QEMU Xilinx GEM emulation 3 * 4 * Copyright (c) 2011 Xilinx, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include <zlib.h> /* For crc32 */ 26 27 #include "hw/sysbus.h" 28 #include "net/net.h" 29 #include "net/checksum.h" 30 31 #ifdef CADENCE_GEM_ERR_DEBUG 32 #define DB_PRINT(...) do { \ 33 fprintf(stderr, ": %s: ", __func__); \ 34 fprintf(stderr, ## __VA_ARGS__); \ 35 } while (0); 36 #else 37 #define DB_PRINT(...) 38 #endif 39 40 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */ 41 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */ 42 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */ 43 #define GEM_USERIO (0x0000000C/4) /* User IO reg */ 44 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */ 45 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */ 46 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */ 47 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */ 48 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */ 49 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */ 50 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */ 51 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */ 52 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */ 53 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintaince reg */ 54 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */ 55 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */ 56 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */ 57 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */ 58 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */ 59 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */ 60 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */ 61 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */ 62 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */ 63 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */ 64 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */ 65 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */ 66 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */ 67 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */ 68 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */ 69 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */ 70 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */ 71 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */ 72 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */ 73 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */ 74 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */ 75 #define GEM_MODID (0x000000FC/4) /* Module ID reg */ 76 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */ 77 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */ 78 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */ 79 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */ 80 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */ 81 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */ 82 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */ 83 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */ 84 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */ 85 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */ 86 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */ 87 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */ 88 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */ 89 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */ 90 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */ 91 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */ 92 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */ 93 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */ 94 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */ 95 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */ 96 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */ 97 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */ 98 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */ 99 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */ 100 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */ 101 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */ 102 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */ 103 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */ 104 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */ 105 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */ 106 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */ 107 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */ 108 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */ 109 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */ 110 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */ 111 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */ 112 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */ 113 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */ 114 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */ 115 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */ 116 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */ 117 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */ 118 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */ 119 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */ 120 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */ 121 122 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */ 123 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */ 124 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */ 125 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */ 126 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */ 127 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */ 128 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */ 129 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */ 130 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */ 131 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */ 132 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */ 133 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */ 134 135 /* Design Configuration Registers */ 136 #define GEM_DESCONF (0x00000280/4) 137 #define GEM_DESCONF2 (0x00000284/4) 138 #define GEM_DESCONF3 (0x00000288/4) 139 #define GEM_DESCONF4 (0x0000028C/4) 140 #define GEM_DESCONF5 (0x00000290/4) 141 #define GEM_DESCONF6 (0x00000294/4) 142 #define GEM_DESCONF7 (0x00000298/4) 143 144 #define GEM_MAXREG (0x00000640/4) /* Last valid GEM address */ 145 146 /*****************************************/ 147 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */ 148 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */ 149 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */ 150 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */ 151 152 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */ 153 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with lenth err */ 154 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */ 155 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */ 156 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */ 157 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */ 158 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ 159 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ 160 161 #define GEM_DMACFG_RBUFSZ_M 0x007F0000 /* DMA RX Buffer Size mask */ 162 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ 163 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ 164 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ 165 166 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */ 167 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */ 168 169 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */ 170 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */ 171 172 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */ 173 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */ 174 #define GEM_INT_TXUSED 0x00000008 175 #define GEM_INT_RXUSED 0x00000004 176 #define GEM_INT_RXCMPL 0x00000002 177 178 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */ 179 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */ 180 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */ 181 #define GEM_PHYMNTNC_ADDR_SHFT 23 182 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */ 183 #define GEM_PHYMNTNC_REG_SHIFT 18 184 185 /* Marvell PHY definitions */ 186 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ 187 188 #define PHY_REG_CONTROL 0 189 #define PHY_REG_STATUS 1 190 #define PHY_REG_PHYID1 2 191 #define PHY_REG_PHYID2 3 192 #define PHY_REG_ANEGADV 4 193 #define PHY_REG_LINKPABIL 5 194 #define PHY_REG_ANEGEXP 6 195 #define PHY_REG_NEXTP 7 196 #define PHY_REG_LINKPNEXTP 8 197 #define PHY_REG_100BTCTRL 9 198 #define PHY_REG_1000BTSTAT 10 199 #define PHY_REG_EXTSTAT 15 200 #define PHY_REG_PHYSPCFC_CTL 16 201 #define PHY_REG_PHYSPCFC_ST 17 202 #define PHY_REG_INT_EN 18 203 #define PHY_REG_INT_ST 19 204 #define PHY_REG_EXT_PHYSPCFC_CTL 20 205 #define PHY_REG_RXERR 21 206 #define PHY_REG_EACD 22 207 #define PHY_REG_LED 24 208 #define PHY_REG_LED_OVRD 25 209 #define PHY_REG_EXT_PHYSPCFC_CTL2 26 210 #define PHY_REG_EXT_PHYSPCFC_ST 27 211 #define PHY_REG_CABLE_DIAG 28 212 213 #define PHY_REG_CONTROL_RST 0x8000 214 #define PHY_REG_CONTROL_LOOP 0x4000 215 #define PHY_REG_CONTROL_ANEG 0x1000 216 217 #define PHY_REG_STATUS_LINK 0x0004 218 #define PHY_REG_STATUS_ANEGCMPL 0x0020 219 220 #define PHY_REG_INT_ST_ANEGCMPL 0x0800 221 #define PHY_REG_INT_ST_LINKC 0x0400 222 #define PHY_REG_INT_ST_ENERGY 0x0010 223 224 /***********************************************************************/ 225 #define GEM_RX_REJECT (-1) 226 #define GEM_RX_PROMISCUOUS_ACCEPT (-2) 227 #define GEM_RX_BROADCAST_ACCEPT (-3) 228 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4) 229 #define GEM_RX_UNICAST_HASH_ACCEPT (-5) 230 231 #define GEM_RX_SAR_ACCEPT 0 232 233 /***********************************************************************/ 234 235 #define DESC_1_USED 0x80000000 236 #define DESC_1_LENGTH 0x00001FFF 237 238 #define DESC_1_TX_WRAP 0x40000000 239 #define DESC_1_TX_LAST 0x00008000 240 241 #define DESC_0_RX_WRAP 0x00000002 242 #define DESC_0_RX_OWNERSHIP 0x00000001 243 244 #define R_DESC_1_RX_SAR_SHIFT 25 245 #define R_DESC_1_RX_SAR_LENGTH 2 246 #define R_DESC_1_RX_SAR_MATCH (1 << 27) 247 #define R_DESC_1_RX_UNICAST_HASH (1 << 29) 248 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30) 249 #define R_DESC_1_RX_BROADCAST (1 << 31) 250 251 #define DESC_1_RX_SOF 0x00004000 252 #define DESC_1_RX_EOF 0x00008000 253 254 static inline unsigned tx_desc_get_buffer(unsigned *desc) 255 { 256 return desc[0]; 257 } 258 259 static inline unsigned tx_desc_get_used(unsigned *desc) 260 { 261 return (desc[1] & DESC_1_USED) ? 1 : 0; 262 } 263 264 static inline void tx_desc_set_used(unsigned *desc) 265 { 266 desc[1] |= DESC_1_USED; 267 } 268 269 static inline unsigned tx_desc_get_wrap(unsigned *desc) 270 { 271 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; 272 } 273 274 static inline unsigned tx_desc_get_last(unsigned *desc) 275 { 276 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; 277 } 278 279 static inline unsigned tx_desc_get_length(unsigned *desc) 280 { 281 return desc[1] & DESC_1_LENGTH; 282 } 283 284 static inline void print_gem_tx_desc(unsigned *desc) 285 { 286 DB_PRINT("TXDESC:\n"); 287 DB_PRINT("bufaddr: 0x%08x\n", *desc); 288 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc)); 289 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc)); 290 DB_PRINT("last: %d\n", tx_desc_get_last(desc)); 291 DB_PRINT("length: %d\n", tx_desc_get_length(desc)); 292 } 293 294 static inline unsigned rx_desc_get_buffer(unsigned *desc) 295 { 296 return desc[0] & ~0x3UL; 297 } 298 299 static inline unsigned rx_desc_get_wrap(unsigned *desc) 300 { 301 return desc[0] & DESC_0_RX_WRAP ? 1 : 0; 302 } 303 304 static inline unsigned rx_desc_get_ownership(unsigned *desc) 305 { 306 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; 307 } 308 309 static inline void rx_desc_set_ownership(unsigned *desc) 310 { 311 desc[0] |= DESC_0_RX_OWNERSHIP; 312 } 313 314 static inline void rx_desc_set_sof(unsigned *desc) 315 { 316 desc[1] |= DESC_1_RX_SOF; 317 } 318 319 static inline void rx_desc_set_eof(unsigned *desc) 320 { 321 desc[1] |= DESC_1_RX_EOF; 322 } 323 324 static inline void rx_desc_set_length(unsigned *desc, unsigned len) 325 { 326 desc[1] &= ~DESC_1_LENGTH; 327 desc[1] |= len; 328 } 329 330 static inline void rx_desc_set_broadcast(unsigned *desc) 331 { 332 desc[1] |= R_DESC_1_RX_BROADCAST; 333 } 334 335 static inline void rx_desc_set_unicast_hash(unsigned *desc) 336 { 337 desc[1] |= R_DESC_1_RX_UNICAST_HASH; 338 } 339 340 static inline void rx_desc_set_multicast_hash(unsigned *desc) 341 { 342 desc[1] |= R_DESC_1_RX_MULTICAST_HASH; 343 } 344 345 static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) 346 { 347 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, 348 sar_idx); 349 desc[1] |= R_DESC_1_RX_SAR_MATCH; 350 } 351 352 #define TYPE_CADENCE_GEM "cadence_gem" 353 #define GEM(obj) OBJECT_CHECK(GemState, (obj), TYPE_CADENCE_GEM) 354 355 typedef struct GemState { 356 SysBusDevice parent_obj; 357 358 MemoryRegion iomem; 359 NICState *nic; 360 NICConf conf; 361 qemu_irq irq; 362 363 /* GEM registers backing store */ 364 uint32_t regs[GEM_MAXREG]; 365 /* Mask of register bits which are write only */ 366 uint32_t regs_wo[GEM_MAXREG]; 367 /* Mask of register bits which are read only */ 368 uint32_t regs_ro[GEM_MAXREG]; 369 /* Mask of register bits which are clear on read */ 370 uint32_t regs_rtc[GEM_MAXREG]; 371 /* Mask of register bits which are write 1 to clear */ 372 uint32_t regs_w1c[GEM_MAXREG]; 373 374 /* PHY registers backing store */ 375 uint16_t phy_regs[32]; 376 377 uint8_t phy_loop; /* Are we in phy loopback? */ 378 379 /* The current DMA descriptor pointers */ 380 uint32_t rx_desc_addr; 381 uint32_t tx_desc_addr; 382 383 uint8_t can_rx_state; /* Debug only */ 384 385 unsigned rx_desc[2]; 386 387 bool sar_active[4]; 388 } GemState; 389 390 /* The broadcast MAC address: 0xFFFFFFFFFFFF */ 391 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 392 393 /* 394 * gem_init_register_masks: 395 * One time initialization. 396 * Set masks to identify which register bits have magical clear properties 397 */ 398 static void gem_init_register_masks(GemState *s) 399 { 400 /* Mask of register bits which are read only*/ 401 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); 402 s->regs_ro[GEM_NWCTRL] = 0xFFF80000; 403 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; 404 s->regs_ro[GEM_DMACFG] = 0xFE00F000; 405 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; 406 s->regs_ro[GEM_RXQBASE] = 0x00000003; 407 s->regs_ro[GEM_TXQBASE] = 0x00000003; 408 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0; 409 s->regs_ro[GEM_ISR] = 0xFFFFFFFF; 410 s->regs_ro[GEM_IMR] = 0xFFFFFFFF; 411 s->regs_ro[GEM_MODID] = 0xFFFFFFFF; 412 413 /* Mask of register bits which are clear on read */ 414 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc)); 415 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF; 416 417 /* Mask of register bits which are write 1 to clear */ 418 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c)); 419 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7; 420 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F; 421 422 /* Mask of register bits which are write only */ 423 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo)); 424 s->regs_wo[GEM_NWCTRL] = 0x00073E60; 425 s->regs_wo[GEM_IER] = 0x07FFFFFF; 426 s->regs_wo[GEM_IDR] = 0x07FFFFFF; 427 } 428 429 /* 430 * phy_update_link: 431 * Make the emulated PHY link state match the QEMU "interface" state. 432 */ 433 static void phy_update_link(GemState *s) 434 { 435 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down); 436 437 /* Autonegotiation status mirrors link status. */ 438 if (qemu_get_queue(s->nic)->link_down) { 439 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL | 440 PHY_REG_STATUS_LINK); 441 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC; 442 } else { 443 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL | 444 PHY_REG_STATUS_LINK); 445 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC | 446 PHY_REG_INT_ST_ANEGCMPL | 447 PHY_REG_INT_ST_ENERGY); 448 } 449 } 450 451 static int gem_can_receive(NetClientState *nc) 452 { 453 GemState *s; 454 455 s = qemu_get_nic_opaque(nc); 456 457 /* Do nothing if receive is not enabled. */ 458 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) { 459 if (s->can_rx_state != 1) { 460 s->can_rx_state = 1; 461 DB_PRINT("can't receive - no enable\n"); 462 } 463 return 0; 464 } 465 466 if (rx_desc_get_ownership(s->rx_desc) == 1) { 467 if (s->can_rx_state != 2) { 468 s->can_rx_state = 2; 469 DB_PRINT("can't receive - busy buffer descriptor 0x%x\n", 470 s->rx_desc_addr); 471 } 472 return 0; 473 } 474 475 if (s->can_rx_state != 0) { 476 s->can_rx_state = 0; 477 DB_PRINT("can receive 0x%x\n", s->rx_desc_addr); 478 } 479 return 1; 480 } 481 482 /* 483 * gem_update_int_status: 484 * Raise or lower interrupt based on current status. 485 */ 486 static void gem_update_int_status(GemState *s) 487 { 488 if (s->regs[GEM_ISR]) { 489 DB_PRINT("asserting int. (0x%08x)\n", s->regs[GEM_ISR]); 490 qemu_set_irq(s->irq, 1); 491 } 492 } 493 494 /* 495 * gem_receive_updatestats: 496 * Increment receive statistics. 497 */ 498 static void gem_receive_updatestats(GemState *s, const uint8_t *packet, 499 unsigned bytes) 500 { 501 uint64_t octets; 502 503 /* Total octets (bytes) received */ 504 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) | 505 s->regs[GEM_OCTRXHI]; 506 octets += bytes; 507 s->regs[GEM_OCTRXLO] = octets >> 32; 508 s->regs[GEM_OCTRXHI] = octets; 509 510 /* Error-free Frames received */ 511 s->regs[GEM_RXCNT]++; 512 513 /* Error-free Broadcast Frames counter */ 514 if (!memcmp(packet, broadcast_addr, 6)) { 515 s->regs[GEM_RXBROADCNT]++; 516 } 517 518 /* Error-free Multicast Frames counter */ 519 if (packet[0] == 0x01) { 520 s->regs[GEM_RXMULTICNT]++; 521 } 522 523 if (bytes <= 64) { 524 s->regs[GEM_RX64CNT]++; 525 } else if (bytes <= 127) { 526 s->regs[GEM_RX65CNT]++; 527 } else if (bytes <= 255) { 528 s->regs[GEM_RX128CNT]++; 529 } else if (bytes <= 511) { 530 s->regs[GEM_RX256CNT]++; 531 } else if (bytes <= 1023) { 532 s->regs[GEM_RX512CNT]++; 533 } else if (bytes <= 1518) { 534 s->regs[GEM_RX1024CNT]++; 535 } else { 536 s->regs[GEM_RX1519CNT]++; 537 } 538 } 539 540 /* 541 * Get the MAC Address bit from the specified position 542 */ 543 static unsigned get_bit(const uint8_t *mac, unsigned bit) 544 { 545 unsigned byte; 546 547 byte = mac[bit / 8]; 548 byte >>= (bit & 0x7); 549 byte &= 1; 550 551 return byte; 552 } 553 554 /* 555 * Calculate a GEM MAC Address hash index 556 */ 557 static unsigned calc_mac_hash(const uint8_t *mac) 558 { 559 int index_bit, mac_bit; 560 unsigned hash_index; 561 562 hash_index = 0; 563 mac_bit = 5; 564 for (index_bit = 5; index_bit >= 0; index_bit--) { 565 hash_index |= (get_bit(mac, mac_bit) ^ 566 get_bit(mac, mac_bit + 6) ^ 567 get_bit(mac, mac_bit + 12) ^ 568 get_bit(mac, mac_bit + 18) ^ 569 get_bit(mac, mac_bit + 24) ^ 570 get_bit(mac, mac_bit + 30) ^ 571 get_bit(mac, mac_bit + 36) ^ 572 get_bit(mac, mac_bit + 42)) << index_bit; 573 mac_bit--; 574 } 575 576 return hash_index; 577 } 578 579 /* 580 * gem_mac_address_filter: 581 * Accept or reject this destination address? 582 * Returns: 583 * GEM_RX_REJECT: reject 584 * >= 0: Specific address accept (which matched SAR is returned) 585 * others for various other modes of accept: 586 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT, 587 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT 588 */ 589 static int gem_mac_address_filter(GemState *s, const uint8_t *packet) 590 { 591 uint8_t *gem_spaddr; 592 int i; 593 594 /* Promiscuous mode? */ 595 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) { 596 return GEM_RX_PROMISCUOUS_ACCEPT; 597 } 598 599 if (!memcmp(packet, broadcast_addr, 6)) { 600 /* Reject broadcast packets? */ 601 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) { 602 return GEM_RX_REJECT; 603 } 604 return GEM_RX_BROADCAST_ACCEPT; 605 } 606 607 /* Accept packets -w- hash match? */ 608 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) || 609 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) { 610 unsigned hash_index; 611 612 hash_index = calc_mac_hash(packet); 613 if (hash_index < 32) { 614 if (s->regs[GEM_HASHLO] & (1<<hash_index)) { 615 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 616 GEM_RX_UNICAST_HASH_ACCEPT; 617 } 618 } else { 619 hash_index -= 32; 620 if (s->regs[GEM_HASHHI] & (1<<hash_index)) { 621 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT : 622 GEM_RX_UNICAST_HASH_ACCEPT; 623 } 624 } 625 } 626 627 /* Check all 4 specific addresses */ 628 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]); 629 for (i = 3; i >= 0; i--) { 630 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) { 631 return GEM_RX_SAR_ACCEPT + i; 632 } 633 } 634 635 /* No address match; reject the packet */ 636 return GEM_RX_REJECT; 637 } 638 639 static void gem_get_rx_desc(GemState *s) 640 { 641 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr); 642 /* read current descriptor */ 643 cpu_physical_memory_read(s->rx_desc_addr, 644 (uint8_t *)s->rx_desc, sizeof(s->rx_desc)); 645 646 /* Descriptor owned by software ? */ 647 if (rx_desc_get_ownership(s->rx_desc) == 1) { 648 DB_PRINT("descriptor 0x%x owned by sw.\n", 649 (unsigned)s->rx_desc_addr); 650 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; 651 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); 652 /* Handle interrupt consequences */ 653 gem_update_int_status(s); 654 } 655 } 656 657 /* 658 * gem_receive: 659 * Fit a packet handed to us by QEMU into the receive descriptor ring. 660 */ 661 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) 662 { 663 GemState *s; 664 unsigned rxbufsize, bytes_to_copy; 665 unsigned rxbuf_offset; 666 uint8_t rxbuf[2048]; 667 uint8_t *rxbuf_ptr; 668 bool first_desc = true; 669 int maf; 670 671 s = qemu_get_nic_opaque(nc); 672 673 /* Is this destination MAC address "for us" ? */ 674 maf = gem_mac_address_filter(s, buf); 675 if (maf == GEM_RX_REJECT) { 676 return -1; 677 } 678 679 /* Discard packets with receive length error enabled ? */ 680 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) { 681 unsigned type_len; 682 683 /* Fish the ethertype / length field out of the RX packet */ 684 type_len = buf[12] << 8 | buf[13]; 685 /* It is a length field, not an ethertype */ 686 if (type_len < 0x600) { 687 if (size < type_len) { 688 /* discard */ 689 return -1; 690 } 691 } 692 } 693 694 /* 695 * Determine configured receive buffer offset (probably 0) 696 */ 697 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >> 698 GEM_NWCFG_BUFF_OFST_S; 699 700 /* The configure size of each receive buffer. Determines how many 701 * buffers needed to hold this packet. 702 */ 703 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >> 704 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL; 705 bytes_to_copy = size; 706 707 /* Pad to minimum length. Assume FCS field is stripped, logic 708 * below will increment it to the real minimum of 64 when 709 * not FCS stripping 710 */ 711 if (size < 60) { 712 size = 60; 713 } 714 715 /* Strip of FCS field ? (usually yes) */ 716 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) { 717 rxbuf_ptr = (void *)buf; 718 } else { 719 unsigned crc_val; 720 721 /* The application wants the FCS field, which QEMU does not provide. 722 * We must try and caclculate one. 723 */ 724 725 memcpy(rxbuf, buf, size); 726 memset(rxbuf + size, 0, sizeof(rxbuf) - size); 727 rxbuf_ptr = rxbuf; 728 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60))); 729 memcpy(rxbuf + size, &crc_val, sizeof(crc_val)); 730 731 bytes_to_copy += 4; 732 size += 4; 733 } 734 735 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size); 736 737 while (bytes_to_copy) { 738 /* Do nothing if receive is not enabled. */ 739 if (!gem_can_receive(nc)) { 740 assert(!first_desc); 741 return -1; 742 } 743 744 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize), 745 rx_desc_get_buffer(s->rx_desc)); 746 747 /* Copy packet data to emulated DMA buffer */ 748 cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc) + rxbuf_offset, 749 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); 750 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); 751 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); 752 753 /* Update the descriptor. */ 754 if (first_desc) { 755 rx_desc_set_sof(s->rx_desc); 756 first_desc = false; 757 } 758 if (bytes_to_copy == 0) { 759 rx_desc_set_eof(s->rx_desc); 760 rx_desc_set_length(s->rx_desc, size); 761 } 762 rx_desc_set_ownership(s->rx_desc); 763 764 switch (maf) { 765 case GEM_RX_PROMISCUOUS_ACCEPT: 766 break; 767 case GEM_RX_BROADCAST_ACCEPT: 768 rx_desc_set_broadcast(s->rx_desc); 769 break; 770 case GEM_RX_UNICAST_HASH_ACCEPT: 771 rx_desc_set_unicast_hash(s->rx_desc); 772 break; 773 case GEM_RX_MULTICAST_HASH_ACCEPT: 774 rx_desc_set_multicast_hash(s->rx_desc); 775 break; 776 case GEM_RX_REJECT: 777 abort(); 778 default: /* SAR */ 779 rx_desc_set_sar(s->rx_desc, maf); 780 } 781 782 /* Descriptor write-back. */ 783 cpu_physical_memory_write(s->rx_desc_addr, 784 (uint8_t *)s->rx_desc, sizeof(s->rx_desc)); 785 786 /* Next descriptor */ 787 if (rx_desc_get_wrap(s->rx_desc)) { 788 DB_PRINT("wrapping RX descriptor list\n"); 789 s->rx_desc_addr = s->regs[GEM_RXQBASE]; 790 } else { 791 DB_PRINT("incrementing RX descriptor list\n"); 792 s->rx_desc_addr += 8; 793 } 794 gem_get_rx_desc(s); 795 } 796 797 /* Count it */ 798 gem_receive_updatestats(s, buf, size); 799 800 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD; 801 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]); 802 803 /* Handle interrupt consequences */ 804 gem_update_int_status(s); 805 806 return size; 807 } 808 809 /* 810 * gem_transmit_updatestats: 811 * Increment transmit statistics. 812 */ 813 static void gem_transmit_updatestats(GemState *s, const uint8_t *packet, 814 unsigned bytes) 815 { 816 uint64_t octets; 817 818 /* Total octets (bytes) transmitted */ 819 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) | 820 s->regs[GEM_OCTTXHI]; 821 octets += bytes; 822 s->regs[GEM_OCTTXLO] = octets >> 32; 823 s->regs[GEM_OCTTXHI] = octets; 824 825 /* Error-free Frames transmitted */ 826 s->regs[GEM_TXCNT]++; 827 828 /* Error-free Broadcast Frames counter */ 829 if (!memcmp(packet, broadcast_addr, 6)) { 830 s->regs[GEM_TXBCNT]++; 831 } 832 833 /* Error-free Multicast Frames counter */ 834 if (packet[0] == 0x01) { 835 s->regs[GEM_TXMCNT]++; 836 } 837 838 if (bytes <= 64) { 839 s->regs[GEM_TX64CNT]++; 840 } else if (bytes <= 127) { 841 s->regs[GEM_TX65CNT]++; 842 } else if (bytes <= 255) { 843 s->regs[GEM_TX128CNT]++; 844 } else if (bytes <= 511) { 845 s->regs[GEM_TX256CNT]++; 846 } else if (bytes <= 1023) { 847 s->regs[GEM_TX512CNT]++; 848 } else if (bytes <= 1518) { 849 s->regs[GEM_TX1024CNT]++; 850 } else { 851 s->regs[GEM_TX1519CNT]++; 852 } 853 } 854 855 /* 856 * gem_transmit: 857 * Fish packets out of the descriptor ring and feed them to QEMU 858 */ 859 static void gem_transmit(GemState *s) 860 { 861 unsigned desc[2]; 862 hwaddr packet_desc_addr; 863 uint8_t tx_packet[2048]; 864 uint8_t *p; 865 unsigned total_bytes; 866 867 /* Do nothing if transmit is not enabled. */ 868 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 869 return; 870 } 871 872 DB_PRINT("\n"); 873 874 /* The packet we will hand off to qemu. 875 * Packets scattered across multiple descriptors are gathered to this 876 * one contiguous buffer first. 877 */ 878 p = tx_packet; 879 total_bytes = 0; 880 881 /* read current descriptor */ 882 packet_desc_addr = s->tx_desc_addr; 883 cpu_physical_memory_read(packet_desc_addr, 884 (uint8_t *)&desc[0], sizeof(desc)); 885 /* Handle all descriptors owned by hardware */ 886 while (tx_desc_get_used(desc) == 0) { 887 888 /* Do nothing if transmit is not enabled. */ 889 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) { 890 return; 891 } 892 print_gem_tx_desc(desc); 893 894 /* The real hardware would eat this (and possibly crash). 895 * For QEMU let's lend a helping hand. 896 */ 897 if ((tx_desc_get_buffer(desc) == 0) || 898 (tx_desc_get_length(desc) == 0)) { 899 DB_PRINT("Invalid TX descriptor @ 0x%x\n", 900 (unsigned)packet_desc_addr); 901 break; 902 } 903 904 /* Gather this fragment of the packet from "dma memory" to our contig. 905 * buffer. 906 */ 907 cpu_physical_memory_read(tx_desc_get_buffer(desc), p, 908 tx_desc_get_length(desc)); 909 p += tx_desc_get_length(desc); 910 total_bytes += tx_desc_get_length(desc); 911 912 /* Last descriptor for this packet; hand the whole thing off */ 913 if (tx_desc_get_last(desc)) { 914 /* Modify the 1st descriptor of this packet to be owned by 915 * the processor. 916 */ 917 cpu_physical_memory_read(s->tx_desc_addr, 918 (uint8_t *)&desc[0], sizeof(desc)); 919 tx_desc_set_used(desc); 920 cpu_physical_memory_write(s->tx_desc_addr, 921 (uint8_t *)&desc[0], sizeof(desc)); 922 /* Advance the hardare current descriptor past this packet */ 923 if (tx_desc_get_wrap(desc)) { 924 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 925 } else { 926 s->tx_desc_addr = packet_desc_addr + 8; 927 } 928 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr); 929 930 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL; 931 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]); 932 933 /* Handle interrupt consequences */ 934 gem_update_int_status(s); 935 936 /* Is checksum offload enabled? */ 937 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) { 938 net_checksum_calculate(tx_packet, total_bytes); 939 } 940 941 /* Update MAC statistics */ 942 gem_transmit_updatestats(s, tx_packet, total_bytes); 943 944 /* Send the packet somewhere */ 945 if (s->phy_loop || (s->regs[GEM_NWCTRL] & GEM_NWCTRL_LOCALLOOP)) { 946 gem_receive(qemu_get_queue(s->nic), tx_packet, total_bytes); 947 } else { 948 qemu_send_packet(qemu_get_queue(s->nic), tx_packet, 949 total_bytes); 950 } 951 952 /* Prepare for next packet */ 953 p = tx_packet; 954 total_bytes = 0; 955 } 956 957 /* read next descriptor */ 958 if (tx_desc_get_wrap(desc)) { 959 packet_desc_addr = s->regs[GEM_TXQBASE]; 960 } else { 961 packet_desc_addr += 8; 962 } 963 cpu_physical_memory_read(packet_desc_addr, 964 (uint8_t *)&desc[0], sizeof(desc)); 965 } 966 967 if (tx_desc_get_used(desc)) { 968 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED; 969 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]); 970 gem_update_int_status(s); 971 } 972 } 973 974 static void gem_phy_reset(GemState *s) 975 { 976 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); 977 s->phy_regs[PHY_REG_CONTROL] = 0x1140; 978 s->phy_regs[PHY_REG_STATUS] = 0x7969; 979 s->phy_regs[PHY_REG_PHYID1] = 0x0141; 980 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2; 981 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1; 982 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1; 983 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F; 984 s->phy_regs[PHY_REG_NEXTP] = 0x2001; 985 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6; 986 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300; 987 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; 988 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; 989 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; 990 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00; 991 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; 992 s->phy_regs[PHY_REG_LED] = 0x4100; 993 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; 994 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B; 995 996 phy_update_link(s); 997 } 998 999 static void gem_reset(DeviceState *d) 1000 { 1001 int i; 1002 GemState *s = GEM(d); 1003 1004 DB_PRINT("\n"); 1005 1006 /* Set post reset register values */ 1007 memset(&s->regs[0], 0, sizeof(s->regs)); 1008 s->regs[GEM_NWCFG] = 0x00080000; 1009 s->regs[GEM_NWSTATUS] = 0x00000006; 1010 s->regs[GEM_DMACFG] = 0x00020784; 1011 s->regs[GEM_IMR] = 0x07ffffff; 1012 s->regs[GEM_TXPAUSE] = 0x0000ffff; 1013 s->regs[GEM_TXPARTIALSF] = 0x000003ff; 1014 s->regs[GEM_RXPARTIALSF] = 0x000003ff; 1015 s->regs[GEM_MODID] = 0x00020118; 1016 s->regs[GEM_DESCONF] = 0x02500111; 1017 s->regs[GEM_DESCONF2] = 0x2ab13fff; 1018 s->regs[GEM_DESCONF5] = 0x002f2145; 1019 s->regs[GEM_DESCONF6] = 0x00000200; 1020 1021 for (i = 0; i < 4; i++) { 1022 s->sar_active[i] = false; 1023 } 1024 1025 gem_phy_reset(s); 1026 1027 gem_update_int_status(s); 1028 } 1029 1030 static uint16_t gem_phy_read(GemState *s, unsigned reg_num) 1031 { 1032 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]); 1033 return s->phy_regs[reg_num]; 1034 } 1035 1036 static void gem_phy_write(GemState *s, unsigned reg_num, uint16_t val) 1037 { 1038 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); 1039 1040 switch (reg_num) { 1041 case PHY_REG_CONTROL: 1042 if (val & PHY_REG_CONTROL_RST) { 1043 /* Phy reset */ 1044 gem_phy_reset(s); 1045 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP); 1046 s->phy_loop = 0; 1047 } 1048 if (val & PHY_REG_CONTROL_ANEG) { 1049 /* Complete autonegotiation immediately */ 1050 val &= ~PHY_REG_CONTROL_ANEG; 1051 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL; 1052 } 1053 if (val & PHY_REG_CONTROL_LOOP) { 1054 DB_PRINT("PHY placed in loopback\n"); 1055 s->phy_loop = 1; 1056 } else { 1057 s->phy_loop = 0; 1058 } 1059 break; 1060 } 1061 s->phy_regs[reg_num] = val; 1062 } 1063 1064 /* 1065 * gem_read32: 1066 * Read a GEM register. 1067 */ 1068 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) 1069 { 1070 GemState *s; 1071 uint32_t retval; 1072 1073 s = (GemState *)opaque; 1074 1075 offset >>= 2; 1076 retval = s->regs[offset]; 1077 1078 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval); 1079 1080 switch (offset) { 1081 case GEM_ISR: 1082 DB_PRINT("lowering irq on ISR read\n"); 1083 qemu_set_irq(s->irq, 0); 1084 break; 1085 case GEM_PHYMNTNC: 1086 if (retval & GEM_PHYMNTNC_OP_R) { 1087 uint32_t phy_addr, reg_num; 1088 1089 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1090 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1091 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1092 retval &= 0xFFFF0000; 1093 retval |= gem_phy_read(s, reg_num); 1094 } else { 1095 retval |= 0xFFFF; /* No device at this address */ 1096 } 1097 } 1098 break; 1099 } 1100 1101 /* Squash read to clear bits */ 1102 s->regs[offset] &= ~(s->regs_rtc[offset]); 1103 1104 /* Do not provide write only bits */ 1105 retval &= ~(s->regs_wo[offset]); 1106 1107 DB_PRINT("0x%08x\n", retval); 1108 return retval; 1109 } 1110 1111 /* 1112 * gem_write32: 1113 * Write a GEM register. 1114 */ 1115 static void gem_write(void *opaque, hwaddr offset, uint64_t val, 1116 unsigned size) 1117 { 1118 GemState *s = (GemState *)opaque; 1119 uint32_t readonly; 1120 1121 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val); 1122 offset >>= 2; 1123 1124 /* Squash bits which are read only in write value */ 1125 val &= ~(s->regs_ro[offset]); 1126 /* Preserve (only) bits which are read only and wtc in register */ 1127 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]); 1128 1129 /* Copy register write to backing store */ 1130 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly; 1131 1132 /* do w1c */ 1133 s->regs[offset] &= ~(s->regs_w1c[offset] & val); 1134 1135 /* Handle register write side effects */ 1136 switch (offset) { 1137 case GEM_NWCTRL: 1138 if (val & GEM_NWCTRL_RXENA) { 1139 gem_get_rx_desc(s); 1140 } 1141 if (val & GEM_NWCTRL_TXSTART) { 1142 gem_transmit(s); 1143 } 1144 if (!(val & GEM_NWCTRL_TXENA)) { 1145 /* Reset to start of Q when transmit disabled. */ 1146 s->tx_desc_addr = s->regs[GEM_TXQBASE]; 1147 } 1148 if (gem_can_receive(qemu_get_queue(s->nic))) { 1149 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 1150 } 1151 break; 1152 1153 case GEM_TXSTATUS: 1154 gem_update_int_status(s); 1155 break; 1156 case GEM_RXQBASE: 1157 s->rx_desc_addr = val; 1158 break; 1159 case GEM_TXQBASE: 1160 s->tx_desc_addr = val; 1161 break; 1162 case GEM_RXSTATUS: 1163 gem_update_int_status(s); 1164 break; 1165 case GEM_IER: 1166 s->regs[GEM_IMR] &= ~val; 1167 gem_update_int_status(s); 1168 break; 1169 case GEM_IDR: 1170 s->regs[GEM_IMR] |= val; 1171 gem_update_int_status(s); 1172 break; 1173 case GEM_SPADDR1LO: 1174 case GEM_SPADDR2LO: 1175 case GEM_SPADDR3LO: 1176 case GEM_SPADDR4LO: 1177 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false; 1178 break; 1179 case GEM_SPADDR1HI: 1180 case GEM_SPADDR2HI: 1181 case GEM_SPADDR3HI: 1182 case GEM_SPADDR4HI: 1183 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true; 1184 break; 1185 case GEM_PHYMNTNC: 1186 if (val & GEM_PHYMNTNC_OP_W) { 1187 uint32_t phy_addr, reg_num; 1188 1189 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; 1190 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { 1191 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; 1192 gem_phy_write(s, reg_num, val); 1193 } 1194 } 1195 break; 1196 } 1197 1198 DB_PRINT("newval: 0x%08x\n", s->regs[offset]); 1199 } 1200 1201 static const MemoryRegionOps gem_ops = { 1202 .read = gem_read, 1203 .write = gem_write, 1204 .endianness = DEVICE_LITTLE_ENDIAN, 1205 }; 1206 1207 static void gem_cleanup(NetClientState *nc) 1208 { 1209 GemState *s = qemu_get_nic_opaque(nc); 1210 1211 DB_PRINT("\n"); 1212 s->nic = NULL; 1213 } 1214 1215 static void gem_set_link(NetClientState *nc) 1216 { 1217 DB_PRINT("\n"); 1218 phy_update_link(qemu_get_nic_opaque(nc)); 1219 } 1220 1221 static NetClientInfo net_gem_info = { 1222 .type = NET_CLIENT_OPTIONS_KIND_NIC, 1223 .size = sizeof(NICState), 1224 .can_receive = gem_can_receive, 1225 .receive = gem_receive, 1226 .cleanup = gem_cleanup, 1227 .link_status_changed = gem_set_link, 1228 }; 1229 1230 static int gem_init(SysBusDevice *sbd) 1231 { 1232 DeviceState *dev = DEVICE(sbd); 1233 GemState *s = GEM(dev); 1234 1235 DB_PRINT("\n"); 1236 1237 gem_init_register_masks(s); 1238 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s, 1239 "enet", sizeof(s->regs)); 1240 sysbus_init_mmio(sbd, &s->iomem); 1241 sysbus_init_irq(sbd, &s->irq); 1242 qemu_macaddr_default_if_unset(&s->conf.macaddr); 1243 1244 s->nic = qemu_new_nic(&net_gem_info, &s->conf, 1245 object_get_typename(OBJECT(dev)), dev->id, s); 1246 1247 return 0; 1248 } 1249 1250 static const VMStateDescription vmstate_cadence_gem = { 1251 .name = "cadence_gem", 1252 .version_id = 2, 1253 .minimum_version_id = 2, 1254 .fields = (VMStateField[]) { 1255 VMSTATE_UINT32_ARRAY(regs, GemState, GEM_MAXREG), 1256 VMSTATE_UINT16_ARRAY(phy_regs, GemState, 32), 1257 VMSTATE_UINT8(phy_loop, GemState), 1258 VMSTATE_UINT32(rx_desc_addr, GemState), 1259 VMSTATE_UINT32(tx_desc_addr, GemState), 1260 VMSTATE_BOOL_ARRAY(sar_active, GemState, 4), 1261 VMSTATE_END_OF_LIST(), 1262 } 1263 }; 1264 1265 static Property gem_properties[] = { 1266 DEFINE_NIC_PROPERTIES(GemState, conf), 1267 DEFINE_PROP_END_OF_LIST(), 1268 }; 1269 1270 static void gem_class_init(ObjectClass *klass, void *data) 1271 { 1272 DeviceClass *dc = DEVICE_CLASS(klass); 1273 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 1274 1275 sdc->init = gem_init; 1276 dc->props = gem_properties; 1277 dc->vmsd = &vmstate_cadence_gem; 1278 dc->reset = gem_reset; 1279 } 1280 1281 static const TypeInfo gem_info = { 1282 .name = TYPE_CADENCE_GEM, 1283 .parent = TYPE_SYS_BUS_DEVICE, 1284 .instance_size = sizeof(GemState), 1285 .class_init = gem_class_init, 1286 }; 1287 1288 static void gem_register_types(void) 1289 { 1290 type_register_static(&gem_info); 1291 } 1292 1293 type_init(gem_register_types) 1294