1 /** 2 * QEMU RTL8139 emulation 3 * 4 * Copyright (c) 2006 Igor Kovalenko 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 24 * Modifications: 25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver) 26 * 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver 28 * HW revision ID changes for FreeBSD driver 29 * 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver 31 * Corrected packet transfer reassembly routine for 8139C+ mode 32 * Rearranged debugging print statements 33 * Implemented PCI timer interrupt (disabled by default) 34 * Implemented Tally Counters, increased VM load/save version 35 * Implemented IP/TCP/UDP checksum task offloading 36 * 37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading 38 * Fixed MTU=1500 for produced ethernet frames 39 * 40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing 41 * segmentation offloading 42 * Removed slirp.h dependency 43 * Added rx/tx buffer reset when enabling rx/tx operation 44 * 45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only 46 * when strictly needed (required for 47 * Darwin) 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading 49 */ 50 51 /* For crc32 */ 52 #include "qemu/osdep.h" 53 #include <zlib.h> 54 55 #include "hw/hw.h" 56 #include "hw/pci/pci.h" 57 #include "sysemu/dma.h" 58 #include "qemu/timer.h" 59 #include "net/net.h" 60 #include "net/eth.h" 61 #include "hw/loader.h" 62 #include "sysemu/sysemu.h" 63 #include "qemu/iov.h" 64 65 /* debug RTL8139 card */ 66 //#define DEBUG_RTL8139 1 67 68 #define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ 69 70 #define SET_MASKED(input, mask, curr) \ 71 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) 72 73 /* arg % size for size which is a power of 2 */ 74 #define MOD2(input, size) \ 75 ( ( input ) & ( size - 1 ) ) 76 77 #define ETHER_TYPE_LEN 2 78 #define ETH_MTU 1500 79 80 #define VLAN_TCI_LEN 2 81 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) 82 83 #if defined (DEBUG_RTL8139) 84 # define DPRINTF(fmt, ...) \ 85 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0) 86 #else 87 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...) 88 { 89 return 0; 90 } 91 #endif 92 93 #define TYPE_RTL8139 "rtl8139" 94 95 #define RTL8139(obj) \ 96 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139) 97 98 /* Symbolic offsets to registers. */ 99 enum RTL8139_registers { 100 MAC0 = 0, /* Ethernet hardware address. */ 101 MAR0 = 8, /* Multicast filter. */ 102 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ 103 /* Dump Tally Conter control register(64bit). C+ mode only */ 104 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 105 RxBuf = 0x30, 106 ChipCmd = 0x37, 107 RxBufPtr = 0x38, 108 RxBufAddr = 0x3A, 109 IntrMask = 0x3C, 110 IntrStatus = 0x3E, 111 TxConfig = 0x40, 112 RxConfig = 0x44, 113 Timer = 0x48, /* A general-purpose counter. */ 114 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 115 Cfg9346 = 0x50, 116 Config0 = 0x51, 117 Config1 = 0x52, 118 FlashReg = 0x54, 119 MediaStatus = 0x58, 120 Config3 = 0x59, 121 Config4 = 0x5A, /* absent on RTL-8139A */ 122 HltClk = 0x5B, 123 MultiIntr = 0x5C, 124 PCIRevisionID = 0x5E, 125 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ 126 BasicModeCtrl = 0x62, 127 BasicModeStatus = 0x64, 128 NWayAdvert = 0x66, 129 NWayLPAR = 0x68, 130 NWayExpansion = 0x6A, 131 /* Undocumented registers, but required for proper operation. */ 132 FIFOTMS = 0x70, /* FIFO Control and test. */ 133 CSCR = 0x74, /* Chip Status and Configuration Register. */ 134 PARA78 = 0x78, 135 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 136 Config5 = 0xD8, /* absent on RTL-8139A */ 137 /* C+ mode */ 138 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ 139 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ 140 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ 141 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ 142 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ 143 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ 144 TxThresh = 0xEC, /* Early Tx threshold */ 145 }; 146 147 enum ClearBitMasks { 148 MultiIntrClear = 0xF000, 149 ChipCmdClear = 0xE2, 150 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 151 }; 152 153 enum ChipCmdBits { 154 CmdReset = 0x10, 155 CmdRxEnb = 0x08, 156 CmdTxEnb = 0x04, 157 RxBufEmpty = 0x01, 158 }; 159 160 /* C+ mode */ 161 enum CplusCmdBits { 162 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */ 163 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */ 164 CPlusRxEnb = 0x0002, 165 CPlusTxEnb = 0x0001, 166 }; 167 168 /* Interrupt register bits, using my own meaningful names. */ 169 enum IntrStatusBits { 170 PCIErr = 0x8000, 171 PCSTimeout = 0x4000, 172 RxFIFOOver = 0x40, 173 RxUnderrun = 0x20, /* Packet Underrun / Link Change */ 174 RxOverflow = 0x10, 175 TxErr = 0x08, 176 TxOK = 0x04, 177 RxErr = 0x02, 178 RxOK = 0x01, 179 180 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 181 }; 182 183 enum TxStatusBits { 184 TxHostOwns = 0x2000, 185 TxUnderrun = 0x4000, 186 TxStatOK = 0x8000, 187 TxOutOfWindow = 0x20000000, 188 TxAborted = 0x40000000, 189 TxCarrierLost = 0x80000000, 190 }; 191 enum RxStatusBits { 192 RxMulticast = 0x8000, 193 RxPhysical = 0x4000, 194 RxBroadcast = 0x2000, 195 RxBadSymbol = 0x0020, 196 RxRunt = 0x0010, 197 RxTooLong = 0x0008, 198 RxCRCErr = 0x0004, 199 RxBadAlign = 0x0002, 200 RxStatusOK = 0x0001, 201 }; 202 203 /* Bits in RxConfig. */ 204 enum rx_mode_bits { 205 AcceptErr = 0x20, 206 AcceptRunt = 0x10, 207 AcceptBroadcast = 0x08, 208 AcceptMulticast = 0x04, 209 AcceptMyPhys = 0x02, 210 AcceptAllPhys = 0x01, 211 }; 212 213 /* Bits in TxConfig. */ 214 enum tx_config_bits { 215 216 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 217 TxIFGShift = 24, 218 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 219 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 220 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 221 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 222 223 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 224 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ 225 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 226 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ 227 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ 228 229 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 230 }; 231 232 233 /* Transmit Status of All Descriptors (TSAD) Register */ 234 enum TSAD_bits { 235 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 236 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 237 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 238 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 239 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 240 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 241 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 242 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 243 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 244 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 245 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 246 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 247 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 248 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 249 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 250 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 251 }; 252 253 254 /* Bits in Config1 */ 255 enum Config1Bits { 256 Cfg1_PM_Enable = 0x01, 257 Cfg1_VPD_Enable = 0x02, 258 Cfg1_PIO = 0x04, 259 Cfg1_MMIO = 0x08, 260 LWAKE = 0x10, /* not on 8139, 8139A */ 261 Cfg1_Driver_Load = 0x20, 262 Cfg1_LED0 = 0x40, 263 Cfg1_LED1 = 0x80, 264 SLEEP = (1 << 1), /* only on 8139, 8139A */ 265 PWRDN = (1 << 0), /* only on 8139, 8139A */ 266 }; 267 268 /* Bits in Config3 */ 269 enum Config3Bits { 270 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 271 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 272 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 273 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 274 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 275 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 276 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 277 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 278 }; 279 280 /* Bits in Config4 */ 281 enum Config4Bits { 282 LWPTN = (1 << 2), /* not on 8139, 8139A */ 283 }; 284 285 /* Bits in Config5 */ 286 enum Config5Bits { 287 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 288 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 289 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 290 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */ 291 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 292 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 293 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 294 }; 295 296 enum RxConfigBits { 297 /* rx fifo threshold */ 298 RxCfgFIFOShift = 13, 299 RxCfgFIFONone = (7 << RxCfgFIFOShift), 300 301 /* Max DMA burst */ 302 RxCfgDMAShift = 8, 303 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 304 305 /* rx ring buffer length */ 306 RxCfgRcv8K = 0, 307 RxCfgRcv16K = (1 << 11), 308 RxCfgRcv32K = (1 << 12), 309 RxCfgRcv64K = (1 << 11) | (1 << 12), 310 311 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 312 RxNoWrap = (1 << 7), 313 }; 314 315 /* Twister tuning parameters from RealTek. 316 Completely undocumented, but required to tune bad links on some boards. */ 317 /* 318 enum CSCRBits { 319 CSCR_LinkOKBit = 0x0400, 320 CSCR_LinkChangeBit = 0x0800, 321 CSCR_LinkStatusBits = 0x0f000, 322 CSCR_LinkDownOffCmd = 0x003c0, 323 CSCR_LinkDownCmd = 0x0f3c0, 324 */ 325 enum CSCRBits { 326 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ 327 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ 328 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ 329 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ 330 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ 331 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ 332 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ 333 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ 334 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ 335 }; 336 337 enum Cfg9346Bits { 338 Cfg9346_Normal = 0x00, 339 Cfg9346_Autoload = 0x40, 340 Cfg9346_Programming = 0x80, 341 Cfg9346_ConfigWrite = 0xC0, 342 }; 343 344 typedef enum { 345 CH_8139 = 0, 346 CH_8139_K, 347 CH_8139A, 348 CH_8139A_G, 349 CH_8139B, 350 CH_8130, 351 CH_8139C, 352 CH_8100, 353 CH_8100B_8139D, 354 CH_8101, 355 } chip_t; 356 357 enum chip_flags { 358 HasHltClk = (1 << 0), 359 HasLWake = (1 << 1), 360 }; 361 362 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 363 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 364 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 365 366 #define RTL8139_PCI_REVID_8139 0x10 367 #define RTL8139_PCI_REVID_8139CPLUS 0x20 368 369 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS 370 371 /* Size is 64 * 16bit words */ 372 #define EEPROM_9346_ADDR_BITS 6 373 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) 374 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) 375 376 enum Chip9346Operation 377 { 378 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ 379 Chip9346_op_read = 0x80, /* 10 AAAAAA */ 380 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ 381 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ 382 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ 383 Chip9346_op_write_all = 0x10, /* 00 01zzzz */ 384 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ 385 }; 386 387 enum Chip9346Mode 388 { 389 Chip9346_none = 0, 390 Chip9346_enter_command_mode, 391 Chip9346_read_command, 392 Chip9346_data_read, /* from output register */ 393 Chip9346_data_write, /* to input register, then to contents at specified address */ 394 Chip9346_data_write_all, /* to input register, then filling contents */ 395 }; 396 397 typedef struct EEprom9346 398 { 399 uint16_t contents[EEPROM_9346_SIZE]; 400 int mode; 401 uint32_t tick; 402 uint8_t address; 403 uint16_t input; 404 uint16_t output; 405 406 uint8_t eecs; 407 uint8_t eesk; 408 uint8_t eedi; 409 uint8_t eedo; 410 } EEprom9346; 411 412 typedef struct RTL8139TallyCounters 413 { 414 /* Tally counters */ 415 uint64_t TxOk; 416 uint64_t RxOk; 417 uint64_t TxERR; 418 uint32_t RxERR; 419 uint16_t MissPkt; 420 uint16_t FAE; 421 uint32_t Tx1Col; 422 uint32_t TxMCol; 423 uint64_t RxOkPhy; 424 uint64_t RxOkBrd; 425 uint32_t RxOkMul; 426 uint16_t TxAbt; 427 uint16_t TxUndrn; 428 } RTL8139TallyCounters; 429 430 /* Clears all tally counters */ 431 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); 432 433 typedef struct RTL8139State { 434 /*< private >*/ 435 PCIDevice parent_obj; 436 /*< public >*/ 437 438 uint8_t phys[8]; /* mac address */ 439 uint8_t mult[8]; /* multicast mask array */ 440 441 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */ 442 uint32_t TxAddr[4]; /* TxAddr0 */ 443 uint32_t RxBuf; /* Receive buffer */ 444 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */ 445 uint32_t RxBufPtr; 446 uint32_t RxBufAddr; 447 448 uint16_t IntrStatus; 449 uint16_t IntrMask; 450 451 uint32_t TxConfig; 452 uint32_t RxConfig; 453 uint32_t RxMissed; 454 455 uint16_t CSCR; 456 457 uint8_t Cfg9346; 458 uint8_t Config0; 459 uint8_t Config1; 460 uint8_t Config3; 461 uint8_t Config4; 462 uint8_t Config5; 463 464 uint8_t clock_enabled; 465 uint8_t bChipCmdState; 466 467 uint16_t MultiIntr; 468 469 uint16_t BasicModeCtrl; 470 uint16_t BasicModeStatus; 471 uint16_t NWayAdvert; 472 uint16_t NWayLPAR; 473 uint16_t NWayExpansion; 474 475 uint16_t CpCmd; 476 uint8_t TxThresh; 477 478 NICState *nic; 479 NICConf conf; 480 481 /* C ring mode */ 482 uint32_t currTxDesc; 483 484 /* C+ mode */ 485 uint32_t cplus_enabled; 486 487 uint32_t currCPlusRxDesc; 488 uint32_t currCPlusTxDesc; 489 490 uint32_t RxRingAddrLO; 491 uint32_t RxRingAddrHI; 492 493 EEprom9346 eeprom; 494 495 uint32_t TCTR; 496 uint32_t TimerInt; 497 int64_t TCTR_base; 498 499 /* Tally counters */ 500 RTL8139TallyCounters tally_counters; 501 502 /* Non-persistent data */ 503 uint8_t *cplus_txbuffer; 504 int cplus_txbuffer_len; 505 int cplus_txbuffer_offset; 506 507 /* PCI interrupt timer */ 508 QEMUTimer *timer; 509 510 MemoryRegion bar_io; 511 MemoryRegion bar_mem; 512 513 /* Support migration to/from old versions */ 514 int rtl8139_mmio_io_addr_dummy; 515 } RTL8139State; 516 517 /* Writes tally counters to memory via DMA */ 518 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr); 519 520 static void rtl8139_set_next_tctr_time(RTL8139State *s); 521 522 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) 523 { 524 DPRINTF("eeprom command 0x%02x\n", command); 525 526 switch (command & Chip9346_op_mask) 527 { 528 case Chip9346_op_read: 529 { 530 eeprom->address = command & EEPROM_9346_ADDR_MASK; 531 eeprom->output = eeprom->contents[eeprom->address]; 532 eeprom->eedo = 0; 533 eeprom->tick = 0; 534 eeprom->mode = Chip9346_data_read; 535 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", 536 eeprom->address, eeprom->output); 537 } 538 break; 539 540 case Chip9346_op_write: 541 { 542 eeprom->address = command & EEPROM_9346_ADDR_MASK; 543 eeprom->input = 0; 544 eeprom->tick = 0; 545 eeprom->mode = Chip9346_none; /* Chip9346_data_write */ 546 DPRINTF("eeprom begin write to address 0x%02x\n", 547 eeprom->address); 548 } 549 break; 550 default: 551 eeprom->mode = Chip9346_none; 552 switch (command & Chip9346_op_ext_mask) 553 { 554 case Chip9346_op_write_enable: 555 DPRINTF("eeprom write enabled\n"); 556 break; 557 case Chip9346_op_write_all: 558 DPRINTF("eeprom begin write all\n"); 559 break; 560 case Chip9346_op_write_disable: 561 DPRINTF("eeprom write disabled\n"); 562 break; 563 } 564 break; 565 } 566 } 567 568 static void prom9346_shift_clock(EEprom9346 *eeprom) 569 { 570 int bit = eeprom->eedi?1:0; 571 572 ++ eeprom->tick; 573 574 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, 575 eeprom->eedo); 576 577 switch (eeprom->mode) 578 { 579 case Chip9346_enter_command_mode: 580 if (bit) 581 { 582 eeprom->mode = Chip9346_read_command; 583 eeprom->tick = 0; 584 eeprom->input = 0; 585 DPRINTF("eeprom: +++ synchronized, begin command read\n"); 586 } 587 break; 588 589 case Chip9346_read_command: 590 eeprom->input = (eeprom->input << 1) | (bit & 1); 591 if (eeprom->tick == 8) 592 { 593 prom9346_decode_command(eeprom, eeprom->input & 0xff); 594 } 595 break; 596 597 case Chip9346_data_read: 598 eeprom->eedo = (eeprom->output & 0x8000)?1:0; 599 eeprom->output <<= 1; 600 if (eeprom->tick == 16) 601 { 602 #if 1 603 // the FreeBSD drivers (rl and re) don't explicitly toggle 604 // CS between reads (or does setting Cfg9346 to 0 count too?), 605 // so we need to enter wait-for-command state here 606 eeprom->mode = Chip9346_enter_command_mode; 607 eeprom->input = 0; 608 eeprom->tick = 0; 609 610 DPRINTF("eeprom: +++ end of read, awaiting next command\n"); 611 #else 612 // original behaviour 613 ++eeprom->address; 614 eeprom->address &= EEPROM_9346_ADDR_MASK; 615 eeprom->output = eeprom->contents[eeprom->address]; 616 eeprom->tick = 0; 617 618 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", 619 eeprom->address, eeprom->output); 620 #endif 621 } 622 break; 623 624 case Chip9346_data_write: 625 eeprom->input = (eeprom->input << 1) | (bit & 1); 626 if (eeprom->tick == 16) 627 { 628 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", 629 eeprom->address, eeprom->input); 630 631 eeprom->contents[eeprom->address] = eeprom->input; 632 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ 633 eeprom->tick = 0; 634 eeprom->input = 0; 635 } 636 break; 637 638 case Chip9346_data_write_all: 639 eeprom->input = (eeprom->input << 1) | (bit & 1); 640 if (eeprom->tick == 16) 641 { 642 int i; 643 for (i = 0; i < EEPROM_9346_SIZE; i++) 644 { 645 eeprom->contents[i] = eeprom->input; 646 } 647 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); 648 649 eeprom->mode = Chip9346_enter_command_mode; 650 eeprom->tick = 0; 651 eeprom->input = 0; 652 } 653 break; 654 655 default: 656 break; 657 } 658 } 659 660 static int prom9346_get_wire(RTL8139State *s) 661 { 662 EEprom9346 *eeprom = &s->eeprom; 663 if (!eeprom->eecs) 664 return 0; 665 666 return eeprom->eedo; 667 } 668 669 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */ 670 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) 671 { 672 EEprom9346 *eeprom = &s->eeprom; 673 uint8_t old_eecs = eeprom->eecs; 674 uint8_t old_eesk = eeprom->eesk; 675 676 eeprom->eecs = eecs; 677 eeprom->eesk = eesk; 678 eeprom->eedi = eedi; 679 680 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, 681 eeprom->eesk, eeprom->eedi, eeprom->eedo); 682 683 if (!old_eecs && eecs) 684 { 685 /* Synchronize start */ 686 eeprom->tick = 0; 687 eeprom->input = 0; 688 eeprom->output = 0; 689 eeprom->mode = Chip9346_enter_command_mode; 690 691 DPRINTF("=== eeprom: begin access, enter command mode\n"); 692 } 693 694 if (!eecs) 695 { 696 DPRINTF("=== eeprom: end access\n"); 697 return; 698 } 699 700 if (!old_eesk && eesk) 701 { 702 /* SK front rules */ 703 prom9346_shift_clock(eeprom); 704 } 705 } 706 707 static void rtl8139_update_irq(RTL8139State *s) 708 { 709 PCIDevice *d = PCI_DEVICE(s); 710 int isr; 711 isr = (s->IntrStatus & s->IntrMask) & 0xffff; 712 713 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, 714 s->IntrMask); 715 716 pci_set_irq(d, (isr != 0)); 717 } 718 719 static int rtl8139_RxWrap(RTL8139State *s) 720 { 721 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */ 722 return (s->RxConfig & (1 << 7)); 723 } 724 725 static int rtl8139_receiver_enabled(RTL8139State *s) 726 { 727 return s->bChipCmdState & CmdRxEnb; 728 } 729 730 static int rtl8139_transmitter_enabled(RTL8139State *s) 731 { 732 return s->bChipCmdState & CmdTxEnb; 733 } 734 735 static int rtl8139_cp_receiver_enabled(RTL8139State *s) 736 { 737 return s->CpCmd & CPlusRxEnb; 738 } 739 740 static int rtl8139_cp_transmitter_enabled(RTL8139State *s) 741 { 742 return s->CpCmd & CPlusTxEnb; 743 } 744 745 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) 746 { 747 PCIDevice *d = PCI_DEVICE(s); 748 749 if (s->RxBufAddr + size > s->RxBufferSize) 750 { 751 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize); 752 753 /* write packet data */ 754 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s))) 755 { 756 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped); 757 758 if (size > wrapped) 759 { 760 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 761 buf, size-wrapped); 762 } 763 764 /* reset buffer pointer */ 765 s->RxBufAddr = 0; 766 767 pci_dma_write(d, s->RxBuf + s->RxBufAddr, 768 buf + (size-wrapped), wrapped); 769 770 s->RxBufAddr = wrapped; 771 772 return; 773 } 774 } 775 776 /* non-wrapping path or overwrapping enabled */ 777 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size); 778 779 s->RxBufAddr += size; 780 } 781 782 #define MIN_BUF_SIZE 60 783 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high) 784 { 785 return low | ((uint64_t)high << 32); 786 } 787 788 /* Workaround for buggy guest driver such as linux who allocates rx 789 * rings after the receiver were enabled. */ 790 static bool rtl8139_cp_rx_valid(RTL8139State *s) 791 { 792 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0); 793 } 794 795 static int rtl8139_can_receive(NetClientState *nc) 796 { 797 RTL8139State *s = qemu_get_nic_opaque(nc); 798 int avail; 799 800 /* Receive (drop) packets if card is disabled. */ 801 if (!s->clock_enabled) 802 return 1; 803 if (!rtl8139_receiver_enabled(s)) 804 return 1; 805 806 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) { 807 /* ??? Flow control not implemented in c+ mode. 808 This is a hack to work around slirp deficiencies anyway. */ 809 return 1; 810 } else { 811 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, 812 s->RxBufferSize); 813 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow)); 814 } 815 } 816 817 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt) 818 { 819 RTL8139State *s = qemu_get_nic_opaque(nc); 820 PCIDevice *d = PCI_DEVICE(s); 821 /* size is the length of the buffer passed to the driver */ 822 int size = size_; 823 const uint8_t *dot1q_buf = NULL; 824 825 uint32_t packet_header = 0; 826 827 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN]; 828 static const uint8_t broadcast_macaddr[6] = 829 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 830 831 DPRINTF(">>> received len=%d\n", size); 832 833 /* test if board clock is stopped */ 834 if (!s->clock_enabled) 835 { 836 DPRINTF("stopped ==========================\n"); 837 return -1; 838 } 839 840 /* first check if receiver is enabled */ 841 842 if (!rtl8139_receiver_enabled(s)) 843 { 844 DPRINTF("receiver disabled ================\n"); 845 return -1; 846 } 847 848 /* XXX: check this */ 849 if (s->RxConfig & AcceptAllPhys) { 850 /* promiscuous: receive all */ 851 DPRINTF(">>> packet received in promiscuous mode\n"); 852 853 } else { 854 if (!memcmp(buf, broadcast_macaddr, 6)) { 855 /* broadcast address */ 856 if (!(s->RxConfig & AcceptBroadcast)) 857 { 858 DPRINTF(">>> broadcast packet rejected\n"); 859 860 /* update tally counter */ 861 ++s->tally_counters.RxERR; 862 863 return size; 864 } 865 866 packet_header |= RxBroadcast; 867 868 DPRINTF(">>> broadcast packet received\n"); 869 870 /* update tally counter */ 871 ++s->tally_counters.RxOkBrd; 872 873 } else if (buf[0] & 0x01) { 874 /* multicast */ 875 if (!(s->RxConfig & AcceptMulticast)) 876 { 877 DPRINTF(">>> multicast packet rejected\n"); 878 879 /* update tally counter */ 880 ++s->tally_counters.RxERR; 881 882 return size; 883 } 884 885 int mcast_idx = compute_mcast_idx(buf); 886 887 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) 888 { 889 DPRINTF(">>> multicast address mismatch\n"); 890 891 /* update tally counter */ 892 ++s->tally_counters.RxERR; 893 894 return size; 895 } 896 897 packet_header |= RxMulticast; 898 899 DPRINTF(">>> multicast packet received\n"); 900 901 /* update tally counter */ 902 ++s->tally_counters.RxOkMul; 903 904 } else if (s->phys[0] == buf[0] && 905 s->phys[1] == buf[1] && 906 s->phys[2] == buf[2] && 907 s->phys[3] == buf[3] && 908 s->phys[4] == buf[4] && 909 s->phys[5] == buf[5]) { 910 /* match */ 911 if (!(s->RxConfig & AcceptMyPhys)) 912 { 913 DPRINTF(">>> rejecting physical address matching packet\n"); 914 915 /* update tally counter */ 916 ++s->tally_counters.RxERR; 917 918 return size; 919 } 920 921 packet_header |= RxPhysical; 922 923 DPRINTF(">>> physical address matching packet received\n"); 924 925 /* update tally counter */ 926 ++s->tally_counters.RxOkPhy; 927 928 } else { 929 930 DPRINTF(">>> unknown packet\n"); 931 932 /* update tally counter */ 933 ++s->tally_counters.RxERR; 934 935 return size; 936 } 937 } 938 939 /* if too small buffer, then expand it 940 * Include some tailroom in case a vlan tag is later removed. */ 941 if (size < MIN_BUF_SIZE + VLAN_HLEN) { 942 memcpy(buf1, buf, size); 943 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size); 944 buf = buf1; 945 if (size < MIN_BUF_SIZE) { 946 size = MIN_BUF_SIZE; 947 } 948 } 949 950 if (rtl8139_cp_receiver_enabled(s)) 951 { 952 if (!rtl8139_cp_rx_valid(s)) { 953 return size; 954 } 955 956 DPRINTF("in C+ Rx mode ================\n"); 957 958 /* begin C+ receiver mode */ 959 960 /* w0 ownership flag */ 961 #define CP_RX_OWN (1<<31) 962 /* w0 end of ring flag */ 963 #define CP_RX_EOR (1<<30) 964 /* w0 bits 0...12 : buffer size */ 965 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) 966 /* w1 tag available flag */ 967 #define CP_RX_TAVA (1<<16) 968 /* w1 bits 0...15 : VLAN tag */ 969 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) 970 /* w2 low 32bit of Rx buffer ptr */ 971 /* w3 high 32bit of Rx buffer ptr */ 972 973 int descriptor = s->currCPlusRxDesc; 974 dma_addr_t cplus_rx_ring_desc; 975 976 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); 977 cplus_rx_ring_desc += 16 * descriptor; 978 979 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " 980 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI, 981 s->RxRingAddrLO, cplus_rx_ring_desc); 982 983 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI; 984 985 pci_dma_read(d, cplus_rx_ring_desc, &val, 4); 986 rxdw0 = le32_to_cpu(val); 987 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4); 988 rxdw1 = le32_to_cpu(val); 989 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4); 990 rxbufLO = le32_to_cpu(val); 991 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4); 992 rxbufHI = le32_to_cpu(val); 993 994 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", 995 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); 996 997 if (!(rxdw0 & CP_RX_OWN)) 998 { 999 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", 1000 descriptor); 1001 1002 s->IntrStatus |= RxOverflow; 1003 ++s->RxMissed; 1004 1005 /* update tally counter */ 1006 ++s->tally_counters.RxERR; 1007 ++s->tally_counters.MissPkt; 1008 1009 rtl8139_update_irq(s); 1010 return size_; 1011 } 1012 1013 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; 1014 1015 /* write VLAN info to descriptor variables. */ 1016 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *) 1017 &buf[ETH_ALEN * 2]) == ETH_P_VLAN) { 1018 dot1q_buf = &buf[ETH_ALEN * 2]; 1019 size -= VLAN_HLEN; 1020 /* if too small buffer, use the tailroom added duing expansion */ 1021 if (size < MIN_BUF_SIZE) { 1022 size = MIN_BUF_SIZE; 1023 } 1024 1025 rxdw1 &= ~CP_RX_VLAN_TAG_MASK; 1026 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ 1027 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *) 1028 &dot1q_buf[ETHER_TYPE_LEN]); 1029 1030 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", 1031 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN])); 1032 } else { 1033 /* reset VLAN tag flag */ 1034 rxdw1 &= ~CP_RX_TAVA; 1035 } 1036 1037 /* TODO: scatter the packet over available receive ring descriptors space */ 1038 1039 if (size+4 > rx_space) 1040 { 1041 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n", 1042 descriptor, rx_space, size); 1043 1044 s->IntrStatus |= RxOverflow; 1045 ++s->RxMissed; 1046 1047 /* update tally counter */ 1048 ++s->tally_counters.RxERR; 1049 ++s->tally_counters.MissPkt; 1050 1051 rtl8139_update_irq(s); 1052 return size_; 1053 } 1054 1055 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI); 1056 1057 /* receive/copy to target memory */ 1058 if (dot1q_buf) { 1059 pci_dma_write(d, rx_addr, buf, 2 * ETH_ALEN); 1060 pci_dma_write(d, rx_addr + 2 * ETH_ALEN, 1061 buf + 2 * ETH_ALEN + VLAN_HLEN, 1062 size - 2 * ETH_ALEN); 1063 } else { 1064 pci_dma_write(d, rx_addr, buf, size); 1065 } 1066 1067 if (s->CpCmd & CPlusRxChkSum) 1068 { 1069 /* do some packet checksumming */ 1070 } 1071 1072 /* write checksum */ 1073 val = cpu_to_le32(crc32(0, buf, size_)); 1074 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4); 1075 1076 /* first segment of received packet flag */ 1077 #define CP_RX_STATUS_FS (1<<29) 1078 /* last segment of received packet flag */ 1079 #define CP_RX_STATUS_LS (1<<28) 1080 /* multicast packet flag */ 1081 #define CP_RX_STATUS_MAR (1<<26) 1082 /* physical-matching packet flag */ 1083 #define CP_RX_STATUS_PAM (1<<25) 1084 /* broadcast packet flag */ 1085 #define CP_RX_STATUS_BAR (1<<24) 1086 /* runt packet flag */ 1087 #define CP_RX_STATUS_RUNT (1<<19) 1088 /* crc error flag */ 1089 #define CP_RX_STATUS_CRC (1<<18) 1090 /* IP checksum error flag */ 1091 #define CP_RX_STATUS_IPF (1<<15) 1092 /* UDP checksum error flag */ 1093 #define CP_RX_STATUS_UDPF (1<<14) 1094 /* TCP checksum error flag */ 1095 #define CP_RX_STATUS_TCPF (1<<13) 1096 1097 /* transfer ownership to target */ 1098 rxdw0 &= ~CP_RX_OWN; 1099 1100 /* set first segment bit */ 1101 rxdw0 |= CP_RX_STATUS_FS; 1102 1103 /* set last segment bit */ 1104 rxdw0 |= CP_RX_STATUS_LS; 1105 1106 /* set received packet type flags */ 1107 if (packet_header & RxBroadcast) 1108 rxdw0 |= CP_RX_STATUS_BAR; 1109 if (packet_header & RxMulticast) 1110 rxdw0 |= CP_RX_STATUS_MAR; 1111 if (packet_header & RxPhysical) 1112 rxdw0 |= CP_RX_STATUS_PAM; 1113 1114 /* set received size */ 1115 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; 1116 rxdw0 |= (size+4); 1117 1118 /* update ring data */ 1119 val = cpu_to_le32(rxdw0); 1120 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4); 1121 val = cpu_to_le32(rxdw1); 1122 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4); 1123 1124 /* update tally counter */ 1125 ++s->tally_counters.RxOk; 1126 1127 /* seek to next Rx descriptor */ 1128 if (rxdw0 & CP_RX_EOR) 1129 { 1130 s->currCPlusRxDesc = 0; 1131 } 1132 else 1133 { 1134 ++s->currCPlusRxDesc; 1135 } 1136 1137 DPRINTF("done C+ Rx mode ----------------\n"); 1138 1139 } 1140 else 1141 { 1142 DPRINTF("in ring Rx mode ================\n"); 1143 1144 /* begin ring receiver mode */ 1145 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize); 1146 1147 /* if receiver buffer is empty then avail == 0 */ 1148 1149 #define RX_ALIGN(x) (((x) + 3) & ~0x3) 1150 1151 if (avail != 0 && RX_ALIGN(size + 8) >= avail) 1152 { 1153 DPRINTF("rx overflow: rx buffer length %d head 0x%04x " 1154 "read 0x%04x === available 0x%04x need 0x%04x\n", 1155 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); 1156 1157 s->IntrStatus |= RxOverflow; 1158 ++s->RxMissed; 1159 rtl8139_update_irq(s); 1160 return 0; 1161 } 1162 1163 packet_header |= RxStatusOK; 1164 1165 packet_header |= (((size+4) << 16) & 0xffff0000); 1166 1167 /* write header */ 1168 uint32_t val = cpu_to_le32(packet_header); 1169 1170 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1171 1172 rtl8139_write_buffer(s, buf, size); 1173 1174 /* write checksum */ 1175 val = cpu_to_le32(crc32(0, buf, size)); 1176 rtl8139_write_buffer(s, (uint8_t *)&val, 4); 1177 1178 /* correct buffer write pointer */ 1179 s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); 1180 1181 /* now we can signal we have received something */ 1182 1183 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", 1184 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 1185 } 1186 1187 s->IntrStatus |= RxOK; 1188 1189 if (do_interrupt) 1190 { 1191 rtl8139_update_irq(s); 1192 } 1193 1194 return size_; 1195 } 1196 1197 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size) 1198 { 1199 return rtl8139_do_receive(nc, buf, size, 1); 1200 } 1201 1202 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) 1203 { 1204 s->RxBufferSize = bufferSize; 1205 s->RxBufPtr = 0; 1206 s->RxBufAddr = 0; 1207 } 1208 1209 static void rtl8139_reset(DeviceState *d) 1210 { 1211 RTL8139State *s = RTL8139(d); 1212 int i; 1213 1214 /* restore MAC address */ 1215 memcpy(s->phys, s->conf.macaddr.a, 6); 1216 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 1217 1218 /* reset interrupt mask */ 1219 s->IntrStatus = 0; 1220 s->IntrMask = 0; 1221 1222 rtl8139_update_irq(s); 1223 1224 /* mark all status registers as owned by host */ 1225 for (i = 0; i < 4; ++i) 1226 { 1227 s->TxStatus[i] = TxHostOwns; 1228 } 1229 1230 s->currTxDesc = 0; 1231 s->currCPlusRxDesc = 0; 1232 s->currCPlusTxDesc = 0; 1233 1234 s->RxRingAddrLO = 0; 1235 s->RxRingAddrHI = 0; 1236 1237 s->RxBuf = 0; 1238 1239 rtl8139_reset_rxring(s, 8192); 1240 1241 /* ACK the reset */ 1242 s->TxConfig = 0; 1243 1244 #if 0 1245 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk 1246 s->clock_enabled = 0; 1247 #else 1248 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake 1249 s->clock_enabled = 1; 1250 #endif 1251 1252 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */; 1253 1254 /* set initial state data */ 1255 s->Config0 = 0x0; /* No boot ROM */ 1256 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */ 1257 s->Config3 = 0x1; /* fast back-to-back compatible */ 1258 s->Config5 = 0x0; 1259 1260 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; 1261 1262 s->CpCmd = 0x0; /* reset C+ mode */ 1263 s->cplus_enabled = 0; 1264 1265 1266 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation 1267 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex 1268 s->BasicModeCtrl = 0x1000; // autonegotiation 1269 1270 s->BasicModeStatus = 0x7809; 1271 //s->BasicModeStatus |= 0x0040; /* UTP medium */ 1272 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ 1273 /* preserve link state */ 1274 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04; 1275 1276 s->NWayAdvert = 0x05e1; /* all modes, full duplex */ 1277 s->NWayLPAR = 0x05e1; /* all modes, full duplex */ 1278 s->NWayExpansion = 0x0001; /* autonegotiation supported */ 1279 1280 /* also reset timer and disable timer interrupt */ 1281 s->TCTR = 0; 1282 s->TimerInt = 0; 1283 s->TCTR_base = 0; 1284 rtl8139_set_next_tctr_time(s); 1285 1286 /* reset tally counters */ 1287 RTL8139TallyCounters_clear(&s->tally_counters); 1288 } 1289 1290 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) 1291 { 1292 counters->TxOk = 0; 1293 counters->RxOk = 0; 1294 counters->TxERR = 0; 1295 counters->RxERR = 0; 1296 counters->MissPkt = 0; 1297 counters->FAE = 0; 1298 counters->Tx1Col = 0; 1299 counters->TxMCol = 0; 1300 counters->RxOkPhy = 0; 1301 counters->RxOkBrd = 0; 1302 counters->RxOkMul = 0; 1303 counters->TxAbt = 0; 1304 counters->TxUndrn = 0; 1305 } 1306 1307 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr) 1308 { 1309 PCIDevice *d = PCI_DEVICE(s); 1310 RTL8139TallyCounters *tally_counters = &s->tally_counters; 1311 uint16_t val16; 1312 uint32_t val32; 1313 uint64_t val64; 1314 1315 val64 = cpu_to_le64(tally_counters->TxOk); 1316 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8); 1317 1318 val64 = cpu_to_le64(tally_counters->RxOk); 1319 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8); 1320 1321 val64 = cpu_to_le64(tally_counters->TxERR); 1322 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8); 1323 1324 val32 = cpu_to_le32(tally_counters->RxERR); 1325 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4); 1326 1327 val16 = cpu_to_le16(tally_counters->MissPkt); 1328 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2); 1329 1330 val16 = cpu_to_le16(tally_counters->FAE); 1331 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2); 1332 1333 val32 = cpu_to_le32(tally_counters->Tx1Col); 1334 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4); 1335 1336 val32 = cpu_to_le32(tally_counters->TxMCol); 1337 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4); 1338 1339 val64 = cpu_to_le64(tally_counters->RxOkPhy); 1340 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8); 1341 1342 val64 = cpu_to_le64(tally_counters->RxOkBrd); 1343 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8); 1344 1345 val32 = cpu_to_le32(tally_counters->RxOkMul); 1346 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4); 1347 1348 val16 = cpu_to_le16(tally_counters->TxAbt); 1349 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2); 1350 1351 val16 = cpu_to_le16(tally_counters->TxUndrn); 1352 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2); 1353 } 1354 1355 /* Loads values of tally counters from VM state file */ 1356 1357 static const VMStateDescription vmstate_tally_counters = { 1358 .name = "tally_counters", 1359 .version_id = 1, 1360 .minimum_version_id = 1, 1361 .fields = (VMStateField[]) { 1362 VMSTATE_UINT64(TxOk, RTL8139TallyCounters), 1363 VMSTATE_UINT64(RxOk, RTL8139TallyCounters), 1364 VMSTATE_UINT64(TxERR, RTL8139TallyCounters), 1365 VMSTATE_UINT32(RxERR, RTL8139TallyCounters), 1366 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters), 1367 VMSTATE_UINT16(FAE, RTL8139TallyCounters), 1368 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters), 1369 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters), 1370 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters), 1371 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters), 1372 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters), 1373 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters), 1374 VMSTATE_END_OF_LIST() 1375 } 1376 }; 1377 1378 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val) 1379 { 1380 DeviceState *d = DEVICE(s); 1381 1382 val &= 0xff; 1383 1384 DPRINTF("ChipCmd write val=0x%08x\n", val); 1385 1386 if (val & CmdReset) 1387 { 1388 DPRINTF("ChipCmd reset\n"); 1389 rtl8139_reset(d); 1390 } 1391 if (val & CmdRxEnb) 1392 { 1393 DPRINTF("ChipCmd enable receiver\n"); 1394 1395 s->currCPlusRxDesc = 0; 1396 } 1397 if (val & CmdTxEnb) 1398 { 1399 DPRINTF("ChipCmd enable transmitter\n"); 1400 1401 s->currCPlusTxDesc = 0; 1402 } 1403 1404 /* mask unwritable bits */ 1405 val = SET_MASKED(val, 0xe3, s->bChipCmdState); 1406 1407 /* Deassert reset pin before next read */ 1408 val &= ~CmdReset; 1409 1410 s->bChipCmdState = val; 1411 } 1412 1413 static int rtl8139_RxBufferEmpty(RTL8139State *s) 1414 { 1415 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize); 1416 1417 if (unread != 0) 1418 { 1419 DPRINTF("receiver buffer data available 0x%04x\n", unread); 1420 return 0; 1421 } 1422 1423 DPRINTF("receiver buffer is empty\n"); 1424 1425 return 1; 1426 } 1427 1428 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s) 1429 { 1430 uint32_t ret = s->bChipCmdState; 1431 1432 if (rtl8139_RxBufferEmpty(s)) 1433 ret |= RxBufEmpty; 1434 1435 DPRINTF("ChipCmd read val=0x%04x\n", ret); 1436 1437 return ret; 1438 } 1439 1440 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val) 1441 { 1442 val &= 0xffff; 1443 1444 DPRINTF("C+ command register write(w) val=0x%04x\n", val); 1445 1446 s->cplus_enabled = 1; 1447 1448 /* mask unwritable bits */ 1449 val = SET_MASKED(val, 0xff84, s->CpCmd); 1450 1451 s->CpCmd = val; 1452 } 1453 1454 static uint32_t rtl8139_CpCmd_read(RTL8139State *s) 1455 { 1456 uint32_t ret = s->CpCmd; 1457 1458 DPRINTF("C+ command register read(w) val=0x%04x\n", ret); 1459 1460 return ret; 1461 } 1462 1463 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val) 1464 { 1465 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val); 1466 } 1467 1468 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s) 1469 { 1470 uint32_t ret = 0; 1471 1472 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret); 1473 1474 return ret; 1475 } 1476 1477 static int rtl8139_config_writable(RTL8139State *s) 1478 { 1479 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite) 1480 { 1481 return 1; 1482 } 1483 1484 DPRINTF("Configuration registers are write-protected\n"); 1485 1486 return 0; 1487 } 1488 1489 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val) 1490 { 1491 val &= 0xffff; 1492 1493 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val); 1494 1495 /* mask unwritable bits */ 1496 uint32_t mask = 0x4cff; 1497 1498 if (1 || !rtl8139_config_writable(s)) 1499 { 1500 /* Speed setting and autonegotiation enable bits are read-only */ 1501 mask |= 0x3000; 1502 /* Duplex mode setting is read-only */ 1503 mask |= 0x0100; 1504 } 1505 1506 val = SET_MASKED(val, mask, s->BasicModeCtrl); 1507 1508 s->BasicModeCtrl = val; 1509 } 1510 1511 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s) 1512 { 1513 uint32_t ret = s->BasicModeCtrl; 1514 1515 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret); 1516 1517 return ret; 1518 } 1519 1520 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val) 1521 { 1522 val &= 0xffff; 1523 1524 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val); 1525 1526 /* mask unwritable bits */ 1527 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus); 1528 1529 s->BasicModeStatus = val; 1530 } 1531 1532 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s) 1533 { 1534 uint32_t ret = s->BasicModeStatus; 1535 1536 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret); 1537 1538 return ret; 1539 } 1540 1541 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) 1542 { 1543 DeviceState *d = DEVICE(s); 1544 1545 val &= 0xff; 1546 1547 DPRINTF("Cfg9346 write val=0x%02x\n", val); 1548 1549 /* mask unwritable bits */ 1550 val = SET_MASKED(val, 0x31, s->Cfg9346); 1551 1552 uint32_t opmode = val & 0xc0; 1553 uint32_t eeprom_val = val & 0xf; 1554 1555 if (opmode == 0x80) { 1556 /* eeprom access */ 1557 int eecs = (eeprom_val & 0x08)?1:0; 1558 int eesk = (eeprom_val & 0x04)?1:0; 1559 int eedi = (eeprom_val & 0x02)?1:0; 1560 prom9346_set_wire(s, eecs, eesk, eedi); 1561 } else if (opmode == 0x40) { 1562 /* Reset. */ 1563 val = 0; 1564 rtl8139_reset(d); 1565 } 1566 1567 s->Cfg9346 = val; 1568 } 1569 1570 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s) 1571 { 1572 uint32_t ret = s->Cfg9346; 1573 1574 uint32_t opmode = ret & 0xc0; 1575 1576 if (opmode == 0x80) 1577 { 1578 /* eeprom access */ 1579 int eedo = prom9346_get_wire(s); 1580 if (eedo) 1581 { 1582 ret |= 0x01; 1583 } 1584 else 1585 { 1586 ret &= ~0x01; 1587 } 1588 } 1589 1590 DPRINTF("Cfg9346 read val=0x%02x\n", ret); 1591 1592 return ret; 1593 } 1594 1595 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val) 1596 { 1597 val &= 0xff; 1598 1599 DPRINTF("Config0 write val=0x%02x\n", val); 1600 1601 if (!rtl8139_config_writable(s)) { 1602 return; 1603 } 1604 1605 /* mask unwritable bits */ 1606 val = SET_MASKED(val, 0xf8, s->Config0); 1607 1608 s->Config0 = val; 1609 } 1610 1611 static uint32_t rtl8139_Config0_read(RTL8139State *s) 1612 { 1613 uint32_t ret = s->Config0; 1614 1615 DPRINTF("Config0 read val=0x%02x\n", ret); 1616 1617 return ret; 1618 } 1619 1620 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val) 1621 { 1622 val &= 0xff; 1623 1624 DPRINTF("Config1 write val=0x%02x\n", val); 1625 1626 if (!rtl8139_config_writable(s)) { 1627 return; 1628 } 1629 1630 /* mask unwritable bits */ 1631 val = SET_MASKED(val, 0xC, s->Config1); 1632 1633 s->Config1 = val; 1634 } 1635 1636 static uint32_t rtl8139_Config1_read(RTL8139State *s) 1637 { 1638 uint32_t ret = s->Config1; 1639 1640 DPRINTF("Config1 read val=0x%02x\n", ret); 1641 1642 return ret; 1643 } 1644 1645 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val) 1646 { 1647 val &= 0xff; 1648 1649 DPRINTF("Config3 write val=0x%02x\n", val); 1650 1651 if (!rtl8139_config_writable(s)) { 1652 return; 1653 } 1654 1655 /* mask unwritable bits */ 1656 val = SET_MASKED(val, 0x8F, s->Config3); 1657 1658 s->Config3 = val; 1659 } 1660 1661 static uint32_t rtl8139_Config3_read(RTL8139State *s) 1662 { 1663 uint32_t ret = s->Config3; 1664 1665 DPRINTF("Config3 read val=0x%02x\n", ret); 1666 1667 return ret; 1668 } 1669 1670 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val) 1671 { 1672 val &= 0xff; 1673 1674 DPRINTF("Config4 write val=0x%02x\n", val); 1675 1676 if (!rtl8139_config_writable(s)) { 1677 return; 1678 } 1679 1680 /* mask unwritable bits */ 1681 val = SET_MASKED(val, 0x0a, s->Config4); 1682 1683 s->Config4 = val; 1684 } 1685 1686 static uint32_t rtl8139_Config4_read(RTL8139State *s) 1687 { 1688 uint32_t ret = s->Config4; 1689 1690 DPRINTF("Config4 read val=0x%02x\n", ret); 1691 1692 return ret; 1693 } 1694 1695 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val) 1696 { 1697 val &= 0xff; 1698 1699 DPRINTF("Config5 write val=0x%02x\n", val); 1700 1701 /* mask unwritable bits */ 1702 val = SET_MASKED(val, 0x80, s->Config5); 1703 1704 s->Config5 = val; 1705 } 1706 1707 static uint32_t rtl8139_Config5_read(RTL8139State *s) 1708 { 1709 uint32_t ret = s->Config5; 1710 1711 DPRINTF("Config5 read val=0x%02x\n", ret); 1712 1713 return ret; 1714 } 1715 1716 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val) 1717 { 1718 if (!rtl8139_transmitter_enabled(s)) 1719 { 1720 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val); 1721 return; 1722 } 1723 1724 DPRINTF("TxConfig write val=0x%08x\n", val); 1725 1726 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig); 1727 1728 s->TxConfig = val; 1729 } 1730 1731 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val) 1732 { 1733 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val); 1734 1735 uint32_t tc = s->TxConfig; 1736 tc &= 0xFFFFFF00; 1737 tc |= (val & 0x000000FF); 1738 rtl8139_TxConfig_write(s, tc); 1739 } 1740 1741 static uint32_t rtl8139_TxConfig_read(RTL8139State *s) 1742 { 1743 uint32_t ret = s->TxConfig; 1744 1745 DPRINTF("TxConfig read val=0x%04x\n", ret); 1746 1747 return ret; 1748 } 1749 1750 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val) 1751 { 1752 DPRINTF("RxConfig write val=0x%08x\n", val); 1753 1754 /* mask unwritable bits */ 1755 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig); 1756 1757 s->RxConfig = val; 1758 1759 /* reset buffer size and read/write pointers */ 1760 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3)); 1761 1762 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize); 1763 } 1764 1765 static uint32_t rtl8139_RxConfig_read(RTL8139State *s) 1766 { 1767 uint32_t ret = s->RxConfig; 1768 1769 DPRINTF("RxConfig read val=0x%08x\n", ret); 1770 1771 return ret; 1772 } 1773 1774 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, 1775 int do_interrupt, const uint8_t *dot1q_buf) 1776 { 1777 struct iovec *iov = NULL; 1778 struct iovec vlan_iov[3]; 1779 1780 if (!size) 1781 { 1782 DPRINTF("+++ empty ethernet frame\n"); 1783 return; 1784 } 1785 1786 if (dot1q_buf && size >= ETH_ALEN * 2) { 1787 iov = (struct iovec[3]) { 1788 { .iov_base = buf, .iov_len = ETH_ALEN * 2 }, 1789 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN }, 1790 { .iov_base = buf + ETH_ALEN * 2, 1791 .iov_len = size - ETH_ALEN * 2 }, 1792 }; 1793 1794 memcpy(vlan_iov, iov, sizeof(vlan_iov)); 1795 iov = vlan_iov; 1796 } 1797 1798 if (TxLoopBack == (s->TxConfig & TxLoopBack)) 1799 { 1800 size_t buf2_size; 1801 uint8_t *buf2; 1802 1803 if (iov) { 1804 buf2_size = iov_size(iov, 3); 1805 buf2 = g_malloc(buf2_size); 1806 iov_to_buf(iov, 3, 0, buf2, buf2_size); 1807 buf = buf2; 1808 } 1809 1810 DPRINTF("+++ transmit loopback mode\n"); 1811 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt); 1812 1813 if (iov) { 1814 g_free(buf2); 1815 } 1816 } 1817 else 1818 { 1819 if (iov) { 1820 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3); 1821 } else { 1822 qemu_send_packet(qemu_get_queue(s->nic), buf, size); 1823 } 1824 } 1825 } 1826 1827 static int rtl8139_transmit_one(RTL8139State *s, int descriptor) 1828 { 1829 if (!rtl8139_transmitter_enabled(s)) 1830 { 1831 DPRINTF("+++ cannot transmit from descriptor %d: transmitter " 1832 "disabled\n", descriptor); 1833 return 0; 1834 } 1835 1836 if (s->TxStatus[descriptor] & TxHostOwns) 1837 { 1838 DPRINTF("+++ cannot transmit from descriptor %d: owned by host " 1839 "(%08x)\n", descriptor, s->TxStatus[descriptor]); 1840 return 0; 1841 } 1842 1843 DPRINTF("+++ transmitting from descriptor %d\n", descriptor); 1844 1845 PCIDevice *d = PCI_DEVICE(s); 1846 int txsize = s->TxStatus[descriptor] & 0x1fff; 1847 uint8_t txbuffer[0x2000]; 1848 1849 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", 1850 txsize, s->TxAddr[descriptor]); 1851 1852 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize); 1853 1854 /* Mark descriptor as transferred */ 1855 s->TxStatus[descriptor] |= TxHostOwns; 1856 s->TxStatus[descriptor] |= TxStatOK; 1857 1858 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); 1859 1860 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, 1861 descriptor); 1862 1863 /* update interrupt */ 1864 s->IntrStatus |= TxOK; 1865 rtl8139_update_irq(s); 1866 1867 return 1; 1868 } 1869 1870 /* structures and macros for task offloading */ 1871 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2) 1872 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f) 1873 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags)) 1874 1875 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) 1876 1877 /* produces ones' complement sum of data */ 1878 static uint16_t ones_complement_sum(uint8_t *data, size_t len) 1879 { 1880 uint32_t result = 0; 1881 1882 for (; len > 1; data+=2, len-=2) 1883 { 1884 result += *(uint16_t*)data; 1885 } 1886 1887 /* add the remainder byte */ 1888 if (len) 1889 { 1890 uint8_t odd[2] = {*data, 0}; 1891 result += *(uint16_t*)odd; 1892 } 1893 1894 while (result>>16) 1895 result = (result & 0xffff) + (result >> 16); 1896 1897 return result; 1898 } 1899 1900 static uint16_t ip_checksum(void *data, size_t len) 1901 { 1902 return ~ones_complement_sum((uint8_t*)data, len); 1903 } 1904 1905 static int rtl8139_cplus_transmit_one(RTL8139State *s) 1906 { 1907 if (!rtl8139_transmitter_enabled(s)) 1908 { 1909 DPRINTF("+++ C+ mode: transmitter disabled\n"); 1910 return 0; 1911 } 1912 1913 if (!rtl8139_cp_transmitter_enabled(s)) 1914 { 1915 DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); 1916 return 0 ; 1917 } 1918 1919 PCIDevice *d = PCI_DEVICE(s); 1920 int descriptor = s->currCPlusTxDesc; 1921 1922 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]); 1923 1924 /* Normal priority ring */ 1925 cplus_tx_ring_desc += 16 * descriptor; 1926 1927 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " 1928 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1], 1929 s->TxAddr[0], cplus_tx_ring_desc); 1930 1931 uint32_t val, txdw0,txdw1,txbufLO,txbufHI; 1932 1933 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 1934 txdw0 = le32_to_cpu(val); 1935 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4); 1936 txdw1 = le32_to_cpu(val); 1937 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4); 1938 txbufLO = le32_to_cpu(val); 1939 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4); 1940 txbufHI = le32_to_cpu(val); 1941 1942 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, 1943 txdw0, txdw1, txbufLO, txbufHI); 1944 1945 /* w0 ownership flag */ 1946 #define CP_TX_OWN (1<<31) 1947 /* w0 end of ring flag */ 1948 #define CP_TX_EOR (1<<30) 1949 /* first segment of received packet flag */ 1950 #define CP_TX_FS (1<<29) 1951 /* last segment of received packet flag */ 1952 #define CP_TX_LS (1<<28) 1953 /* large send packet flag */ 1954 #define CP_TX_LGSEN (1<<27) 1955 /* large send MSS mask, bits 16...25 */ 1956 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1) 1957 1958 /* IP checksum offload flag */ 1959 #define CP_TX_IPCS (1<<18) 1960 /* UDP checksum offload flag */ 1961 #define CP_TX_UDPCS (1<<17) 1962 /* TCP checksum offload flag */ 1963 #define CP_TX_TCPCS (1<<16) 1964 1965 /* w0 bits 0...15 : buffer size */ 1966 #define CP_TX_BUFFER_SIZE (1<<16) 1967 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) 1968 /* w1 add tag flag */ 1969 #define CP_TX_TAGC (1<<17) 1970 /* w1 bits 0...15 : VLAN tag (big endian) */ 1971 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) 1972 /* w2 low 32bit of Rx buffer ptr */ 1973 /* w3 high 32bit of Rx buffer ptr */ 1974 1975 /* set after transmission */ 1976 /* FIFO underrun flag */ 1977 #define CP_TX_STATUS_UNF (1<<25) 1978 /* transmit error summary flag, valid if set any of three below */ 1979 #define CP_TX_STATUS_TES (1<<23) 1980 /* out-of-window collision flag */ 1981 #define CP_TX_STATUS_OWC (1<<22) 1982 /* link failure flag */ 1983 #define CP_TX_STATUS_LNKF (1<<21) 1984 /* excessive collisions flag */ 1985 #define CP_TX_STATUS_EXC (1<<20) 1986 1987 if (!(txdw0 & CP_TX_OWN)) 1988 { 1989 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); 1990 return 0 ; 1991 } 1992 1993 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); 1994 1995 if (txdw0 & CP_TX_FS) 1996 { 1997 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " 1998 "descriptor\n", descriptor); 1999 2000 /* reset internal buffer offset */ 2001 s->cplus_txbuffer_offset = 0; 2002 } 2003 2004 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; 2005 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); 2006 2007 /* make sure we have enough space to assemble the packet */ 2008 if (!s->cplus_txbuffer) 2009 { 2010 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; 2011 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len); 2012 s->cplus_txbuffer_offset = 0; 2013 2014 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", 2015 s->cplus_txbuffer_len); 2016 } 2017 2018 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) 2019 { 2020 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ 2021 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; 2022 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" 2023 "length to %d\n", txsize); 2024 } 2025 2026 /* append more data to the packet */ 2027 2028 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " 2029 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr, 2030 s->cplus_txbuffer_offset); 2031 2032 pci_dma_read(d, tx_addr, 2033 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize); 2034 s->cplus_txbuffer_offset += txsize; 2035 2036 /* seek to next Rx descriptor */ 2037 if (txdw0 & CP_TX_EOR) 2038 { 2039 s->currCPlusTxDesc = 0; 2040 } 2041 else 2042 { 2043 ++s->currCPlusTxDesc; 2044 if (s->currCPlusTxDesc >= 64) 2045 s->currCPlusTxDesc = 0; 2046 } 2047 2048 /* transfer ownership to target */ 2049 txdw0 &= ~CP_RX_OWN; 2050 2051 /* reset error indicator bits */ 2052 txdw0 &= ~CP_TX_STATUS_UNF; 2053 txdw0 &= ~CP_TX_STATUS_TES; 2054 txdw0 &= ~CP_TX_STATUS_OWC; 2055 txdw0 &= ~CP_TX_STATUS_LNKF; 2056 txdw0 &= ~CP_TX_STATUS_EXC; 2057 2058 /* update ring data */ 2059 val = cpu_to_le32(txdw0); 2060 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4); 2061 2062 /* Now decide if descriptor being processed is holding the last segment of packet */ 2063 if (txdw0 & CP_TX_LS) 2064 { 2065 uint8_t dot1q_buffer_space[VLAN_HLEN]; 2066 uint16_t *dot1q_buffer; 2067 2068 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", 2069 descriptor); 2070 2071 /* can transfer fully assembled packet */ 2072 2073 uint8_t *saved_buffer = s->cplus_txbuffer; 2074 int saved_size = s->cplus_txbuffer_offset; 2075 int saved_buffer_len = s->cplus_txbuffer_len; 2076 2077 /* create vlan tag */ 2078 if (txdw1 & CP_TX_TAGC) { 2079 /* the vlan tag is in BE byte order in the descriptor 2080 * BE + le_to_cpu() + ~swap()~ = cpu */ 2081 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", 2082 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); 2083 2084 dot1q_buffer = (uint16_t *) dot1q_buffer_space; 2085 dot1q_buffer[0] = cpu_to_be16(ETH_P_VLAN); 2086 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ 2087 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); 2088 } else { 2089 dot1q_buffer = NULL; 2090 } 2091 2092 /* reset the card space to protect from recursive call */ 2093 s->cplus_txbuffer = NULL; 2094 s->cplus_txbuffer_offset = 0; 2095 s->cplus_txbuffer_len = 0; 2096 2097 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) 2098 { 2099 DPRINTF("+++ C+ mode offloaded task checksum\n"); 2100 2101 /* Large enough for Ethernet and IP headers? */ 2102 if (saved_size < ETH_HLEN + sizeof(struct ip_header)) { 2103 goto skip_offload; 2104 } 2105 2106 /* ip packet header */ 2107 struct ip_header *ip = NULL; 2108 int hlen = 0; 2109 uint8_t ip_protocol = 0; 2110 uint16_t ip_data_len = 0; 2111 2112 uint8_t *eth_payload_data = NULL; 2113 size_t eth_payload_len = 0; 2114 2115 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); 2116 if (proto != ETH_P_IP) 2117 { 2118 goto skip_offload; 2119 } 2120 2121 DPRINTF("+++ C+ mode has IP packet\n"); 2122 2123 /* Note on memory alignment: eth_payload_data is 16-bit aligned 2124 * since saved_buffer is allocated with g_malloc() and ETH_HLEN is 2125 * even. 32-bit accesses must use ldl/stl wrappers to avoid 2126 * unaligned accesses. 2127 */ 2128 eth_payload_data = saved_buffer + ETH_HLEN; 2129 eth_payload_len = saved_size - ETH_HLEN; 2130 2131 ip = (struct ip_header*)eth_payload_data; 2132 2133 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { 2134 DPRINTF("+++ C+ mode packet has bad IP version %d " 2135 "expected %d\n", IP_HEADER_VERSION(ip), 2136 IP_HEADER_VERSION_4); 2137 goto skip_offload; 2138 } 2139 2140 hlen = IP_HDR_GET_LEN(ip); 2141 if (hlen < sizeof(struct ip_header) || hlen > eth_payload_len) { 2142 goto skip_offload; 2143 } 2144 2145 ip_protocol = ip->ip_p; 2146 2147 ip_data_len = be16_to_cpu(ip->ip_len); 2148 if (ip_data_len < hlen || ip_data_len > eth_payload_len) { 2149 goto skip_offload; 2150 } 2151 ip_data_len -= hlen; 2152 2153 if (txdw0 & CP_TX_IPCS) 2154 { 2155 DPRINTF("+++ C+ mode need IP checksum\n"); 2156 2157 ip->ip_sum = 0; 2158 ip->ip_sum = ip_checksum(ip, hlen); 2159 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", 2160 hlen, ip->ip_sum); 2161 } 2162 2163 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) 2164 { 2165 /* Large enough for the TCP header? */ 2166 if (ip_data_len < sizeof(tcp_header)) { 2167 goto skip_offload; 2168 } 2169 2170 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK; 2171 2172 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d " 2173 "frame data %d specified MSS=%d\n", ETH_MTU, 2174 ip_data_len, saved_size - ETH_HLEN, large_send_mss); 2175 2176 int tcp_send_offset = 0; 2177 int send_count = 0; 2178 2179 /* maximum IP header length is 60 bytes */ 2180 uint8_t saved_ip_header[60]; 2181 2182 /* save IP header template; data area is used in tcp checksum calculation */ 2183 memcpy(saved_ip_header, eth_payload_data, hlen); 2184 2185 /* a placeholder for checksum calculation routine in tcp case */ 2186 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2187 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2188 2189 /* pointer to TCP header */ 2190 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); 2191 2192 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); 2193 2194 /* Invalid TCP data offset? */ 2195 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) { 2196 goto skip_offload; 2197 } 2198 2199 /* ETH_MTU = ip header len + tcp header len + payload */ 2200 int tcp_data_len = ip_data_len - tcp_hlen; 2201 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen; 2202 2203 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " 2204 "data len %d TCP chunk size %d\n", ip_data_len, 2205 tcp_hlen, tcp_data_len, tcp_chunk_size); 2206 2207 /* note the cycle below overwrites IP header data, 2208 but restores it from saved_ip_header before sending packet */ 2209 2210 int is_last_frame = 0; 2211 2212 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size) 2213 { 2214 uint16_t chunk_size = tcp_chunk_size; 2215 2216 /* check if this is the last frame */ 2217 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len) 2218 { 2219 is_last_frame = 1; 2220 chunk_size = tcp_data_len - tcp_send_offset; 2221 } 2222 2223 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", 2224 ldl_be_p(&p_tcp_hdr->th_seq)); 2225 2226 /* add 4 TCP pseudoheader fields */ 2227 /* copy IP source and destination fields */ 2228 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2229 2230 DPRINTF("+++ C+ mode TSO calculating TCP checksum for " 2231 "packet with %d bytes data\n", tcp_hlen + 2232 chunk_size); 2233 2234 if (tcp_send_offset) 2235 { 2236 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); 2237 } 2238 2239 /* keep PUSH and FIN flags only for the last frame */ 2240 if (!is_last_frame) 2241 { 2242 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TH_PUSH | TH_FIN); 2243 } 2244 2245 /* recalculate TCP checksum */ 2246 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2247 p_tcpip_hdr->zeros = 0; 2248 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2249 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); 2250 2251 p_tcp_hdr->th_sum = 0; 2252 2253 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); 2254 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", 2255 tcp_checksum); 2256 2257 p_tcp_hdr->th_sum = tcp_checksum; 2258 2259 /* restore IP header */ 2260 memcpy(eth_payload_data, saved_ip_header, hlen); 2261 2262 /* set IP data length and recalculate IP checksum */ 2263 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); 2264 2265 /* increment IP id for subsequent frames */ 2266 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id)); 2267 2268 ip->ip_sum = 0; 2269 ip->ip_sum = ip_checksum(eth_payload_data, hlen); 2270 DPRINTF("+++ C+ mode TSO IP header len=%d " 2271 "checksum=%04x\n", hlen, ip->ip_sum); 2272 2273 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; 2274 DPRINTF("+++ C+ mode TSO transferring packet size " 2275 "%d\n", tso_send_size); 2276 rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 2277 0, (uint8_t *) dot1q_buffer); 2278 2279 /* add transferred count to TCP sequence number */ 2280 stl_be_p(&p_tcp_hdr->th_seq, 2281 chunk_size + ldl_be_p(&p_tcp_hdr->th_seq)); 2282 ++send_count; 2283 } 2284 2285 /* Stop sending this frame */ 2286 saved_size = 0; 2287 } 2288 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS)) 2289 { 2290 DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); 2291 2292 /* maximum IP header length is 60 bytes */ 2293 uint8_t saved_ip_header[60]; 2294 memcpy(saved_ip_header, eth_payload_data, hlen); 2295 2296 uint8_t *data_to_checksum = eth_payload_data + hlen - 12; 2297 // size_t data_to_checksum_len = eth_payload_len - hlen + 12; 2298 2299 /* add 4 TCP pseudoheader fields */ 2300 /* copy IP source and destination fields */ 2301 memcpy(data_to_checksum, saved_ip_header + 12, 8); 2302 2303 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) 2304 { 2305 DPRINTF("+++ C+ mode calculating TCP checksum for " 2306 "packet with %d bytes data\n", ip_data_len); 2307 2308 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; 2309 p_tcpip_hdr->zeros = 0; 2310 p_tcpip_hdr->ip_proto = IP_PROTO_TCP; 2311 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2312 2313 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); 2314 2315 p_tcp_hdr->th_sum = 0; 2316 2317 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2318 DPRINTF("+++ C+ mode TCP checksum %04x\n", 2319 tcp_checksum); 2320 2321 p_tcp_hdr->th_sum = tcp_checksum; 2322 } 2323 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) 2324 { 2325 DPRINTF("+++ C+ mode calculating UDP checksum for " 2326 "packet with %d bytes data\n", ip_data_len); 2327 2328 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; 2329 p_udpip_hdr->zeros = 0; 2330 p_udpip_hdr->ip_proto = IP_PROTO_UDP; 2331 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); 2332 2333 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); 2334 2335 p_udp_hdr->uh_sum = 0; 2336 2337 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); 2338 DPRINTF("+++ C+ mode UDP checksum %04x\n", 2339 udp_checksum); 2340 2341 p_udp_hdr->uh_sum = udp_checksum; 2342 } 2343 2344 /* restore IP header */ 2345 memcpy(eth_payload_data, saved_ip_header, hlen); 2346 } 2347 } 2348 2349 skip_offload: 2350 /* update tally counter */ 2351 ++s->tally_counters.TxOk; 2352 2353 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); 2354 2355 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, 2356 (uint8_t *) dot1q_buffer); 2357 2358 /* restore card space if there was no recursion and reset offset */ 2359 if (!s->cplus_txbuffer) 2360 { 2361 s->cplus_txbuffer = saved_buffer; 2362 s->cplus_txbuffer_len = saved_buffer_len; 2363 s->cplus_txbuffer_offset = 0; 2364 } 2365 else 2366 { 2367 g_free(saved_buffer); 2368 } 2369 } 2370 else 2371 { 2372 DPRINTF("+++ C+ mode transmission continue to next descriptor\n"); 2373 } 2374 2375 return 1; 2376 } 2377 2378 static void rtl8139_cplus_transmit(RTL8139State *s) 2379 { 2380 int txcount = 0; 2381 2382 while (rtl8139_cplus_transmit_one(s)) 2383 { 2384 ++txcount; 2385 } 2386 2387 /* Mark transfer completed */ 2388 if (!txcount) 2389 { 2390 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", 2391 s->currCPlusTxDesc); 2392 } 2393 else 2394 { 2395 /* update interrupt status */ 2396 s->IntrStatus |= TxOK; 2397 rtl8139_update_irq(s); 2398 } 2399 } 2400 2401 static void rtl8139_transmit(RTL8139State *s) 2402 { 2403 int descriptor = s->currTxDesc, txcount = 0; 2404 2405 /*while*/ 2406 if (rtl8139_transmit_one(s, descriptor)) 2407 { 2408 ++s->currTxDesc; 2409 s->currTxDesc %= 4; 2410 ++txcount; 2411 } 2412 2413 /* Mark transfer completed */ 2414 if (!txcount) 2415 { 2416 DPRINTF("transmitter queue stalled, current TxDesc = %d\n", 2417 s->currTxDesc); 2418 } 2419 } 2420 2421 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) 2422 { 2423 2424 int descriptor = txRegOffset/4; 2425 2426 /* handle C+ transmit mode register configuration */ 2427 2428 if (s->cplus_enabled) 2429 { 2430 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " 2431 "descriptor=%d\n", txRegOffset, val, descriptor); 2432 2433 /* handle Dump Tally Counters command */ 2434 s->TxStatus[descriptor] = val; 2435 2436 if (descriptor == 0 && (val & 0x8)) 2437 { 2438 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]); 2439 2440 /* dump tally counters to specified memory location */ 2441 RTL8139TallyCounters_dma_write(s, tc_addr); 2442 2443 /* mark dump completed */ 2444 s->TxStatus[0] &= ~0x8; 2445 } 2446 2447 return; 2448 } 2449 2450 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", 2451 txRegOffset, val, descriptor); 2452 2453 /* mask only reserved bits */ 2454 val &= ~0xff00c000; /* these bits are reset on write */ 2455 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]); 2456 2457 s->TxStatus[descriptor] = val; 2458 2459 /* attempt to start transmission */ 2460 rtl8139_transmit(s); 2461 } 2462 2463 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[], 2464 uint32_t base, uint8_t addr, 2465 int size) 2466 { 2467 uint32_t reg = (addr - base) / 4; 2468 uint32_t offset = addr & 0x3; 2469 uint32_t ret = 0; 2470 2471 if (addr & (size - 1)) { 2472 DPRINTF("not implemented read for TxStatus/TxAddr " 2473 "addr=0x%x size=0x%x\n", addr, size); 2474 return ret; 2475 } 2476 2477 switch (size) { 2478 case 1: /* fall through */ 2479 case 2: /* fall through */ 2480 case 4: 2481 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); 2482 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", 2483 reg, addr, size, ret); 2484 break; 2485 default: 2486 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size); 2487 break; 2488 } 2489 2490 return ret; 2491 } 2492 2493 static uint16_t rtl8139_TSAD_read(RTL8139State *s) 2494 { 2495 uint16_t ret = 0; 2496 2497 /* Simulate TSAD, it is read only anyway */ 2498 2499 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) 2500 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) 2501 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) 2502 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) 2503 2504 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) 2505 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) 2506 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) 2507 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) 2508 2509 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) 2510 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) 2511 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) 2512 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) 2513 2514 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) 2515 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) 2516 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) 2517 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; 2518 2519 2520 DPRINTF("TSAD read val=0x%04x\n", ret); 2521 2522 return ret; 2523 } 2524 2525 static uint16_t rtl8139_CSCR_read(RTL8139State *s) 2526 { 2527 uint16_t ret = s->CSCR; 2528 2529 DPRINTF("CSCR read val=0x%04x\n", ret); 2530 2531 return ret; 2532 } 2533 2534 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) 2535 { 2536 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); 2537 2538 s->TxAddr[txAddrOffset/4] = val; 2539 } 2540 2541 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) 2542 { 2543 uint32_t ret = s->TxAddr[txAddrOffset/4]; 2544 2545 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); 2546 2547 return ret; 2548 } 2549 2550 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) 2551 { 2552 DPRINTF("RxBufPtr write val=0x%04x\n", val); 2553 2554 /* this value is off by 16 */ 2555 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); 2556 2557 /* more buffer space may be available so try to receive */ 2558 qemu_flush_queued_packets(qemu_get_queue(s->nic)); 2559 2560 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", 2561 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); 2562 } 2563 2564 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s) 2565 { 2566 /* this value is off by 16 */ 2567 uint32_t ret = s->RxBufPtr - 0x10; 2568 2569 DPRINTF("RxBufPtr read val=0x%04x\n", ret); 2570 2571 return ret; 2572 } 2573 2574 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s) 2575 { 2576 /* this value is NOT off by 16 */ 2577 uint32_t ret = s->RxBufAddr; 2578 2579 DPRINTF("RxBufAddr read val=0x%04x\n", ret); 2580 2581 return ret; 2582 } 2583 2584 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val) 2585 { 2586 DPRINTF("RxBuf write val=0x%08x\n", val); 2587 2588 s->RxBuf = val; 2589 2590 /* may need to reset rxring here */ 2591 } 2592 2593 static uint32_t rtl8139_RxBuf_read(RTL8139State *s) 2594 { 2595 uint32_t ret = s->RxBuf; 2596 2597 DPRINTF("RxBuf read val=0x%08x\n", ret); 2598 2599 return ret; 2600 } 2601 2602 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) 2603 { 2604 DPRINTF("IntrMask write(w) val=0x%04x\n", val); 2605 2606 /* mask unwritable bits */ 2607 val = SET_MASKED(val, 0x1e00, s->IntrMask); 2608 2609 s->IntrMask = val; 2610 2611 rtl8139_update_irq(s); 2612 2613 } 2614 2615 static uint32_t rtl8139_IntrMask_read(RTL8139State *s) 2616 { 2617 uint32_t ret = s->IntrMask; 2618 2619 DPRINTF("IntrMask read(w) val=0x%04x\n", ret); 2620 2621 return ret; 2622 } 2623 2624 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val) 2625 { 2626 DPRINTF("IntrStatus write(w) val=0x%04x\n", val); 2627 2628 #if 0 2629 2630 /* writing to ISR has no effect */ 2631 2632 return; 2633 2634 #else 2635 uint16_t newStatus = s->IntrStatus & ~val; 2636 2637 /* mask unwritable bits */ 2638 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus); 2639 2640 /* writing 1 to interrupt status register bit clears it */ 2641 s->IntrStatus = 0; 2642 rtl8139_update_irq(s); 2643 2644 s->IntrStatus = newStatus; 2645 rtl8139_set_next_tctr_time(s); 2646 rtl8139_update_irq(s); 2647 2648 #endif 2649 } 2650 2651 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s) 2652 { 2653 uint32_t ret = s->IntrStatus; 2654 2655 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret); 2656 2657 #if 0 2658 2659 /* reading ISR clears all interrupts */ 2660 s->IntrStatus = 0; 2661 2662 rtl8139_update_irq(s); 2663 2664 #endif 2665 2666 return ret; 2667 } 2668 2669 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val) 2670 { 2671 DPRINTF("MultiIntr write(w) val=0x%04x\n", val); 2672 2673 /* mask unwritable bits */ 2674 val = SET_MASKED(val, 0xf000, s->MultiIntr); 2675 2676 s->MultiIntr = val; 2677 } 2678 2679 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s) 2680 { 2681 uint32_t ret = s->MultiIntr; 2682 2683 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret); 2684 2685 return ret; 2686 } 2687 2688 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val) 2689 { 2690 RTL8139State *s = opaque; 2691 2692 switch (addr) 2693 { 2694 case MAC0 ... MAC0+4: 2695 s->phys[addr - MAC0] = val; 2696 break; 2697 case MAC0+5: 2698 s->phys[addr - MAC0] = val; 2699 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys); 2700 break; 2701 case MAC0+6 ... MAC0+7: 2702 /* reserved */ 2703 break; 2704 case MAR0 ... MAR0+7: 2705 s->mult[addr - MAR0] = val; 2706 break; 2707 case ChipCmd: 2708 rtl8139_ChipCmd_write(s, val); 2709 break; 2710 case Cfg9346: 2711 rtl8139_Cfg9346_write(s, val); 2712 break; 2713 case TxConfig: /* windows driver sometimes writes using byte-lenth call */ 2714 rtl8139_TxConfig_writeb(s, val); 2715 break; 2716 case Config0: 2717 rtl8139_Config0_write(s, val); 2718 break; 2719 case Config1: 2720 rtl8139_Config1_write(s, val); 2721 break; 2722 case Config3: 2723 rtl8139_Config3_write(s, val); 2724 break; 2725 case Config4: 2726 rtl8139_Config4_write(s, val); 2727 break; 2728 case Config5: 2729 rtl8139_Config5_write(s, val); 2730 break; 2731 case MediaStatus: 2732 /* ignore */ 2733 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", 2734 val); 2735 break; 2736 2737 case HltClk: 2738 DPRINTF("HltClk write val=0x%08x\n", val); 2739 if (val == 'R') 2740 { 2741 s->clock_enabled = 1; 2742 } 2743 else if (val == 'H') 2744 { 2745 s->clock_enabled = 0; 2746 } 2747 break; 2748 2749 case TxThresh: 2750 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val); 2751 s->TxThresh = val; 2752 break; 2753 2754 case TxPoll: 2755 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); 2756 if (val & (1 << 7)) 2757 { 2758 DPRINTF("C+ TxPoll high priority transmission (not " 2759 "implemented)\n"); 2760 //rtl8139_cplus_transmit(s); 2761 } 2762 if (val & (1 << 6)) 2763 { 2764 DPRINTF("C+ TxPoll normal priority transmission\n"); 2765 rtl8139_cplus_transmit(s); 2766 } 2767 2768 break; 2769 2770 default: 2771 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, 2772 val); 2773 break; 2774 } 2775 } 2776 2777 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val) 2778 { 2779 RTL8139State *s = opaque; 2780 2781 switch (addr) 2782 { 2783 case IntrMask: 2784 rtl8139_IntrMask_write(s, val); 2785 break; 2786 2787 case IntrStatus: 2788 rtl8139_IntrStatus_write(s, val); 2789 break; 2790 2791 case MultiIntr: 2792 rtl8139_MultiIntr_write(s, val); 2793 break; 2794 2795 case RxBufPtr: 2796 rtl8139_RxBufPtr_write(s, val); 2797 break; 2798 2799 case BasicModeCtrl: 2800 rtl8139_BasicModeCtrl_write(s, val); 2801 break; 2802 case BasicModeStatus: 2803 rtl8139_BasicModeStatus_write(s, val); 2804 break; 2805 case NWayAdvert: 2806 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val); 2807 s->NWayAdvert = val; 2808 break; 2809 case NWayLPAR: 2810 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val); 2811 break; 2812 case NWayExpansion: 2813 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val); 2814 s->NWayExpansion = val; 2815 break; 2816 2817 case CpCmd: 2818 rtl8139_CpCmd_write(s, val); 2819 break; 2820 2821 case IntrMitigate: 2822 rtl8139_IntrMitigate_write(s, val); 2823 break; 2824 2825 default: 2826 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", 2827 addr, val); 2828 2829 rtl8139_io_writeb(opaque, addr, val & 0xff); 2830 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2831 break; 2832 } 2833 } 2834 2835 static void rtl8139_set_next_tctr_time(RTL8139State *s) 2836 { 2837 const uint64_t ns_per_period = (uint64_t)PCI_PERIOD << 32; 2838 2839 DPRINTF("entered rtl8139_set_next_tctr_time\n"); 2840 2841 /* This function is called at least once per period, so it is a good 2842 * place to update the timer base. 2843 * 2844 * After one iteration of this loop the value in the Timer register does 2845 * not change, but the device model is counting up by 2^32 ticks (approx. 2846 * 130 seconds). 2847 */ 2848 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2849 s->TCTR_base += ns_per_period; 2850 } 2851 2852 if (!s->TimerInt) { 2853 timer_del(s->timer); 2854 } else { 2855 uint64_t delta = (uint64_t)s->TimerInt * PCI_PERIOD; 2856 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) { 2857 delta += ns_per_period; 2858 } 2859 timer_mod(s->timer, s->TCTR_base + delta); 2860 } 2861 } 2862 2863 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val) 2864 { 2865 RTL8139State *s = opaque; 2866 2867 switch (addr) 2868 { 2869 case RxMissed: 2870 DPRINTF("RxMissed clearing on write\n"); 2871 s->RxMissed = 0; 2872 break; 2873 2874 case TxConfig: 2875 rtl8139_TxConfig_write(s, val); 2876 break; 2877 2878 case RxConfig: 2879 rtl8139_RxConfig_write(s, val); 2880 break; 2881 2882 case TxStatus0 ... TxStatus0+4*4-1: 2883 rtl8139_TxStatus_write(s, addr-TxStatus0, val); 2884 break; 2885 2886 case TxAddr0 ... TxAddr0+4*4-1: 2887 rtl8139_TxAddr_write(s, addr-TxAddr0, val); 2888 break; 2889 2890 case RxBuf: 2891 rtl8139_RxBuf_write(s, val); 2892 break; 2893 2894 case RxRingAddrLO: 2895 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val); 2896 s->RxRingAddrLO = val; 2897 break; 2898 2899 case RxRingAddrHI: 2900 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val); 2901 s->RxRingAddrHI = val; 2902 break; 2903 2904 case Timer: 2905 DPRINTF("TCTR Timer reset on write\n"); 2906 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2907 rtl8139_set_next_tctr_time(s); 2908 break; 2909 2910 case FlashReg: 2911 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val); 2912 if (s->TimerInt != val) { 2913 s->TimerInt = val; 2914 rtl8139_set_next_tctr_time(s); 2915 } 2916 break; 2917 2918 default: 2919 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", 2920 addr, val); 2921 rtl8139_io_writeb(opaque, addr, val & 0xff); 2922 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); 2923 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); 2924 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff); 2925 break; 2926 } 2927 } 2928 2929 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr) 2930 { 2931 RTL8139State *s = opaque; 2932 int ret; 2933 2934 switch (addr) 2935 { 2936 case MAC0 ... MAC0+5: 2937 ret = s->phys[addr - MAC0]; 2938 break; 2939 case MAC0+6 ... MAC0+7: 2940 ret = 0; 2941 break; 2942 case MAR0 ... MAR0+7: 2943 ret = s->mult[addr - MAR0]; 2944 break; 2945 case TxStatus0 ... TxStatus0+4*4-1: 2946 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 2947 addr, 1); 2948 break; 2949 case ChipCmd: 2950 ret = rtl8139_ChipCmd_read(s); 2951 break; 2952 case Cfg9346: 2953 ret = rtl8139_Cfg9346_read(s); 2954 break; 2955 case Config0: 2956 ret = rtl8139_Config0_read(s); 2957 break; 2958 case Config1: 2959 ret = rtl8139_Config1_read(s); 2960 break; 2961 case Config3: 2962 ret = rtl8139_Config3_read(s); 2963 break; 2964 case Config4: 2965 ret = rtl8139_Config4_read(s); 2966 break; 2967 case Config5: 2968 ret = rtl8139_Config5_read(s); 2969 break; 2970 2971 case MediaStatus: 2972 /* The LinkDown bit of MediaStatus is inverse with link status */ 2973 ret = 0xd0 | (~s->BasicModeStatus & 0x04); 2974 DPRINTF("MediaStatus read 0x%x\n", ret); 2975 break; 2976 2977 case HltClk: 2978 ret = s->clock_enabled; 2979 DPRINTF("HltClk read 0x%x\n", ret); 2980 break; 2981 2982 case PCIRevisionID: 2983 ret = RTL8139_PCI_REVID; 2984 DPRINTF("PCI Revision ID read 0x%x\n", ret); 2985 break; 2986 2987 case TxThresh: 2988 ret = s->TxThresh; 2989 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret); 2990 break; 2991 2992 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ 2993 ret = s->TxConfig >> 24; 2994 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret); 2995 break; 2996 2997 default: 2998 DPRINTF("not implemented read(b) addr=0x%x\n", addr); 2999 ret = 0; 3000 break; 3001 } 3002 3003 return ret; 3004 } 3005 3006 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr) 3007 { 3008 RTL8139State *s = opaque; 3009 uint32_t ret; 3010 3011 switch (addr) 3012 { 3013 case TxAddr0 ... TxAddr0+4*4-1: 3014 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); 3015 break; 3016 case IntrMask: 3017 ret = rtl8139_IntrMask_read(s); 3018 break; 3019 3020 case IntrStatus: 3021 ret = rtl8139_IntrStatus_read(s); 3022 break; 3023 3024 case MultiIntr: 3025 ret = rtl8139_MultiIntr_read(s); 3026 break; 3027 3028 case RxBufPtr: 3029 ret = rtl8139_RxBufPtr_read(s); 3030 break; 3031 3032 case RxBufAddr: 3033 ret = rtl8139_RxBufAddr_read(s); 3034 break; 3035 3036 case BasicModeCtrl: 3037 ret = rtl8139_BasicModeCtrl_read(s); 3038 break; 3039 case BasicModeStatus: 3040 ret = rtl8139_BasicModeStatus_read(s); 3041 break; 3042 case NWayAdvert: 3043 ret = s->NWayAdvert; 3044 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret); 3045 break; 3046 case NWayLPAR: 3047 ret = s->NWayLPAR; 3048 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret); 3049 break; 3050 case NWayExpansion: 3051 ret = s->NWayExpansion; 3052 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret); 3053 break; 3054 3055 case CpCmd: 3056 ret = rtl8139_CpCmd_read(s); 3057 break; 3058 3059 case IntrMitigate: 3060 ret = rtl8139_IntrMitigate_read(s); 3061 break; 3062 3063 case TxSummary: 3064 ret = rtl8139_TSAD_read(s); 3065 break; 3066 3067 case CSCR: 3068 ret = rtl8139_CSCR_read(s); 3069 break; 3070 3071 default: 3072 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); 3073 3074 ret = rtl8139_io_readb(opaque, addr); 3075 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3076 3077 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); 3078 break; 3079 } 3080 3081 return ret; 3082 } 3083 3084 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr) 3085 { 3086 RTL8139State *s = opaque; 3087 uint32_t ret; 3088 3089 switch (addr) 3090 { 3091 case RxMissed: 3092 ret = s->RxMissed; 3093 3094 DPRINTF("RxMissed read val=0x%08x\n", ret); 3095 break; 3096 3097 case TxConfig: 3098 ret = rtl8139_TxConfig_read(s); 3099 break; 3100 3101 case RxConfig: 3102 ret = rtl8139_RxConfig_read(s); 3103 break; 3104 3105 case TxStatus0 ... TxStatus0+4*4-1: 3106 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, 3107 addr, 4); 3108 break; 3109 3110 case TxAddr0 ... TxAddr0+4*4-1: 3111 ret = rtl8139_TxAddr_read(s, addr-TxAddr0); 3112 break; 3113 3114 case RxBuf: 3115 ret = rtl8139_RxBuf_read(s); 3116 break; 3117 3118 case RxRingAddrLO: 3119 ret = s->RxRingAddrLO; 3120 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret); 3121 break; 3122 3123 case RxRingAddrHI: 3124 ret = s->RxRingAddrHI; 3125 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret); 3126 break; 3127 3128 case Timer: 3129 ret = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base) / 3130 PCI_PERIOD; 3131 DPRINTF("TCTR Timer read val=0x%08x\n", ret); 3132 break; 3133 3134 case FlashReg: 3135 ret = s->TimerInt; 3136 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret); 3137 break; 3138 3139 default: 3140 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); 3141 3142 ret = rtl8139_io_readb(opaque, addr); 3143 ret |= rtl8139_io_readb(opaque, addr + 1) << 8; 3144 ret |= rtl8139_io_readb(opaque, addr + 2) << 16; 3145 ret |= rtl8139_io_readb(opaque, addr + 3) << 24; 3146 3147 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret); 3148 break; 3149 } 3150 3151 return ret; 3152 } 3153 3154 /* */ 3155 3156 static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val) 3157 { 3158 rtl8139_io_writeb(opaque, addr & 0xFF, val); 3159 } 3160 3161 static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val) 3162 { 3163 rtl8139_io_writew(opaque, addr & 0xFF, val); 3164 } 3165 3166 static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val) 3167 { 3168 rtl8139_io_writel(opaque, addr & 0xFF, val); 3169 } 3170 3171 static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr) 3172 { 3173 return rtl8139_io_readb(opaque, addr & 0xFF); 3174 } 3175 3176 static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr) 3177 { 3178 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF); 3179 return val; 3180 } 3181 3182 static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr) 3183 { 3184 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF); 3185 return val; 3186 } 3187 3188 static int rtl8139_post_load(void *opaque, int version_id) 3189 { 3190 RTL8139State* s = opaque; 3191 rtl8139_set_next_tctr_time(s); 3192 if (version_id < 4) { 3193 s->cplus_enabled = s->CpCmd != 0; 3194 } 3195 3196 /* nc.link_down can't be migrated, so infer link_down according 3197 * to link status bit in BasicModeStatus */ 3198 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0; 3199 3200 return 0; 3201 } 3202 3203 static bool rtl8139_hotplug_ready_needed(void *opaque) 3204 { 3205 return qdev_machine_modified(); 3206 } 3207 3208 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={ 3209 .name = "rtl8139/hotplug_ready", 3210 .version_id = 1, 3211 .minimum_version_id = 1, 3212 .needed = rtl8139_hotplug_ready_needed, 3213 .fields = (VMStateField[]) { 3214 VMSTATE_END_OF_LIST() 3215 } 3216 }; 3217 3218 static void rtl8139_pre_save(void *opaque) 3219 { 3220 RTL8139State* s = opaque; 3221 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 3222 3223 /* for migration to older versions */ 3224 s->TCTR = (current_time - s->TCTR_base) / PCI_PERIOD; 3225 s->rtl8139_mmio_io_addr_dummy = 0; 3226 } 3227 3228 static const VMStateDescription vmstate_rtl8139 = { 3229 .name = "rtl8139", 3230 .version_id = 4, 3231 .minimum_version_id = 3, 3232 .post_load = rtl8139_post_load, 3233 .pre_save = rtl8139_pre_save, 3234 .fields = (VMStateField[]) { 3235 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State), 3236 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6), 3237 VMSTATE_BUFFER(mult, RTL8139State), 3238 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4), 3239 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4), 3240 3241 VMSTATE_UINT32(RxBuf, RTL8139State), 3242 VMSTATE_UINT32(RxBufferSize, RTL8139State), 3243 VMSTATE_UINT32(RxBufPtr, RTL8139State), 3244 VMSTATE_UINT32(RxBufAddr, RTL8139State), 3245 3246 VMSTATE_UINT16(IntrStatus, RTL8139State), 3247 VMSTATE_UINT16(IntrMask, RTL8139State), 3248 3249 VMSTATE_UINT32(TxConfig, RTL8139State), 3250 VMSTATE_UINT32(RxConfig, RTL8139State), 3251 VMSTATE_UINT32(RxMissed, RTL8139State), 3252 VMSTATE_UINT16(CSCR, RTL8139State), 3253 3254 VMSTATE_UINT8(Cfg9346, RTL8139State), 3255 VMSTATE_UINT8(Config0, RTL8139State), 3256 VMSTATE_UINT8(Config1, RTL8139State), 3257 VMSTATE_UINT8(Config3, RTL8139State), 3258 VMSTATE_UINT8(Config4, RTL8139State), 3259 VMSTATE_UINT8(Config5, RTL8139State), 3260 3261 VMSTATE_UINT8(clock_enabled, RTL8139State), 3262 VMSTATE_UINT8(bChipCmdState, RTL8139State), 3263 3264 VMSTATE_UINT16(MultiIntr, RTL8139State), 3265 3266 VMSTATE_UINT16(BasicModeCtrl, RTL8139State), 3267 VMSTATE_UINT16(BasicModeStatus, RTL8139State), 3268 VMSTATE_UINT16(NWayAdvert, RTL8139State), 3269 VMSTATE_UINT16(NWayLPAR, RTL8139State), 3270 VMSTATE_UINT16(NWayExpansion, RTL8139State), 3271 3272 VMSTATE_UINT16(CpCmd, RTL8139State), 3273 VMSTATE_UINT8(TxThresh, RTL8139State), 3274 3275 VMSTATE_UNUSED(4), 3276 VMSTATE_MACADDR(conf.macaddr, RTL8139State), 3277 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State), 3278 3279 VMSTATE_UINT32(currTxDesc, RTL8139State), 3280 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State), 3281 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State), 3282 VMSTATE_UINT32(RxRingAddrLO, RTL8139State), 3283 VMSTATE_UINT32(RxRingAddrHI, RTL8139State), 3284 3285 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE), 3286 VMSTATE_INT32(eeprom.mode, RTL8139State), 3287 VMSTATE_UINT32(eeprom.tick, RTL8139State), 3288 VMSTATE_UINT8(eeprom.address, RTL8139State), 3289 VMSTATE_UINT16(eeprom.input, RTL8139State), 3290 VMSTATE_UINT16(eeprom.output, RTL8139State), 3291 3292 VMSTATE_UINT8(eeprom.eecs, RTL8139State), 3293 VMSTATE_UINT8(eeprom.eesk, RTL8139State), 3294 VMSTATE_UINT8(eeprom.eedi, RTL8139State), 3295 VMSTATE_UINT8(eeprom.eedo, RTL8139State), 3296 3297 VMSTATE_UINT32(TCTR, RTL8139State), 3298 VMSTATE_UINT32(TimerInt, RTL8139State), 3299 VMSTATE_INT64(TCTR_base, RTL8139State), 3300 3301 VMSTATE_STRUCT(tally_counters, RTL8139State, 0, 3302 vmstate_tally_counters, RTL8139TallyCounters), 3303 3304 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4), 3305 VMSTATE_END_OF_LIST() 3306 }, 3307 .subsections = (const VMStateDescription*[]) { 3308 &vmstate_rtl8139_hotplug_ready, 3309 NULL 3310 } 3311 }; 3312 3313 /***********************************************************/ 3314 /* PCI RTL8139 definitions */ 3315 3316 static void rtl8139_ioport_write(void *opaque, hwaddr addr, 3317 uint64_t val, unsigned size) 3318 { 3319 switch (size) { 3320 case 1: 3321 rtl8139_io_writeb(opaque, addr, val); 3322 break; 3323 case 2: 3324 rtl8139_io_writew(opaque, addr, val); 3325 break; 3326 case 4: 3327 rtl8139_io_writel(opaque, addr, val); 3328 break; 3329 } 3330 } 3331 3332 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr, 3333 unsigned size) 3334 { 3335 switch (size) { 3336 case 1: 3337 return rtl8139_io_readb(opaque, addr); 3338 case 2: 3339 return rtl8139_io_readw(opaque, addr); 3340 case 4: 3341 return rtl8139_io_readl(opaque, addr); 3342 } 3343 3344 return -1; 3345 } 3346 3347 static const MemoryRegionOps rtl8139_io_ops = { 3348 .read = rtl8139_ioport_read, 3349 .write = rtl8139_ioport_write, 3350 .impl = { 3351 .min_access_size = 1, 3352 .max_access_size = 4, 3353 }, 3354 .endianness = DEVICE_LITTLE_ENDIAN, 3355 }; 3356 3357 static const MemoryRegionOps rtl8139_mmio_ops = { 3358 .old_mmio = { 3359 .read = { 3360 rtl8139_mmio_readb, 3361 rtl8139_mmio_readw, 3362 rtl8139_mmio_readl, 3363 }, 3364 .write = { 3365 rtl8139_mmio_writeb, 3366 rtl8139_mmio_writew, 3367 rtl8139_mmio_writel, 3368 }, 3369 }, 3370 .endianness = DEVICE_LITTLE_ENDIAN, 3371 }; 3372 3373 static void rtl8139_timer(void *opaque) 3374 { 3375 RTL8139State *s = opaque; 3376 3377 if (!s->clock_enabled) 3378 { 3379 DPRINTF(">>> timer: clock is not running\n"); 3380 return; 3381 } 3382 3383 s->IntrStatus |= PCSTimeout; 3384 rtl8139_update_irq(s); 3385 rtl8139_set_next_tctr_time(s); 3386 } 3387 3388 static void pci_rtl8139_uninit(PCIDevice *dev) 3389 { 3390 RTL8139State *s = RTL8139(dev); 3391 3392 g_free(s->cplus_txbuffer); 3393 s->cplus_txbuffer = NULL; 3394 timer_del(s->timer); 3395 timer_free(s->timer); 3396 qemu_del_nic(s->nic); 3397 } 3398 3399 static void rtl8139_set_link_status(NetClientState *nc) 3400 { 3401 RTL8139State *s = qemu_get_nic_opaque(nc); 3402 3403 if (nc->link_down) { 3404 s->BasicModeStatus &= ~0x04; 3405 } else { 3406 s->BasicModeStatus |= 0x04; 3407 } 3408 3409 s->IntrStatus |= RxUnderrun; 3410 rtl8139_update_irq(s); 3411 } 3412 3413 static NetClientInfo net_rtl8139_info = { 3414 .type = NET_CLIENT_OPTIONS_KIND_NIC, 3415 .size = sizeof(NICState), 3416 .can_receive = rtl8139_can_receive, 3417 .receive = rtl8139_receive, 3418 .link_status_changed = rtl8139_set_link_status, 3419 }; 3420 3421 static void pci_rtl8139_realize(PCIDevice *dev, Error **errp) 3422 { 3423 RTL8139State *s = RTL8139(dev); 3424 DeviceState *d = DEVICE(dev); 3425 uint8_t *pci_conf; 3426 3427 pci_conf = dev->config; 3428 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */ 3429 /* TODO: start of capability list, but no capability 3430 * list bit in status register, and offset 0xdc seems unused. */ 3431 pci_conf[PCI_CAPABILITY_LIST] = 0xdc; 3432 3433 memory_region_init_io(&s->bar_io, OBJECT(s), &rtl8139_io_ops, s, 3434 "rtl8139", 0x100); 3435 memory_region_init_io(&s->bar_mem, OBJECT(s), &rtl8139_mmio_ops, s, 3436 "rtl8139", 0x100); 3437 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io); 3438 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem); 3439 3440 qemu_macaddr_default_if_unset(&s->conf.macaddr); 3441 3442 /* prepare eeprom */ 3443 s->eeprom.contents[0] = 0x8129; 3444 #if 1 3445 /* PCI vendor and device ID should be mirrored here */ 3446 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK; 3447 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139; 3448 #endif 3449 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8; 3450 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8; 3451 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8; 3452 3453 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf, 3454 object_get_typename(OBJECT(dev)), d->id, s); 3455 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); 3456 3457 s->cplus_txbuffer = NULL; 3458 s->cplus_txbuffer_len = 0; 3459 s->cplus_txbuffer_offset = 0; 3460 3461 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rtl8139_timer, s); 3462 } 3463 3464 static void rtl8139_instance_init(Object *obj) 3465 { 3466 RTL8139State *s = RTL8139(obj); 3467 3468 device_add_bootindex_property(obj, &s->conf.bootindex, 3469 "bootindex", "/ethernet-phy@0", 3470 DEVICE(obj), NULL); 3471 } 3472 3473 static Property rtl8139_properties[] = { 3474 DEFINE_NIC_PROPERTIES(RTL8139State, conf), 3475 DEFINE_PROP_END_OF_LIST(), 3476 }; 3477 3478 static void rtl8139_class_init(ObjectClass *klass, void *data) 3479 { 3480 DeviceClass *dc = DEVICE_CLASS(klass); 3481 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3482 3483 k->realize = pci_rtl8139_realize; 3484 k->exit = pci_rtl8139_uninit; 3485 k->romfile = "efi-rtl8139.rom"; 3486 k->vendor_id = PCI_VENDOR_ID_REALTEK; 3487 k->device_id = PCI_DEVICE_ID_REALTEK_8139; 3488 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */ 3489 k->class_id = PCI_CLASS_NETWORK_ETHERNET; 3490 dc->reset = rtl8139_reset; 3491 dc->vmsd = &vmstate_rtl8139; 3492 dc->props = rtl8139_properties; 3493 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 3494 } 3495 3496 static const TypeInfo rtl8139_info = { 3497 .name = TYPE_RTL8139, 3498 .parent = TYPE_PCI_DEVICE, 3499 .instance_size = sizeof(RTL8139State), 3500 .class_init = rtl8139_class_init, 3501 .instance_init = rtl8139_instance_init, 3502 }; 3503 3504 static void rtl8139_register_types(void) 3505 { 3506 type_register_static(&rtl8139_info); 3507 } 3508 3509 type_init(rtl8139_register_types) 3510