1*740dafc0SNiek Linnenbank /* 2*740dafc0SNiek Linnenbank * Allwinner H3 System on Chip emulation 3*740dafc0SNiek Linnenbank * 4*740dafc0SNiek Linnenbank * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 5*740dafc0SNiek Linnenbank * 6*740dafc0SNiek Linnenbank * This program is free software: you can redistribute it and/or modify 7*740dafc0SNiek Linnenbank * it under the terms of the GNU General Public License as published by 8*740dafc0SNiek Linnenbank * the Free Software Foundation, either version 2 of the License, or 9*740dafc0SNiek Linnenbank * (at your option) any later version. 10*740dafc0SNiek Linnenbank * 11*740dafc0SNiek Linnenbank * This program is distributed in the hope that it will be useful, 12*740dafc0SNiek Linnenbank * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*740dafc0SNiek Linnenbank * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*740dafc0SNiek Linnenbank * GNU General Public License for more details. 15*740dafc0SNiek Linnenbank * 16*740dafc0SNiek Linnenbank * You should have received a copy of the GNU General Public License 17*740dafc0SNiek Linnenbank * along with this program. If not, see <http://www.gnu.org/licenses/>. 18*740dafc0SNiek Linnenbank */ 19*740dafc0SNiek Linnenbank 20*740dafc0SNiek Linnenbank /* 21*740dafc0SNiek Linnenbank * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 22*740dafc0SNiek Linnenbank * processor cores. Features and specifications include DDR2/DDR3 memory, 23*740dafc0SNiek Linnenbank * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and 24*740dafc0SNiek Linnenbank * various I/O modules. 25*740dafc0SNiek Linnenbank * 26*740dafc0SNiek Linnenbank * This implementation is based on the following datasheet: 27*740dafc0SNiek Linnenbank * 28*740dafc0SNiek Linnenbank * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf 29*740dafc0SNiek Linnenbank * 30*740dafc0SNiek Linnenbank * The latest datasheet and more info can be found on the Linux Sunxi wiki: 31*740dafc0SNiek Linnenbank * 32*740dafc0SNiek Linnenbank * https://linux-sunxi.org/H3 33*740dafc0SNiek Linnenbank */ 34*740dafc0SNiek Linnenbank 35*740dafc0SNiek Linnenbank #ifndef HW_ARM_ALLWINNER_H3_H 36*740dafc0SNiek Linnenbank #define HW_ARM_ALLWINNER_H3_H 37*740dafc0SNiek Linnenbank 38*740dafc0SNiek Linnenbank #include "qom/object.h" 39*740dafc0SNiek Linnenbank #include "hw/arm/boot.h" 40*740dafc0SNiek Linnenbank #include "hw/timer/allwinner-a10-pit.h" 41*740dafc0SNiek Linnenbank #include "hw/intc/arm_gic.h" 42*740dafc0SNiek Linnenbank #include "target/arm/cpu.h" 43*740dafc0SNiek Linnenbank 44*740dafc0SNiek Linnenbank /** 45*740dafc0SNiek Linnenbank * Allwinner H3 device list 46*740dafc0SNiek Linnenbank * 47*740dafc0SNiek Linnenbank * This enumeration is can be used refer to a particular device in the 48*740dafc0SNiek Linnenbank * Allwinner H3 SoC. For example, the physical memory base address for 49*740dafc0SNiek Linnenbank * each device can be found in the AwH3State object in the memmap member 50*740dafc0SNiek Linnenbank * using the device enum value as index. 51*740dafc0SNiek Linnenbank * 52*740dafc0SNiek Linnenbank * @see AwH3State 53*740dafc0SNiek Linnenbank */ 54*740dafc0SNiek Linnenbank enum { 55*740dafc0SNiek Linnenbank AW_H3_SRAM_A1, 56*740dafc0SNiek Linnenbank AW_H3_SRAM_A2, 57*740dafc0SNiek Linnenbank AW_H3_SRAM_C, 58*740dafc0SNiek Linnenbank AW_H3_PIT, 59*740dafc0SNiek Linnenbank AW_H3_UART0, 60*740dafc0SNiek Linnenbank AW_H3_UART1, 61*740dafc0SNiek Linnenbank AW_H3_UART2, 62*740dafc0SNiek Linnenbank AW_H3_UART3, 63*740dafc0SNiek Linnenbank AW_H3_GIC_DIST, 64*740dafc0SNiek Linnenbank AW_H3_GIC_CPU, 65*740dafc0SNiek Linnenbank AW_H3_GIC_HYP, 66*740dafc0SNiek Linnenbank AW_H3_GIC_VCPU, 67*740dafc0SNiek Linnenbank AW_H3_SDRAM 68*740dafc0SNiek Linnenbank }; 69*740dafc0SNiek Linnenbank 70*740dafc0SNiek Linnenbank /** Total number of CPU cores in the H3 SoC */ 71*740dafc0SNiek Linnenbank #define AW_H3_NUM_CPUS (4) 72*740dafc0SNiek Linnenbank 73*740dafc0SNiek Linnenbank /** 74*740dafc0SNiek Linnenbank * Allwinner H3 object model 75*740dafc0SNiek Linnenbank * @{ 76*740dafc0SNiek Linnenbank */ 77*740dafc0SNiek Linnenbank 78*740dafc0SNiek Linnenbank /** Object type for the Allwinner H3 SoC */ 79*740dafc0SNiek Linnenbank #define TYPE_AW_H3 "allwinner-h3" 80*740dafc0SNiek Linnenbank 81*740dafc0SNiek Linnenbank /** Convert input object to Allwinner H3 state object */ 82*740dafc0SNiek Linnenbank #define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) 83*740dafc0SNiek Linnenbank 84*740dafc0SNiek Linnenbank /** @} */ 85*740dafc0SNiek Linnenbank 86*740dafc0SNiek Linnenbank /** 87*740dafc0SNiek Linnenbank * Allwinner H3 object 88*740dafc0SNiek Linnenbank * 89*740dafc0SNiek Linnenbank * This struct contains the state of all the devices 90*740dafc0SNiek Linnenbank * which are currently emulated by the H3 SoC code. 91*740dafc0SNiek Linnenbank */ 92*740dafc0SNiek Linnenbank typedef struct AwH3State { 93*740dafc0SNiek Linnenbank /*< private >*/ 94*740dafc0SNiek Linnenbank DeviceState parent_obj; 95*740dafc0SNiek Linnenbank /*< public >*/ 96*740dafc0SNiek Linnenbank 97*740dafc0SNiek Linnenbank ARMCPU cpus[AW_H3_NUM_CPUS]; 98*740dafc0SNiek Linnenbank const hwaddr *memmap; 99*740dafc0SNiek Linnenbank AwA10PITState timer; 100*740dafc0SNiek Linnenbank GICState gic; 101*740dafc0SNiek Linnenbank MemoryRegion sram_a1; 102*740dafc0SNiek Linnenbank MemoryRegion sram_a2; 103*740dafc0SNiek Linnenbank MemoryRegion sram_c; 104*740dafc0SNiek Linnenbank } AwH3State; 105*740dafc0SNiek Linnenbank 106*740dafc0SNiek Linnenbank #endif /* HW_ARM_ALLWINNER_H3_H */ 107