xref: /qemu/include/hw/arm/allwinner-h3.h (revision 8063396b)
1740dafc0SNiek Linnenbank /*
2740dafc0SNiek Linnenbank  * Allwinner H3 System on Chip emulation
3740dafc0SNiek Linnenbank  *
4740dafc0SNiek Linnenbank  * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5740dafc0SNiek Linnenbank  *
6740dafc0SNiek Linnenbank  * This program is free software: you can redistribute it and/or modify
7740dafc0SNiek Linnenbank  * it under the terms of the GNU General Public License as published by
8740dafc0SNiek Linnenbank  * the Free Software Foundation, either version 2 of the License, or
9740dafc0SNiek Linnenbank  * (at your option) any later version.
10740dafc0SNiek Linnenbank  *
11740dafc0SNiek Linnenbank  * This program is distributed in the hope that it will be useful,
12740dafc0SNiek Linnenbank  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13740dafc0SNiek Linnenbank  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14740dafc0SNiek Linnenbank  * GNU General Public License for more details.
15740dafc0SNiek Linnenbank  *
16740dafc0SNiek Linnenbank  * You should have received a copy of the GNU General Public License
17740dafc0SNiek Linnenbank  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18740dafc0SNiek Linnenbank  */
19740dafc0SNiek Linnenbank 
20740dafc0SNiek Linnenbank /*
21740dafc0SNiek Linnenbank  * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
22740dafc0SNiek Linnenbank  * processor cores. Features and specifications include DDR2/DDR3 memory,
23740dafc0SNiek Linnenbank  * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
24740dafc0SNiek Linnenbank  * various I/O modules.
25740dafc0SNiek Linnenbank  *
26740dafc0SNiek Linnenbank  * This implementation is based on the following datasheet:
27740dafc0SNiek Linnenbank  *
28740dafc0SNiek Linnenbank  *   https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
29740dafc0SNiek Linnenbank  *
30740dafc0SNiek Linnenbank  * The latest datasheet and more info can be found on the Linux Sunxi wiki:
31740dafc0SNiek Linnenbank  *
32740dafc0SNiek Linnenbank  *   https://linux-sunxi.org/H3
33740dafc0SNiek Linnenbank  */
34740dafc0SNiek Linnenbank 
35740dafc0SNiek Linnenbank #ifndef HW_ARM_ALLWINNER_H3_H
36740dafc0SNiek Linnenbank #define HW_ARM_ALLWINNER_H3_H
37740dafc0SNiek Linnenbank 
38740dafc0SNiek Linnenbank #include "qom/object.h"
39740dafc0SNiek Linnenbank #include "hw/arm/boot.h"
40740dafc0SNiek Linnenbank #include "hw/timer/allwinner-a10-pit.h"
41740dafc0SNiek Linnenbank #include "hw/intc/arm_gic.h"
42fef06c8bSNiek Linnenbank #include "hw/misc/allwinner-h3-ccu.h"
43d26af5deSNiek Linnenbank #include "hw/misc/allwinner-cpucfg.h"
44b71d0385SNiek Linnenbank #include "hw/misc/allwinner-h3-dramc.h"
457e83c9ddSNiek Linnenbank #include "hw/misc/allwinner-h3-sysctrl.h"
466556617cSNiek Linnenbank #include "hw/misc/allwinner-sid.h"
4782e48382SNiek Linnenbank #include "hw/sd/allwinner-sdhost.h"
4829d08975SNiek Linnenbank #include "hw/net/allwinner-sun8i-emac.h"
49a9ad9e73SNiek Linnenbank #include "hw/rtc/allwinner-rtc.h"
50740dafc0SNiek Linnenbank #include "target/arm/cpu.h"
51a80beb16SNiek Linnenbank #include "sysemu/block-backend.h"
52740dafc0SNiek Linnenbank 
53740dafc0SNiek Linnenbank /**
54740dafc0SNiek Linnenbank  * Allwinner H3 device list
55740dafc0SNiek Linnenbank  *
56740dafc0SNiek Linnenbank  * This enumeration is can be used refer to a particular device in the
57740dafc0SNiek Linnenbank  * Allwinner H3 SoC. For example, the physical memory base address for
58740dafc0SNiek Linnenbank  * each device can be found in the AwH3State object in the memmap member
59740dafc0SNiek Linnenbank  * using the device enum value as index.
60740dafc0SNiek Linnenbank  *
61740dafc0SNiek Linnenbank  * @see AwH3State
62740dafc0SNiek Linnenbank  */
63740dafc0SNiek Linnenbank enum {
644af44e1eSEduardo Habkost     AW_H3_DEV_SRAM_A1,
654af44e1eSEduardo Habkost     AW_H3_DEV_SRAM_A2,
664af44e1eSEduardo Habkost     AW_H3_DEV_SRAM_C,
674af44e1eSEduardo Habkost     AW_H3_DEV_SYSCTRL,
684af44e1eSEduardo Habkost     AW_H3_DEV_MMC0,
694af44e1eSEduardo Habkost     AW_H3_DEV_SID,
704af44e1eSEduardo Habkost     AW_H3_DEV_EHCI0,
714af44e1eSEduardo Habkost     AW_H3_DEV_OHCI0,
724af44e1eSEduardo Habkost     AW_H3_DEV_EHCI1,
734af44e1eSEduardo Habkost     AW_H3_DEV_OHCI1,
744af44e1eSEduardo Habkost     AW_H3_DEV_EHCI2,
754af44e1eSEduardo Habkost     AW_H3_DEV_OHCI2,
764af44e1eSEduardo Habkost     AW_H3_DEV_EHCI3,
774af44e1eSEduardo Habkost     AW_H3_DEV_OHCI3,
784af44e1eSEduardo Habkost     AW_H3_DEV_CCU,
794af44e1eSEduardo Habkost     AW_H3_DEV_PIT,
804af44e1eSEduardo Habkost     AW_H3_DEV_UART0,
814af44e1eSEduardo Habkost     AW_H3_DEV_UART1,
824af44e1eSEduardo Habkost     AW_H3_DEV_UART2,
834af44e1eSEduardo Habkost     AW_H3_DEV_UART3,
844af44e1eSEduardo Habkost     AW_H3_DEV_EMAC,
854af44e1eSEduardo Habkost     AW_H3_DEV_DRAMCOM,
864af44e1eSEduardo Habkost     AW_H3_DEV_DRAMCTL,
874af44e1eSEduardo Habkost     AW_H3_DEV_DRAMPHY,
884af44e1eSEduardo Habkost     AW_H3_DEV_GIC_DIST,
894af44e1eSEduardo Habkost     AW_H3_DEV_GIC_CPU,
904af44e1eSEduardo Habkost     AW_H3_DEV_GIC_HYP,
914af44e1eSEduardo Habkost     AW_H3_DEV_GIC_VCPU,
924af44e1eSEduardo Habkost     AW_H3_DEV_RTC,
934af44e1eSEduardo Habkost     AW_H3_DEV_CPUCFG,
944af44e1eSEduardo Habkost     AW_H3_DEV_SDRAM
95740dafc0SNiek Linnenbank };
96740dafc0SNiek Linnenbank 
97740dafc0SNiek Linnenbank /** Total number of CPU cores in the H3 SoC */
98740dafc0SNiek Linnenbank #define AW_H3_NUM_CPUS      (4)
99740dafc0SNiek Linnenbank 
100740dafc0SNiek Linnenbank /**
101740dafc0SNiek Linnenbank  * Allwinner H3 object model
102740dafc0SNiek Linnenbank  * @{
103740dafc0SNiek Linnenbank  */
104740dafc0SNiek Linnenbank 
105740dafc0SNiek Linnenbank /** Object type for the Allwinner H3 SoC */
106740dafc0SNiek Linnenbank #define TYPE_AW_H3 "allwinner-h3"
107740dafc0SNiek Linnenbank 
108740dafc0SNiek Linnenbank /** Convert input object to Allwinner H3 state object */
109*8063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(AwH3State, AW_H3)
110740dafc0SNiek Linnenbank 
111740dafc0SNiek Linnenbank /** @} */
112740dafc0SNiek Linnenbank 
113740dafc0SNiek Linnenbank /**
114740dafc0SNiek Linnenbank  * Allwinner H3 object
115740dafc0SNiek Linnenbank  *
116740dafc0SNiek Linnenbank  * This struct contains the state of all the devices
117740dafc0SNiek Linnenbank  * which are currently emulated by the H3 SoC code.
118740dafc0SNiek Linnenbank  */
119db1015e9SEduardo Habkost struct AwH3State {
120740dafc0SNiek Linnenbank     /*< private >*/
121740dafc0SNiek Linnenbank     DeviceState parent_obj;
122740dafc0SNiek Linnenbank     /*< public >*/
123740dafc0SNiek Linnenbank 
124740dafc0SNiek Linnenbank     ARMCPU cpus[AW_H3_NUM_CPUS];
125740dafc0SNiek Linnenbank     const hwaddr *memmap;
126740dafc0SNiek Linnenbank     AwA10PITState timer;
127fef06c8bSNiek Linnenbank     AwH3ClockCtlState ccu;
128d26af5deSNiek Linnenbank     AwCpuCfgState cpucfg;
129b71d0385SNiek Linnenbank     AwH3DramCtlState dramc;
1307e83c9ddSNiek Linnenbank     AwH3SysCtrlState sysctrl;
1316556617cSNiek Linnenbank     AwSidState sid;
13282e48382SNiek Linnenbank     AwSdHostState mmc0;
13329d08975SNiek Linnenbank     AwSun8iEmacState emac;
134a9ad9e73SNiek Linnenbank     AwRtcState rtc;
135740dafc0SNiek Linnenbank     GICState gic;
136740dafc0SNiek Linnenbank     MemoryRegion sram_a1;
137740dafc0SNiek Linnenbank     MemoryRegion sram_a2;
138740dafc0SNiek Linnenbank     MemoryRegion sram_c;
139db1015e9SEduardo Habkost };
140740dafc0SNiek Linnenbank 
141a80beb16SNiek Linnenbank /**
142a80beb16SNiek Linnenbank  * Emulate Boot ROM firmware setup functionality.
143a80beb16SNiek Linnenbank  *
144a80beb16SNiek Linnenbank  * A real Allwinner H3 SoC contains a Boot ROM
145a80beb16SNiek Linnenbank  * which is the first code that runs right after
146a80beb16SNiek Linnenbank  * the SoC is powered on. The Boot ROM is responsible
147a80beb16SNiek Linnenbank  * for loading user code (e.g. a bootloader) from any
148a80beb16SNiek Linnenbank  * of the supported external devices and writing the
149a80beb16SNiek Linnenbank  * downloaded code to internal SRAM. After loading the SoC
150a80beb16SNiek Linnenbank  * begins executing the code written to SRAM.
151a80beb16SNiek Linnenbank  *
152a80beb16SNiek Linnenbank  * This function emulates the Boot ROM by copying 32 KiB
153a80beb16SNiek Linnenbank  * of data from the given block device and writes it to
154a80beb16SNiek Linnenbank  * the start of the first internal SRAM memory.
155a80beb16SNiek Linnenbank  *
156a80beb16SNiek Linnenbank  * @s: Allwinner H3 state object pointer
157a80beb16SNiek Linnenbank  * @blk: Block backend device object pointer
158a80beb16SNiek Linnenbank  */
159a80beb16SNiek Linnenbank void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
160a80beb16SNiek Linnenbank 
161740dafc0SNiek Linnenbank #endif /* HW_ARM_ALLWINNER_H3_H */
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