xref: /qemu/include/hw/arm/allwinner-h3.h (revision b71d0385)
1740dafc0SNiek Linnenbank /*
2740dafc0SNiek Linnenbank  * Allwinner H3 System on Chip emulation
3740dafc0SNiek Linnenbank  *
4740dafc0SNiek Linnenbank  * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5740dafc0SNiek Linnenbank  *
6740dafc0SNiek Linnenbank  * This program is free software: you can redistribute it and/or modify
7740dafc0SNiek Linnenbank  * it under the terms of the GNU General Public License as published by
8740dafc0SNiek Linnenbank  * the Free Software Foundation, either version 2 of the License, or
9740dafc0SNiek Linnenbank  * (at your option) any later version.
10740dafc0SNiek Linnenbank  *
11740dafc0SNiek Linnenbank  * This program is distributed in the hope that it will be useful,
12740dafc0SNiek Linnenbank  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13740dafc0SNiek Linnenbank  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14740dafc0SNiek Linnenbank  * GNU General Public License for more details.
15740dafc0SNiek Linnenbank  *
16740dafc0SNiek Linnenbank  * You should have received a copy of the GNU General Public License
17740dafc0SNiek Linnenbank  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18740dafc0SNiek Linnenbank  */
19740dafc0SNiek Linnenbank 
20740dafc0SNiek Linnenbank /*
21740dafc0SNiek Linnenbank  * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
22740dafc0SNiek Linnenbank  * processor cores. Features and specifications include DDR2/DDR3 memory,
23740dafc0SNiek Linnenbank  * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
24740dafc0SNiek Linnenbank  * various I/O modules.
25740dafc0SNiek Linnenbank  *
26740dafc0SNiek Linnenbank  * This implementation is based on the following datasheet:
27740dafc0SNiek Linnenbank  *
28740dafc0SNiek Linnenbank  *   https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
29740dafc0SNiek Linnenbank  *
30740dafc0SNiek Linnenbank  * The latest datasheet and more info can be found on the Linux Sunxi wiki:
31740dafc0SNiek Linnenbank  *
32740dafc0SNiek Linnenbank  *   https://linux-sunxi.org/H3
33740dafc0SNiek Linnenbank  */
34740dafc0SNiek Linnenbank 
35740dafc0SNiek Linnenbank #ifndef HW_ARM_ALLWINNER_H3_H
36740dafc0SNiek Linnenbank #define HW_ARM_ALLWINNER_H3_H
37740dafc0SNiek Linnenbank 
38740dafc0SNiek Linnenbank #include "qom/object.h"
39740dafc0SNiek Linnenbank #include "hw/arm/boot.h"
40740dafc0SNiek Linnenbank #include "hw/timer/allwinner-a10-pit.h"
41740dafc0SNiek Linnenbank #include "hw/intc/arm_gic.h"
42fef06c8bSNiek Linnenbank #include "hw/misc/allwinner-h3-ccu.h"
43d26af5deSNiek Linnenbank #include "hw/misc/allwinner-cpucfg.h"
44*b71d0385SNiek Linnenbank #include "hw/misc/allwinner-h3-dramc.h"
457e83c9ddSNiek Linnenbank #include "hw/misc/allwinner-h3-sysctrl.h"
466556617cSNiek Linnenbank #include "hw/misc/allwinner-sid.h"
4782e48382SNiek Linnenbank #include "hw/sd/allwinner-sdhost.h"
4829d08975SNiek Linnenbank #include "hw/net/allwinner-sun8i-emac.h"
49740dafc0SNiek Linnenbank #include "target/arm/cpu.h"
50a80beb16SNiek Linnenbank #include "sysemu/block-backend.h"
51740dafc0SNiek Linnenbank 
52740dafc0SNiek Linnenbank /**
53740dafc0SNiek Linnenbank  * Allwinner H3 device list
54740dafc0SNiek Linnenbank  *
55740dafc0SNiek Linnenbank  * This enumeration is can be used refer to a particular device in the
56740dafc0SNiek Linnenbank  * Allwinner H3 SoC. For example, the physical memory base address for
57740dafc0SNiek Linnenbank  * each device can be found in the AwH3State object in the memmap member
58740dafc0SNiek Linnenbank  * using the device enum value as index.
59740dafc0SNiek Linnenbank  *
60740dafc0SNiek Linnenbank  * @see AwH3State
61740dafc0SNiek Linnenbank  */
62740dafc0SNiek Linnenbank enum {
63740dafc0SNiek Linnenbank     AW_H3_SRAM_A1,
64740dafc0SNiek Linnenbank     AW_H3_SRAM_A2,
65740dafc0SNiek Linnenbank     AW_H3_SRAM_C,
667e83c9ddSNiek Linnenbank     AW_H3_SYSCTRL,
6782e48382SNiek Linnenbank     AW_H3_MMC0,
686556617cSNiek Linnenbank     AW_H3_SID,
692e4dfe80SNiek Linnenbank     AW_H3_EHCI0,
702e4dfe80SNiek Linnenbank     AW_H3_OHCI0,
712e4dfe80SNiek Linnenbank     AW_H3_EHCI1,
722e4dfe80SNiek Linnenbank     AW_H3_OHCI1,
732e4dfe80SNiek Linnenbank     AW_H3_EHCI2,
742e4dfe80SNiek Linnenbank     AW_H3_OHCI2,
752e4dfe80SNiek Linnenbank     AW_H3_EHCI3,
762e4dfe80SNiek Linnenbank     AW_H3_OHCI3,
77fef06c8bSNiek Linnenbank     AW_H3_CCU,
78740dafc0SNiek Linnenbank     AW_H3_PIT,
79740dafc0SNiek Linnenbank     AW_H3_UART0,
80740dafc0SNiek Linnenbank     AW_H3_UART1,
81740dafc0SNiek Linnenbank     AW_H3_UART2,
82740dafc0SNiek Linnenbank     AW_H3_UART3,
8329d08975SNiek Linnenbank     AW_H3_EMAC,
84*b71d0385SNiek Linnenbank     AW_H3_DRAMCOM,
85*b71d0385SNiek Linnenbank     AW_H3_DRAMCTL,
86*b71d0385SNiek Linnenbank     AW_H3_DRAMPHY,
87740dafc0SNiek Linnenbank     AW_H3_GIC_DIST,
88740dafc0SNiek Linnenbank     AW_H3_GIC_CPU,
89740dafc0SNiek Linnenbank     AW_H3_GIC_HYP,
90740dafc0SNiek Linnenbank     AW_H3_GIC_VCPU,
91d26af5deSNiek Linnenbank     AW_H3_CPUCFG,
92740dafc0SNiek Linnenbank     AW_H3_SDRAM
93740dafc0SNiek Linnenbank };
94740dafc0SNiek Linnenbank 
95740dafc0SNiek Linnenbank /** Total number of CPU cores in the H3 SoC */
96740dafc0SNiek Linnenbank #define AW_H3_NUM_CPUS      (4)
97740dafc0SNiek Linnenbank 
98740dafc0SNiek Linnenbank /**
99740dafc0SNiek Linnenbank  * Allwinner H3 object model
100740dafc0SNiek Linnenbank  * @{
101740dafc0SNiek Linnenbank  */
102740dafc0SNiek Linnenbank 
103740dafc0SNiek Linnenbank /** Object type for the Allwinner H3 SoC */
104740dafc0SNiek Linnenbank #define TYPE_AW_H3 "allwinner-h3"
105740dafc0SNiek Linnenbank 
106740dafc0SNiek Linnenbank /** Convert input object to Allwinner H3 state object */
107740dafc0SNiek Linnenbank #define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
108740dafc0SNiek Linnenbank 
109740dafc0SNiek Linnenbank /** @} */
110740dafc0SNiek Linnenbank 
111740dafc0SNiek Linnenbank /**
112740dafc0SNiek Linnenbank  * Allwinner H3 object
113740dafc0SNiek Linnenbank  *
114740dafc0SNiek Linnenbank  * This struct contains the state of all the devices
115740dafc0SNiek Linnenbank  * which are currently emulated by the H3 SoC code.
116740dafc0SNiek Linnenbank  */
117740dafc0SNiek Linnenbank typedef struct AwH3State {
118740dafc0SNiek Linnenbank     /*< private >*/
119740dafc0SNiek Linnenbank     DeviceState parent_obj;
120740dafc0SNiek Linnenbank     /*< public >*/
121740dafc0SNiek Linnenbank 
122740dafc0SNiek Linnenbank     ARMCPU cpus[AW_H3_NUM_CPUS];
123740dafc0SNiek Linnenbank     const hwaddr *memmap;
124740dafc0SNiek Linnenbank     AwA10PITState timer;
125fef06c8bSNiek Linnenbank     AwH3ClockCtlState ccu;
126d26af5deSNiek Linnenbank     AwCpuCfgState cpucfg;
127*b71d0385SNiek Linnenbank     AwH3DramCtlState dramc;
1287e83c9ddSNiek Linnenbank     AwH3SysCtrlState sysctrl;
1296556617cSNiek Linnenbank     AwSidState sid;
13082e48382SNiek Linnenbank     AwSdHostState mmc0;
13129d08975SNiek Linnenbank     AwSun8iEmacState emac;
132740dafc0SNiek Linnenbank     GICState gic;
133740dafc0SNiek Linnenbank     MemoryRegion sram_a1;
134740dafc0SNiek Linnenbank     MemoryRegion sram_a2;
135740dafc0SNiek Linnenbank     MemoryRegion sram_c;
136740dafc0SNiek Linnenbank } AwH3State;
137740dafc0SNiek Linnenbank 
138a80beb16SNiek Linnenbank /**
139a80beb16SNiek Linnenbank  * Emulate Boot ROM firmware setup functionality.
140a80beb16SNiek Linnenbank  *
141a80beb16SNiek Linnenbank  * A real Allwinner H3 SoC contains a Boot ROM
142a80beb16SNiek Linnenbank  * which is the first code that runs right after
143a80beb16SNiek Linnenbank  * the SoC is powered on. The Boot ROM is responsible
144a80beb16SNiek Linnenbank  * for loading user code (e.g. a bootloader) from any
145a80beb16SNiek Linnenbank  * of the supported external devices and writing the
146a80beb16SNiek Linnenbank  * downloaded code to internal SRAM. After loading the SoC
147a80beb16SNiek Linnenbank  * begins executing the code written to SRAM.
148a80beb16SNiek Linnenbank  *
149a80beb16SNiek Linnenbank  * This function emulates the Boot ROM by copying 32 KiB
150a80beb16SNiek Linnenbank  * of data from the given block device and writes it to
151a80beb16SNiek Linnenbank  * the start of the first internal SRAM memory.
152a80beb16SNiek Linnenbank  *
153a80beb16SNiek Linnenbank  * @s: Allwinner H3 state object pointer
154a80beb16SNiek Linnenbank  * @blk: Block backend device object pointer
155a80beb16SNiek Linnenbank  */
156a80beb16SNiek Linnenbank void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
157a80beb16SNiek Linnenbank 
158740dafc0SNiek Linnenbank #endif /* HW_ARM_ALLWINNER_H3_H */
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