1 /* 2 * Allwinner H3 System on Chip emulation 3 * 4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com> 5 * 6 * This program is free software: you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation, either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /* 21 * The Allwinner H3 is a System on Chip containing four ARM Cortex A7 22 * processor cores. Features and specifications include DDR2/DDR3 memory, 23 * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and 24 * various I/O modules. 25 * 26 * This implementation is based on the following datasheet: 27 * 28 * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf 29 * 30 * The latest datasheet and more info can be found on the Linux Sunxi wiki: 31 * 32 * https://linux-sunxi.org/H3 33 */ 34 35 #ifndef HW_ARM_ALLWINNER_H3_H 36 #define HW_ARM_ALLWINNER_H3_H 37 38 #include "qom/object.h" 39 #include "hw/arm/boot.h" 40 #include "hw/timer/allwinner-a10-pit.h" 41 #include "hw/intc/arm_gic.h" 42 #include "hw/misc/allwinner-h3-ccu.h" 43 #include "hw/misc/allwinner-h3-sysctrl.h" 44 #include "target/arm/cpu.h" 45 46 /** 47 * Allwinner H3 device list 48 * 49 * This enumeration is can be used refer to a particular device in the 50 * Allwinner H3 SoC. For example, the physical memory base address for 51 * each device can be found in the AwH3State object in the memmap member 52 * using the device enum value as index. 53 * 54 * @see AwH3State 55 */ 56 enum { 57 AW_H3_SRAM_A1, 58 AW_H3_SRAM_A2, 59 AW_H3_SRAM_C, 60 AW_H3_SYSCTRL, 61 AW_H3_EHCI0, 62 AW_H3_OHCI0, 63 AW_H3_EHCI1, 64 AW_H3_OHCI1, 65 AW_H3_EHCI2, 66 AW_H3_OHCI2, 67 AW_H3_EHCI3, 68 AW_H3_OHCI3, 69 AW_H3_CCU, 70 AW_H3_PIT, 71 AW_H3_UART0, 72 AW_H3_UART1, 73 AW_H3_UART2, 74 AW_H3_UART3, 75 AW_H3_GIC_DIST, 76 AW_H3_GIC_CPU, 77 AW_H3_GIC_HYP, 78 AW_H3_GIC_VCPU, 79 AW_H3_SDRAM 80 }; 81 82 /** Total number of CPU cores in the H3 SoC */ 83 #define AW_H3_NUM_CPUS (4) 84 85 /** 86 * Allwinner H3 object model 87 * @{ 88 */ 89 90 /** Object type for the Allwinner H3 SoC */ 91 #define TYPE_AW_H3 "allwinner-h3" 92 93 /** Convert input object to Allwinner H3 state object */ 94 #define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3) 95 96 /** @} */ 97 98 /** 99 * Allwinner H3 object 100 * 101 * This struct contains the state of all the devices 102 * which are currently emulated by the H3 SoC code. 103 */ 104 typedef struct AwH3State { 105 /*< private >*/ 106 DeviceState parent_obj; 107 /*< public >*/ 108 109 ARMCPU cpus[AW_H3_NUM_CPUS]; 110 const hwaddr *memmap; 111 AwA10PITState timer; 112 AwH3ClockCtlState ccu; 113 AwH3SysCtrlState sysctrl; 114 GICState gic; 115 MemoryRegion sram_a1; 116 MemoryRegion sram_a2; 117 MemoryRegion sram_c; 118 } AwH3State; 119 120 #endif /* HW_ARM_ALLWINNER_H3_H */ 121